4 * Copyright (c) 2015-2020 Amazon.com, Inc. or its affiliates.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
19 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
21 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
22 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
23 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
24 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
28 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 #include <sys/types.h>
39 #include "ena-com/ena_com.h"
40 #include "ena-com/ena_eth_com.h"
42 #define DRV_MODULE_VER_MAJOR 2
43 #define DRV_MODULE_VER_MINOR 2
44 #define DRV_MODULE_VER_SUBMINOR 0
46 #define DRV_MODULE_NAME "ena"
48 #ifndef DRV_MODULE_VERSION
49 #define DRV_MODULE_VERSION \
50 __XSTRING(DRV_MODULE_VER_MAJOR) "." \
51 __XSTRING(DRV_MODULE_VER_MINOR) "." \
52 __XSTRING(DRV_MODULE_VER_SUBMINOR)
54 #define DEVICE_NAME "Elastic Network Adapter (ENA)"
55 #define DEVICE_DESC "ENA adapter"
57 /* Calculate DMA mask - width for ena cannot exceed 48, so it is safe */
58 #define ENA_DMA_BIT_MASK(x) ((1ULL << (x)) - 1ULL)
60 /* 1 for AENQ + ADMIN */
61 #define ENA_ADMIN_MSIX_VEC 1
62 #define ENA_MAX_MSIX_VEC(io_queues) (ENA_ADMIN_MSIX_VEC + (io_queues))
67 #define ENA_BUS_DMA_SEGS 32
69 #define ENA_DEFAULT_BUF_RING_SIZE 4096
71 #define ENA_DEFAULT_RING_SIZE 1024
72 #define ENA_MIN_RING_SIZE 256
75 * Refill Rx queue when number of required descriptors is above
76 * QUEUE_SIZE / ENA_RX_REFILL_THRESH_DIVIDER or ENA_RX_REFILL_THRESH_PACKET
78 #define ENA_RX_REFILL_THRESH_DIVIDER 8
79 #define ENA_RX_REFILL_THRESH_PACKET 256
81 #define ENA_IRQNAME_SIZE 40
83 #define ENA_PKT_MAX_BUFS 19
85 #define ENA_RX_RSS_TABLE_LOG_SIZE 7
86 #define ENA_RX_RSS_TABLE_SIZE (1 << ENA_RX_RSS_TABLE_LOG_SIZE)
88 #define ENA_HASH_KEY_SIZE 40
90 #define ENA_MAX_FRAME_LEN 10000
91 #define ENA_MIN_FRAME_LEN 60
93 #define ENA_TX_RESUME_THRESH (ENA_PKT_MAX_BUFS + 2)
95 #define DB_THRESHOLD 64
99 * TX budget for cleaning. It should be half of the RX budget to reduce amount
100 * of TCP retransmissions.
102 #define TX_BUDGET 128
103 /* RX cleanup budget. -1 stands for infinity. */
104 #define RX_BUDGET 256
106 * How many times we can repeat cleanup in the io irq handling routine if the
107 * RX or TX budget was depleted.
109 #define CLEAN_BUDGET 8
111 #define RX_IRQ_INTERVAL 20
112 #define TX_IRQ_INTERVAL 50
114 #define ENA_MIN_MTU 128
116 #define ENA_TSO_MAXSIZE 65536
118 #define ENA_MMIO_DISABLE_REG_READ BIT(0)
120 #define ENA_TX_RING_IDX_NEXT(idx, ring_size) (((idx) + 1) & ((ring_size) - 1))
122 #define ENA_RX_RING_IDX_NEXT(idx, ring_size) (((idx) + 1) & ((ring_size) - 1))
124 #define ENA_IO_TXQ_IDX(q) (2 * (q))
125 #define ENA_IO_RXQ_IDX(q) (2 * (q) + 1)
127 #define ENA_MGMNT_IRQ_IDX 0
128 #define ENA_IO_IRQ_FIRST_IDX 1
129 #define ENA_IO_IRQ_IDX(q) (ENA_IO_IRQ_FIRST_IDX + (q))
131 #define ENA_MAX_NO_INTERRUPT_ITERATIONS 3
134 * ENA device should send keep alive msg every 1 sec.
135 * We wait for 6 sec just to be on the safe side.
137 #define DEFAULT_KEEP_ALIVE_TO (SBT_1S * 6)
139 /* Time in jiffies before concluding the transmitter is hung. */
140 #define DEFAULT_TX_CMP_TO (SBT_1S * 5)
142 /* Number of queues to check for missing queues per timer tick */
143 #define DEFAULT_TX_MONITORED_QUEUES (4)
145 /* Max number of timeouted packets before device reset */
146 #define DEFAULT_TX_CMP_THRESHOLD (128)
149 * Supported PCI vendor and devices IDs
151 #define PCI_VENDOR_ID_AMAZON 0x1d0f
153 #define PCI_DEV_ID_ENA_PF 0x0ec2
154 #define PCI_DEV_ID_ENA_LLQ_PF 0x1ec2
155 #define PCI_DEV_ID_ENA_VF 0xec20
156 #define PCI_DEV_ID_ENA_LLQ_VF 0xec21
159 * Flags indicating current ENA driver state
162 ENA_FLAG_DEVICE_RUNNING,
165 ENA_FLAG_MSIX_ENABLED,
166 ENA_FLAG_TRIGGER_RESET,
167 ENA_FLAG_ONGOING_RESET,
168 ENA_FLAG_DEV_UP_BEFORE_RESET,
170 ENA_FLAGS_NUMBER = ENA_FLAG_RSS_ACTIVE
173 BITSET_DEFINE(_ena_state, ENA_FLAGS_NUMBER);
174 typedef struct _ena_state ena_state_t;
176 #define ENA_FLAG_ZERO(adapter) \
177 BIT_ZERO(ENA_FLAGS_NUMBER, &(adapter)->flags)
178 #define ENA_FLAG_ISSET(bit, adapter) \
179 BIT_ISSET(ENA_FLAGS_NUMBER, (bit), &(adapter)->flags)
180 #define ENA_FLAG_SET_ATOMIC(bit, adapter) \
181 BIT_SET_ATOMIC(ENA_FLAGS_NUMBER, (bit), &(adapter)->flags)
182 #define ENA_FLAG_CLEAR_ATOMIC(bit, adapter) \
183 BIT_CLR_ATOMIC(ENA_FLAGS_NUMBER, (bit), &(adapter)->flags)
190 typedef struct _ena_vendor_info_t {
197 /* Interrupt resources */
198 struct resource *res;
199 driver_filter_t *handler;
205 char name[ENA_IRQNAME_SIZE];
209 struct ena_adapter *adapter;
210 struct ena_ring *tx_ring;
211 struct ena_ring *rx_ring;
213 struct task cleanup_task;
214 struct taskqueue *cleanup_tq;
220 struct ena_calc_queue_size_ctx {
221 struct ena_com_dev_get_features_ctx *get_feat_ctx;
222 struct ena_com_dev *ena_dev;
224 uint32_t tx_queue_size;
225 uint32_t rx_queue_size;
226 uint32_t max_tx_queue_size;
227 uint32_t max_rx_queue_size;
228 uint16_t max_tx_sgl_size;
229 uint16_t max_rx_sgl_size;
233 struct ena_netmap_tx_info {
234 uint32_t socket_buf_idx[ENA_PKT_MAX_BUFS];
235 bus_dmamap_t map_seg[ENA_PKT_MAX_BUFS];
236 unsigned int sockets_used;
240 struct ena_tx_buffer {
242 /* # of ena desc for this specific mbuf
243 * (includes data desc and metadata desc) */
244 unsigned int tx_descs;
245 /* # of buffers used by this mbuf */
246 unsigned int num_of_bufs;
250 /* Used to detect missing tx packets */
251 struct bintime timestamp;
255 struct ena_netmap_tx_info nm_info;
256 #endif /* DEV_NETMAP */
258 struct ena_com_buf bufs[ENA_PKT_MAX_BUFS];
259 } __aligned(CACHE_LINE_SIZE);
261 struct ena_rx_buffer {
264 struct ena_com_buf ena_buf;
266 uint32_t netmap_buf_idx;
267 #endif /* DEV_NETMAP */
268 } __aligned(CACHE_LINE_SIZE);
270 struct ena_stats_tx {
273 counter_u64_t prepare_ctx_err;
274 counter_u64_t dma_mapping_err;
275 counter_u64_t doorbells;
276 counter_u64_t missing_tx_comp;
277 counter_u64_t bad_req_id;
278 counter_u64_t collapse;
279 counter_u64_t collapse_err;
280 counter_u64_t queue_wakeup;
281 counter_u64_t queue_stop;
282 counter_u64_t llq_buffer_copy;
285 struct ena_stats_rx {
288 counter_u64_t refil_partial;
289 counter_u64_t bad_csum;
290 counter_u64_t mjum_alloc_fail;
291 counter_u64_t mbuf_alloc_fail;
292 counter_u64_t dma_mapping_err;
293 counter_u64_t bad_desc_num;
294 counter_u64_t bad_req_id;
295 counter_u64_t empty_rx_ring;
299 /* Holds the empty requests for TX/RX out of order completions */
301 uint16_t *free_tx_ids;
302 uint16_t *free_rx_ids;
304 struct ena_com_dev *ena_dev;
305 struct ena_adapter *adapter;
306 struct ena_com_io_cq *ena_com_io_cq;
307 struct ena_com_io_sq *ena_com_io_sq;
311 /* Determines if device will use LLQ or normal mode for TX */
312 enum ena_admin_placement_policy_type tx_mem_queue_type;
314 /* The maximum length the driver can push to the device (For LLQ) */
315 uint8_t tx_max_header_size;
316 /* The maximum (and default) mbuf size for the Rx descriptor. */
321 bool first_interrupt;
322 uint16_t no_interrupt_event_cnt;
324 struct ena_com_rx_buf_info ena_bufs[ENA_PKT_MAX_BUFS];
329 uint16_t next_to_use;
330 uint16_t next_to_clean;
333 struct ena_tx_buffer *tx_buffer_info; /* contex of tx packet */
334 struct ena_rx_buffer *rx_buffer_info; /* contex of rx packet */
336 int ring_size; /* number of tx/rx_buffer_info's entries */
338 struct buf_ring *br; /* only for TX */
339 uint32_t buf_ring_size;
345 struct task enqueue_task;
346 struct taskqueue *enqueue_tq;
350 struct ena_stats_tx tx_stats;
351 struct ena_stats_rx rx_stats;
356 /* For Tx ring to indicate if it's running or not */
360 /* How many packets are sent in one Tx loop, used for doorbells */
364 uint8_t *push_buf_intermediate_buf;
368 #endif /* DEV_NETMAP */
369 } __aligned(CACHE_LINE_SIZE);
371 struct ena_stats_dev {
372 counter_u64_t wd_expired;
373 counter_u64_t interface_up;
374 counter_u64_t interface_down;
375 counter_u64_t admin_q_pause;
378 struct ena_hw_stats {
379 counter_u64_t rx_packets;
380 counter_u64_t tx_packets;
382 counter_u64_t rx_bytes;
383 counter_u64_t tx_bytes;
385 counter_u64_t rx_drops;
386 counter_u64_t tx_drops;
389 /* Board specific private data structure */
391 struct ena_com_dev *ena_dev;
393 /* OS defined structs */
396 struct ifmedia media;
399 struct resource *memory;
400 struct resource *registers;
402 struct sx global_lock;
405 struct msix_entry *msix_entries;
408 /* DMA tags used throughout the driver adapter for Tx and Rx */
409 bus_dma_tag_t tx_buf_tag;
410 bus_dma_tag_t rx_buf_tag;
415 uint32_t num_io_queues;
416 uint32_t max_num_io_queues;
418 uint32_t requested_tx_ring_size;
419 uint32_t requested_rx_ring_size;
421 uint32_t max_tx_ring_size;
422 uint32_t max_rx_ring_size;
424 uint16_t max_tx_sgl_size;
425 uint16_t max_rx_sgl_size;
427 uint32_t tx_offload_cap;
429 uint32_t buf_ring_size;
432 uint8_t rss_ind_tbl[ENA_RX_RSS_TABLE_SIZE];
434 uint8_t mac_addr[ETHER_ADDR_LEN];
439 /* Queue will represent one TX and one RX ring */
440 struct ena_que que[ENA_MAX_NUM_IO_QUEUES]
441 __aligned(CACHE_LINE_SIZE);
444 struct ena_ring tx_ring[ENA_MAX_NUM_IO_QUEUES]
445 __aligned(CACHE_LINE_SIZE);
448 struct ena_ring rx_ring[ENA_MAX_NUM_IO_QUEUES]
449 __aligned(CACHE_LINE_SIZE);
451 struct ena_irq irq_tbl[ENA_MAX_MSIX_VEC(ENA_MAX_NUM_IO_QUEUES)];
454 struct callout timer_service;
455 sbintime_t keep_alive_timestamp;
456 uint32_t next_monitored_tx_qid;
457 struct task reset_task;
458 struct taskqueue *reset_tq;
460 sbintime_t keep_alive_timeout;
461 sbintime_t missing_tx_timeout;
462 uint32_t missing_tx_max_queues;
463 uint32_t missing_tx_threshold;
464 bool disable_meta_caching;
467 struct ena_stats_dev dev_stats;
468 struct ena_hw_stats hw_stats;
470 enum ena_regs_reset_reason_types reset_reason;
473 #define ENA_RING_MTX_LOCK(_ring) mtx_lock(&(_ring)->ring_mtx)
474 #define ENA_RING_MTX_TRYLOCK(_ring) mtx_trylock(&(_ring)->ring_mtx)
475 #define ENA_RING_MTX_UNLOCK(_ring) mtx_unlock(&(_ring)->ring_mtx)
477 #define ENA_LOCK_INIT(adapter) \
478 sx_init(&(adapter)->global_lock, "ENA global lock")
479 #define ENA_LOCK_DESTROY(adapter) sx_destroy(&(adapter)->global_lock)
480 #define ENA_LOCK_LOCK(adapter) sx_xlock(&(adapter)->global_lock)
481 #define ENA_LOCK_UNLOCK(adapter) sx_unlock(&(adapter)->global_lock)
483 #define clamp_t(type, _x, min, max) min_t(type, max_t(type, _x, min), max)
484 #define clamp_val(val, lo, hi) clamp_t(__typeof(val), val, lo, hi)
486 static inline int ena_mbuf_count(struct mbuf *mbuf)
490 while ((mbuf = mbuf->m_next) != NULL)
496 int ena_up(struct ena_adapter *adapter);
497 void ena_down(struct ena_adapter *adapter);
498 int ena_restore_device(struct ena_adapter *adapter);
499 void ena_destroy_device(struct ena_adapter *adapter, bool graceful);
500 int ena_refill_rx_bufs(struct ena_ring *rx_ring, uint32_t num);
501 int ena_update_buf_ring_size(struct ena_adapter *adapter,
502 uint32_t new_buf_ring_size);
503 int ena_update_queue_size(struct ena_adapter *adapter, uint32_t new_tx_size,
504 uint32_t new_rx_size);
505 int ena_update_io_queue_nb(struct ena_adapter *adapter, uint32_t new_num);
508 ena_trigger_reset(struct ena_adapter *adapter,
509 enum ena_regs_reset_reason_types reset_reason)
511 if (likely(!ENA_FLAG_ISSET(ENA_FLAG_TRIGGER_RESET, adapter))) {
512 adapter->reset_reason = reset_reason;
513 ENA_FLAG_SET_ATOMIC(ENA_FLAG_TRIGGER_RESET, adapter);
517 #endif /* !(ENA_H) */