4 * Copyright (c) 2015-2017 Amazon.com, Inc. or its affiliates.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
19 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
21 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
22 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
23 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
24 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
28 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 #include <sys/types.h>
39 #include "ena-com/ena_com.h"
40 #include "ena-com/ena_eth_com.h"
42 #define DRV_MODULE_VER_MAJOR 0
43 #define DRV_MODULE_VER_MINOR 7
44 #define DRV_MODULE_VER_SUBMINOR 0
46 #define DRV_MODULE_NAME "ena"
48 #ifndef DRV_MODULE_VERSION
49 #define DRV_MODULE_VERSION \
50 __XSTRING(DRV_MODULE_VER_MAJOR) "." \
51 __XSTRING(DRV_MODULE_VER_MINOR) "." \
52 __XSTRING(DRV_MODULE_VER_SUBMINOR)
54 #define DEVICE_NAME "Elastic Network Adapter (ENA)"
55 #define DEVICE_DESC "ENA adapter"
57 /* Calculate DMA mask - width for ena cannot exceed 48, so it is safe */
58 #define ENA_DMA_BIT_MASK(x) ((1ULL << (x)) - 1ULL)
60 /* 1 for AENQ + ADMIN */
61 #define ENA_MAX_MSIX_VEC(io_queues) (1 + (io_queues))
66 #define ENA_BUS_DMA_SEGS 32
68 #define ENA_DEFAULT_RING_SIZE 1024
69 #define ENA_DEFAULT_SMALL_PACKET_LEN 128
70 #define ENA_DEFAULT_MAX_RX_BUFF_ALLOC_SIZE 1536
72 #define ENA_RX_REFILL_THRESH_DEVIDER 8
74 #define ENA_MAX_PUSH_PKT_SIZE 128
76 #define ENA_NAME_MAX_LEN 20
77 #define ENA_IRQNAME_SIZE 40
79 #define ENA_PKT_MAX_BUFS 19
80 #define ENA_STALL_TIMEOUT 100
82 #define ENA_RX_RSS_TABLE_LOG_SIZE 7
83 #define ENA_RX_RSS_TABLE_SIZE (1 << ENA_RX_RSS_TABLE_LOG_SIZE)
85 #define ENA_HASH_KEY_SIZE 40
87 #define ENA_DMA_BITS_MASK 40
88 #define ENA_MAX_FRAME_LEN 10000
89 #define ENA_MIN_FRAME_LEN 60
90 #define ENA_RX_HASH_KEY_NUM 10
91 #define ENA_RX_THASH_TABLE_SIZE (1 << 8)
93 #define ENA_TX_CLEANUP_TRESHOLD 128
95 #define DB_THRESHOLD 64
99 * TX budget for cleaning. It should be half of the RX budget to reduce amount
100 * of TCP retransmissions.
102 #define TX_BUDGET 128
103 /* RX cleanup budget. -1 stands for infinity. */
104 #define RX_BUDGET 256
106 * How many times we can repeat cleanup in the io irq handling routine if the
107 * RX or TX budget was depleted.
109 #define CLEAN_BUDGET 8
111 #define RX_IRQ_INTERVAL 20
112 #define TX_IRQ_INTERVAL 50
114 #define ENA_MAX_MTU 9216
115 #define ENA_TSO_MAXSIZE 65536
116 #define ENA_TSO_NSEGS ENA_PKT_MAX_BUFS
117 #define ENA_RX_OFFSET NET_SKB_PAD + NET_IP_ALIGN
119 #define ENA_MMIO_DISABLE_REG_READ BIT(0)
121 #define ENA_TX_RING_IDX_NEXT(idx, ring_size) (((idx) + 1) & ((ring_size) - 1))
123 #define ENA_RX_RING_IDX_NEXT(idx, ring_size) (((idx) + 1) & ((ring_size) - 1))
124 #define ENA_RX_RING_IDX_ADD(idx, n, ring_size) \
125 (((idx) + (n)) & ((ring_size) - 1))
127 #define ENA_IO_TXQ_IDX(q) (2 * (q))
128 #define ENA_IO_RXQ_IDX(q) (2 * (q) + 1)
130 #define ENA_MGMNT_IRQ_IDX 0
131 #define ENA_IO_IRQ_FIRST_IDX 1
132 #define ENA_IO_IRQ_IDX(q) (ENA_IO_IRQ_FIRST_IDX + (q))
135 * ENA device should send keep alive msg every 1 sec.
136 * We wait for 6 sec just to be on the safe side.
138 #define DEFAULT_KEEP_ALIVE_TO (SBT_1S * 6)
140 /* Time in jiffies before concluding the transmitter is hung. */
141 #define DEFAULT_TX_CMP_TO (SBT_1S * 5)
143 /* Number of queues to check for missing queues per timer tick */
144 #define DEFAULT_TX_MONITORED_QUEUES (4)
146 /* Max number of timeouted packets before device reset */
147 #define DEFAULT_TX_CMP_THRESHOLD (128)
150 * Supported PCI vendor and devices IDs
152 #define PCI_VENDOR_ID_AMAZON 0x1d0f
154 #define PCI_DEV_ID_ENA_PF 0x0ec2
155 #define PCI_DEV_ID_ENA_LLQ_PF 0x1ec2
156 #define PCI_DEV_ID_ENA_VF 0xec20
157 #define PCI_DEV_ID_ENA_LLQ_VF 0xec21
164 typedef struct _ena_vendor_info_t {
165 unsigned int vendor_id;
166 unsigned int device_id;
171 /* Interrupt resources */
172 struct resource *res;
173 driver_intr_t *handler;
179 char name[ENA_IRQNAME_SIZE];
183 struct ena_adapter *adapter;
184 struct ena_ring *tx_ring;
185 struct ena_ring *rx_ring;
190 struct ena_tx_buffer {
192 /* # of ena desc for this specific mbuf
193 * (includes data desc and metadata desc) */
194 unsigned int tx_descs;
195 /* # of buffers used by this mbuf */
196 unsigned int num_of_bufs;
199 /* Used to detect missing tx packets */
200 struct bintime timestamp;
203 struct ena_com_buf bufs[ENA_PKT_MAX_BUFS];
204 } __aligned(CACHE_LINE_SIZE);
206 struct ena_rx_buffer {
209 struct ena_com_buf ena_buf;
210 } __aligned(CACHE_LINE_SIZE);
213 struct ena_stats_tx {
216 counter_u64_t queue_stop;
217 counter_u64_t prepare_ctx_err;
218 counter_u64_t queue_wakeup;
219 counter_u64_t dma_mapping_err;
221 counter_u64_t unsupported_desc_num;
223 counter_u64_t napi_comp;
225 counter_u64_t tx_poll;
226 counter_u64_t doorbells;
227 counter_u64_t missing_tx_comp;
228 counter_u64_t bad_req_id;
229 counter_u64_t collapse;
230 counter_u64_t collapse_err;
233 struct ena_stats_rx {
236 counter_u64_t refil_partial;
237 counter_u64_t bad_csum;
239 counter_u64_t page_alloc_fail;
240 counter_u64_t mbuf_alloc_fail;
241 counter_u64_t dma_mapping_err;
242 counter_u64_t bad_desc_num;
244 counter_u64_t small_copy_len_pkt;
249 /* Holds the empty requests for TX out of order completions */
250 uint16_t *free_tx_ids;
251 struct ena_com_dev *ena_dev;
252 struct ena_adapter *adapter;
253 struct ena_com_io_cq *ena_com_io_cq;
254 struct ena_com_io_sq *ena_com_io_sq;
256 /* The maximum length the driver can push to the device (For LLQ) */
257 enum ena_admin_placement_policy_type tx_mem_queue_type;
258 uint16_t rx_small_copy_len;
261 uint8_t tx_max_header_size;
263 struct ena_com_rx_buf_info ena_bufs[ENA_PKT_MAX_BUFS];
264 uint32_t smoothed_interval;
265 enum ena_intr_moder_level moder_tbl_idx;
270 uint16_t next_to_use;
271 uint16_t next_to_clean;
274 struct ena_tx_buffer *tx_buffer_info; /* contex of tx packet */
275 struct ena_rx_buffer *rx_buffer_info; /* contex of rx packet */
277 int ring_size; /* number of tx/rx_buffer_info's entries */
279 struct buf_ring *br; /* only for TX */
282 struct task enqueue_task;
283 struct taskqueue *enqueue_tq;
284 struct task cmpl_task;
285 struct taskqueue *cmpl_tq;
288 struct ena_stats_tx tx_stats;
289 struct ena_stats_rx rx_stats;
292 } __aligned(CACHE_LINE_SIZE);
294 struct ena_stats_dev {
296 counter_u64_t tx_timeout;
298 counter_u64_t io_suspend;
300 counter_u64_t io_resume;
302 counter_u64_t wd_expired;
303 counter_u64_t interface_up;
304 counter_u64_t interface_down;
306 counter_u64_t admin_q_pause;
309 struct ena_hw_stats {
319 /* Board specific private data structure */
321 struct ena_com_dev *ena_dev;
323 /* OS defined structs */
326 struct ifmedia media;
329 struct resource * memory;
330 struct resource * registers;
332 struct mtx global_mtx;
336 uint32_t msix_enabled;
337 struct msix_entry *msix_entries;
340 /* DMA tags used throughout the driver adapter for Tx and Rx */
341 bus_dma_tag_t tx_buf_tag;
342 bus_dma_tag_t rx_buf_tag;
345 * RX packets that shorter that this len will be copied to the skb
348 unsigned int small_copy_len;
350 uint16_t max_tx_sgl_size;
351 uint16_t max_rx_sgl_size;
353 uint32_t tx_offload_cap;
355 /* Tx fast path data */
358 unsigned int tx_usecs, rx_usecs; /* Interrupt coalescing */
360 unsigned int tx_ring_size;
361 unsigned int rx_ring_size;
364 uint8_t rss_ind_tbl[ENA_RX_RSS_TABLE_SIZE];
369 uint8_t mac_addr[ETHER_ADDR_LEN];
372 char name[ENA_NAME_MAX_LEN];
380 /* Queue will represent one TX and one RX ring */
381 struct ena_que que[ENA_MAX_NUM_IO_QUEUES]
382 __aligned(CACHE_LINE_SIZE);
385 struct ena_ring tx_ring[ENA_MAX_NUM_IO_QUEUES]
386 __aligned(CACHE_LINE_SIZE);
389 struct ena_ring rx_ring[ENA_MAX_NUM_IO_QUEUES]
390 __aligned(CACHE_LINE_SIZE);
392 struct ena_irq irq_tbl[ENA_MAX_MSIX_VEC(ENA_MAX_NUM_IO_QUEUES)];
395 struct callout timer_service;
396 sbintime_t keep_alive_timestamp;
397 uint32_t next_monitored_tx_qid;
398 struct task reset_task;
399 struct taskqueue *reset_tq;
401 sbintime_t keep_alive_timeout;
402 sbintime_t missing_tx_timeout;
403 uint32_t missing_tx_max_queues;
404 uint32_t missing_tx_threshold;
406 /* Task updating hw stats */
407 struct task stats_task;
408 struct taskqueue *stats_tq;
411 struct ena_stats_dev dev_stats;
412 struct ena_hw_stats hw_stats;
416 #define ENA_DEV_LOCK mtx_lock(&adapter->global_mtx)
417 #define ENA_DEV_UNLOCK mtx_unlock(&adapter->global_mtx)
419 #define ENA_RING_MTX_LOCK(_ring) mtx_lock(&(_ring)->ring_mtx)
420 #define ENA_RING_MTX_TRYLOCK(_ring) mtx_trylock(&(_ring)->ring_mtx)
421 #define ENA_RING_MTX_UNLOCK(_ring) mtx_unlock(&(_ring)->ring_mtx)
423 struct ena_dev *ena_efa_enadev_get(device_t pdev);
425 int ena_register_adapter(struct ena_adapter *adapter);
426 void ena_unregister_adapter(struct ena_adapter *adapter);
428 int ena_update_stats_counters(struct ena_adapter *adapter);
430 static inline int ena_mbuf_count(struct mbuf *mbuf)
434 while ((mbuf = mbuf->m_next) != NULL)
440 #endif /* !(ENA_H) */