4 * Copyright (c) 2015-2017 Amazon.com, Inc. or its affiliates.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
19 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
21 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
22 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
23 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
24 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
28 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 #include <sys/types.h>
39 #include "ena-com/ena_com.h"
40 #include "ena-com/ena_eth_com.h"
42 #define DRV_MODULE_VER_MAJOR 0
43 #define DRV_MODULE_VER_MINOR 8
44 #define DRV_MODULE_VER_SUBMINOR 1
46 #define DRV_MODULE_NAME "ena"
48 #ifndef DRV_MODULE_VERSION
49 #define DRV_MODULE_VERSION \
50 __XSTRING(DRV_MODULE_VER_MAJOR) "." \
51 __XSTRING(DRV_MODULE_VER_MINOR) "." \
52 __XSTRING(DRV_MODULE_VER_SUBMINOR)
54 #define DEVICE_NAME "Elastic Network Adapter (ENA)"
55 #define DEVICE_DESC "ENA adapter"
57 /* Calculate DMA mask - width for ena cannot exceed 48, so it is safe */
58 #define ENA_DMA_BIT_MASK(x) ((1ULL << (x)) - 1ULL)
60 /* 1 for AENQ + ADMIN */
61 #define ENA_ADMIN_MSIX_VEC 1
62 #define ENA_MAX_MSIX_VEC(io_queues) (ENA_ADMIN_MSIX_VEC + (io_queues))
67 #define ENA_BUS_DMA_SEGS 32
69 #define ENA_DEFAULT_RING_SIZE 1024
71 #define ENA_RX_REFILL_THRESH_DIVIDER 8
73 #define ENA_IRQNAME_SIZE 40
75 #define ENA_PKT_MAX_BUFS 19
77 #define ENA_RX_RSS_TABLE_LOG_SIZE 7
78 #define ENA_RX_RSS_TABLE_SIZE (1 << ENA_RX_RSS_TABLE_LOG_SIZE)
80 #define ENA_HASH_KEY_SIZE 40
82 #define ENA_MAX_FRAME_LEN 10000
83 #define ENA_MIN_FRAME_LEN 60
85 #define ENA_TX_CLEANUP_THRESHOLD 128
87 #define DB_THRESHOLD 64
91 * TX budget for cleaning. It should be half of the RX budget to reduce amount
92 * of TCP retransmissions.
95 /* RX cleanup budget. -1 stands for infinity. */
98 * How many times we can repeat cleanup in the io irq handling routine if the
99 * RX or TX budget was depleted.
101 #define CLEAN_BUDGET 8
103 #define RX_IRQ_INTERVAL 20
104 #define TX_IRQ_INTERVAL 50
106 #define ENA_MIN_MTU 128
108 #define ENA_TSO_MAXSIZE 65536
110 #define ENA_MMIO_DISABLE_REG_READ BIT(0)
112 #define ENA_TX_RING_IDX_NEXT(idx, ring_size) (((idx) + 1) & ((ring_size) - 1))
114 #define ENA_RX_RING_IDX_NEXT(idx, ring_size) (((idx) + 1) & ((ring_size) - 1))
116 #define ENA_IO_TXQ_IDX(q) (2 * (q))
117 #define ENA_IO_RXQ_IDX(q) (2 * (q) + 1)
119 #define ENA_MGMNT_IRQ_IDX 0
120 #define ENA_IO_IRQ_FIRST_IDX 1
121 #define ENA_IO_IRQ_IDX(q) (ENA_IO_IRQ_FIRST_IDX + (q))
124 * ENA device should send keep alive msg every 1 sec.
125 * We wait for 6 sec just to be on the safe side.
127 #define DEFAULT_KEEP_ALIVE_TO (SBT_1S * 6)
129 /* Time in jiffies before concluding the transmitter is hung. */
130 #define DEFAULT_TX_CMP_TO (SBT_1S * 5)
132 /* Number of queues to check for missing queues per timer tick */
133 #define DEFAULT_TX_MONITORED_QUEUES (4)
135 /* Max number of timeouted packets before device reset */
136 #define DEFAULT_TX_CMP_THRESHOLD (128)
139 * Supported PCI vendor and devices IDs
141 #define PCI_VENDOR_ID_AMAZON 0x1d0f
143 #define PCI_DEV_ID_ENA_PF 0x0ec2
144 #define PCI_DEV_ID_ENA_LLQ_PF 0x1ec2
145 #define PCI_DEV_ID_ENA_VF 0xec20
146 #define PCI_DEV_ID_ENA_LLQ_VF 0xec21
153 typedef struct _ena_vendor_info_t {
160 /* Interrupt resources */
161 struct resource *res;
162 driver_intr_t *handler;
168 char name[ENA_IRQNAME_SIZE];
172 struct ena_adapter *adapter;
173 struct ena_ring *tx_ring;
174 struct ena_ring *rx_ring;
179 struct ena_tx_buffer {
181 /* # of ena desc for this specific mbuf
182 * (includes data desc and metadata desc) */
183 unsigned int tx_descs;
184 /* # of buffers used by this mbuf */
185 unsigned int num_of_bufs;
188 /* Used to detect missing tx packets */
189 struct bintime timestamp;
192 struct ena_com_buf bufs[ENA_PKT_MAX_BUFS];
193 } __aligned(CACHE_LINE_SIZE);
195 struct ena_rx_buffer {
198 struct ena_com_buf ena_buf;
199 } __aligned(CACHE_LINE_SIZE);
201 struct ena_stats_tx {
204 counter_u64_t prepare_ctx_err;
205 counter_u64_t dma_mapping_err;
206 counter_u64_t doorbells;
207 counter_u64_t missing_tx_comp;
208 counter_u64_t bad_req_id;
209 counter_u64_t collapse;
210 counter_u64_t collapse_err;
213 struct ena_stats_rx {
216 counter_u64_t refil_partial;
217 counter_u64_t bad_csum;
218 counter_u64_t mjum_alloc_fail;
219 counter_u64_t mbuf_alloc_fail;
220 counter_u64_t dma_mapping_err;
221 counter_u64_t bad_desc_num;
222 counter_u64_t bad_req_id;
223 counter_u64_t empty_rx_ring;
227 /* Holds the empty requests for TX/RX out of order completions */
229 uint16_t *free_tx_ids;
230 uint16_t *free_rx_ids;
232 struct ena_com_dev *ena_dev;
233 struct ena_adapter *adapter;
234 struct ena_com_io_cq *ena_com_io_cq;
235 struct ena_com_io_sq *ena_com_io_sq;
239 /* Determines if device will use LLQ or normal mode for TX */
240 enum ena_admin_placement_policy_type tx_mem_queue_type;
241 /* The maximum length the driver can push to the device (For LLQ) */
242 uint8_t tx_max_header_size;
244 struct ena_com_rx_buf_info ena_bufs[ENA_PKT_MAX_BUFS];
247 * Fields used for Adaptive Interrupt Modulation - to be implemented in
248 * the future releases
250 uint32_t smoothed_interval;
251 enum ena_intr_moder_level moder_tbl_idx;
256 uint16_t next_to_use;
257 uint16_t next_to_clean;
260 struct ena_tx_buffer *tx_buffer_info; /* contex of tx packet */
261 struct ena_rx_buffer *rx_buffer_info; /* contex of rx packet */
263 int ring_size; /* number of tx/rx_buffer_info's entries */
265 struct buf_ring *br; /* only for TX */
272 struct task enqueue_task;
273 struct taskqueue *enqueue_tq;
276 struct task cmpl_task;
277 struct taskqueue *cmpl_tq;
282 struct ena_stats_tx tx_stats;
283 struct ena_stats_rx rx_stats;
287 } __aligned(CACHE_LINE_SIZE);
289 struct ena_stats_dev {
290 counter_u64_t wd_expired;
291 counter_u64_t interface_up;
292 counter_u64_t interface_down;
293 counter_u64_t admin_q_pause;
296 struct ena_hw_stats {
297 counter_u64_t rx_packets;
298 counter_u64_t tx_packets;
300 counter_u64_t rx_bytes;
301 counter_u64_t tx_bytes;
303 counter_u64_t rx_drops;
306 /* Board specific private data structure */
308 struct ena_com_dev *ena_dev;
310 /* OS defined structs */
313 struct ifmedia media;
316 struct resource *memory;
317 struct resource *registers;
319 struct mtx global_mtx;
323 uint32_t msix_enabled;
324 struct msix_entry *msix_entries;
327 /* DMA tags used throughout the driver adapter for Tx and Rx */
328 bus_dma_tag_t tx_buf_tag;
329 bus_dma_tag_t rx_buf_tag;
334 uint16_t max_tx_sgl_size;
335 uint16_t max_rx_sgl_size;
337 uint32_t tx_offload_cap;
339 /* Tx fast path data */
342 unsigned int tx_ring_size;
343 unsigned int rx_ring_size;
346 uint8_t rss_ind_tbl[ENA_RX_RSS_TABLE_SIZE];
349 uint8_t mac_addr[ETHER_ADDR_LEN];
357 /* Queue will represent one TX and one RX ring */
358 struct ena_que que[ENA_MAX_NUM_IO_QUEUES]
359 __aligned(CACHE_LINE_SIZE);
362 struct ena_ring tx_ring[ENA_MAX_NUM_IO_QUEUES]
363 __aligned(CACHE_LINE_SIZE);
366 struct ena_ring rx_ring[ENA_MAX_NUM_IO_QUEUES]
367 __aligned(CACHE_LINE_SIZE);
369 struct ena_irq irq_tbl[ENA_MAX_MSIX_VEC(ENA_MAX_NUM_IO_QUEUES)];
372 struct callout timer_service;
373 sbintime_t keep_alive_timestamp;
374 uint32_t next_monitored_tx_qid;
375 struct task reset_task;
376 struct taskqueue *reset_tq;
378 sbintime_t keep_alive_timeout;
379 sbintime_t missing_tx_timeout;
380 uint32_t missing_tx_max_queues;
381 uint32_t missing_tx_threshold;
384 struct ena_stats_dev dev_stats;
385 struct ena_hw_stats hw_stats;
387 enum ena_regs_reset_reason_types reset_reason;
390 #define ENA_RING_MTX_LOCK(_ring) mtx_lock(&(_ring)->ring_mtx)
391 #define ENA_RING_MTX_TRYLOCK(_ring) mtx_trylock(&(_ring)->ring_mtx)
392 #define ENA_RING_MTX_UNLOCK(_ring) mtx_unlock(&(_ring)->ring_mtx)
394 static inline int ena_mbuf_count(struct mbuf *mbuf)
398 while ((mbuf = mbuf->m_next) != NULL)
404 #endif /* !(ENA_H) */