4 * Copyright (c) 2015-2020 Amazon.com, Inc. or its affiliates.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
19 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
21 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
22 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
23 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
24 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
28 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
34 #include "ena_datapath.h"
36 #include "ena_netmap.h"
37 #endif /* DEV_NETMAP */
39 /*********************************************************************
40 * Static functions prototypes
41 *********************************************************************/
43 static int ena_tx_cleanup(struct ena_ring *);
44 static int ena_rx_cleanup(struct ena_ring *);
45 static inline int validate_tx_req_id(struct ena_ring *, uint16_t);
46 static void ena_rx_hash_mbuf(struct ena_ring *, struct ena_com_rx_ctx *,
48 static struct mbuf* ena_rx_mbuf(struct ena_ring *, struct ena_com_rx_buf_info *,
49 struct ena_com_rx_ctx *, uint16_t *);
50 static inline void ena_rx_checksum(struct ena_ring *, struct ena_com_rx_ctx *,
52 static void ena_tx_csum(struct ena_com_tx_ctx *, struct mbuf *, bool);
53 static int ena_check_and_collapse_mbuf(struct ena_ring *tx_ring,
55 static int ena_xmit_mbuf(struct ena_ring *, struct mbuf **);
56 static void ena_start_xmit(struct ena_ring *);
58 /*********************************************************************
60 *********************************************************************/
63 ena_cleanup(void *arg, int pending)
65 struct ena_que *que = arg;
66 struct ena_adapter *adapter = que->adapter;
67 if_t ifp = adapter->ifp;
68 struct ena_ring *tx_ring;
69 struct ena_ring *rx_ring;
70 struct ena_com_io_cq* io_cq;
71 struct ena_eth_io_intr_reg intr_reg;
75 if (unlikely((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0))
78 ena_trace(ENA_DBG, "MSI-X TX/RX routine\n");
80 tx_ring = que->tx_ring;
81 rx_ring = que->rx_ring;
83 ena_qid = ENA_IO_TXQ_IDX(qid);
84 io_cq = &adapter->ena_dev->io_cq_queues[ena_qid];
86 tx_ring->first_interrupt = true;
87 rx_ring->first_interrupt = true;
89 for (i = 0; i < CLEAN_BUDGET; ++i) {
90 rxc = ena_rx_cleanup(rx_ring);
91 txc = ena_tx_cleanup(tx_ring);
93 if (unlikely((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0))
96 if ((txc != TX_BUDGET) && (rxc != RX_BUDGET))
100 /* Signal that work is done and unmask interrupt */
101 ena_com_update_intr_reg(&intr_reg,
105 ena_com_unmask_intr(io_cq, &intr_reg);
109 ena_deferred_mq_start(void *arg, int pending)
111 struct ena_ring *tx_ring = (struct ena_ring *)arg;
112 struct ifnet *ifp = tx_ring->adapter->ifp;
114 while (!drbr_empty(ifp, tx_ring->br) &&
116 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) {
117 ENA_RING_MTX_LOCK(tx_ring);
118 ena_start_xmit(tx_ring);
119 ENA_RING_MTX_UNLOCK(tx_ring);
124 ena_mq_start(if_t ifp, struct mbuf *m)
126 struct ena_adapter *adapter = ifp->if_softc;
127 struct ena_ring *tx_ring;
128 int ret, is_drbr_empty;
131 if (unlikely((if_getdrvflags(adapter->ifp) & IFF_DRV_RUNNING) == 0))
134 /* Which queue to use */
136 * If everything is setup correctly, it should be the
137 * same bucket that the current CPU we're on is.
138 * It should improve performance.
140 if (M_HASHTYPE_GET(m) != M_HASHTYPE_NONE) {
141 i = m->m_pkthdr.flowid % adapter->num_io_queues;
143 i = curcpu % adapter->num_io_queues;
145 tx_ring = &adapter->tx_ring[i];
147 /* Check if drbr is empty before putting packet */
148 is_drbr_empty = drbr_empty(ifp, tx_ring->br);
149 ret = drbr_enqueue(ifp, tx_ring->br, m);
150 if (unlikely(ret != 0)) {
151 taskqueue_enqueue(tx_ring->enqueue_tq, &tx_ring->enqueue_task);
155 if (is_drbr_empty && (ENA_RING_MTX_TRYLOCK(tx_ring) != 0)) {
156 ena_start_xmit(tx_ring);
157 ENA_RING_MTX_UNLOCK(tx_ring);
159 taskqueue_enqueue(tx_ring->enqueue_tq, &tx_ring->enqueue_task);
168 struct ena_adapter *adapter = ifp->if_softc;
169 struct ena_ring *tx_ring = adapter->tx_ring;
172 for(i = 0; i < adapter->num_io_queues; ++i, ++tx_ring)
173 if (!drbr_empty(ifp, tx_ring->br)) {
174 ENA_RING_MTX_LOCK(tx_ring);
175 drbr_flush(ifp, tx_ring->br);
176 ENA_RING_MTX_UNLOCK(tx_ring);
182 /*********************************************************************
184 *********************************************************************/
187 validate_tx_req_id(struct ena_ring *tx_ring, uint16_t req_id)
189 struct ena_adapter *adapter = tx_ring->adapter;
190 struct ena_tx_buffer *tx_info = NULL;
192 if (likely(req_id < tx_ring->ring_size)) {
193 tx_info = &tx_ring->tx_buffer_info[req_id];
194 if (tx_info->mbuf != NULL)
196 device_printf(adapter->pdev,
197 "tx_info doesn't have valid mbuf\n");
200 device_printf(adapter->pdev, "Invalid req_id: %hu\n", req_id);
201 counter_u64_add(tx_ring->tx_stats.bad_req_id, 1);
203 /* Trigger device reset */
204 ena_trigger_reset(adapter, ENA_REGS_RESET_INV_TX_REQ_ID);
210 * ena_tx_cleanup - clear sent packets and corresponding descriptors
211 * @tx_ring: ring for which we want to clean packets
213 * Once packets are sent, we ask the device in a loop for no longer used
214 * descriptors. We find the related mbuf chain in a map (index in an array)
215 * and free it, then update ring state.
216 * This is performed in "endless" loop, updating ring pointers every
217 * TX_COMMIT. The first check of free descriptor is performed before the actual
218 * loop, then repeated at the loop end.
221 ena_tx_cleanup(struct ena_ring *tx_ring)
223 struct ena_adapter *adapter;
224 struct ena_com_io_cq* io_cq;
225 uint16_t next_to_clean;
228 unsigned int total_done = 0;
230 int commit = TX_COMMIT;
231 int budget = TX_BUDGET;
235 adapter = tx_ring->que->adapter;
236 ena_qid = ENA_IO_TXQ_IDX(tx_ring->que->id);
237 io_cq = &adapter->ena_dev->io_cq_queues[ena_qid];
238 next_to_clean = tx_ring->next_to_clean;
241 if (netmap_tx_irq(adapter->ifp, tx_ring->qid) != NM_IRQ_PASS)
243 #endif /* DEV_NETMAP */
246 struct ena_tx_buffer *tx_info;
249 rc = ena_com_tx_comp_req_id_get(io_cq, &req_id);
250 if (unlikely(rc != 0))
253 rc = validate_tx_req_id(tx_ring, req_id);
254 if (unlikely(rc != 0))
257 tx_info = &tx_ring->tx_buffer_info[req_id];
259 mbuf = tx_info->mbuf;
261 tx_info->mbuf = NULL;
262 bintime_clear(&tx_info->timestamp);
264 bus_dmamap_sync(adapter->tx_buf_tag, tx_info->dmamap,
265 BUS_DMASYNC_POSTWRITE);
266 bus_dmamap_unload(adapter->tx_buf_tag,
269 ena_trace(ENA_DBG | ENA_TXPTH, "tx: q %d mbuf %p completed\n",
274 total_done += tx_info->tx_descs;
276 tx_ring->free_tx_ids[next_to_clean] = req_id;
277 next_to_clean = ENA_TX_RING_IDX_NEXT(next_to_clean,
280 if (unlikely(--commit == 0)) {
282 /* update ring state every TX_COMMIT descriptor */
283 tx_ring->next_to_clean = next_to_clean;
285 &adapter->ena_dev->io_sq_queues[ena_qid],
287 ena_com_update_dev_comp_head(io_cq);
290 } while (likely(--budget));
292 work_done = TX_BUDGET - budget;
294 ena_trace(ENA_DBG | ENA_TXPTH, "tx: q %d done. total pkts: %d\n",
295 tx_ring->qid, work_done);
297 /* If there is still something to commit update ring state */
298 if (likely(commit != TX_COMMIT)) {
299 tx_ring->next_to_clean = next_to_clean;
300 ena_com_comp_ack(&adapter->ena_dev->io_sq_queues[ena_qid],
302 ena_com_update_dev_comp_head(io_cq);
306 * Need to make the rings circular update visible to
307 * ena_xmit_mbuf() before checking for tx_ring->running.
311 above_thresh = ena_com_sq_have_enough_space(tx_ring->ena_com_io_sq,
312 ENA_TX_RESUME_THRESH);
313 if (unlikely(!tx_ring->running && above_thresh)) {
314 ENA_RING_MTX_LOCK(tx_ring);
316 ena_com_sq_have_enough_space(tx_ring->ena_com_io_sq,
317 ENA_TX_RESUME_THRESH);
318 if (!tx_ring->running && above_thresh) {
319 tx_ring->running = true;
320 counter_u64_add(tx_ring->tx_stats.queue_wakeup, 1);
321 taskqueue_enqueue(tx_ring->enqueue_tq,
322 &tx_ring->enqueue_task);
324 ENA_RING_MTX_UNLOCK(tx_ring);
331 ena_rx_hash_mbuf(struct ena_ring *rx_ring, struct ena_com_rx_ctx *ena_rx_ctx,
334 struct ena_adapter *adapter = rx_ring->adapter;
336 if (likely(ENA_FLAG_ISSET(ENA_FLAG_RSS_ACTIVE, adapter))) {
337 mbuf->m_pkthdr.flowid = ena_rx_ctx->hash;
339 if (ena_rx_ctx->frag &&
340 (ena_rx_ctx->l3_proto != ENA_ETH_IO_L3_PROTO_UNKNOWN)) {
341 M_HASHTYPE_SET(mbuf, M_HASHTYPE_OPAQUE_HASH);
345 switch (ena_rx_ctx->l3_proto) {
346 case ENA_ETH_IO_L3_PROTO_IPV4:
347 switch (ena_rx_ctx->l4_proto) {
348 case ENA_ETH_IO_L4_PROTO_TCP:
349 M_HASHTYPE_SET(mbuf, M_HASHTYPE_RSS_TCP_IPV4);
351 case ENA_ETH_IO_L4_PROTO_UDP:
352 M_HASHTYPE_SET(mbuf, M_HASHTYPE_RSS_UDP_IPV4);
355 M_HASHTYPE_SET(mbuf, M_HASHTYPE_RSS_IPV4);
358 case ENA_ETH_IO_L3_PROTO_IPV6:
359 switch (ena_rx_ctx->l4_proto) {
360 case ENA_ETH_IO_L4_PROTO_TCP:
361 M_HASHTYPE_SET(mbuf, M_HASHTYPE_RSS_TCP_IPV6);
363 case ENA_ETH_IO_L4_PROTO_UDP:
364 M_HASHTYPE_SET(mbuf, M_HASHTYPE_RSS_UDP_IPV6);
367 M_HASHTYPE_SET(mbuf, M_HASHTYPE_RSS_IPV6);
370 case ENA_ETH_IO_L3_PROTO_UNKNOWN:
371 M_HASHTYPE_SET(mbuf, M_HASHTYPE_NONE);
374 M_HASHTYPE_SET(mbuf, M_HASHTYPE_OPAQUE_HASH);
377 mbuf->m_pkthdr.flowid = rx_ring->qid;
378 M_HASHTYPE_SET(mbuf, M_HASHTYPE_NONE);
383 * ena_rx_mbuf - assemble mbuf from descriptors
384 * @rx_ring: ring for which we want to clean packets
385 * @ena_bufs: buffer info
386 * @ena_rx_ctx: metadata for this packet(s)
387 * @next_to_clean: ring pointer, will be updated only upon success
391 ena_rx_mbuf(struct ena_ring *rx_ring, struct ena_com_rx_buf_info *ena_bufs,
392 struct ena_com_rx_ctx *ena_rx_ctx, uint16_t *next_to_clean)
395 struct ena_rx_buffer *rx_info;
396 struct ena_adapter *adapter;
397 unsigned int descs = ena_rx_ctx->descs;
399 uint16_t ntc, len, req_id, buf = 0;
401 ntc = *next_to_clean;
402 adapter = rx_ring->adapter;
404 len = ena_bufs[buf].len;
405 req_id = ena_bufs[buf].req_id;
406 rc = validate_rx_req_id(rx_ring, req_id);
407 if (unlikely(rc != 0))
410 rx_info = &rx_ring->rx_buffer_info[req_id];
411 if (unlikely(rx_info->mbuf == NULL)) {
412 device_printf(adapter->pdev, "NULL mbuf in rx_info");
416 ena_trace(ENA_DBG | ENA_RXPTH, "rx_info %p, mbuf %p, paddr %jx\n",
417 rx_info, rx_info->mbuf, (uintmax_t)rx_info->ena_buf.paddr);
419 bus_dmamap_sync(adapter->rx_buf_tag, rx_info->map,
420 BUS_DMASYNC_POSTREAD);
421 mbuf = rx_info->mbuf;
422 mbuf->m_flags |= M_PKTHDR;
423 mbuf->m_pkthdr.len = len;
425 mbuf->m_pkthdr.rcvif = rx_ring->que->adapter->ifp;
427 /* Fill mbuf with hash key and it's interpretation for optimization */
428 ena_rx_hash_mbuf(rx_ring, ena_rx_ctx, mbuf);
430 ena_trace(ENA_DBG | ENA_RXPTH, "rx mbuf 0x%p, flags=0x%x, len: %d\n",
431 mbuf, mbuf->m_flags, mbuf->m_pkthdr.len);
433 /* DMA address is not needed anymore, unmap it */
434 bus_dmamap_unload(rx_ring->adapter->rx_buf_tag, rx_info->map);
436 rx_info->mbuf = NULL;
437 rx_ring->free_rx_ids[ntc] = req_id;
438 ntc = ENA_RX_RING_IDX_NEXT(ntc, rx_ring->ring_size);
441 * While we have more than 1 descriptors for one rcvd packet, append
442 * other mbufs to the main one
446 len = ena_bufs[buf].len;
447 req_id = ena_bufs[buf].req_id;
448 rc = validate_rx_req_id(rx_ring, req_id);
449 if (unlikely(rc != 0)) {
451 * If the req_id is invalid, then the device will be
452 * reset. In that case we must free all mbufs that
453 * were already gathered.
458 rx_info = &rx_ring->rx_buffer_info[req_id];
460 if (unlikely(rx_info->mbuf == NULL)) {
461 device_printf(adapter->pdev, "NULL mbuf in rx_info");
463 * If one of the required mbufs was not allocated yet,
464 * we can break there.
465 * All earlier used descriptors will be reallocated
466 * later and not used mbufs can be reused.
467 * The next_to_clean pointer will not be updated in case
468 * of an error, so caller should advance it manually
469 * in error handling routine to keep it up to date
476 bus_dmamap_sync(adapter->rx_buf_tag, rx_info->map,
477 BUS_DMASYNC_POSTREAD);
478 if (unlikely(m_append(mbuf, len, rx_info->mbuf->m_data) == 0)) {
479 counter_u64_add(rx_ring->rx_stats.mbuf_alloc_fail, 1);
480 ena_trace(ENA_WARNING, "Failed to append Rx mbuf %p\n",
484 ena_trace(ENA_DBG | ENA_RXPTH,
485 "rx mbuf updated. len %d\n", mbuf->m_pkthdr.len);
487 /* Free already appended mbuf, it won't be useful anymore */
488 bus_dmamap_unload(rx_ring->adapter->rx_buf_tag, rx_info->map);
489 m_freem(rx_info->mbuf);
490 rx_info->mbuf = NULL;
492 rx_ring->free_rx_ids[ntc] = req_id;
493 ntc = ENA_RX_RING_IDX_NEXT(ntc, rx_ring->ring_size);
496 *next_to_clean = ntc;
502 * ena_rx_checksum - indicate in mbuf if hw indicated a good cksum
505 ena_rx_checksum(struct ena_ring *rx_ring, struct ena_com_rx_ctx *ena_rx_ctx,
509 /* if IP and error */
510 if (unlikely((ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV4) &&
511 ena_rx_ctx->l3_csum_err)) {
512 /* ipv4 checksum error */
513 mbuf->m_pkthdr.csum_flags = 0;
514 counter_u64_add(rx_ring->rx_stats.bad_csum, 1);
515 ena_trace(ENA_DBG, "RX IPv4 header checksum error\n");
520 if ((ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_TCP) ||
521 (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_UDP)) {
522 if (ena_rx_ctx->l4_csum_err) {
523 /* TCP/UDP checksum error */
524 mbuf->m_pkthdr.csum_flags = 0;
525 counter_u64_add(rx_ring->rx_stats.bad_csum, 1);
526 ena_trace(ENA_DBG, "RX L4 checksum error\n");
528 mbuf->m_pkthdr.csum_flags = CSUM_IP_CHECKED;
529 mbuf->m_pkthdr.csum_flags |= CSUM_IP_VALID;
535 * ena_rx_cleanup - handle rx irq
536 * @arg: ring for which irq is being handled
539 ena_rx_cleanup(struct ena_ring *rx_ring)
541 struct ena_adapter *adapter;
543 struct ena_com_rx_ctx ena_rx_ctx;
544 struct ena_com_io_cq* io_cq;
545 struct ena_com_io_sq* io_sq;
548 uint16_t next_to_clean;
549 uint32_t refill_required;
550 uint32_t refill_threshold;
551 uint32_t do_if_input = 0;
554 int budget = RX_BUDGET;
557 #endif /* DEV_NETMAP */
559 adapter = rx_ring->que->adapter;
561 qid = rx_ring->que->id;
562 ena_qid = ENA_IO_RXQ_IDX(qid);
563 io_cq = &adapter->ena_dev->io_cq_queues[ena_qid];
564 io_sq = &adapter->ena_dev->io_sq_queues[ena_qid];
565 next_to_clean = rx_ring->next_to_clean;
568 if (netmap_rx_irq(adapter->ifp, rx_ring->qid, &done) != NM_IRQ_PASS)
570 #endif /* DEV_NETMAP */
572 ena_trace(ENA_DBG, "rx: qid %d\n", qid);
575 ena_rx_ctx.ena_bufs = rx_ring->ena_bufs;
576 ena_rx_ctx.max_bufs = adapter->max_rx_sgl_size;
577 ena_rx_ctx.descs = 0;
578 bus_dmamap_sync(io_cq->cdesc_addr.mem_handle.tag,
579 io_cq->cdesc_addr.mem_handle.map, BUS_DMASYNC_POSTREAD);
580 rc = ena_com_rx_pkt(io_cq, io_sq, &ena_rx_ctx);
582 if (unlikely(rc != 0))
585 if (unlikely(ena_rx_ctx.descs == 0))
588 ena_trace(ENA_DBG | ENA_RXPTH, "rx: q %d got packet from ena. "
589 "descs #: %d l3 proto %d l4 proto %d hash: %x\n",
590 rx_ring->qid, ena_rx_ctx.descs, ena_rx_ctx.l3_proto,
591 ena_rx_ctx.l4_proto, ena_rx_ctx.hash);
593 /* Receive mbuf from the ring */
594 mbuf = ena_rx_mbuf(rx_ring, rx_ring->ena_bufs,
595 &ena_rx_ctx, &next_to_clean);
596 bus_dmamap_sync(io_cq->cdesc_addr.mem_handle.tag,
597 io_cq->cdesc_addr.mem_handle.map, BUS_DMASYNC_PREREAD);
598 /* Exit if we failed to retrieve a buffer */
599 if (unlikely(mbuf == NULL)) {
600 for (i = 0; i < ena_rx_ctx.descs; ++i) {
601 rx_ring->free_rx_ids[next_to_clean] =
602 rx_ring->ena_bufs[i].req_id;
604 ENA_RX_RING_IDX_NEXT(next_to_clean,
611 if (((ifp->if_capenable & IFCAP_RXCSUM) != 0) ||
612 ((ifp->if_capenable & IFCAP_RXCSUM_IPV6) != 0)) {
613 ena_rx_checksum(rx_ring, &ena_rx_ctx, mbuf);
617 counter_u64_add_protected(rx_ring->rx_stats.bytes,
619 counter_u64_add_protected(adapter->hw_stats.rx_bytes,
623 * LRO is only for IP/TCP packets and TCP checksum of the packet
624 * should be computed by hardware.
627 if (((ifp->if_capenable & IFCAP_LRO) != 0) &&
628 ((mbuf->m_pkthdr.csum_flags & CSUM_IP_VALID) != 0) &&
629 (ena_rx_ctx.l4_proto == ENA_ETH_IO_L4_PROTO_TCP)) {
631 * Send to the stack if:
632 * - LRO not enabled, or
633 * - no LRO resources, or
634 * - lro enqueue fails
636 if ((rx_ring->lro.lro_cnt != 0) &&
637 (tcp_lro_rx(&rx_ring->lro, mbuf, 0) == 0))
640 if (do_if_input != 0) {
641 ena_trace(ENA_DBG | ENA_RXPTH,
642 "calling if_input() with mbuf %p\n", mbuf);
643 (*ifp->if_input)(ifp, mbuf);
647 counter_u64_add_protected(rx_ring->rx_stats.cnt, 1);
648 counter_u64_add_protected(adapter->hw_stats.rx_packets, 1);
652 rx_ring->next_to_clean = next_to_clean;
654 refill_required = ena_com_free_q_entries(io_sq);
655 refill_threshold = min_t(int,
656 rx_ring->ring_size / ENA_RX_REFILL_THRESH_DIVIDER,
657 ENA_RX_REFILL_THRESH_PACKET);
659 if (refill_required > refill_threshold) {
660 ena_com_update_dev_comp_head(rx_ring->ena_com_io_cq);
661 ena_refill_rx_bufs(rx_ring, refill_required);
664 tcp_lro_flush_all(&rx_ring->lro);
666 return (RX_BUDGET - budget);
669 counter_u64_add(rx_ring->rx_stats.bad_desc_num, 1);
671 /* Too many desc from the device. Trigger reset */
672 ena_trigger_reset(adapter, ENA_REGS_RESET_TOO_MANY_RX_DESCS);
678 ena_tx_csum(struct ena_com_tx_ctx *ena_tx_ctx, struct mbuf *mbuf,
679 bool disable_meta_caching)
681 struct ena_com_tx_meta *ena_meta;
682 struct ether_vlan_header *eh;
683 struct mbuf *mbuf_next;
694 ena_meta = &ena_tx_ctx->ena_meta;
695 mss = mbuf->m_pkthdr.tso_segsz;
700 if ((mbuf->m_pkthdr.csum_flags & CSUM_TSO) != 0)
703 if ((mbuf->m_pkthdr.csum_flags & CSUM_OFFLOAD) != 0)
707 if (disable_meta_caching) {
708 memset(ena_meta, 0, sizeof(*ena_meta));
709 ena_tx_ctx->meta_valid = 1;
711 ena_tx_ctx->meta_valid = 0;
716 /* Determine where frame payload starts. */
717 eh = mtod(mbuf, struct ether_vlan_header *);
718 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
719 etype = ntohs(eh->evl_proto);
720 ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
722 etype = ntohs(eh->evl_encap_proto);
723 ehdrlen = ETHER_HDR_LEN;
726 mbuf_next = m_getptr(mbuf, ehdrlen, &offset);
727 ip = (struct ip *)(mtodo(mbuf_next, offset));
728 iphlen = ip->ip_hl << 2;
730 mbuf_next = m_getptr(mbuf, iphlen + ehdrlen, &offset);
731 th = (struct tcphdr *)(mtodo(mbuf_next, offset));
733 if ((mbuf->m_pkthdr.csum_flags & CSUM_IP) != 0) {
734 ena_tx_ctx->l3_csum_enable = 1;
736 if ((mbuf->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
737 ena_tx_ctx->tso_enable = 1;
738 ena_meta->l4_hdr_len = (th->th_off);
743 ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV4;
744 if ((ip->ip_off & htons(IP_DF)) != 0)
748 ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV6;
754 if (ip->ip_p == IPPROTO_TCP) {
755 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_TCP;
756 if ((mbuf->m_pkthdr.csum_flags &
757 (CSUM_IP_TCP | CSUM_IP6_TCP)) != 0)
758 ena_tx_ctx->l4_csum_enable = 1;
760 ena_tx_ctx->l4_csum_enable = 0;
761 } else if (ip->ip_p == IPPROTO_UDP) {
762 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UDP;
763 if ((mbuf->m_pkthdr.csum_flags &
764 (CSUM_IP_UDP | CSUM_IP6_UDP)) != 0)
765 ena_tx_ctx->l4_csum_enable = 1;
767 ena_tx_ctx->l4_csum_enable = 0;
769 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UNKNOWN;
770 ena_tx_ctx->l4_csum_enable = 0;
774 ena_meta->l3_hdr_len = iphlen;
775 ena_meta->l3_hdr_offset = ehdrlen;
776 ena_tx_ctx->meta_valid = 1;
780 ena_check_and_collapse_mbuf(struct ena_ring *tx_ring, struct mbuf **mbuf)
782 struct ena_adapter *adapter;
783 struct mbuf *collapsed_mbuf;
786 adapter = tx_ring->adapter;
787 num_frags = ena_mbuf_count(*mbuf);
789 /* One segment must be reserved for configuration descriptor. */
790 if (num_frags < adapter->max_tx_sgl_size)
792 counter_u64_add(tx_ring->tx_stats.collapse, 1);
794 collapsed_mbuf = m_collapse(*mbuf, M_NOWAIT,
795 adapter->max_tx_sgl_size - 1);
796 if (unlikely(collapsed_mbuf == NULL)) {
797 counter_u64_add(tx_ring->tx_stats.collapse_err, 1);
801 /* If mbuf was collapsed succesfully, original mbuf is released. */
802 *mbuf = collapsed_mbuf;
808 ena_tx_map_mbuf(struct ena_ring *tx_ring, struct ena_tx_buffer *tx_info,
809 struct mbuf *mbuf, void **push_hdr, u16 *header_len)
811 struct ena_adapter *adapter = tx_ring->adapter;
812 struct ena_com_buf *ena_buf;
813 bus_dma_segment_t segs[ENA_BUS_DMA_SEGS];
815 uint32_t mbuf_head_len;
819 mbuf_head_len = mbuf->m_len;
820 tx_info->mbuf = mbuf;
821 ena_buf = tx_info->bufs;
824 * For easier maintaining of the DMA map, map the whole mbuf even if
825 * the LLQ is used. The descriptors will be filled using the segments.
827 rc = bus_dmamap_load_mbuf_sg(adapter->tx_buf_tag, tx_info->dmamap, mbuf,
828 segs, &nsegs, BUS_DMA_NOWAIT);
829 if (unlikely((rc != 0) || (nsegs == 0))) {
830 ena_trace(ENA_WARNING,
831 "dmamap load failed! err: %d nsegs: %d\n", rc, nsegs);
835 if (tx_ring->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {
837 * When the device is LLQ mode, the driver will copy
838 * the header into the device memory space.
839 * the ena_com layer assumes the header is in a linear
841 * This assumption might be wrong since part of the header
842 * can be in the fragmented buffers.
843 * First check if header fits in the mbuf. If not, copy it to
844 * separate buffer that will be holding linearized data.
846 *header_len = min_t(uint32_t, mbuf->m_pkthdr.len, tx_ring->tx_max_header_size);
848 /* If header is in linear space, just point into mbuf's data. */
849 if (likely(*header_len <= mbuf_head_len)) {
850 *push_hdr = mbuf->m_data;
852 * Otherwise, copy whole portion of header from multiple mbufs
853 * to intermediate buffer.
856 m_copydata(mbuf, 0, *header_len, tx_ring->push_buf_intermediate_buf);
857 *push_hdr = tx_ring->push_buf_intermediate_buf;
859 counter_u64_add(tx_ring->tx_stats.llq_buffer_copy, 1);
862 ena_trace(ENA_DBG | ENA_TXPTH,
863 "mbuf: %p header_buf->vaddr: %p push_len: %d\n",
864 mbuf, *push_hdr, *header_len);
866 /* If packet is fitted in LLQ header, no need for DMA segments. */
867 if (mbuf->m_pkthdr.len <= tx_ring->tx_max_header_size) {
870 offset = tx_ring->tx_max_header_size;
872 * As Header part is mapped to LLQ header, we can skip it and just
873 * map the residuum of the mbuf to DMA Segments.
876 if (offset >= segs[iseg].ds_len) {
877 offset -= segs[iseg].ds_len;
879 ena_buf->paddr = segs[iseg].ds_addr + offset;
880 ena_buf->len = segs[iseg].ds_len - offset;
882 tx_info->num_of_bufs++;
891 * header_len is just a hint for the device. Because FreeBSD is not
892 * giving us information about packet header length and it is not
893 * guaranteed that all packet headers will be in the 1st mbuf, setting
894 * header_len to 0 is making the device ignore this value and resolve
895 * header on it's own.
900 /* Map rest of the mbuf */
901 while (iseg < nsegs) {
902 ena_buf->paddr = segs[iseg].ds_addr;
903 ena_buf->len = segs[iseg].ds_len;
906 tx_info->num_of_bufs++;
912 counter_u64_add(tx_ring->tx_stats.dma_mapping_err, 1);
913 tx_info->mbuf = NULL;
918 ena_xmit_mbuf(struct ena_ring *tx_ring, struct mbuf **mbuf)
920 struct ena_adapter *adapter;
921 struct ena_tx_buffer *tx_info;
922 struct ena_com_tx_ctx ena_tx_ctx;
923 struct ena_com_dev *ena_dev;
924 struct ena_com_io_sq* io_sq;
926 uint16_t next_to_use;
933 ena_qid = ENA_IO_TXQ_IDX(tx_ring->que->id);
934 adapter = tx_ring->que->adapter;
935 ena_dev = adapter->ena_dev;
936 io_sq = &ena_dev->io_sq_queues[ena_qid];
938 rc = ena_check_and_collapse_mbuf(tx_ring, mbuf);
939 if (unlikely(rc != 0)) {
940 ena_trace(ENA_WARNING,
941 "Failed to collapse mbuf! err: %d\n", rc);
945 ena_trace(ENA_DBG | ENA_TXPTH, "Tx: %d bytes\n", (*mbuf)->m_pkthdr.len);
947 next_to_use = tx_ring->next_to_use;
948 req_id = tx_ring->free_tx_ids[next_to_use];
949 tx_info = &tx_ring->tx_buffer_info[req_id];
950 tx_info->num_of_bufs = 0;
952 rc = ena_tx_map_mbuf(tx_ring, tx_info, *mbuf, &push_hdr, &header_len);
953 if (unlikely(rc != 0)) {
954 ena_trace(ENA_WARNING, "Failed to map TX mbuf\n");
957 memset(&ena_tx_ctx, 0x0, sizeof(struct ena_com_tx_ctx));
958 ena_tx_ctx.ena_bufs = tx_info->bufs;
959 ena_tx_ctx.push_header = push_hdr;
960 ena_tx_ctx.num_bufs = tx_info->num_of_bufs;
961 ena_tx_ctx.req_id = req_id;
962 ena_tx_ctx.header_len = header_len;
964 /* Set flags and meta data */
965 ena_tx_csum(&ena_tx_ctx, *mbuf, adapter->disable_meta_caching);
967 if (tx_ring->acum_pkts == DB_THRESHOLD ||
968 ena_com_is_doorbell_needed(tx_ring->ena_com_io_sq, &ena_tx_ctx)) {
969 ena_trace(ENA_DBG | ENA_TXPTH,
970 "llq tx max burst size of queue %d achieved, writing doorbell to send burst\n",
972 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
973 counter_u64_add(tx_ring->tx_stats.doorbells, 1);
974 tx_ring->acum_pkts = 0;
977 /* Prepare the packet's descriptors and send them to device */
978 rc = ena_com_prepare_tx(io_sq, &ena_tx_ctx, &nb_hw_desc);
979 if (unlikely(rc != 0)) {
980 if (likely(rc == ENA_COM_NO_MEM)) {
981 ena_trace(ENA_DBG | ENA_TXPTH,
982 "tx ring[%d] if out of space\n", tx_ring->que->id);
984 device_printf(adapter->pdev,
985 "failed to prepare tx bufs\n");
987 counter_u64_add(tx_ring->tx_stats.prepare_ctx_err, 1);
992 counter_u64_add_protected(tx_ring->tx_stats.cnt, 1);
993 counter_u64_add_protected(tx_ring->tx_stats.bytes,
994 (*mbuf)->m_pkthdr.len);
996 counter_u64_add_protected(adapter->hw_stats.tx_packets, 1);
997 counter_u64_add_protected(adapter->hw_stats.tx_bytes,
998 (*mbuf)->m_pkthdr.len);
1001 tx_info->tx_descs = nb_hw_desc;
1002 getbinuptime(&tx_info->timestamp);
1003 tx_info->print_once = true;
1005 tx_ring->next_to_use = ENA_TX_RING_IDX_NEXT(next_to_use,
1006 tx_ring->ring_size);
1008 /* stop the queue when no more space available, the packet can have up
1009 * to sgl_size + 2. one for the meta descriptor and one for header
1010 * (if the header is larger than tx_max_header_size).
1012 if (unlikely(!ena_com_sq_have_enough_space(tx_ring->ena_com_io_sq,
1013 adapter->max_tx_sgl_size + 2))) {
1014 ena_trace(ENA_DBG | ENA_TXPTH, "Stop queue %d\n",
1017 tx_ring->running = false;
1018 counter_u64_add(tx_ring->tx_stats.queue_stop, 1);
1020 /* There is a rare condition where this function decides to
1021 * stop the queue but meanwhile tx_cleanup() updates
1022 * next_to_completion and terminates.
1023 * The queue will remain stopped forever.
1024 * To solve this issue this function performs mb(), checks
1025 * the wakeup condition and wakes up the queue if needed.
1029 if (ena_com_sq_have_enough_space(tx_ring->ena_com_io_sq,
1030 ENA_TX_RESUME_THRESH)) {
1031 tx_ring->running = true;
1032 counter_u64_add(tx_ring->tx_stats.queue_wakeup, 1);
1036 bus_dmamap_sync(adapter->tx_buf_tag, tx_info->dmamap,
1037 BUS_DMASYNC_PREWRITE);
1042 tx_info->mbuf = NULL;
1043 bus_dmamap_unload(adapter->tx_buf_tag, tx_info->dmamap);
1049 ena_start_xmit(struct ena_ring *tx_ring)
1052 struct ena_adapter *adapter = tx_ring->adapter;
1053 struct ena_com_io_sq* io_sq;
1057 if (unlikely((if_getdrvflags(adapter->ifp) & IFF_DRV_RUNNING) == 0))
1060 if (unlikely(!ENA_FLAG_ISSET(ENA_FLAG_LINK_UP, adapter)))
1063 ena_qid = ENA_IO_TXQ_IDX(tx_ring->que->id);
1064 io_sq = &adapter->ena_dev->io_sq_queues[ena_qid];
1066 while ((mbuf = drbr_peek(adapter->ifp, tx_ring->br)) != NULL) {
1067 ena_trace(ENA_DBG | ENA_TXPTH, "\ndequeued mbuf %p with flags %#x and"
1068 " header csum flags %#jx\n",
1069 mbuf, mbuf->m_flags, (uint64_t)mbuf->m_pkthdr.csum_flags);
1071 if (unlikely(!tx_ring->running)) {
1072 drbr_putback(adapter->ifp, tx_ring->br, mbuf);
1076 if (unlikely((ret = ena_xmit_mbuf(tx_ring, &mbuf)) != 0)) {
1077 if (ret == ENA_COM_NO_MEM) {
1078 drbr_putback(adapter->ifp, tx_ring->br, mbuf);
1079 } else if (ret == ENA_COM_NO_SPACE) {
1080 drbr_putback(adapter->ifp, tx_ring->br, mbuf);
1083 drbr_advance(adapter->ifp, tx_ring->br);
1089 drbr_advance(adapter->ifp, tx_ring->br);
1091 if (unlikely((if_getdrvflags(adapter->ifp) &
1092 IFF_DRV_RUNNING) == 0))
1095 tx_ring->acum_pkts++;
1097 BPF_MTAP(adapter->ifp, mbuf);
1100 if (likely(tx_ring->acum_pkts != 0)) {
1101 /* Trigger the dma engine */
1102 ena_com_write_sq_doorbell(io_sq);
1103 counter_u64_add(tx_ring->tx_stats.doorbells, 1);
1104 tx_ring->acum_pkts = 0;
1107 if (unlikely(!tx_ring->running))
1108 taskqueue_enqueue(tx_ring->que->cleanup_tq,
1109 &tx_ring->que->cleanup_task);