2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2021 Alstom Group.
5 * Copyright (c) 2021 Semihalf.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
33 #include <sys/param.h>
35 #include <dev/enetc/enetc_hw.h>
38 struct enetc_rx_queue {
39 struct enetc_softc *sc;
42 union enetc_rx_bd *ring;
49 struct enetc_tx_queue {
50 struct enetc_softc *sc;
52 union enetc_tx_bd *ring;
61 struct enetc_ctrl_queue {
64 struct iflib_dma_info dma;
65 struct enetc_cbd *ring;
74 if_softc_ctx_t shared;
75 #define tx_num_queues shared->isc_ntxqsets
76 #define rx_num_queues shared->isc_nrxqsets
77 #define tx_queue_size shared->isc_ntxd[0]
78 #define rx_queue_size shared->isc_nrxd[0]
80 struct resource *regs;
84 struct enetc_tx_queue *tx_queues;
85 struct enetc_rx_queue *rx_queues;
86 struct enetc_ctrl_queue ctrl_queue;
88 /* Default RX queue configuration. */
91 * Hardware VLAN hash based filtering uses a 64bit bitmap.
92 * We need to know how many vids are in given position to
93 * know when to remove the bit from the bitmap.
95 #define VLAN_BITMAP_SIZE 64
96 uint8_t vlan_bitmap[64];
98 struct if_irq admin_irq;
101 struct ifmedia fixed_ifmedia;
105 #define ENETC_RD4(sc, reg) \
106 bus_read_4((sc)->regs, reg)
107 #define ENETC_WR4(sc, reg, value) \
108 bus_write_4((sc)->regs, reg, value)
110 #define ENETC_PORT_RD8(sc, reg) \
111 bus_read_8((sc)->regs, ENETC_PORT_BASE + (reg))
112 #define ENETC_PORT_RD4(sc, reg) \
113 bus_read_4((sc)->regs, ENETC_PORT_BASE + (reg))
114 #define ENETC_PORT_WR4(sc, reg, value) \
115 bus_write_4((sc)->regs, ENETC_PORT_BASE + (reg), value)
116 #define ENETC_PORT_RD2(sc, reg) \
117 bus_read_2((sc)->regs, ENETC_PORT_BASE + (reg))
118 #define ENETC_PORT_WR2(sc, reg, value) \
119 bus_write_2((sc)->regs, ENETC_PORT_BASE + (reg), value)
121 #define ENETC_TXQ_RD4(sc, q, reg) \
122 ENETC_RD4((sc), ENETC_BDR(TX, q, reg))
123 #define ENETC_TXQ_WR4(sc, q, reg, value) \
124 ENETC_WR4((sc), ENETC_BDR(TX, q, reg), value)
125 #define ENETC_RXQ_RD4(sc, q, reg) \
126 ENETC_RD4((sc), ENETC_BDR(RX, q, reg))
127 #define ENETC_RXQ_WR4(sc, q, reg, value) \
128 ENETC_WR4((sc), ENETC_BDR(RX, q, reg), value)
130 /* Device constants */
132 #define ENETC_MAX_FRAME_LEN 9600
134 #define ENETC_MAX_QUEUES 4
136 /* Max supported nr of descriptors per frame. */
137 #define ENETC_MAX_SCATTER 15
140 * Up to 4096 transmit/receive descriptors are supported,
141 * their number has to be a multple of 64.
143 #define ENETC_MIN_DESC 64
144 #define ENETC_MAX_DESC 4096
145 #define ENETC_DEFAULT_DESC 512
146 #define ENETC_DESC_ALIGN 64
148 /* Rings have to be 128B aligned. */
149 #define ENETC_RING_ALIGN 128
151 #define ENETC_MSIX_COUNT 32
153 #define ENETC_RX_INTR_PKT_THR 16
155 /* Rx threshold irq timeout, 100us */
156 #define ENETC_RX_INTR_TIME_THR ((100ULL * ENETC_CLK) / 1000000ULL)
158 #define ENETC_RX_IP_ALIGN 2