2 * Copyright (c) 2004 Scott Long
3 * Copyright (c) 2005 Marius Strobl <marius@FreeBSD.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 /* $NetBSD: esp_sbus.c,v 1.51 2009/09/17 16:28:12 tsutsui Exp $ */
32 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc.
33 * All rights reserved.
35 * This code is derived from software contributed to The NetBSD Foundation
36 * by Charles M. Hannum; Jason R. Thorpe of the Numerical Aerospace
37 * Simulation Facility, NASA Ames Research Center; Paul Kranenburg.
39 * Redistribution and use in source and binary forms, with or without
40 * modification, are permitted provided that the following conditions
42 * 1. Redistributions of source code must retain the above copyright
43 * notice, this list of conditions and the following disclaimer.
44 * 2. Redistributions in binary form must reproduce the above copyright
45 * notice, this list of conditions and the following disclaimer in the
46 * documentation and/or other materials provided with the distribution.
48 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
49 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
50 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
51 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
52 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
53 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
54 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
55 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
56 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
57 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
58 * POSSIBILITY OF SUCH DAMAGE.
61 #include <sys/cdefs.h>
62 __FBSDID("$FreeBSD$");
64 #include <sys/param.h>
65 #include <sys/systm.h>
67 #include <sys/kernel.h>
69 #include <sys/module.h>
70 #include <sys/mutex.h>
72 #include <dev/ofw/ofw_bus.h>
73 #include <dev/ofw/openfirm.h>
74 #include <machine/bus.h>
75 #include <machine/ofw_machdep.h>
76 #include <machine/resource.h>
80 #include <cam/cam_ccb.h>
81 #include <cam/scsi/scsi_all.h>
82 #include <cam/scsi/scsi_message.h>
84 #include <sparc64/sbus/lsi64854reg.h>
85 #include <sparc64/sbus/lsi64854var.h>
86 #include <sparc64/sbus/sbusvar.h>
88 #include <dev/esp/ncr53c9xreg.h>
89 #include <dev/esp/ncr53c9xvar.h>
91 /* #define ESP_SBUS_DEBUG */
94 struct ncr53c9x_softc sc_ncr53c9x; /* glue to MI code */
95 struct device *sc_dev;
97 struct resource *sc_res;
99 struct resource *sc_irqres;
102 struct lsi64854_softc *sc_dma; /* pointer to my DMA */
105 static devclass_t esp_devclass;
107 static int esp_probe(device_t);
108 static int esp_dma_attach(device_t);
109 static int esp_dma_detach(device_t);
110 static int esp_sbus_attach(device_t);
111 static int esp_sbus_detach(device_t);
112 static int esp_suspend(device_t);
113 static int esp_resume(device_t);
115 static device_method_t esp_dma_methods[] = {
116 DEVMETHOD(device_probe, esp_probe),
117 DEVMETHOD(device_attach, esp_dma_attach),
118 DEVMETHOD(device_detach, esp_dma_detach),
119 DEVMETHOD(device_suspend, esp_suspend),
120 DEVMETHOD(device_resume, esp_resume),
124 static driver_t esp_dma_driver = {
127 sizeof(struct esp_softc)
130 DRIVER_MODULE(esp, dma, esp_dma_driver, esp_devclass, 0, 0);
131 MODULE_DEPEND(esp, dma, 1, 1, 1);
133 static device_method_t esp_sbus_methods[] = {
134 DEVMETHOD(device_probe, esp_probe),
135 DEVMETHOD(device_attach, esp_sbus_attach),
136 DEVMETHOD(device_detach, esp_sbus_detach),
137 DEVMETHOD(device_suspend, esp_suspend),
138 DEVMETHOD(device_resume, esp_resume),
142 static driver_t esp_sbus_driver = {
145 sizeof(struct esp_softc)
148 DRIVER_MODULE(esp, sbus, esp_sbus_driver, esp_devclass, 0, 0);
149 MODULE_DEPEND(esp, sbus, 1, 1, 1);
152 * Functions and the switch for the MI code
154 static uint8_t esp_read_reg(struct ncr53c9x_softc *sc, int reg);
155 static void esp_write_reg(struct ncr53c9x_softc *sc, int reg, uint8_t v);
156 static int esp_dma_isintr(struct ncr53c9x_softc *sc);
157 static void esp_dma_reset(struct ncr53c9x_softc *sc);
158 static int esp_dma_intr(struct ncr53c9x_softc *sc);
159 static int esp_dma_setup(struct ncr53c9x_softc *sc, void **addr,
160 size_t *len, int datain, size_t *dmasize);
161 static void esp_dma_go(struct ncr53c9x_softc *sc);
162 static void esp_dma_stop(struct ncr53c9x_softc *sc);
163 static int esp_dma_isactive(struct ncr53c9x_softc *sc);
164 static int espattach(struct esp_softc *esc,
165 const struct ncr53c9x_glue *gluep);
166 static int espdetach(struct esp_softc *esc);
168 static const struct ncr53c9x_glue const esp_sbus_glue = {
178 NULL, /* gl_clear_latched_intr */
182 esp_probe(device_t dev)
186 name = ofw_bus_get_name(dev);
187 if (strcmp("SUNW,fas", name) == 0) {
188 device_set_desc(dev, "Sun FAS366 Fast-Wide SCSI");
189 return (BUS_PROBE_DEFAULT);
190 } else if (strcmp("esp", name) == 0) {
191 device_set_desc(dev, "Sun ESP SCSI/Sun FAS Fast-SCSI");
192 return (BUS_PROBE_DEFAULT);
199 esp_sbus_attach(device_t dev)
201 struct esp_softc *esc;
202 struct ncr53c9x_softc *sc;
203 struct lsi64854_softc *lsc;
205 int error, i, nchildren;
207 esc = device_get_softc(dev);
208 sc = &esc->sc_ncr53c9x;
212 sc->sc_freq = sbus_get_clockfreq(dev);
214 if (strcmp(ofw_bus_get_name(dev), "SUNW,fas") == 0) {
216 * Allocate space for DMA, in SUNW,fas there are no
217 * separate DMA devices.
219 lsc = malloc(sizeof (struct lsi64854_softc), M_DEVBUF,
222 device_printf(dev, "out of memory (lsi64854_softc)\n");
228 * SUNW,fas have 2 register spaces: DMA (lsi64854) and
229 * SCSI core (ncr53c9x).
232 /* Allocate DMA registers. */
234 if ((lsc->sc_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
235 &i, RF_ACTIVE)) == NULL) {
236 device_printf(dev, "cannot allocate DMA registers\n");
241 /* Create a parent DMA tag based on this bus. */
242 error = bus_dma_tag_create(
243 bus_get_dma_tag(dev), /* parent */
244 1, 0, /* alignment, boundary */
245 BUS_SPACE_MAXADDR, /* lowaddr */
246 BUS_SPACE_MAXADDR, /* highaddr */
247 NULL, NULL, /* filter, filterarg */
248 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
250 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
252 NULL, NULL, /* no locking */
253 &lsc->sc_parent_dmat);
255 device_printf(dev, "cannot allocate parent DMA tag\n");
259 i = sbus_get_burstsz(dev);
261 #ifdef ESP_SBUS_DEBUG
262 printf("%s: burst 0x%x\n", __func__, i);
265 lsc->sc_burst = (i & SBUS_BURST_32) ? 32 :
266 (i & SBUS_BURST_16) ? 16 : 0;
268 lsc->sc_channel = L64854_CHANNEL_SCSI;
273 * Allocate SCSI core registers.
276 if ((esc->sc_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
277 &i, RF_ACTIVE)) == NULL) {
279 "cannot allocate SCSI core registers\n");
281 goto fail_sbus_lpdma;
285 * Search accompanying DMA engine. It should have been
286 * already attached otherwise there isn't much we can do.
288 if (device_get_children(device_get_parent(dev), &children,
290 device_printf(dev, "cannot determine siblings\n");
293 for (i = 0; i < nchildren; i++) {
294 if (device_is_attached(children[i]) &&
295 sbus_get_slot(children[i]) == sbus_get_slot(dev) &&
296 strcmp(ofw_bus_get_name(children[i]), "dma") == 0) {
298 esc->sc_dma = (struct lsi64854_softc *)
299 device_get_softc(children[i]);
303 free(children, M_TEMP);
304 if (esc->sc_dma == NULL) {
305 device_printf(dev, "cannot find DMA engine\n");
308 esc->sc_dma->sc_client = sc;
311 * Allocate SCSI core registers.
314 if ((esc->sc_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
315 &i, RF_ACTIVE)) == NULL) {
317 "cannot allocate SCSI core registers\n");
322 error = espattach(esc, &esp_sbus_glue);
324 device_printf(dev, "espattach failed\n");
331 bus_release_resource(dev, SYS_RES_MEMORY, rman_get_rid(esc->sc_res),
333 if (strcmp(ofw_bus_get_name(dev), "SUNW,fas") != 0)
336 bus_dma_tag_destroy(lsc->sc_parent_dmat);
338 bus_release_resource(dev, SYS_RES_MEMORY, rman_get_rid(lsc->sc_res),
346 esp_sbus_detach(device_t dev)
348 struct esp_softc *esc;
349 struct lsi64854_softc *lsc;
352 esc = device_get_softc(dev);
355 error = espdetach(esc);
358 bus_release_resource(dev, SYS_RES_MEMORY, rman_get_rid(esc->sc_res),
360 if (strcmp(ofw_bus_get_name(dev), "SUNW,fas") != 0)
362 bus_dma_tag_destroy(lsc->sc_parent_dmat);
363 bus_release_resource(dev, SYS_RES_MEMORY, rman_get_rid(lsc->sc_res),
371 esp_dma_attach(device_t dev)
373 struct esp_softc *esc;
374 struct ncr53c9x_softc *sc;
377 esc = device_get_softc(dev);
378 sc = &esc->sc_ncr53c9x;
381 if (OF_getprop(ofw_bus_get_node(dev), "clock-frequency",
382 &sc->sc_freq, sizeof(sc->sc_freq)) == -1) {
383 printf("failed to query OFW for clock-frequency\n");
388 esc->sc_dma = (struct lsi64854_softc *)
389 device_get_softc(device_get_parent(dev));
390 esc->sc_dma->sc_client = sc;
393 * Allocate SCSI core registers.
396 if ((esc->sc_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
397 &i, RF_ACTIVE)) == NULL) {
398 device_printf(dev, "cannot allocate SCSI core registers\n");
402 error = espattach(esc, &esp_sbus_glue);
404 device_printf(dev, "espattach failed\n");
411 bus_release_resource(dev, SYS_RES_MEMORY, rman_get_rid(esc->sc_res),
417 esp_dma_detach(device_t dev)
419 struct esp_softc *esc;
422 esc = device_get_softc(dev);
424 error = espdetach(esc);
427 bus_release_resource(dev, SYS_RES_MEMORY, rman_get_rid(esc->sc_res),
434 esp_suspend(device_t dev)
441 esp_resume(device_t dev)
448 espattach(struct esp_softc *esc, const struct ncr53c9x_glue *gluep)
450 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x;
451 unsigned int uid = 0;
456 /* Attach the DMA engine. */
457 error = lsi64854_attach(esc->sc_dma);
459 device_printf(esc->sc_dev, "lsi64854_attach failed\n");
463 sc->sc_id = OF_getscsinitid(esc->sc_dev);
465 #ifdef ESP_SBUS_DEBUG
466 device_printf(esc->sc_dev, "%s: sc_id %d, freq %d\n",
467 __func__, sc->sc_id, sc->sc_freq);
471 * The `ESC' DMA chip must be reset before we can access
474 if (esc->sc_dma->sc_rev == DMAREV_ESC)
475 DMA_RESET(esc->sc_dma);
478 * Set up glue for MI code early; we use some of it here.
483 sc->sc_freq /= 1000000;
486 * XXX More of this should be in ncr53c9x_attach(), but
487 * XXX should we really poke around the chip that much in
488 * XXX the MI code? Think about this more...
492 * Read the part-unique ID code of the SCSI chip. The contained
493 * value is only valid if all of the following conditions are met:
494 * - After power-up or chip reset.
495 * - Before any value is written to this register.
496 * - The NCRCFG2_FE bit is set.
497 * - A (NCRCMD_NOP | NCRCMD_DMA) command has been issued.
499 NCRCMD(sc, NCRCMD_RSTCHIP);
500 NCRCMD(sc, NCRCMD_NOP);
501 sc->sc_cfg2 = NCRCFG2_FE;
502 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2);
503 NCRCMD(sc, NCRCMD_NOP | NCRCMD_DMA);
504 uid = NCR_READ_REG(sc, NCR_UID);
507 * It is necessary to try to load the 2nd config register here,
508 * to find out what rev the esp chip is, else the ncr53c9x_reset
509 * will not set up the defaults correctly.
511 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB;
512 NCR_WRITE_REG(sc, NCR_CFG1, sc->sc_cfg1);
514 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2);
515 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_RPE;
516 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2);
518 if ((NCR_READ_REG(sc, NCR_CFG2) & ~NCRCFG2_RSVD) !=
519 (NCRCFG2_SCSI2 | NCRCFG2_RPE)) {
520 sc->sc_rev = NCR_VARIANT_ESP100;
522 sc->sc_cfg2 = NCRCFG2_SCSI2;
523 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2);
525 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3);
526 sc->sc_cfg3 = (NCRCFG3_CDB | NCRCFG3_FCLK);
527 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3);
528 if (NCR_READ_REG(sc, NCR_CFG3) !=
529 (NCRCFG3_CDB | NCRCFG3_FCLK)) {
530 sc->sc_rev = NCR_VARIANT_ESP100A;
532 /* NCRCFG2_FE enables > 64K transfers. */
533 sc->sc_cfg2 |= NCRCFG2_FE;
535 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3);
536 if (sc->sc_freq <= 25)
537 sc->sc_rev = NCR_VARIANT_ESP200;
539 switch ((uid & 0xf8) >> 3) {
541 sc->sc_rev = NCR_VARIANT_FAS100A;
545 if ((uid & 0x07) == 0x02)
546 sc->sc_rev = NCR_VARIANT_FAS216;
548 sc->sc_rev = NCR_VARIANT_FAS236;
552 sc->sc_rev = NCR_VARIANT_FAS366;
557 * We could just treat unknown chips
558 * as ESP200 but then we would most
559 * likely drive them out of specs.
561 device_printf(esc->sc_dev,
569 #ifdef ESP_SBUS_DEBUG
570 printf("%s: revision %d, uid 0x%x\n", __func__, sc->sc_rev, uid);
574 * XXX minsync and maxxfer _should_ be set up in MI code,
575 * XXX but it appears to have some dependency on what sort
576 * XXX of DMA we're hooked up to, etc.
580 * This is the value used to start sync negotiations
581 * Note that the NCR register "SYNCTP" is programmed
582 * in "clocks per byte", and has a minimum value of 4.
583 * The SCSI period used in negotiation is one-fourth
584 * of the time (in nanoseconds) needed to transfer one byte.
585 * Since the chip's clock is given in MHz, we have the following
586 * formula: 4 * period = (1000 / freq) * 4
588 sc->sc_minsync = 1000 / sc->sc_freq;
590 sc->sc_maxoffset = 15;
591 sc->sc_extended_geom = 1;
594 * Alas, we must now modify the value a bit, because it's
595 * only valid when can switch on FASTCLK and FASTSCSI bits
596 * in config register 3...
598 switch (sc->sc_rev) {
599 case NCR_VARIANT_ESP100:
600 sc->sc_maxwidth = MSG_EXT_WDTR_BUS_8_BIT;
601 sc->sc_maxxfer = 64 * 1024;
602 sc->sc_minsync = 0; /* No synch on old chip? */
605 case NCR_VARIANT_ESP100A:
606 sc->sc_maxwidth = MSG_EXT_WDTR_BUS_8_BIT;
607 sc->sc_maxxfer = 64 * 1024;
608 /* Min clocks/byte is 5 */
609 sc->sc_minsync = ncr53c9x_cpb2stp(sc, 5);
612 case NCR_VARIANT_ESP200:
613 sc->sc_maxwidth = MSG_EXT_WDTR_BUS_8_BIT;
614 sc->sc_maxxfer = 16 * 1024 * 1024;
615 /* Min clocks/byte is 5 */
616 sc->sc_minsync = ncr53c9x_cpb2stp(sc, 5);
619 case NCR_VARIANT_FAS100A:
620 case NCR_VARIANT_FAS216:
621 case NCR_VARIANT_FAS236:
623 * The onboard SCSI chips in Sun Ultra 1 are actually
624 * documented to be NCR53C9X which use NCRCFG3_FCLK and
625 * NCRCFG3_FSCSI. BSD/OS however probes these chips as
626 * FAS100A and uses NCRF9XCFG3_FCLK and NCRF9XCFG3_FSCSI
627 * instead which seems to be correct as otherwise sync
628 * negotiation just doesn't work. Using NCRF9XCFG3_FCLK
629 * and NCRF9XCFG3_FSCSI with these chips in fact also
630 * yields Fast-SCSI speed.
632 sc->sc_features = NCR_F_FASTSCSI;
633 sc->sc_cfg3 = NCRF9XCFG3_FCLK;
634 sc->sc_cfg3_fscsi = NCRF9XCFG3_FSCSI;
635 sc->sc_maxwidth = MSG_EXT_WDTR_BUS_8_BIT;
636 sc->sc_maxxfer = 16 * 1024 * 1024;
639 case NCR_VARIANT_FAS366:
640 sc->sc_maxwidth = MSG_EXT_WDTR_BUS_16_BIT;
641 sc->sc_maxxfer = 16 * 1024 * 1024;
645 /* Establish interrupt channel. */
647 if ((esc->sc_irqres = bus_alloc_resource_any(esc->sc_dev, SYS_RES_IRQ,
648 &i, RF_SHAREABLE|RF_ACTIVE)) == NULL) {
649 device_printf(esc->sc_dev, "cannot allocate interrupt\n");
652 if (bus_setup_intr(esc->sc_dev, esc->sc_irqres,
653 INTR_MPSAFE | INTR_TYPE_CAM, NULL, ncr53c9x_intr, sc,
655 device_printf(esc->sc_dev, "cannot set up interrupt\n");
660 /* Turn on target selection using the `DMA' method. */
661 if (sc->sc_rev != NCR_VARIANT_FAS366)
662 sc->sc_features |= NCR_F_DMASELECT;
664 /* Do the common parts of attachment. */
665 sc->sc_dev = esc->sc_dev;
666 error = ncr53c9x_attach(sc);
668 device_printf(esc->sc_dev, "ncr53c9x_attach failed\n");
675 bus_teardown_intr(esc->sc_dev, esc->sc_irqres, esc->sc_irq);
677 bus_release_resource(esc->sc_dev, SYS_RES_IRQ,
678 rman_get_rid(esc->sc_irqres), esc->sc_irqres);
680 lsi64854_detach(esc->sc_dma);
682 NCR_LOCK_DESTROY(sc);
687 espdetach(struct esp_softc *esc)
689 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x;
692 bus_teardown_intr(esc->sc_dev, esc->sc_irqres, esc->sc_irq);
693 error = ncr53c9x_detach(sc);
696 error = lsi64854_detach(esc->sc_dma);
699 NCR_LOCK_DESTROY(sc);
700 bus_release_resource(esc->sc_dev, SYS_RES_IRQ,
701 rman_get_rid(esc->sc_irqres), esc->sc_irqres);
710 #ifdef ESP_SBUS_DEBUG
711 static int esp_sbus_debug = 0;
713 static const struct {
716 } const esp__read_regnames [] = {
717 { "TCL", 0}, /* 0/00 */
718 { "TCM", 0}, /* 1/04 */
719 { "FIFO", 0}, /* 2/08 */
720 { "CMD", 0}, /* 3/0c */
721 { "STAT", 0}, /* 4/10 */
722 { "INTR", 0}, /* 5/14 */
723 { "STEP", 0}, /* 6/18 */
724 { "FFLAGS", 1}, /* 7/1c */
725 { "CFG1", 1}, /* 8/20 */
726 { "STAT2", 0}, /* 9/24 */
727 { "CFG4", 1}, /* a/28 */
728 { "CFG2", 1}, /* b/2c */
729 { "CFG3", 1}, /* c/30 */
730 { "-none", 1}, /* d/34 */
731 { "TCH", 1}, /* e/38 */
732 { "TCX", 1}, /* f/3c */
735 static const const struct {
738 } const esp__write_regnames[] = {
739 { "TCL", 1}, /* 0/00 */
740 { "TCM", 1}, /* 1/04 */
741 { "FIFO", 0}, /* 2/08 */
742 { "CMD", 0}, /* 3/0c */
743 { "SELID", 1}, /* 4/10 */
744 { "TIMEOUT", 1}, /* 5/14 */
745 { "SYNCTP", 1}, /* 6/18 */
746 { "SYNCOFF", 1}, /* 7/1c */
747 { "CFG1", 1}, /* 8/20 */
748 { "CCF", 1}, /* 9/24 */
749 { "TEST", 1}, /* a/28 */
750 { "CFG2", 1}, /* b/2c */
751 { "CFG3", 1}, /* c/30 */
752 { "-none", 1}, /* d/34 */
753 { "TCH", 1}, /* e/38 */
754 { "TCX", 1}, /* f/3c */
759 esp_read_reg(struct ncr53c9x_softc *sc, int reg)
761 struct esp_softc *esc = (struct esp_softc *)sc;
764 v = bus_read_1(esc->sc_res, reg * 4);
766 #ifdef ESP_SBUS_DEBUG
767 if (esp_sbus_debug && (reg < 0x10) && esp__read_regnames[reg].r_flag)
768 printf("RD:%x <%s> %x\n", reg * 4, ((unsigned)reg < 0x10) ?
769 esp__read_regnames[reg].r_name : "<***>", v);
776 esp_write_reg(struct ncr53c9x_softc *sc, int reg, uint8_t v)
778 struct esp_softc *esc = (struct esp_softc *)sc;
780 #ifdef ESP_SBUS_DEBUG
781 if (esp_sbus_debug && (reg < 0x10) && esp__write_regnames[reg].r_flag)
782 printf("WR:%x <%s> %x\n", reg * 4, ((unsigned)reg < 0x10) ?
783 esp__write_regnames[reg].r_name : "<***>", v);
786 bus_write_1(esc->sc_res, reg * 4, v);
790 esp_dma_isintr(struct ncr53c9x_softc *sc)
792 struct esp_softc *esc = (struct esp_softc *)sc;
794 return (DMA_ISINTR(esc->sc_dma));
798 esp_dma_reset(struct ncr53c9x_softc *sc)
800 struct esp_softc *esc = (struct esp_softc *)sc;
802 DMA_RESET(esc->sc_dma);
806 esp_dma_intr(struct ncr53c9x_softc *sc)
808 struct esp_softc *esc = (struct esp_softc *)sc;
810 return (DMA_INTR(esc->sc_dma));
814 esp_dma_setup(struct ncr53c9x_softc *sc, void **addr, size_t *len,
815 int datain, size_t *dmasize)
817 struct esp_softc *esc = (struct esp_softc *)sc;
819 return (DMA_SETUP(esc->sc_dma, addr, len, datain, dmasize));
823 esp_dma_go(struct ncr53c9x_softc *sc)
825 struct esp_softc *esc = (struct esp_softc *)sc;
831 esp_dma_stop(struct ncr53c9x_softc *sc)
833 struct esp_softc *esc = (struct esp_softc *)sc;
835 L64854_SCSR(esc->sc_dma, L64854_GCSR(esc->sc_dma) & ~D_EN_DMA);
839 esp_dma_isactive(struct ncr53c9x_softc *sc)
841 struct esp_softc *esc = (struct esp_softc *)sc;
843 return (DMA_ISACTIVE(esc->sc_dma));