1 /* $NetBSD: ncr53c9xvar.h,v 1.55 2011/07/31 18:39:00 jakllsch Exp $ */
4 * Copyright (c) 1997 The NetBSD Foundation, Inc.
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
9 * NASA Ames Research Center.
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 * 3. All advertising materials mentioning features or use of this software
20 * must display the following acknowledgement:
21 * This product includes software developed by the NetBSD
22 * Foundation, Inc. and its contributors.
23 * 4. Neither the name of The NetBSD Foundation nor the names of its
24 * contributors may be used to endorse or promote products derived
25 * from this software without specific prior written permission.
27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37 * POSSIBILITY OF SUCH DAMAGE.
41 * Copyright (c) 1994 Peter Galbavy. All rights reserved.
43 * Redistribution and use in source and binary forms, with or without
44 * modification, are permitted provided that the following conditions
46 * 1. Redistributions of source code must retain the above copyright
47 * notice, this list of conditions and the following disclaimer.
48 * 2. Redistributions in binary form must reproduce the above copyright
49 * notice, this list of conditions and the following disclaimer in the
50 * documentation and/or other materials provided with the distribution.
51 * 3. All advertising materials mentioning features or use of this software
52 * must display the following acknowledgement:
53 * This product includes software developed by Peter Galbavy.
54 * 4. The name of the author may not be used to endorse or promote products
55 * derived from this software without specific prior written permission.
57 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
58 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
59 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
60 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
61 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
62 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
63 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
64 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
65 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
66 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
71 #ifndef _DEV_IC_NCR53C9XVAR_H_
72 #define _DEV_IC_NCR53C9XVAR_H_
76 /* Set this to 1 for normal debug, or 2 for per-target tracing. */
77 /* #define NCR53C9X_DEBUG 2 */
79 /* Wide or differential can have 16 targets */
82 #define NCR_ABORT_TIMEOUT 2000 /* time to wait for abort */
83 #define NCR_SENSE_TIMEOUT 1000 /* time to wait for sense */
85 #define FREQTOCCF(freq) (((freq + 4) / 5))
88 * NCR 53c9x variants. Note these values are used as indexes into
89 * a table; do not modify them unless you know what you are doing.
91 #define NCR_VARIANT_ESP100 0
92 #define NCR_VARIANT_ESP100A 1
93 #define NCR_VARIANT_ESP200 2
94 #define NCR_VARIANT_NCR53C94 3
95 #define NCR_VARIANT_NCR53C96 4
96 #define NCR_VARIANT_ESP406 5
97 #define NCR_VARIANT_FAS408 6
98 #define NCR_VARIANT_FAS216 7
99 #define NCR_VARIANT_AM53C974 8
100 #define NCR_VARIANT_FAS366 9
101 #define NCR_VARIANT_NCR53C90_86C01 10
102 #define NCR_VARIANT_FAS100A 11
103 #define NCR_VARIANT_FAS236 12
104 #define NCR_VARIANT_MAX 13
106 /* XXX Max tag depth. Should this be defined in the register header? */
107 #define NCR_TAG_DEPTH 256
110 * ECB. Holds additional information for each SCSI command Comments: We
111 * need a separate scsi command block because we may need to overwrite it
112 * with a request sense command. Basicly, we refrain from fiddling with
113 * the ccb union (except do the expected updating of return values).
114 * We'll generally update: ccb->ccb_h.status and ccb->csio.{resid,
115 * scsi_status,sense_data}.
117 struct ncr53c9x_ecb {
118 /* These fields are preserved between alloc and free */
119 struct ncr53c9x_softc *sc;
123 union ccb *ccb; /* SCSI xfer ctrl block from above */
124 TAILQ_ENTRY(ncr53c9x_ecb) free_links;
125 TAILQ_ENTRY(ncr53c9x_ecb) chain;
126 #define ECB_ALLOC 0x01
127 #define ECB_READY 0x02
128 #define ECB_SENSE 0x04
129 #define ECB_ABORT 0x40
130 #define ECB_RESET 0x80
131 #define ECB_TENTATIVE_DONE 0x100
136 uint8_t msg[3]; /* Selection Id msg and tags */
137 struct scsi_generic cmd; /* SCSI command block */
139 uint8_t *daddr; /* Saved data pointer */
140 int clen; /* Size of command in cmd.cmd */
141 int dleft; /* Residue */
142 uint8_t stat; /* SCSI status byte */
143 uint8_t tag[2]; /* TAG bytes */
146 #if defined(NCR53C9X_DEBUG) && NCR53C9X_DEBUG > 1
150 #if defined(NCR53C9X_DEBUG) && NCR53C9X_DEBUG > 1
151 #define ECB_TRACE(ecb, msg, a, b) do { \
152 const char *f = "[" msg "]"; \
153 int n = strlen((ecb)->trace); \
154 if (n < (sizeof((ecb)->trace)-100)) \
155 sprintf((ecb)->trace + n, f, a, b); \
156 } while (/* CONSTCOND */0)
158 #define ECB_TRACE(ecb, msg, a, b)
162 * Some info about each (possible) target and LUN on the SCSI bus.
164 * SCSI I and II devices can have up to 8 LUNs, each with up to 256
165 * outstanding tags. SCSI III devices have 64-bit LUN identifiers
166 * that can be sparsely allocated.
168 * Since SCSI II devices can have up to 8 LUNs, we use an array
169 * of 8 pointers to ncr53c9x_linfo structures for fast lookup.
170 * Longer LUNs need to traverse the linked list.
173 struct ncr53c9x_linfo {
175 LIST_ENTRY(ncr53c9x_linfo) link;
177 uint8_t used; /* # slots in use */
178 uint8_t avail; /* where to start scanning */
180 struct ncr53c9x_ecb *untagged;
181 struct ncr53c9x_ecb *queued[NCR_TAG_DEPTH];
184 struct ncr53c9x_xinfo {
190 struct ncr53c9x_tinfo {
191 int cmds; /* # of commands processed */
192 int dconns; /* # of disconnects */
193 int touts; /* # of timeouts */
194 int perrs; /* # of parity errors */
195 int senses; /* # of request sense commands sent */
197 #define T_SYNCHOFF 0x01 /* SYNC mode is permanently off */
198 #define T_RSELECTOFF 0x02 /* RE-SELECT mode is off */
199 #define T_TAG 0x04 /* Turn on TAG QUEUEs */
200 #define T_SDTRSENT 0x08 /* SDTR message has been sent to */
201 #define T_WDTRSENT 0x10 /* WDTR message has been sent to */
202 struct ncr53c9x_xinfo curr;
203 struct ncr53c9x_xinfo goal;
204 LIST_HEAD(lun_list, ncr53c9x_linfo) luns;
205 struct ncr53c9x_linfo *lun[NCR_NLUN]; /* For speedy lookups */
208 /* Look up a lun in a tinfo */
209 #define TINFO_LUN(t, l) ( \
210 (((l) < NCR_NLUN) && (((t)->lun[(l)]) != NULL)) \
212 : ncr53c9x_lunsearch((t), (int64_t)(l)) \
215 /* Register a linenumber (for debugging). */
218 #define NCR_SHOWECBS 0x01
219 #define NCR_SHOWINTS 0x02
220 #define NCR_SHOWCMDS 0x04
221 #define NCR_SHOWMISC 0x08
222 #define NCR_SHOWTRAC 0x10
223 #define NCR_SHOWSTART 0x20
224 #define NCR_SHOWPHASE 0x40
225 #define NCR_SHOWDMA 0x80
226 #define NCR_SHOWCCMDS 0x100
227 #define NCR_SHOWMSGS 0x200
229 #ifdef NCR53C9X_DEBUG
230 extern int ncr53c9x_debug;
231 #define NCR_ECBS(str) \
233 if ((ncr53c9x_debug & NCR_SHOWECBS) != 0) \
235 } while (/* CONSTCOND */0)
236 #define NCR_MISC(str) \
238 if ((ncr53c9x_debug & NCR_SHOWMISC) != 0) \
240 } while (/* CONSTCOND */0)
241 #define NCR_INTS(str) \
243 if ((ncr53c9x_debug & NCR_SHOWINTS) != 0) \
245 } while (/* CONSTCOND */0)
246 #define NCR_TRACE(str) \
248 if ((ncr53c9x_debug & NCR_SHOWTRAC) != 0) \
250 } while (/* CONSTCOND */0)
251 #define NCR_CMDS(str) \
253 if ((ncr53c9x_debug & NCR_SHOWCMDS) != 0) \
255 } while (/* CONSTCOND */0)
256 #define NCR_START(str) \
258 if ((ncr53c9x_debug & NCR_SHOWSTART) != 0) \
260 } while (/* CONSTCOND */0)
261 #define NCR_PHASE(str) \
263 if ((ncr53c9x_debug & NCR_SHOWPHASE) != 0) \
265 } while (/* CONSTCOND */0)
266 #define NCR_DMA(str) \
268 if ((ncr53c9x_debug & NCR_SHOWDMA) != 0) \
270 } while (/* CONSTCOND */0)
271 #define NCR_MSGS(str) \
273 if ((ncr53c9x_debug & NCR_SHOWMSGS) != 0) \
275 } while (/* CONSTCOND */0)
277 #define NCR_ECBS(str)
278 #define NCR_MISC(str)
279 #define NCR_INTS(str)
280 #define NCR_TRACE(str)
281 #define NCR_CMDS(str)
282 #define NCR_START(str)
283 #define NCR_PHASE(str)
285 #define NCR_MSGS(str)
288 #define NCR_MAX_MSG_LEN 8
290 struct ncr53c9x_softc;
293 * Function switch used as glue to MD code.
295 struct ncr53c9x_glue {
296 /* Mandatory entry points. */
297 uint8_t (*gl_read_reg)(struct ncr53c9x_softc *, int);
298 void (*gl_write_reg)(struct ncr53c9x_softc *, int, uint8_t);
299 int (*gl_dma_isintr)(struct ncr53c9x_softc *);
300 void (*gl_dma_reset)(struct ncr53c9x_softc *);
301 int (*gl_dma_intr)(struct ncr53c9x_softc *);
302 int (*gl_dma_setup)(struct ncr53c9x_softc *, void **, size_t *,
304 void (*gl_dma_go)(struct ncr53c9x_softc *);
305 void (*gl_dma_stop)(struct ncr53c9x_softc *);
306 int (*gl_dma_isactive)(struct ncr53c9x_softc *);
308 /* Optional entry points. */
309 void (*gl_clear_latched_intr)(struct ncr53c9x_softc *);
312 struct ncr53c9x_softc {
313 device_t sc_dev; /* us as a device */
315 struct cam_sim *sc_sim; /* our scsi adapter */
316 struct cam_path *sc_path; /* our scsi channel */
317 struct callout sc_watchdog; /* periodic timer */
319 const struct ncr53c9x_glue *sc_glue; /* glue to MD code */
321 int sc_cfflags; /* Copy of config flags */
323 /* register defaults */
324 uint8_t sc_cfg1; /* Config 1 */
325 uint8_t sc_cfg2; /* Config 2, not ESP100 */
326 uint8_t sc_cfg3; /* Config 3, ESP200,FAS */
327 uint8_t sc_cfg3_fscsi; /* Chip-specific FSCSI bit */
328 uint8_t sc_cfg4; /* Config 4, only ESP200 */
329 uint8_t sc_cfg5; /* Config 5, only ESP200 */
330 uint8_t sc_ccf; /* Clock Conversion */
333 /* register copies, see espreadregs() */
338 uint8_t sc_espfflags;
340 /* Lists of command blocks */
341 TAILQ_HEAD(ecb_list, ncr53c9x_ecb) ready_list;
343 struct ncr53c9x_ecb *sc_nexus; /* Current command */
345 struct ncr53c9x_tinfo *sc_tinfo;
347 /* Data about the current nexus (updated for every cmd switch) */
348 void *sc_dp; /* Current data pointer */
349 ssize_t sc_dleft; /* Data left to transfer */
352 int sc_phase; /* Copy of what bus phase we are in */
353 int sc_prevphase; /* Copy of what bus phase we were in */
354 uint8_t sc_state; /* State applicable to the adapter */
355 uint8_t sc_flags; /* See below */
360 uint16_t sc_msgify; /* IDENTIFY message associated with nexus */
361 uint16_t sc_msgout; /* What message is on its way out? */
362 uint16_t sc_msgpriq; /* One or more messages to send (encoded) */
363 uint16_t sc_msgoutq; /* What messages have been sent so far? */
365 uint8_t *sc_omess; /* MSGOUT buffer */
366 int sc_omess_self; /* MSGOUT buffer is self-allocated */
367 void *sc_omp; /* Message pointer (for multibyte messages) */
369 uint8_t *sc_imess; /* MSGIN buffer */
370 int sc_imess_self; /* MSGIN buffer is self-allocated */
371 void *sc_imp; /* Message pointer (for multibyte messages) */
374 void *sc_cmdp; /* Command pointer (for DMAed commands) */
375 size_t sc_cmdlen; /* Size of command in transit */
377 /* Hardware attributes */
378 int sc_freq; /* SCSI bus frequency in MHz */
379 int sc_id; /* Our SCSI id */
380 int sc_rev; /* Chip revision */
381 int sc_features; /* Chip features */
382 int sc_minsync; /* Minimum sync period / 4 */
383 int sc_maxxfer; /* Maximum transfer size */
384 int sc_maxoffset; /* Maximum offset */
385 int sc_maxwidth; /* Maximum width */
386 int sc_extended_geom; /* Should we return extended geometry */
388 struct mtx sc_lock; /* driver mutex */
390 struct ncr53c9x_ecb *ecb_array;
391 TAILQ_HEAD(,ncr53c9x_ecb) free_list;
394 /* values for sc_state */
395 #define NCR_IDLE 1 /* Waiting for something to do */
396 #define NCR_SELECTING 2 /* SCSI command is arbiting */
397 #define NCR_RESELECTED 3 /* Has been reselected */
398 #define NCR_IDENTIFIED 4 /* Has gotten IFY but not TAG */
399 #define NCR_CONNECTED 5 /* Actively using the SCSI bus */
400 #define NCR_DISCONNECT 6 /* MSG_DISCONNECT received */
401 #define NCR_CMDCOMPLETE 7 /* MSG_CMDCOMPLETE received */
402 #define NCR_CLEANING 8
403 #define NCR_SBR 9 /* Expect a SCSI RST because we commanded it */
405 /* values for sc_flags */
406 #define NCR_DROP_MSGI 0x01 /* Discard all msgs (parity err detected) */
407 #define NCR_ABORTING 0x02 /* Bailing out */
408 #define NCR_ICCS 0x04 /* Expect status phase results */
409 #define NCR_WAITI 0x08 /* Waiting for non-DMA data to arrive */
410 #define NCR_ATN 0x10 /* ATN asserted */
411 #define NCR_EXPECT_ILLCMD 0x20 /* Expect Illegal Command Interrupt */
413 /* values for sc_features */
414 #define NCR_F_HASCFG3 0x01 /* chip has CFG3 register */
415 #define NCR_F_FASTSCSI 0x02 /* chip supports Fast mode */
416 #define NCR_F_DMASELECT 0x04 /* can do dmaselect */
417 #define NCR_F_SELATN3 0x08 /* chip supports SELATN3 command */
419 /* values for sc_msgout */
420 #define SEND_DEV_RESET 0x0001
421 #define SEND_PARITY_ERROR 0x0002
422 #define SEND_INIT_DET_ERR 0x0004
423 #define SEND_REJECT 0x0008
424 #define SEND_IDENTIFY 0x0010
425 #define SEND_ABORT 0x0020
426 #define SEND_TAG 0x0040
427 #define SEND_WDTR 0x0080
428 #define SEND_SDTR 0x0100
430 /* SCSI Status codes */
431 #define ST_MASK 0x3e /* bit 0,6,7 is reserved */
438 /* Information transfer phases */
439 #define DATA_OUT_PHASE (0)
440 #define DATA_IN_PHASE (IOI)
441 #define COMMAND_PHASE (CDI)
442 #define STATUS_PHASE (CDI | IOI)
443 #define MESSAGE_OUT_PHASE (MSGI | CDI)
444 #define MESSAGE_IN_PHASE (MSGI | CDI | IOI)
446 #define PHASE_MASK (MSGI | CDI | IOI)
448 /* Some pseudo phases for getphase()*/
449 #define BUSFREE_PHASE 0x100 /* Re/Selection no longer valid */
450 #define INVALID_PHASE 0x101 /* Re/Selection valid, but no REQ yet */
451 #define PSEUDO_PHASE 0x100 /* "pseudo" bit */
454 * Macros to read and write the chip's registers.
456 #define NCR_READ_REG(sc, reg) \
457 (*(sc)->sc_glue->gl_read_reg)((sc), (reg))
458 #define NCR_WRITE_REG(sc, reg, val) \
459 (*(sc)->sc_glue->gl_write_reg)((sc), (reg), (val))
461 #ifdef NCR53C9X_DEBUG
462 #define NCRCMD(sc, cmd) do { \
463 if ((ncr53c9x_debug & NCR_SHOWCCMDS) != 0) \
464 printf("<CMD:0x%x %d>", (unsigned int)cmd, __LINE__); \
465 sc->sc_lastcmd = cmd; \
466 NCR_WRITE_REG(sc, NCR_CMD, cmd); \
467 } while (/* CONSTCOND */ 0)
469 #define NCRCMD(sc, cmd) NCR_WRITE_REG(sc, NCR_CMD, cmd)
475 #define NCR_LOCK_INIT(_sc) \
476 mtx_init(&(_sc)->sc_lock, "ncr", "ncr53c9x lock", MTX_DEF);
477 #define NCR_LOCK_INITIALIZED(_sc) mtx_initialized(&(_sc)->sc_lock)
478 #define NCR_LOCK(_sc) mtx_lock(&(_sc)->sc_lock)
479 #define NCR_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_lock)
480 #define NCR_LOCK_ASSERT(_sc, _what) mtx_assert(&(_sc)->sc_lock, (_what))
481 #define NCR_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_lock)
484 * DMA macros for NCR53c9x
486 #define NCRDMA_ISINTR(sc) (*(sc)->sc_glue->gl_dma_isintr)((sc))
487 #define NCRDMA_RESET(sc) (*(sc)->sc_glue->gl_dma_reset)((sc))
488 #define NCRDMA_INTR(sc) (*(sc)->sc_glue->gl_dma_intr)((sc))
489 #define NCRDMA_SETUP(sc, addr, len, datain, dmasize) \
490 (*(sc)->sc_glue->gl_dma_setup)((sc), (addr), (len), (datain), (dmasize))
491 #define NCRDMA_GO(sc) (*(sc)->sc_glue->gl_dma_go)((sc))
492 #define NCRDMA_STOP(sc) (*(sc)->sc_glue->gl_dma_stop)((sc))
493 #define NCRDMA_ISACTIVE(sc) (*(sc)->sc_glue->gl_dma_isactive)((sc))
496 * Macro to convert the chip register Clock Per Byte value to
497 * Synchronous Transfer Period.
499 #define ncr53c9x_cpb2stp(sc, cpb) \
500 ((250 * (cpb)) / (sc)->sc_freq)
502 int ncr53c9x_attach(struct ncr53c9x_softc *sc);
503 int ncr53c9x_detach(struct ncr53c9x_softc *sc);
504 void ncr53c9x_intr(void *arg);
506 #endif /* _DEV_IC_NCR53C9XVAR_H_ */