2 * Copyright (c) 2007 Sepherosa Ziehau. All rights reserved.
4 * This code is derived from software contributed to The DragonFly Project
5 * by Sepherosa Ziehau <sepherosa@gmail.com>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * 3. Neither the name of The DragonFly Project nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific, prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
24 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
25 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
27 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
28 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
29 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 * $DragonFly: src/sys/dev/netif/et/if_etvar.h,v 1.4 2007/10/23 14:28:42 sephe Exp $
41 #define ET_RING_ALIGN 4096
42 #define ET_STATUS_ALIGN 8
43 #define ET_NSEG_MAX 32 /* XXX no limit actually */
44 #define ET_NSEG_SPARE 8
46 #define ET_TX_NDESC 512
47 #define ET_RX_NDESC 512
49 #define ET_RX_NSTAT (ET_RX_NRING * ET_RX_NDESC)
51 #define ET_TX_RING_SIZE (ET_TX_NDESC * sizeof(struct et_txdesc))
52 #define ET_RX_RING_SIZE (ET_RX_NDESC * sizeof(struct et_rxdesc))
53 #define ET_RXSTAT_RING_SIZE (ET_RX_NSTAT * sizeof(struct et_rxstat))
55 #define ET_JUMBO_FRAMELEN (ET_MEM_SIZE - ET_MEM_RXSIZE_MIN - \
57 #define ET_JUMBO_MTU (ET_JUMBO_FRAMELEN - ETHER_HDR_LEN - \
58 EVL_ENCAPLEN - ETHER_CRC_LEN)
60 #define ET_FRAMELEN(mtu) (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + \
61 (mtu) + ETHER_CRC_LEN)
63 #define ET_JSLOTS (ET_RX_NDESC + 128)
64 #define ET_JLEN (ET_JUMBO_FRAMELEN + ETHER_ALIGN)
65 #define ET_JUMBO_MEM_SIZE (ET_JSLOTS * ET_JLEN)
67 #define CSR_WRITE_4(sc, reg, val) \
68 bus_write_4((sc)->sc_mem_res, (reg), (val))
69 #define CSR_READ_4(sc, reg) \
70 bus_read_4((sc)->sc_mem_res, (reg))
72 #define ET_ADDR_HI(addr) ((uint64_t) (addr) >> 32)
73 #define ET_ADDR_LO(addr) ((uint64_t) (addr) & 0xffffffff)
78 uint32_t td_ctrl1; /* ET_TDCTRL1_ */
79 uint32_t td_ctrl2; /* ET_TDCTRL2_ */
82 #define ET_TDCTRL1_LEN_MASK 0x0000FFFF
84 #define ET_TDCTRL2_LAST_FRAG 0x00000001
85 #define ET_TDCTRL2_FIRST_FRAG 0x00000002
86 #define ET_TDCTRL2_INTR 0x00000004
87 #define ET_TDCTRL2_CTRL_WORD 0x00000008
88 #define ET_TDCTRL2_HDX_BACKP 0x00000010
89 #define ET_TDCTRL2_XMIT_PAUSE 0x00000020
90 #define ET_TDCTRL2_FRAME_ERR 0x00000040
91 #define ET_TDCTRL2_NO_CRC 0x00000080
92 #define ET_TDCTRL2_MAC_OVRRD 0x00000100
93 #define ET_TDCTRL2_PAD_PACKET 0x00000200
94 #define ET_TDCTRL2_JUMBO_PACKET 0x00000400
95 #define ET_TDCTRL2_INS_VLAN 0x00000800
96 #define ET_TDCTRL2_CSUM_IP 0x00001000
97 #define ET_TDCTRL2_CSUM_TCP 0x00002000
98 #define ET_TDCTRL2_CSUM_UDP 0x00004000
103 uint32_t rd_ctrl; /* ET_RDCTRL_ */
106 #define ET_RDCTRL_BUFIDX_MASK 0x000003FF
110 uint32_t rxst_info2; /* ET_RXST_INFO2_ */
113 #define ET_RXST_INFO1_HASH_PASS 0x00000001
114 #define ET_RXST_INFO1_IPCSUM 0x00000002
115 #define ET_RXST_INFO1_IPCSUM_OK 0x00000004
116 #define ET_RXST_INFO1_TCPCSUM 0x00000008
117 #define ET_RXST_INFO1_TCPCSUM_OK 0x00000010
118 #define ET_RXST_INFO1_WOL 0x00000020
119 #define ET_RXST_INFO1_RXMAC_ERR 0x00000040
120 #define ET_RXST_INFO1_DROP 0x00000080
121 #define ET_RXST_INFO1_FRAME_TRUNC 0x00000100
122 #define ET_RXST_INFO1_JUMBO 0x00000200
123 #define ET_RXST_INFO1_VLAN 0x00000400
124 #define ET_RXST_INFO1_PREV_FRMAE_DROP 0x00010000
125 #define ET_RXST_INFO1_SHORT 0x00020000
126 #define ET_RXST_INFO1_BAD_CARRIER 0x00040000
127 #define ET_RXST_INFO1_CODE_ERR 0x00080000
128 #define ET_RXST_INFO1_CRC_ERR 0x00100000
129 #define ET_RXST_INFO1_LEN_MISMATCH 0x00200000
130 #define ET_RXST_INFO1_TOO_LONG 0x00400000
131 #define ET_RXST_INFO1_OK 0x00800000
132 #define ET_RXST_INFO1_MULTICAST 0x01000000
133 #define ET_RXST_INFO1_BROADCAST 0x02000000
134 #define ET_RXST_INFO1_DRIBBLE 0x04000000
135 #define ET_RXST_INFO1_CTL_FRAME 0x08000000
136 #define ET_RXST_INFO1_PAUSE_FRAME 0x10000000
137 #define ET_RXST_INFO1_UNKWN_CTL_FRAME 0x20000000
138 #define ET_RXST_INFO1_VLAN_TAG 0x40000000
139 #define ET_RXST_INFO1_LONG_EVENT 0x80000000
141 #define ET_RXST_INFO2_LEN_MASK 0x0000FFFF
142 #define ET_RXST_INFO2_LEN_SHIFT 0
143 #define ET_RXST_INFO2_BUFIDX_MASK 0x03FF0000
144 #define ET_RXST_INFO2_BUFIDX_SHIFT 16
145 #define ET_RXST_INFO2_RINGIDX_MASK 0x0C000000
146 #define ET_RXST_INFO2_RINGIDX_SHIFT 26
150 uint32_t rxs_stat_ring; /* ET_RXS_STATRING_ */
153 #define ET_RXS_STATRING_INDEX_MASK 0x0FFF0000
154 #define ET_RXS_STATRING_INDEX_SHIFT 16
155 #define ET_RXS_STATRING_WRAP 0x10000000
158 struct mbuf *tb_mbuf;
159 bus_dmamap_t tb_dmap;
163 struct mbuf *rb_mbuf;
164 bus_dmamap_t rb_dmap;
167 struct et_txstatus_data {
168 uint32_t *txsd_status;
169 bus_addr_t txsd_paddr;
170 bus_dma_tag_t txsd_dtag;
171 bus_dmamap_t txsd_dmap;
174 struct et_rxstatus_data {
175 struct et_rxstatus *rxsd_status;
176 bus_addr_t rxsd_paddr;
177 bus_dma_tag_t rxsd_dtag;
178 bus_dmamap_t rxsd_dmap;
181 struct et_rxstat_ring {
182 struct et_rxstat *rsr_stat;
183 bus_addr_t rsr_paddr;
184 bus_dma_tag_t rsr_dtag;
185 bus_dmamap_t rsr_dmap;
191 struct et_txdesc_ring {
192 struct et_txdesc *tr_desc;
194 bus_dma_tag_t tr_dtag;
195 bus_dmamap_t tr_dmap;
201 struct et_rxdesc_ring {
202 struct et_rxdesc *rr_desc;
204 bus_dma_tag_t rr_dtag;
205 bus_dmamap_t rr_dmap;
212 struct et_txbuf_data {
213 struct et_txbuf tbd_buf[ET_TX_NDESC];
221 struct et_rxbuf_data;
223 struct et_rxbuf_data {
224 struct et_rxbuf rbd_buf[ET_RX_NDESC];
226 struct et_softc *rbd_softc;
227 struct et_rxdesc_ring *rbd_ring;
230 int (*rbd_newbuf)(struct et_rxbuf_data *, int);
231 void (*rbd_discard)(struct et_rxbuf_data *, int);
240 struct resource *sc_irq_res;
241 struct resource *sc_mem_res;
243 struct arpcom arpcom;
245 uint32_t sc_flags; /* ET_FLAG_ */
252 struct callout sc_tick;
256 bus_dma_tag_t sc_dtag;
258 struct et_rxdesc_ring sc_rx_ring[ET_RX_NRING];
259 struct et_rxstat_ring sc_rxstat_ring;
260 struct et_rxstatus_data sc_rx_status;
262 struct et_txdesc_ring sc_tx_ring;
263 struct et_txstatus_data sc_tx_status;
265 bus_dma_tag_t sc_mbuf_dtag;
266 bus_dma_tag_t sc_rx_mini_tag;
267 bus_dmamap_t sc_rx_mini_sparemap;
268 bus_dma_tag_t sc_rx_tag;
269 bus_dmamap_t sc_rx_sparemap;
270 bus_dma_tag_t sc_tx_tag;
271 struct et_rxbuf_data sc_rx_data[ET_RX_NRING];
272 struct et_txbuf_data sc_tx_data;
280 int sc_rx_intr_npkts;
281 int sc_rx_intr_delay;
282 int sc_tx_intr_nsegs;
286 #define ET_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
287 #define ET_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
288 #define ET_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED)
290 #define ET_FLAG_PCIE 0x0001
291 #define ET_FLAG_MSI 0x0002
292 #define ET_FLAG_TXRX_ENABLED 0x0100
293 #define ET_FLAG_JUMBO 0x0200
295 #endif /* !_IF_ETVAR_H */