2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2022 Adrian Chadd <adrian@FreeBSD.org>.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #include <sys/param.h>
30 #include <sys/errno.h>
31 #include <sys/kernel.h>
32 #include <sys/malloc.h>
33 #include <sys/module.h>
34 #include <sys/socket.h>
35 #include <sys/sockio.h>
36 #include <sys/sysctl.h>
37 #include <sys/systm.h>
40 #include <net/if_var.h>
41 #include <net/if_arp.h>
42 #include <net/ethernet.h>
43 #include <net/if_dl.h>
44 #include <net/if_media.h>
45 #include <net/if_types.h>
47 #include <machine/bus.h>
48 #include <dev/iicbus/iic.h>
49 #include <dev/iicbus/iiconf.h>
50 #include <dev/iicbus/iicbus.h>
51 #include <dev/mii/mii.h>
52 #include <dev/mii/miivar.h>
53 #include <dev/mdio/mdio.h>
54 #include <dev/extres/clk/clk.h>
55 #include <dev/extres/hwreset/hwreset.h>
57 #include <dev/fdt/fdt_common.h>
58 #include <dev/ofw/ofw_bus.h>
59 #include <dev/ofw/ofw_bus_subr.h>
61 #include <dev/etherswitch/etherswitch.h>
63 #include <dev/etherswitch/ar40xx/ar40xx_var.h>
64 #include <dev/etherswitch/ar40xx/ar40xx_reg.h>
65 #include <dev/etherswitch/ar40xx/ar40xx_phy.h>
66 #include <dev/etherswitch/ar40xx/ar40xx_debug.h>
67 #include <dev/etherswitch/ar40xx/ar40xx_hw.h>
68 #include <dev/etherswitch/ar40xx/ar40xx_hw_psgmii.h>
69 #include <dev/etherswitch/ar40xx/ar40xx_hw_port.h>
70 #include <dev/etherswitch/ar40xx/ar40xx_hw_mib.h>
71 #include <dev/etherswitch/ar40xx/ar40xx_hw_vtu.h>
72 #include <dev/etherswitch/ar40xx/ar40xx_hw_atu.h>
75 #include "miibus_if.h"
76 #include "etherswitch_if.h"
78 static struct ofw_compat_data compat_data[] = {
79 { "qcom,ess-switch", 1 },
84 ar40xx_probe(device_t dev)
87 if (! ofw_bus_status_okay(dev))
90 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
93 device_set_desc(dev, "IPQ4018 ESS Switch fabric / PSGMII PHY");
94 return (BUS_PROBE_DEFAULT);
98 ar40xx_tick(void *arg)
100 struct ar40xx_softc *sc = arg;
102 (void) ar40xx_phy_tick(sc);
103 callout_reset(&sc->sc_phy_callout, hz, ar40xx_tick, sc);
107 ar40xx_statchg(device_t dev)
109 struct ar40xx_softc *sc = device_get_softc(dev);
111 AR40XX_DPRINTF(sc, AR40XX_DBG_PORT_STATUS, "%s\n", __func__);
115 ar40xx_readphy(device_t dev, int phy, int reg)
117 struct ar40xx_softc *sc = device_get_softc(dev);
119 return MDIO_READREG(sc->sc_mdio_dev, phy, reg);
123 ar40xx_writephy(device_t dev, int phy, int reg, int val)
125 struct ar40xx_softc *sc = device_get_softc(dev);
127 return MDIO_WRITEREG(sc->sc_mdio_dev, phy, reg, val);
131 * Do the initial switch configuration.
134 ar40xx_reset_switch(struct ar40xx_softc *sc)
138 AR40XX_DPRINTF(sc, AR40XX_DBG_HW_INIT, "%s: called\n", __func__);
140 /* blank the VLAN config */
141 memset(&sc->sc_vlan, 0, sizeof(sc->sc_vlan));
143 /* initial vlan port mapping */
144 for (i = 0; i < AR40XX_NUM_VTU_ENTRIES; i++)
145 sc->sc_vlan.vlan_id[i] = 0;
147 /* init vlan config */
148 ret = ar40xx_hw_vlan_init(sc);
150 /* init monitor config */
151 sc->sc_monitor.mirror_tx = false;
152 sc->sc_monitor.mirror_rx = false;
153 sc->sc_monitor.source_port = 0;
154 sc->sc_monitor.monitor_port = 0;
156 /* apply switch config */
157 ret = ar40xx_hw_sw_hw_apply(sc);
163 ar40xx_sysctl_dump_port_state(SYSCTL_HANDLER_ARGS)
165 struct ar40xx_softc *sc = arg1;
172 error = sysctl_handle_int(oidp, &val, 0, req);
173 if (error || !req->newptr)
176 if (val < 0 || val > 5) {
182 device_printf(sc->sc_dev, "port %d: PORT_STATUS=0x%08x\n", val,
183 AR40XX_REG_READ(sc, AR40XX_REG_PORT_STATUS(val)));
184 device_printf(sc->sc_dev, "port %d: PORT_HEADER=0x%08x\n", val,
185 AR40XX_REG_READ(sc, AR40XX_REG_PORT_HEADER(val)));
186 device_printf(sc->sc_dev, "port %d: PORT_VLAN0=0x%08x\n", val,
187 AR40XX_REG_READ(sc, AR40XX_REG_PORT_VLAN0(val)));
188 device_printf(sc->sc_dev, "port %d: PORT_VLAN1=0x%08x\n", val,
189 AR40XX_REG_READ(sc, AR40XX_REG_PORT_VLAN1(val)));
190 device_printf(sc->sc_dev, "port %d: PORT_LOOKUP=0x%08x\n", val,
191 AR40XX_REG_READ(sc, AR40XX_REG_PORT_LOOKUP(val)));
192 device_printf(sc->sc_dev, "port %d: PORT_HOL_CTRL1=0x%08x\n", val,
193 AR40XX_REG_READ(sc, AR40XX_REG_PORT_HOL_CTRL1(val)));
194 device_printf(sc->sc_dev, "port %d: PORT_FLOWCTRL_THRESH=0x%08x\n",
195 val, AR40XX_REG_READ(sc, AR40XX_REG_PORT_FLOWCTRL_THRESH(val)));
203 ar40xx_sysctl_dump_port_mibstats(SYSCTL_HANDLER_ARGS)
205 struct ar40xx_softc *sc = arg1;
212 error = sysctl_handle_int(oidp, &val, 0, req);
213 if (error || !req->newptr)
216 if (val < 0 || val > 5) {
222 /* Yes, this snapshots all ports */
223 (void) ar40xx_hw_mib_capture(sc);
224 (void) ar40xx_hw_mib_fetch(sc, val);
233 ar40xx_sysctl_attach(struct ar40xx_softc *sc)
235 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(sc->sc_dev);
236 struct sysctl_oid *tree = device_get_sysctl_tree(sc->sc_dev);
238 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
239 "debug", CTLFLAG_RW, &sc->sc_debug, 0,
242 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
243 "port_state", CTLTYPE_INT | CTLFLAG_RW, sc,
244 0, ar40xx_sysctl_dump_port_state, "I", "");
246 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
247 "port_mibstats", CTLTYPE_INT | CTLFLAG_RW, sc,
248 0, ar40xx_sysctl_dump_port_mibstats, "I", "");
254 ar40xx_detach(device_t dev)
256 struct ar40xx_softc *sc = device_get_softc(dev);
259 device_printf(sc->sc_dev, "%s: called\n", __func__);
261 callout_drain(&sc->sc_phy_callout);
264 for (i = 0; i < AR40XX_NUM_PHYS; i++) {
265 if (sc->sc_phys.miibus[i] != NULL)
266 device_delete_child(dev, sc->sc_phys.miibus[i]);
267 if (sc->sc_phys.ifp[i] != NULL)
268 if_free(sc->sc_phys.ifp[i]);
269 free(sc->sc_phys.ifname[i], M_DEVBUF);
272 bus_generic_detach(dev);
273 mtx_destroy(&sc->sc_mtx);
279 ar40xx_attach(device_t dev)
281 struct ar40xx_softc *sc = device_get_softc(dev);
282 phandle_t psgmii_p, root_p, mdio_p;
286 mtx_init(&sc->sc_mtx, "ar40xx_switch", NULL, MTX_DEF);
288 psgmii_p = OF_finddevice("/soc/ess-psgmii");
289 if (psgmii_p == -1) {
291 "%s: couldn't find /soc/ess-psgmii DT node\n",
297 * Get the ipq4019-mdio node here, to talk to our local PHYs
300 root_p = OF_finddevice("/soc");
301 mdio_p = ofw_bus_find_compatible(root_p, "qcom,ipq4019-mdio");
303 device_printf(dev, "%s: couldn't find ipq4019-mdio DT node\n",
307 sc->sc_mdio_phandle = mdio_p;
308 sc->sc_mdio_dev = OF_device_from_xref(OF_xref_from_node(mdio_p));
309 if (sc->sc_mdio_dev == NULL) {
311 "%s: couldn't get mdio device (mdio_p=%u)\n",
316 /* get psgmii base address from psgmii node */
317 ret = OF_decode_addr(psgmii_p, 0, &sc->sc_psgmii_mem_tag,
318 &sc->sc_psgmii_mem_handle,
319 &sc->sc_psgmii_mem_size);
321 device_printf(dev, "%s: couldn't map psgmii mem (%d)\n",
326 /* get switch base address */
327 sc->sc_ess_mem_rid = 0;
328 sc->sc_ess_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
329 &sc->sc_ess_mem_rid, RF_ACTIVE);
330 if (sc->sc_ess_mem_res == NULL) {
331 device_printf(dev, "%s: failed to find memory resource\n",
335 sc->sc_ess_mem_size = (size_t) bus_get_resource_count(dev,
336 SYS_RES_MEMORY, sc->sc_ess_mem_rid);
337 if (sc->sc_ess_mem_size == 0) {
338 device_printf(dev, "%s: failed to get device memory size\n",
343 ret = OF_getencprop(ofw_bus_get_node(dev), "switch_mac_mode",
344 &sc->sc_config.switch_mac_mode,
345 sizeof(sc->sc_config.switch_mac_mode));
347 device_printf(dev, "%s: missing switch_mac_mode property\n",
352 ret = OF_getencprop(ofw_bus_get_node(dev), "switch_cpu_bmp",
353 &sc->sc_config.switch_cpu_bmp,
354 sizeof(sc->sc_config.switch_cpu_bmp));
356 device_printf(dev, "%s: missing switch_cpu_bmp property\n",
361 ret = OF_getencprop(ofw_bus_get_node(dev), "switch_lan_bmp",
362 &sc->sc_config.switch_lan_bmp,
363 sizeof(sc->sc_config.switch_lan_bmp));
365 device_printf(dev, "%s: missing switch_lan_bmp property\n",
370 ret = OF_getencprop(ofw_bus_get_node(dev), "switch_wan_bmp",
371 &sc->sc_config.switch_wan_bmp,
372 sizeof(sc->sc_config.switch_wan_bmp));
374 device_printf(dev, "%s: missing switch_wan_bmp property\n",
379 ret = clk_get_by_ofw_name(dev, 0, "ess_clk", &sc->sc_ess_clk);
381 device_printf(dev, "%s: failed to find ess_clk (%d)\n",
385 ret = clk_enable(sc->sc_ess_clk);
387 device_printf(dev, "%s: failed to enable clock (%d)\n",
392 ret = hwreset_get_by_ofw_name(dev, 0, "ess_rst", &sc->sc_ess_rst);
394 device_printf(dev, "%s: failed to find ess_rst (%d)\n",
400 * Ok, at this point we have enough resources to do an initial
401 * reset and configuration.
406 /* Initial PSGMII/RGMII port configuration */
407 ret = ar40xx_hw_psgmii_init_config(sc);
409 device_printf(sc->sc_dev,
410 "ERROR: failed to init PSGMII (%d)\n", ret);
415 * ESS reset - this resets both the ethernet switch
416 * AND the ethernet block.
418 ret = ar40xx_hw_ess_reset(sc);
420 device_printf(sc->sc_dev,
421 "ERROR: failed to reset ESS block (%d)\n", ret);
426 * Check the PHY IDs for each of the PHYs from 0..4;
427 * this is useful to make sure that we can SEE the external
431 ret = ar40xx_hw_phy_get_ids(sc);
433 device_printf(sc->sc_dev,
434 "ERROR: failed to check PHY IDs (%d)\n", ret);
440 * Do PSGMII PHY self-test; work-around issues.
442 ret = ar40xx_hw_psgmii_self_test(sc);
444 device_printf(sc->sc_dev,
445 "ERROR: failed to do PSGMII self-test (%d)\n", ret);
449 /* Return port config to runtime state */
450 ret = ar40xx_hw_psgmii_self_test_clean(sc);
452 device_printf(sc->sc_dev,
453 "ERROR: failed to do PSGMII runtime config (%d)\n", ret);
458 ret = ar40xx_hw_psgmii_set_mac_mode(sc,
459 sc->sc_config.switch_mac_mode);
461 /* Initialise each hardware port */
462 for (i = 0; i < AR40XX_NUM_PORTS; i++) {
463 ret = ar40xx_hw_port_init(sc, i);
466 /* initialise the global switch configuration */
467 ret = ar40xx_hw_init_globals(sc);
469 /* reset the switch vlan/port learning config */
470 ret = ar40xx_reset_switch(sc);
473 ret = ar40xx_hw_port_cpuport_setup(sc);
478 /* We may end up needing the QM workaround code here.. */
479 device_printf(dev, "%s: TODO: QM error check\n", __func__);
483 ret = ar40xx_attach_phys(sc);
485 ret = bus_generic_probe(dev);
486 bus_enumerate_hinted_children(dev);
487 ret = bus_generic_attach(dev);
490 callout_init_mtx(&sc->sc_phy_callout, &sc->sc_mtx, 0);
493 * Setup the etherswitch info block.
495 strlcpy(sc->sc_info.es_name, device_get_desc(dev),
496 sizeof(sc->sc_info.es_name));
497 sc->sc_info.es_nports = AR40XX_NUM_PORTS;
498 sc->sc_info.es_vlan_caps = ETHERSWITCH_VLAN_DOT1Q;
499 /* XXX TODO: double-tag / 802.1ad */
500 sc->sc_info.es_nvlangroups = AR40XX_NUM_VTU_ENTRIES;
503 * Fetch the initial port configuration.
509 ar40xx_sysctl_attach(sc);
520 ar40xx_lock(device_t dev)
522 struct ar40xx_softc *sc = device_get_softc(dev);
528 ar40xx_unlock(device_t dev)
530 struct ar40xx_softc *sc = device_get_softc(dev);
532 AR40XX_LOCK_ASSERT(sc);
536 static etherswitch_info_t *
537 ar40xx_getinfo(device_t dev)
539 struct ar40xx_softc *sc = device_get_softc(dev);
541 return (&sc->sc_info);
545 ar40xx_readreg(device_t dev, int addr)
547 struct ar40xx_softc *sc = device_get_softc(dev);
549 if (addr >= sc->sc_ess_mem_size - 1)
552 AR40XX_REG_BARRIER_READ(sc);
554 return AR40XX_REG_READ(sc, addr);
558 ar40xx_writereg(device_t dev, int addr, int value)
560 struct ar40xx_softc *sc = device_get_softc(dev);
562 if (addr >= sc->sc_ess_mem_size - 1)
565 AR40XX_REG_WRITE(sc, addr, value);
566 AR40XX_REG_BARRIER_WRITE(sc);
571 * Get the port configuration and status.
574 ar40xx_getport(device_t dev, etherswitch_port_t *p)
576 struct ar40xx_softc *sc = device_get_softc(dev);
577 struct mii_data *mii = NULL;
578 struct ifmediareq *ifmr;
581 if (p->es_port < 0 || p->es_port > sc->sc_info.es_nports)
585 /* Fetch the current VLAN configuration for this port */
587 ar40xx_hw_get_port_pvid(sc, p->es_port, &p->es_pvid);
590 * The VLAN egress aren't appropriate to the ports;
591 * instead it's part of the VLAN group config.
595 mii = ar40xx_phy_miiforport(sc, p->es_port);
599 if (p->es_port == 0) {
601 p->es_flags |= ETHERSWITCH_PORT_CPU;
604 ifmr->ifm_current = ifmr->ifm_active =
605 IFM_ETHER | IFM_1000_T | IFM_FDX;
607 ifmr->ifm_status = IFM_ACTIVE | IFM_AVALID;
608 } else if (mii != NULL) {
610 err = ifmedia_ioctl(mii->mii_ifp, &p->es_ifr,
611 &mii->mii_media, SIOCGIFMEDIA);
622 * Set the port configuration and status.
625 ar40xx_setport(device_t dev, etherswitch_port_t *p)
627 struct ar40xx_softc *sc = device_get_softc(dev);
629 struct mii_data *mii;
633 if (p->es_port < 0 || p->es_port > sc->sc_info.es_nports)
638 ret = ar40xx_hw_set_port_pvid(sc, p->es_port, p->es_pvid);
643 /* XXX TODO: tag strip/unstrip, double-tag, etc */
646 /* Don't change media config on CPU port */
650 mii = ar40xx_phy_miiforport(sc, p->es_port);
654 ifp = ar40xx_phy_ifpforport(sc, p->es_port);
656 ifm = &mii->mii_media;
657 return (ifmedia_ioctl(ifp, &p->es_ifr, ifm, SIOCSIFMEDIA));
663 * Get the current VLAN group (per-port, ISL, dot1q) configuration.
665 * For now the only supported operating mode is dot1q.
668 ar40xx_getvgroup(device_t dev, etherswitch_vlangroup_t *vg)
670 struct ar40xx_softc *sc = device_get_softc(dev);
673 if (vg->es_vlangroup > sc->sc_info.es_nvlangroups)
676 vg->es_untagged_ports = 0;
677 vg->es_member_ports = 0;
682 /* Note: only supporting 802.1q VLAN config for now */
683 if (sc->sc_vlan.vlan != 1) {
684 vg->es_member_ports = 0;
685 vg->es_untagged_ports = 0;
690 /* Get vlangroup mapping to VLAN id */
691 vid = sc->sc_vlan.vlan_id[vg->es_vlangroup];
692 if ((vid & ETHERSWITCH_VID_VALID) == 0) {
693 /* Not an active vgroup; bail */
699 ret = ar40xx_hw_vtu_get_vlan(sc, vid, &vg->es_member_ports,
700 &vg->es_untagged_ports);
705 vg->es_vid |= ETHERSWITCH_VID_VALID;
712 * Set the current VLAN group (per-port, ISL, dot1q) configuration.
714 * For now the only supported operating mode is dot1q.
717 ar40xx_setvgroup(device_t dev, etherswitch_vlangroup_t *vg)
719 struct ar40xx_softc *sc = device_get_softc(dev);
722 /* For now we only support 802.1q mode */
723 if (sc->sc_vlan.vlan == 0)
727 vid = sc->sc_vlan.vlan_id[vg->es_vlangroup];
729 * If we have an 802.1q VID and it's different to the current one,
730 * purge the current VTU entry.
733 ((vid & ETHERSWITCH_VID_VALID) != 0) &&
734 ((vid & ETHERSWITCH_VID_MASK) !=
735 (vg->es_vid & ETHERSWITCH_VID_MASK))) {
736 AR40XX_DPRINTF(sc, AR40XX_DBG_VTU_OP,
737 "%s: purging VID %d first\n", __func__, vid);
738 err = ar40xx_hw_vtu_flush(sc);
746 vid = vg->es_vid & ETHERSWITCH_VID_MASK;
747 sc->sc_vlan.vlan_id[vg->es_vlangroup] = vid;
749 /* Setting it to 0 disables the group */
753 /* Add valid bit for this entry */
754 sc->sc_vlan.vlan_id[vg->es_vlangroup] = vid | ETHERSWITCH_VID_VALID;
756 /* Update hardware */
757 err = ar40xx_hw_vtu_load_vlan(sc, vid, vg->es_member_ports,
758 vg->es_untagged_ports);
764 /* Update the config for the given entry */
765 sc->sc_vlan.vlan_ports[vg->es_vlangroup] = vg->es_member_ports;
766 sc->sc_vlan.vlan_untagged[vg->es_vlangroup] = vg->es_untagged_ports;
774 * Get the current configuration mode.
777 ar40xx_getconf(device_t dev, etherswitch_conf_t *conf)
779 struct ar40xx_softc *sc = device_get_softc(dev);
784 /* Only support dot1q VLAN for now */
785 conf->cmd = ETHERSWITCH_CONF_VLAN_MODE;
786 conf->vlan_mode = ETHERSWITCH_VLAN_DOT1Q;
788 /* Switch MAC address */
789 ret = ar40xx_hw_read_switch_mac_address(sc, &conf->switch_macaddr);
791 conf->cmd |= ETHERSWITCH_CONF_SWITCH_MACADDR;
799 * Set the current configuration and do a switch reset.
801 * For now the only supported operating mode is dot1q, don't
802 * allow it to be set to non-dot1q.
805 ar40xx_setconf(device_t dev, etherswitch_conf_t *conf)
807 struct ar40xx_softc *sc = device_get_softc(dev);
810 if (conf->cmd & ETHERSWITCH_CONF_VLAN_MODE) {
811 /* Only support dot1q VLAN for now */
812 if (conf->vlan_mode != ETHERSWITCH_VLAN_DOT1Q)
816 if (conf->cmd & ETHERSWITCH_CONF_SWITCH_MACADDR) {
818 ret = ar40xx_hw_read_switch_mac_address(sc,
819 &conf->switch_macaddr);
827 * Flush all ATU entries.
830 ar40xx_atu_flush_all(device_t dev)
832 struct ar40xx_softc *sc = device_get_softc(dev);
836 ret = ar40xx_hw_atu_flush_all(sc);
842 * Flush all ATU entries for the given port.
845 ar40xx_atu_flush_port(device_t dev, int port)
847 struct ar40xx_softc *sc = device_get_softc(dev);
851 ret = ar40xx_hw_atu_flush_port(sc, port);
857 * Load the ATU table into local storage so it can be iterated
861 ar40xx_atu_fetch_table(device_t dev, etherswitch_atu_table_t *table)
863 struct ar40xx_softc *sc = device_get_softc(dev);
866 memset(&sc->atu.entries, 0, sizeof(sc->atu.entries));
868 table->es_nitems = 0;
873 err = ar40xx_hw_atu_fetch_entry(sc, NULL, 0);
877 while (nitems < AR40XX_NUM_ATU_ENTRIES) {
878 err = ar40xx_hw_atu_fetch_entry(sc,
879 &sc->atu.entries[nitems], 1);
882 sc->atu.entries[nitems].id = nitems;
886 sc->atu.count = nitems;
887 table->es_nitems = nitems;
894 * Iterate over the ATU table entries that have been previously
898 ar40xx_atu_fetch_table_entry(device_t dev, etherswitch_atu_entry_t *e)
900 struct ar40xx_softc *sc = device_get_softc(dev);
905 if (id > sc->atu.count) {
909 memcpy(e, &sc->atu.entries[id], sizeof(*e));
915 static device_method_t ar40xx_methods[] = {
916 /* Device interface */
917 DEVMETHOD(device_probe, ar40xx_probe),
918 DEVMETHOD(device_attach, ar40xx_attach),
919 DEVMETHOD(device_detach, ar40xx_detach),
922 DEVMETHOD(bus_add_child, device_add_child_ordered),
925 DEVMETHOD(miibus_readreg, ar40xx_readphy),
926 DEVMETHOD(miibus_writereg, ar40xx_writephy),
927 DEVMETHOD(miibus_statchg, ar40xx_statchg),
930 DEVMETHOD(mdio_readreg, ar40xx_readphy),
931 DEVMETHOD(mdio_writereg, ar40xx_writephy),
933 /* etherswitch interface */
934 DEVMETHOD(etherswitch_lock, ar40xx_lock),
935 DEVMETHOD(etherswitch_unlock, ar40xx_unlock),
936 DEVMETHOD(etherswitch_getinfo, ar40xx_getinfo),
937 DEVMETHOD(etherswitch_readreg, ar40xx_readreg),
938 DEVMETHOD(etherswitch_writereg, ar40xx_writereg),
939 DEVMETHOD(etherswitch_readphyreg, ar40xx_readphy),
940 DEVMETHOD(etherswitch_writephyreg, ar40xx_writephy),
941 DEVMETHOD(etherswitch_getport, ar40xx_getport),
942 DEVMETHOD(etherswitch_setport, ar40xx_setport),
943 DEVMETHOD(etherswitch_getvgroup, ar40xx_getvgroup),
944 DEVMETHOD(etherswitch_setvgroup, ar40xx_setvgroup),
945 DEVMETHOD(etherswitch_getconf, ar40xx_getconf),
946 DEVMETHOD(etherswitch_setconf, ar40xx_setconf),
947 DEVMETHOD(etherswitch_flush_all, ar40xx_atu_flush_all),
948 DEVMETHOD(etherswitch_flush_port, ar40xx_atu_flush_port),
949 DEVMETHOD(etherswitch_fetch_table, ar40xx_atu_fetch_table),
950 DEVMETHOD(etherswitch_fetch_table_entry,
951 ar40xx_atu_fetch_table_entry),
956 DEFINE_CLASS_0(ar40xx, ar40xx_driver, ar40xx_methods,
957 sizeof(struct ar40xx_softc));
958 static devclass_t ar40xx_devclass;
960 DRIVER_MODULE(ar40xx, simplebus, ar40xx_driver, ar40xx_devclass, 0, 0);
961 DRIVER_MODULE(ar40xx, ofwbus, ar40xx_driver, ar40xx_devclass, 0, 0);
962 DRIVER_MODULE(miibus, ar40xx, miibus_driver, 0, 0);
963 DRIVER_MODULE(mdio, ar40xx, mdio_driver, mdio_devclass, 0, 0);
964 DRIVER_MODULE(etherswitch, ar40xx, etherswitch_driver, etherswitch_devclass, 0, 0);
965 MODULE_DEPEND(ar40xx, mdio, 1, 1, 1);
966 MODULE_DEPEND(ar40xx, miibus, 1, 1, 1);
967 MODULE_DEPEND(ar40xx, etherswitch, 1, 1, 1);
968 MODULE_VERSION(ar40xx, 1);