2 * Copyright (c) 2011-2012 Stefan Bethke.
3 * Copyright (c) 2014 Adrian Chadd.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #include <sys/param.h>
32 #include <sys/errno.h>
33 #include <sys/kernel.h>
34 #include <sys/module.h>
35 #include <sys/socket.h>
36 #include <sys/sockio.h>
37 #include <sys/sysctl.h>
38 #include <sys/systm.h>
41 #include <net/if_arp.h>
42 #include <net/ethernet.h>
43 #include <net/if_dl.h>
44 #include <net/if_media.h>
45 #include <net/if_types.h>
47 #include <machine/bus.h>
48 #include <dev/iicbus/iic.h>
49 #include <dev/iicbus/iiconf.h>
50 #include <dev/iicbus/iicbus.h>
51 #include <dev/mii/mii.h>
52 #include <dev/mii/miivar.h>
53 #include <dev/etherswitch/mdio.h>
55 #include <dev/etherswitch/etherswitch.h>
57 #include <dev/etherswitch/arswitch/arswitchreg.h>
58 #include <dev/etherswitch/arswitch/arswitchvar.h>
59 #include <dev/etherswitch/arswitch/arswitch_reg.h>
60 #include <dev/etherswitch/arswitch/arswitch_phy.h>
61 #include <dev/etherswitch/arswitch/arswitch_vlans.h>
63 #include <dev/etherswitch/arswitch/arswitch_8327.h>
66 #include "miibus_if.h"
67 #include "etherswitch_if.h"
72 * There should be a default hardware setup hint set for the default
73 * switch config. Otherwise the default is "all ports in one vlangroup",
74 * which means both CPU ports can see each other and that will quickly
75 * lead to traffic storms/loops.
79 ar8327_vlan_op(struct arswitch_softc *sc, uint32_t op, uint32_t vid,
85 * Wait for the "done" bit to finish.
87 if (arswitch_waitreg(sc->sc_dev, AR8327_REG_VTU_FUNC1,
88 AR8327_VTU_FUNC1_BUSY, 0, 5))
92 * If it's a "load" operation, then ensure 'data' is loaded
95 if ((op & AR8327_VTU_FUNC1_OP) == AR8327_VTU_FUNC1_OP_LOAD) {
96 err = arswitch_writereg(sc->sc_dev, AR8327_REG_VTU_FUNC0, data);
104 op |= ((vid & 0xfff) << AR8327_VTU_FUNC1_VID_S);
107 * Set busy bit to start loading in the command.
109 op |= AR8327_VTU_FUNC1_BUSY;
110 arswitch_writereg(sc->sc_dev, AR8327_REG_VTU_FUNC1, op);
113 * Finally - wait for it to load.
115 if (arswitch_waitreg(sc->sc_dev, AR8327_REG_VTU_FUNC1,
116 AR8327_VTU_FUNC1_BUSY, 0, 5))
123 ar8327_phy_fixup(struct arswitch_softc *sc, int phy)
126 device_printf(sc->sc_dev,
127 "%s: called; phy=%d; chiprev=%d\n", __func__,
130 switch (sc->chip_rev) {
132 /* For 100M waveform */
133 arswitch_writedbg(sc->sc_dev, phy, 0, 0x02ea);
134 /* Turn on Gigabit clock */
135 arswitch_writedbg(sc->sc_dev, phy, 0x3d, 0x68a0);
139 arswitch_writemmd(sc->sc_dev, phy, 0x7, 0x3c);
140 arswitch_writemmd(sc->sc_dev, phy, 0x4007, 0x0);
143 arswitch_writemmd(sc->sc_dev, phy, 0x3, 0x800d);
144 arswitch_writemmd(sc->sc_dev, phy, 0x4003, 0x803f);
146 arswitch_writedbg(sc->sc_dev, phy, 0x3d, 0x6860);
147 arswitch_writedbg(sc->sc_dev, phy, 0x5, 0x2c46);
148 arswitch_writedbg(sc->sc_dev, phy, 0x3c, 0x6000);
154 ar8327_get_pad_cfg(struct ar8327_pad_cfg *cfg)
166 case AR8327_PAD_MAC2MAC_MII:
167 t = AR8327_PAD_MAC_MII_EN;
169 t |= AR8327_PAD_MAC_MII_RXCLK_SEL;
171 t |= AR8327_PAD_MAC_MII_TXCLK_SEL;
174 case AR8327_PAD_MAC2MAC_GMII:
175 t = AR8327_PAD_MAC_GMII_EN;
177 t |= AR8327_PAD_MAC_GMII_RXCLK_SEL;
179 t |= AR8327_PAD_MAC_GMII_TXCLK_SEL;
182 case AR8327_PAD_MAC_SGMII:
183 t = AR8327_PAD_SGMII_EN;
186 * WAR for the Qualcomm Atheros AP136 board.
187 * It seems that RGMII TX/RX delay settings needs to be
188 * applied for SGMII mode as well, The ethernet is not
189 * reliable without this.
191 t |= cfg->txclk_delay_sel << AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S;
192 t |= cfg->rxclk_delay_sel << AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S;
193 if (cfg->rxclk_delay_en)
194 t |= AR8327_PAD_RGMII_RXCLK_DELAY_EN;
195 if (cfg->txclk_delay_en)
196 t |= AR8327_PAD_RGMII_TXCLK_DELAY_EN;
198 if (cfg->sgmii_delay_en)
199 t |= AR8327_PAD_SGMII_DELAY_EN;
203 case AR8327_PAD_MAC2PHY_MII:
204 t = AR8327_PAD_PHY_MII_EN;
206 t |= AR8327_PAD_PHY_MII_RXCLK_SEL;
208 t |= AR8327_PAD_PHY_MII_TXCLK_SEL;
211 case AR8327_PAD_MAC2PHY_GMII:
212 t = AR8327_PAD_PHY_GMII_EN;
213 if (cfg->pipe_rxclk_sel)
214 t |= AR8327_PAD_PHY_GMII_PIPE_RXCLK_SEL;
216 t |= AR8327_PAD_PHY_GMII_RXCLK_SEL;
218 t |= AR8327_PAD_PHY_GMII_TXCLK_SEL;
221 case AR8327_PAD_MAC_RGMII:
222 t = AR8327_PAD_RGMII_EN;
223 t |= cfg->txclk_delay_sel << AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S;
224 t |= cfg->rxclk_delay_sel << AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S;
225 if (cfg->rxclk_delay_en)
226 t |= AR8327_PAD_RGMII_RXCLK_DELAY_EN;
227 if (cfg->txclk_delay_en)
228 t |= AR8327_PAD_RGMII_TXCLK_DELAY_EN;
231 case AR8327_PAD_PHY_GMII:
232 t = AR8327_PAD_PHYX_GMII_EN;
235 case AR8327_PAD_PHY_RGMII:
236 t = AR8327_PAD_PHYX_RGMII_EN;
239 case AR8327_PAD_PHY_MII:
240 t = AR8327_PAD_PHYX_MII_EN;
248 * Map the hard-coded port config from the switch setup to
249 * the chipset port config (status, duplex, flow, etc.)
252 ar8327_get_port_init_status(struct ar8327_port_cfg *cfg)
256 if (!cfg->force_link)
257 return (AR8X16_PORT_STS_LINK_AUTO);
259 t = AR8X16_PORT_STS_TXMAC | AR8X16_PORT_STS_RXMAC;
260 t |= cfg->duplex ? AR8X16_PORT_STS_DUPLEX : 0;
261 t |= cfg->rxpause ? AR8X16_PORT_STS_RXFLOW : 0;
262 t |= cfg->txpause ? AR8X16_PORT_STS_TXFLOW : 0;
264 switch (cfg->speed) {
265 case AR8327_PORT_SPEED_10:
266 t |= AR8X16_PORT_STS_SPEED_10;
268 case AR8327_PORT_SPEED_100:
269 t |= AR8X16_PORT_STS_SPEED_100;
271 case AR8327_PORT_SPEED_1000:
272 t |= AR8X16_PORT_STS_SPEED_1000;
280 * Fetch the port data for the given port.
282 * This goes and does dirty things with the hints space
283 * to determine what the configuration parameters should be.
285 * Returns 1 if the structure was successfully parsed and
286 * the contents are valid; 0 otherwise.
289 ar8327_fetch_pdata_port(struct arswitch_softc *sc,
290 struct ar8327_port_cfg *pcfg,
296 /* Check if force_link exists */
298 snprintf(sbuf, 128, "port.%d.force_link", port);
299 (void) resource_int_value(device_get_name(sc->sc_dev),
300 device_get_unit(sc->sc_dev),
304 pcfg->force_link = 1;
306 /* force_link is set; let's parse the rest of the fields */
307 snprintf(sbuf, 128, "port.%d.speed", port);
308 if (resource_int_value(device_get_name(sc->sc_dev),
309 device_get_unit(sc->sc_dev),
313 pcfg->speed = AR8327_PORT_SPEED_10;
316 pcfg->speed = AR8327_PORT_SPEED_100;
319 pcfg->speed = AR8327_PORT_SPEED_1000;
322 device_printf(sc->sc_dev,
323 "%s: invalid port %d duplex value (%d)\n",
331 snprintf(sbuf, 128, "port.%d.duplex", port);
332 if (resource_int_value(device_get_name(sc->sc_dev),
333 device_get_unit(sc->sc_dev),
337 snprintf(sbuf, 128, "port.%d.txpause", port);
338 if (resource_int_value(device_get_name(sc->sc_dev),
339 device_get_unit(sc->sc_dev),
343 snprintf(sbuf, 128, "port.%d.rxpause", port);
344 if (resource_int_value(device_get_name(sc->sc_dev),
345 device_get_unit(sc->sc_dev),
350 device_printf(sc->sc_dev,
351 "%s: port %d: speed=%d, duplex=%d, txpause=%d, rxpause=%d\n",
364 * Parse the pad configuration from the boot hints.
366 * The (mostly optional) fields are:
369 * uint32_t rxclk_sel;
370 * uint32_t txclk_sel;
371 * uint32_t txclk_delay_sel;
372 * uint32_t rxclk_delay_sel;
373 * uint32_t txclk_delay_en;
374 * uint32_t rxclk_delay_en;
375 * uint32_t sgmii_delay_en;
376 * uint32_t pipe_rxclk_sel;
378 * If mode isn't in the hints, 0 is returned.
379 * Else the structure is fleshed out and 1 is returned.
382 ar8327_fetch_pdata_pad(struct arswitch_softc *sc,
383 struct ar8327_pad_cfg *pc,
389 /* Check if mode exists */
391 snprintf(sbuf, 128, "pad.%d.mode", pad);
392 if (resource_int_value(device_get_name(sc->sc_dev),
393 device_get_unit(sc->sc_dev),
397 /* assume that 'mode' exists and was found */
400 snprintf(sbuf, 128, "pad.%d.rxclk_sel", pad);
401 if (resource_int_value(device_get_name(sc->sc_dev),
402 device_get_unit(sc->sc_dev),
406 snprintf(sbuf, 128, "pad.%d.txclk_sel", pad);
407 if (resource_int_value(device_get_name(sc->sc_dev),
408 device_get_unit(sc->sc_dev),
412 snprintf(sbuf, 128, "pad.%d.txclk_delay_sel", pad);
413 if (resource_int_value(device_get_name(sc->sc_dev),
414 device_get_unit(sc->sc_dev),
416 pc->txclk_delay_sel = val;
418 snprintf(sbuf, 128, "pad.%d.rxclk_delay_sel", pad);
419 if (resource_int_value(device_get_name(sc->sc_dev),
420 device_get_unit(sc->sc_dev),
422 pc->rxclk_delay_sel = val;
424 snprintf(sbuf, 128, "pad.%d.txclk_delay_en", pad);
425 if (resource_int_value(device_get_name(sc->sc_dev),
426 device_get_unit(sc->sc_dev),
428 pc->txclk_delay_en = val;
430 snprintf(sbuf, 128, "pad.%d.rxclk_delay_en", pad);
431 if (resource_int_value(device_get_name(sc->sc_dev),
432 device_get_unit(sc->sc_dev),
434 pc->rxclk_delay_en = val;
436 snprintf(sbuf, 128, "pad.%d.sgmii_delay_en", pad);
437 if (resource_int_value(device_get_name(sc->sc_dev),
438 device_get_unit(sc->sc_dev),
440 pc->sgmii_delay_en = val;
442 snprintf(sbuf, 128, "pad.%d.pipe_rxclk_sel", pad);
443 if (resource_int_value(device_get_name(sc->sc_dev),
444 device_get_unit(sc->sc_dev),
446 pc->pipe_rxclk_sel = val;
449 device_printf(sc->sc_dev,
450 "%s: pad %d: mode=%d, rxclk_sel=%d, txclk_sel=%d, "
451 "txclk_delay_sel=%d, rxclk_delay_sel=%d, txclk_delay_en=%d, "
452 "rxclk_enable_en=%d, sgmii_delay_en=%d, pipe_rxclk_sel=%d\n",
470 * Fetch the SGMII configuration block from the boot hints.
473 ar8327_fetch_pdata_sgmii(struct arswitch_softc *sc,
474 struct ar8327_sgmii_cfg *scfg)
480 if (resource_int_value(device_get_name(sc->sc_dev),
481 device_get_unit(sc->sc_dev),
482 "sgmii.ctrl", &val) != 0)
484 scfg->sgmii_ctrl = val;
488 if (resource_int_value(device_get_name(sc->sc_dev),
489 device_get_unit(sc->sc_dev),
490 "sgmii.serdes_aen", &val) != 0)
492 scfg->serdes_aen = val;
498 * Fetch the LED configuration from the boot hints.
501 ar8327_fetch_pdata_led(struct arswitch_softc *sc,
502 struct ar8327_led_cfg *lcfg)
507 if (resource_int_value(device_get_name(sc->sc_dev),
508 device_get_unit(sc->sc_dev),
509 "led.ctrl0", &val) != 0)
511 lcfg->led_ctrl0 = val;
514 if (resource_int_value(device_get_name(sc->sc_dev),
515 device_get_unit(sc->sc_dev),
516 "led.ctrl1", &val) != 0)
518 lcfg->led_ctrl1 = val;
521 if (resource_int_value(device_get_name(sc->sc_dev),
522 device_get_unit(sc->sc_dev),
523 "led.ctrl2", &val) != 0)
525 lcfg->led_ctrl2 = val;
528 if (resource_int_value(device_get_name(sc->sc_dev),
529 device_get_unit(sc->sc_dev),
530 "led.ctrl3", &val) != 0)
532 lcfg->led_ctrl3 = val;
535 if (resource_int_value(device_get_name(sc->sc_dev),
536 device_get_unit(sc->sc_dev),
537 "led.open_drain", &val) != 0)
539 lcfg->open_drain = val;
545 * Initialise the ar8327 specific hardware features from
546 * the hints provided in the boot environment.
549 ar8327_init_pdata(struct arswitch_softc *sc)
551 struct ar8327_pad_cfg pc;
552 struct ar8327_port_cfg port_cfg;
553 struct ar8327_sgmii_cfg scfg;
554 struct ar8327_led_cfg lcfg;
555 uint32_t t, new_pos, pos;
558 bzero(&port_cfg, sizeof(port_cfg));
559 sc->ar8327.port0_status = 0;
560 if (ar8327_fetch_pdata_port(sc, &port_cfg, 0))
561 sc->ar8327.port0_status = ar8327_get_port_init_status(&port_cfg);
564 bzero(&port_cfg, sizeof(port_cfg));
565 sc->ar8327.port6_status = 0;
566 if (ar8327_fetch_pdata_port(sc, &port_cfg, 6))
567 sc->ar8327.port6_status = ar8327_get_port_init_status(&port_cfg);
570 bzero(&pc, sizeof(pc));
572 if (ar8327_fetch_pdata_pad(sc, &pc, 0))
573 t = ar8327_get_pad_cfg(&pc);
575 if (AR8X16_IS_SWITCH(sc, AR8337))
576 t |= AR8337_PAD_MAC06_EXCHANGE_EN;
578 arswitch_writereg(sc->sc_dev, AR8327_REG_PAD0_MODE, t);
581 bzero(&pc, sizeof(pc));
583 if (ar8327_fetch_pdata_pad(sc, &pc, 5))
584 t = ar8327_get_pad_cfg(&pc);
585 arswitch_writereg(sc->sc_dev, AR8327_REG_PAD5_MODE, t);
588 bzero(&pc, sizeof(pc));
590 if (ar8327_fetch_pdata_pad(sc, &pc, 6))
591 t = ar8327_get_pad_cfg(&pc);
592 arswitch_writereg(sc->sc_dev, AR8327_REG_PAD6_MODE, t);
594 pos = arswitch_readreg(sc->sc_dev, AR8327_REG_POWER_ON_STRIP);
598 bzero(&lcfg, sizeof(lcfg));
599 if (ar8327_fetch_pdata_led(sc, &lcfg)) {
601 new_pos |= AR8327_POWER_ON_STRIP_LED_OPEN_EN;
603 new_pos &= ~AR8327_POWER_ON_STRIP_LED_OPEN_EN;
605 arswitch_writereg(sc->sc_dev, AR8327_REG_LED_CTRL0,
607 arswitch_writereg(sc->sc_dev, AR8327_REG_LED_CTRL1,
609 arswitch_writereg(sc->sc_dev, AR8327_REG_LED_CTRL2,
611 arswitch_writereg(sc->sc_dev, AR8327_REG_LED_CTRL3,
615 new_pos |= AR8327_POWER_ON_STRIP_POWER_ON_SEL;
619 bzero(&scfg, sizeof(scfg));
620 if (ar8327_fetch_pdata_sgmii(sc, &scfg)) {
621 device_printf(sc->sc_dev, "%s: SGMII cfg?\n", __func__);
623 if (sc->chip_rev == 1)
624 t |= AR8327_SGMII_CTRL_EN_PLL |
625 AR8327_SGMII_CTRL_EN_RX |
626 AR8327_SGMII_CTRL_EN_TX;
628 t &= ~(AR8327_SGMII_CTRL_EN_PLL |
629 AR8327_SGMII_CTRL_EN_RX |
630 AR8327_SGMII_CTRL_EN_TX);
632 arswitch_writereg(sc->sc_dev, AR8327_REG_SGMII_CTRL, t);
635 new_pos &= ~AR8327_POWER_ON_STRIP_SERDES_AEN;
637 new_pos |= AR8327_POWER_ON_STRIP_SERDES_AEN;
640 arswitch_writereg(sc->sc_dev, AR8327_REG_POWER_ON_STRIP, new_pos);
646 ar8327_hw_setup(struct arswitch_softc *sc)
651 /* pdata fetch and setup */
652 err = ar8327_init_pdata(sc);
658 for (i = 0; i < AR8327_NUM_PHYS; i++) {
660 ar8327_phy_fixup(sc, i);
662 /* start PHY autonegotiation? */
663 /* XXX is this done as part of the normal PHY setup? */
667 /* Let things settle */
674 * Initialise other global values, for the AR8327.
677 ar8327_hw_global_setup(struct arswitch_softc *sc)
681 /* enable CPU port and disable mirror port */
682 t = AR8327_FWD_CTRL0_CPU_PORT_EN |
683 AR8327_FWD_CTRL0_MIRROR_PORT;
684 arswitch_writereg(sc->sc_dev, AR8327_REG_FWD_CTRL0, t);
686 /* forward multicast and broadcast frames to CPU */
687 t = (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_UC_FLOOD_S) |
688 (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_MC_FLOOD_S) |
689 (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_BC_FLOOD_S);
690 arswitch_writereg(sc->sc_dev, AR8327_REG_FWD_CTRL1, t);
692 /* enable jumbo frames */
693 /* XXX need to macro-shift the value! */
694 arswitch_modifyreg(sc->sc_dev, AR8327_REG_MAX_FRAME_SIZE,
695 AR8327_MAX_FRAME_SIZE_MTU, 9018 + 8 + 2);
697 /* Enable MIB counters */
698 arswitch_modifyreg(sc->sc_dev, AR8327_REG_MODULE_EN,
699 AR8327_MODULE_EN_MIB, AR8327_MODULE_EN_MIB);
701 /* Disable EEE on all ports due to stability issues */
702 t = arswitch_readreg(sc->sc_dev, AR8327_REG_EEE_CTRL);
703 t |= AR8327_EEE_CTRL_DISABLE_PHY(0) |
704 AR8327_EEE_CTRL_DISABLE_PHY(1) |
705 AR8327_EEE_CTRL_DISABLE_PHY(2) |
706 AR8327_EEE_CTRL_DISABLE_PHY(3) |
707 AR8327_EEE_CTRL_DISABLE_PHY(4);
708 arswitch_writereg(sc->sc_dev, AR8327_REG_EEE_CTRL, t);
710 /* Set the right number of ports */
711 /* GMAC0 (CPU), GMAC1..5 (PHYs), GMAC6 (CPU) */
712 sc->info.es_nports = 7;
718 * Port setup. Called at attach time.
721 ar8327_port_init(struct arswitch_softc *sc, int port)
726 /* For now, port can see all other ports */
729 if (port == AR8X16_PORT_CPU)
730 t = sc->ar8327.port0_status;
732 t = sc->ar8327.port6_status;
734 t = AR8X16_PORT_STS_LINK_AUTO;
736 arswitch_writereg(sc->sc_dev, AR8327_REG_PORT_STATUS(port), t);
737 arswitch_writereg(sc->sc_dev, AR8327_REG_PORT_HEADER(port), 0);
740 * Default to 1 port group.
742 t = 1 << AR8327_PORT_VLAN0_DEF_SVID_S;
743 t |= 1 << AR8327_PORT_VLAN0_DEF_CVID_S;
744 arswitch_writereg(sc->sc_dev, AR8327_REG_PORT_VLAN0(port), t);
746 t = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH << AR8327_PORT_VLAN1_OUT_MODE_S;
747 arswitch_writereg(sc->sc_dev, AR8327_REG_PORT_VLAN1(port), t);
750 * This doesn't configure any ports which this port can "see".
751 * bits 0-6 control which ports a frame coming into this port
752 * can be sent out to.
754 * So by doing this, we're making it impossible to send frames out
757 t = AR8327_PORT_LOOKUP_LEARN;
758 t |= AR8X16_PORT_CTRL_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S;
760 /* So this allows traffic to any port except ourselves */
761 t |= (ports & ~(1 << port));
762 arswitch_writereg(sc->sc_dev, AR8327_REG_PORT_LOOKUP(port), t);
766 ar8327_port_vlan_setup(struct arswitch_softc *sc, etherswitch_port_t *p)
769 /* Check: ADDTAG/STRIPTAG - exclusive */
775 sc->hal.arswitch_vlan_set_pvid(sc, p->es_port, p->es_pvid);
787 * Get the port VLAN configuration.
790 ar8327_port_vlan_get(struct arswitch_softc *sc, etherswitch_port_t *p)
795 /* Retrieve the PVID */
796 sc->hal.arswitch_vlan_get_pvid(sc, p->es_port, &p->es_pvid);
798 /* Retrieve the current port configuration from the VTU */
810 ar8327_port_disable_mirror(struct arswitch_softc *sc, int port)
813 arswitch_modifyreg(sc->sc_dev,
814 AR8327_REG_PORT_LOOKUP(port),
815 AR8327_PORT_LOOKUP_ING_MIRROR_EN,
817 arswitch_modifyreg(sc->sc_dev,
818 AR8327_REG_PORT_HOL_CTRL1(port),
819 AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN,
824 ar8327_reset_vlans(struct arswitch_softc *sc)
830 ARSWITCH_LOCK_ASSERT(sc, MA_NOTOWNED);
833 /* Clear the existing VLAN configuration */
834 memset(sc->vid, 0, sizeof(sc->vid));
839 arswitch_modifyreg(sc->sc_dev, AR8327_REG_FWD_CTRL0,
840 AR8327_FWD_CTRL0_MIRROR_PORT,
841 (0xF << AR8327_FWD_CTRL0_MIRROR_PORT_S));
844 * XXX TODO: disable any Q-in-Q port configuration,
845 * tagging, egress filters, etc.
849 * For now, let's default to one portgroup, just so traffic
850 * flows. All ports can see other ports. There are two CPU GMACs
851 * (GMAC0, GMAC6), GMAC1..GMAC5 are external PHYs.
853 * (ETHERSWITCH_VLAN_PORT)
858 * XXX TODO: set things up correctly for vlans!
860 for (i = 0; i < AR8327_NUM_PORTS; i++) {
863 if (sc->vlan_mode == ETHERSWITCH_VLAN_PORT) {
864 sc->vid[i] = i | ETHERSWITCH_VID_VALID;
865 /* set egress == out_keep */
866 ingress = AR8X16_PORT_VLAN_MODE_PORT_ONLY;
867 /* in_port_only, forward */
868 egress = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH;
869 } else if (sc->vlan_mode == ETHERSWITCH_VLAN_DOT1Q) {
870 ingress = AR8X16_PORT_VLAN_MODE_SECURE;
871 egress = AR8327_PORT_VLAN1_OUT_MODE_UNMOD;
873 /* set egress == out_keep */
874 ingress = AR8X16_PORT_VLAN_MODE_PORT_ONLY;
875 /* in_port_only, forward */
876 egress = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH;
879 /* set pvid = 1; there's only one vlangroup to start with */
880 t = 1 << AR8327_PORT_VLAN0_DEF_SVID_S;
881 t |= 1 << AR8327_PORT_VLAN0_DEF_CVID_S;
882 arswitch_writereg(sc->sc_dev, AR8327_REG_PORT_VLAN0(i), t);
884 t = AR8327_PORT_VLAN1_PORT_VLAN_PROP;
885 t |= egress << AR8327_PORT_VLAN1_OUT_MODE_S;
886 arswitch_writereg(sc->sc_dev, AR8327_REG_PORT_VLAN1(i), t);
888 /* Ports can see other ports */
889 /* XXX not entirely true for dot1q? */
890 t = (ports & ~(1 << i)); /* all ports besides us */
891 t |= AR8327_PORT_LOOKUP_LEARN;
893 t |= ingress << AR8327_PORT_LOOKUP_IN_MODE_S;
894 t |= AR8X16_PORT_CTRL_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S;
895 arswitch_writereg(sc->sc_dev, AR8327_REG_PORT_LOOKUP(i), t);
899 * Disable port mirroring entirely.
901 for (i = 0; i < AR8327_NUM_PORTS; i++) {
902 ar8327_port_disable_mirror(sc, i);
906 * If dot1q - set pvid; dot1q, etc.
908 if (sc->vlan_mode == ETHERSWITCH_VLAN_DOT1Q) {
910 for (i = 0; i < AR8327_NUM_PORTS; i++) {
911 /* Each port - pvid 1 */
912 sc->hal.arswitch_vlan_set_pvid(sc, i, sc->vid[0]);
914 /* Initialise vlan1 - all ports, untagged */
915 sc->hal.arswitch_set_dot1q_vlan(sc, ports, ports, sc->vid[0]);
916 sc->vid[0] |= ETHERSWITCH_VID_VALID;
923 ar8327_vlan_get_port(struct arswitch_softc *sc, uint32_t *ports, int vid)
928 ARSWITCH_LOCK_ASSERT(sc, MA_OWNED);
930 /* For port based vlans the vlanid is the same as the port index. */
931 port = vid & ETHERSWITCH_VID_MASK;
932 reg = arswitch_readreg(sc->sc_dev, AR8327_REG_PORT_LOOKUP(port));
938 ar8327_vlan_set_port(struct arswitch_softc *sc, uint32_t ports, int vid)
942 ARSWITCH_LOCK_ASSERT(sc, MA_OWNED);
944 /* For port based vlans the vlanid is the same as the port index. */
945 port = vid & ETHERSWITCH_VID_MASK;
947 err = arswitch_modifyreg(sc->sc_dev, AR8327_REG_PORT_LOOKUP(port),
948 0x7f, /* vlan membership mask */
957 ar8327_vlan_getvgroup(struct arswitch_softc *sc, etherswitch_vlangroup_t *vg)
960 return (ar8xxx_getvgroup(sc, vg));
964 ar8327_vlan_setvgroup(struct arswitch_softc *sc, etherswitch_vlangroup_t *vg)
967 return (ar8xxx_setvgroup(sc, vg));
971 ar8327_get_pvid(struct arswitch_softc *sc, int port, int *pvid)
975 ARSWITCH_LOCK_ASSERT(sc, MA_OWNED);
978 * XXX for now, assuming it's CVID; likely very wrong!
980 port = port & ETHERSWITCH_VID_MASK;
981 reg = arswitch_readreg(sc->sc_dev, AR8327_REG_PORT_VLAN0(port));
982 reg = reg >> AR8327_PORT_VLAN0_DEF_CVID_S;
990 ar8327_set_pvid(struct arswitch_softc *sc, int port, int pvid)
994 /* Limit pvid to valid values */
997 t = pvid << AR8327_PORT_VLAN0_DEF_SVID_S;
998 t |= pvid << AR8327_PORT_VLAN0_DEF_CVID_S;
999 arswitch_writereg(sc->sc_dev, AR8327_REG_PORT_VLAN0(port), t);
1005 ar8327_atu_flush(struct arswitch_softc *sc)
1010 ret = arswitch_waitreg(sc->sc_dev,
1011 AR8327_REG_ATU_FUNC,
1012 AR8327_ATU_FUNC_BUSY,
1017 device_printf(sc->sc_dev, "%s: waitreg failed\n", __func__);
1020 arswitch_writereg(sc->sc_dev,
1021 AR8327_REG_ATU_FUNC,
1022 AR8327_ATU_FUNC_OP_FLUSH);
1027 ar8327_flush_dot1q_vlan(struct arswitch_softc *sc)
1030 return (ar8327_vlan_op(sc, AR8327_VTU_FUNC1_OP_FLUSH, 0, 0));
1034 ar8327_purge_dot1q_vlan(struct arswitch_softc *sc, int vid)
1037 return (ar8327_vlan_op(sc, AR8327_VTU_FUNC1_OP_PURGE, vid, 0));
1041 ar8327_get_dot1q_vlan(struct arswitch_softc *sc, uint32_t *ports,
1042 uint32_t *untagged_ports, int vid)
1045 uint32_t op, reg, val;
1047 op = AR8327_VTU_FUNC1_OP_GET_ONE;
1049 /* Filter out the vid flags; only grab the VLAN ID */
1052 /* XXX TODO: the VTU here stores egress mode - keep, tag, untagged, none */
1053 r = ar8327_vlan_op(sc, op, vid, 0);
1055 device_printf(sc->sc_dev, "%s: %d: op failed\n", __func__, vid);
1058 reg = arswitch_readreg(sc->sc_dev, AR8327_REG_VTU_FUNC0);
1059 DPRINTF(sc->sc_dev, "%s: %d: reg=0x%08x\n", __func__, vid, reg);
1062 * If any of the bits are set, update the port mask.
1063 * Worry about the port config itself when getport() is called.
1066 for (i = 0; i < AR8327_NUM_PORTS; i++) {
1067 val = reg >> AR8327_VTU_FUNC0_EG_MODE_S(i);
1069 /* XXX KEEP (unmodified?) */
1070 if (val == AR8327_VTU_FUNC0_EG_MODE_TAG) {
1072 } else if (val == AR8327_VTU_FUNC0_EG_MODE_UNTAG) {
1074 *untagged_ports |= (1 << i);
1082 ar8327_set_dot1q_vlan(struct arswitch_softc *sc, uint32_t ports,
1083 uint32_t untagged_ports, int vid)
1086 uint32_t op, val, mode;
1088 op = AR8327_VTU_FUNC1_OP_LOAD;
1092 "%s: vid: %d, ports=0x%08x, untagged_ports=0x%08x\n",
1099 * Mark it as valid; and that it should use per-VLAN MAC table,
1100 * not VID=0 when doing MAC lookups
1102 val = AR8327_VTU_FUNC0_VALID | AR8327_VTU_FUNC0_IVL;
1104 for (i = 0; i < AR8327_NUM_PORTS; i++) {
1105 if ((ports & BIT(i)) == 0)
1106 mode = AR8327_VTU_FUNC0_EG_MODE_NOT;
1107 else if (untagged_ports & BIT(i))
1108 mode = AR8327_VTU_FUNC0_EG_MODE_UNTAG;
1110 mode = AR8327_VTU_FUNC0_EG_MODE_TAG;
1112 val |= mode << AR8327_VTU_FUNC0_EG_MODE_S(i);
1115 return (ar8327_vlan_op(sc, op, vid, val));
1119 ar8327_attach(struct arswitch_softc *sc)
1122 sc->hal.arswitch_hw_setup = ar8327_hw_setup;
1123 sc->hal.arswitch_hw_global_setup = ar8327_hw_global_setup;
1125 sc->hal.arswitch_port_init = ar8327_port_init;
1127 sc->hal.arswitch_vlan_getvgroup = ar8327_vlan_getvgroup;
1128 sc->hal.arswitch_vlan_setvgroup = ar8327_vlan_setvgroup;
1129 sc->hal.arswitch_port_vlan_setup = ar8327_port_vlan_setup;
1130 sc->hal.arswitch_port_vlan_get = ar8327_port_vlan_get;
1131 sc->hal.arswitch_flush_dot1q_vlan = ar8327_flush_dot1q_vlan;
1132 sc->hal.arswitch_purge_dot1q_vlan = ar8327_purge_dot1q_vlan;
1133 sc->hal.arswitch_set_dot1q_vlan = ar8327_set_dot1q_vlan;
1134 sc->hal.arswitch_get_dot1q_vlan = ar8327_get_dot1q_vlan;
1136 sc->hal.arswitch_vlan_init_hw = ar8327_reset_vlans;
1137 sc->hal.arswitch_vlan_get_pvid = ar8327_get_pvid;
1138 sc->hal.arswitch_vlan_set_pvid = ar8327_set_pvid;
1140 sc->hal.arswitch_get_port_vlan = ar8327_vlan_get_port;
1141 sc->hal.arswitch_set_port_vlan = ar8327_vlan_set_port;
1143 sc->hal.arswitch_atu_flush = ar8327_atu_flush;
1146 * Reading the PHY via the MDIO interface currently doesn't
1149 * So for now, just go direct to the PHY registers themselves.
1150 * This has always worked on external devices, but not internal
1151 * devices (AR934x, AR724x, AR933x.)
1153 sc->hal.arswitch_phy_read = arswitch_readphy_external;
1154 sc->hal.arswitch_phy_write = arswitch_writephy_external;
1156 /* Set the switch vlan capabilities. */
1157 sc->info.es_vlan_caps = ETHERSWITCH_VLAN_DOT1Q |
1158 ETHERSWITCH_VLAN_PORT | ETHERSWITCH_VLAN_DOUBLE_TAG;
1159 sc->info.es_nvlangroups = AR8X16_MAX_VLANS;