2 * Copyright (c) 2011-2012 Stefan Bethke.
3 * Copyright (c) 2014 Adrian Chadd.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #include <sys/param.h>
32 #include <sys/errno.h>
33 #include <sys/kernel.h>
34 #include <sys/module.h>
35 #include <sys/socket.h>
36 #include <sys/sockio.h>
37 #include <sys/sysctl.h>
38 #include <sys/systm.h>
41 #include <net/if_arp.h>
42 #include <net/ethernet.h>
43 #include <net/if_dl.h>
44 #include <net/if_media.h>
45 #include <net/if_types.h>
47 #include <machine/bus.h>
48 #include <dev/iicbus/iic.h>
49 #include <dev/iicbus/iiconf.h>
50 #include <dev/iicbus/iicbus.h>
51 #include <dev/mii/mii.h>
52 #include <dev/mii/miivar.h>
53 #include <dev/mdio/mdio.h>
55 #include <dev/etherswitch/etherswitch.h>
57 #include <dev/etherswitch/arswitch/arswitchreg.h>
58 #include <dev/etherswitch/arswitch/arswitchvar.h>
59 #include <dev/etherswitch/arswitch/arswitch_reg.h>
60 #include <dev/etherswitch/arswitch/arswitch_phy.h>
61 #include <dev/etherswitch/arswitch/arswitch_vlans.h>
63 #include <dev/etherswitch/arswitch/arswitch_8327.h>
66 #include "miibus_if.h"
67 #include "etherswitch_if.h"
72 * There should be a default hardware setup hint set for the default
73 * switch config. Otherwise the default is "all ports in one vlangroup",
74 * which means both CPU ports can see each other and that will quickly
75 * lead to traffic storms/loops.
78 /* Map port+led to register+shift */
79 struct ar8327_led_mapping ar8327_led_mapping[AR8327_NUM_PHYS][ETHERSWITCH_PORT_MAX_LEDS] =
82 {AR8327_REG_LED_CTRL0, 14 },
83 {AR8327_REG_LED_CTRL1, 14 },
84 {AR8327_REG_LED_CTRL2, 14 }
87 {AR8327_REG_LED_CTRL3, 8 },
88 {AR8327_REG_LED_CTRL3, 10 },
89 {AR8327_REG_LED_CTRL3, 12 }
92 {AR8327_REG_LED_CTRL3, 14 },
93 {AR8327_REG_LED_CTRL3, 16 },
94 {AR8327_REG_LED_CTRL3, 18 }
97 {AR8327_REG_LED_CTRL3, 20 },
98 {AR8327_REG_LED_CTRL3, 22 },
99 {AR8327_REG_LED_CTRL3, 24 }
102 {AR8327_REG_LED_CTRL0, 30 },
103 {AR8327_REG_LED_CTRL1, 30 },
104 {AR8327_REG_LED_CTRL2, 30 }
109 ar8327_vlan_op(struct arswitch_softc *sc, uint32_t op, uint32_t vid,
115 * Wait for the "done" bit to finish.
117 if (arswitch_waitreg(sc->sc_dev, AR8327_REG_VTU_FUNC1,
118 AR8327_VTU_FUNC1_BUSY, 0, 5))
122 * If it's a "load" operation, then ensure 'data' is loaded
125 if ((op & AR8327_VTU_FUNC1_OP) == AR8327_VTU_FUNC1_OP_LOAD) {
126 err = arswitch_writereg(sc->sc_dev, AR8327_REG_VTU_FUNC0, data);
134 op |= ((vid & 0xfff) << AR8327_VTU_FUNC1_VID_S);
137 * Set busy bit to start loading in the command.
139 op |= AR8327_VTU_FUNC1_BUSY;
140 arswitch_writereg(sc->sc_dev, AR8327_REG_VTU_FUNC1, op);
143 * Finally - wait for it to load.
145 if (arswitch_waitreg(sc->sc_dev, AR8327_REG_VTU_FUNC1,
146 AR8327_VTU_FUNC1_BUSY, 0, 5))
153 ar8327_phy_fixup(struct arswitch_softc *sc, int phy)
156 device_printf(sc->sc_dev,
157 "%s: called; phy=%d; chiprev=%d\n", __func__,
160 switch (sc->chip_rev) {
162 /* For 100M waveform */
163 arswitch_writedbg(sc->sc_dev, phy, 0, 0x02ea);
164 /* Turn on Gigabit clock */
165 arswitch_writedbg(sc->sc_dev, phy, 0x3d, 0x68a0);
169 arswitch_writemmd(sc->sc_dev, phy, 0x7, 0x3c);
170 arswitch_writemmd(sc->sc_dev, phy, 0x4007, 0x0);
173 arswitch_writemmd(sc->sc_dev, phy, 0x3, 0x800d);
174 arswitch_writemmd(sc->sc_dev, phy, 0x4003, 0x803f);
176 arswitch_writedbg(sc->sc_dev, phy, 0x3d, 0x6860);
177 arswitch_writedbg(sc->sc_dev, phy, 0x5, 0x2c46);
178 arswitch_writedbg(sc->sc_dev, phy, 0x3c, 0x6000);
184 ar8327_get_pad_cfg(struct ar8327_pad_cfg *cfg)
196 case AR8327_PAD_MAC2MAC_MII:
197 t = AR8327_PAD_MAC_MII_EN;
199 t |= AR8327_PAD_MAC_MII_RXCLK_SEL;
201 t |= AR8327_PAD_MAC_MII_TXCLK_SEL;
204 case AR8327_PAD_MAC2MAC_GMII:
205 t = AR8327_PAD_MAC_GMII_EN;
207 t |= AR8327_PAD_MAC_GMII_RXCLK_SEL;
209 t |= AR8327_PAD_MAC_GMII_TXCLK_SEL;
212 case AR8327_PAD_MAC_SGMII:
213 t = AR8327_PAD_SGMII_EN;
216 * WAR for the Qualcomm Atheros AP136 board.
217 * It seems that RGMII TX/RX delay settings needs to be
218 * applied for SGMII mode as well, The ethernet is not
219 * reliable without this.
221 t |= cfg->txclk_delay_sel << AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S;
222 t |= cfg->rxclk_delay_sel << AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S;
223 if (cfg->rxclk_delay_en)
224 t |= AR8327_PAD_RGMII_RXCLK_DELAY_EN;
225 if (cfg->txclk_delay_en)
226 t |= AR8327_PAD_RGMII_TXCLK_DELAY_EN;
228 if (cfg->sgmii_delay_en)
229 t |= AR8327_PAD_SGMII_DELAY_EN;
233 case AR8327_PAD_MAC2PHY_MII:
234 t = AR8327_PAD_PHY_MII_EN;
236 t |= AR8327_PAD_PHY_MII_RXCLK_SEL;
238 t |= AR8327_PAD_PHY_MII_TXCLK_SEL;
241 case AR8327_PAD_MAC2PHY_GMII:
242 t = AR8327_PAD_PHY_GMII_EN;
243 if (cfg->pipe_rxclk_sel)
244 t |= AR8327_PAD_PHY_GMII_PIPE_RXCLK_SEL;
246 t |= AR8327_PAD_PHY_GMII_RXCLK_SEL;
248 t |= AR8327_PAD_PHY_GMII_TXCLK_SEL;
251 case AR8327_PAD_MAC_RGMII:
252 t = AR8327_PAD_RGMII_EN;
253 t |= cfg->txclk_delay_sel << AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S;
254 t |= cfg->rxclk_delay_sel << AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S;
255 if (cfg->rxclk_delay_en)
256 t |= AR8327_PAD_RGMII_RXCLK_DELAY_EN;
257 if (cfg->txclk_delay_en)
258 t |= AR8327_PAD_RGMII_TXCLK_DELAY_EN;
261 case AR8327_PAD_PHY_GMII:
262 t = AR8327_PAD_PHYX_GMII_EN;
265 case AR8327_PAD_PHY_RGMII:
266 t = AR8327_PAD_PHYX_RGMII_EN;
269 case AR8327_PAD_PHY_MII:
270 t = AR8327_PAD_PHYX_MII_EN;
278 * Map the hard-coded port config from the switch setup to
279 * the chipset port config (status, duplex, flow, etc.)
282 ar8327_get_port_init_status(struct ar8327_port_cfg *cfg)
286 if (!cfg->force_link)
287 return (AR8X16_PORT_STS_LINK_AUTO);
289 t = AR8X16_PORT_STS_TXMAC | AR8X16_PORT_STS_RXMAC;
290 t |= cfg->duplex ? AR8X16_PORT_STS_DUPLEX : 0;
291 t |= cfg->rxpause ? AR8X16_PORT_STS_RXFLOW : 0;
292 t |= cfg->txpause ? AR8X16_PORT_STS_TXFLOW : 0;
294 switch (cfg->speed) {
295 case AR8327_PORT_SPEED_10:
296 t |= AR8X16_PORT_STS_SPEED_10;
298 case AR8327_PORT_SPEED_100:
299 t |= AR8X16_PORT_STS_SPEED_100;
301 case AR8327_PORT_SPEED_1000:
302 t |= AR8X16_PORT_STS_SPEED_1000;
310 * Fetch the port data for the given port.
312 * This goes and does dirty things with the hints space
313 * to determine what the configuration parameters should be.
315 * Returns 1 if the structure was successfully parsed and
316 * the contents are valid; 0 otherwise.
319 ar8327_fetch_pdata_port(struct arswitch_softc *sc,
320 struct ar8327_port_cfg *pcfg,
326 /* Check if force_link exists */
328 snprintf(sbuf, 128, "port.%d.force_link", port);
329 (void) resource_int_value(device_get_name(sc->sc_dev),
330 device_get_unit(sc->sc_dev),
334 pcfg->force_link = 1;
336 /* force_link is set; let's parse the rest of the fields */
337 snprintf(sbuf, 128, "port.%d.speed", port);
338 if (resource_int_value(device_get_name(sc->sc_dev),
339 device_get_unit(sc->sc_dev),
343 pcfg->speed = AR8327_PORT_SPEED_10;
346 pcfg->speed = AR8327_PORT_SPEED_100;
349 pcfg->speed = AR8327_PORT_SPEED_1000;
352 device_printf(sc->sc_dev,
353 "%s: invalid port %d duplex value (%d)\n",
361 snprintf(sbuf, 128, "port.%d.duplex", port);
362 if (resource_int_value(device_get_name(sc->sc_dev),
363 device_get_unit(sc->sc_dev),
367 snprintf(sbuf, 128, "port.%d.txpause", port);
368 if (resource_int_value(device_get_name(sc->sc_dev),
369 device_get_unit(sc->sc_dev),
373 snprintf(sbuf, 128, "port.%d.rxpause", port);
374 if (resource_int_value(device_get_name(sc->sc_dev),
375 device_get_unit(sc->sc_dev),
380 device_printf(sc->sc_dev,
381 "%s: port %d: speed=%d, duplex=%d, txpause=%d, rxpause=%d\n",
394 * Parse the pad configuration from the boot hints.
396 * The (mostly optional) fields are:
399 * uint32_t rxclk_sel;
400 * uint32_t txclk_sel;
401 * uint32_t txclk_delay_sel;
402 * uint32_t rxclk_delay_sel;
403 * uint32_t txclk_delay_en;
404 * uint32_t rxclk_delay_en;
405 * uint32_t sgmii_delay_en;
406 * uint32_t pipe_rxclk_sel;
408 * If mode isn't in the hints, 0 is returned.
409 * Else the structure is fleshed out and 1 is returned.
412 ar8327_fetch_pdata_pad(struct arswitch_softc *sc,
413 struct ar8327_pad_cfg *pc,
419 /* Check if mode exists */
421 snprintf(sbuf, 128, "pad.%d.mode", pad);
422 if (resource_int_value(device_get_name(sc->sc_dev),
423 device_get_unit(sc->sc_dev),
427 /* assume that 'mode' exists and was found */
430 snprintf(sbuf, 128, "pad.%d.rxclk_sel", pad);
431 if (resource_int_value(device_get_name(sc->sc_dev),
432 device_get_unit(sc->sc_dev),
436 snprintf(sbuf, 128, "pad.%d.txclk_sel", pad);
437 if (resource_int_value(device_get_name(sc->sc_dev),
438 device_get_unit(sc->sc_dev),
442 snprintf(sbuf, 128, "pad.%d.txclk_delay_sel", pad);
443 if (resource_int_value(device_get_name(sc->sc_dev),
444 device_get_unit(sc->sc_dev),
446 pc->txclk_delay_sel = val;
448 snprintf(sbuf, 128, "pad.%d.rxclk_delay_sel", pad);
449 if (resource_int_value(device_get_name(sc->sc_dev),
450 device_get_unit(sc->sc_dev),
452 pc->rxclk_delay_sel = val;
454 snprintf(sbuf, 128, "pad.%d.txclk_delay_en", pad);
455 if (resource_int_value(device_get_name(sc->sc_dev),
456 device_get_unit(sc->sc_dev),
458 pc->txclk_delay_en = val;
460 snprintf(sbuf, 128, "pad.%d.rxclk_delay_en", pad);
461 if (resource_int_value(device_get_name(sc->sc_dev),
462 device_get_unit(sc->sc_dev),
464 pc->rxclk_delay_en = val;
466 snprintf(sbuf, 128, "pad.%d.sgmii_delay_en", pad);
467 if (resource_int_value(device_get_name(sc->sc_dev),
468 device_get_unit(sc->sc_dev),
470 pc->sgmii_delay_en = val;
472 snprintf(sbuf, 128, "pad.%d.pipe_rxclk_sel", pad);
473 if (resource_int_value(device_get_name(sc->sc_dev),
474 device_get_unit(sc->sc_dev),
476 pc->pipe_rxclk_sel = val;
479 device_printf(sc->sc_dev,
480 "%s: pad %d: mode=%d, rxclk_sel=%d, txclk_sel=%d, "
481 "txclk_delay_sel=%d, rxclk_delay_sel=%d, txclk_delay_en=%d, "
482 "rxclk_enable_en=%d, sgmii_delay_en=%d, pipe_rxclk_sel=%d\n",
500 * Fetch the SGMII configuration block from the boot hints.
503 ar8327_fetch_pdata_sgmii(struct arswitch_softc *sc,
504 struct ar8327_sgmii_cfg *scfg)
510 if (resource_int_value(device_get_name(sc->sc_dev),
511 device_get_unit(sc->sc_dev),
512 "sgmii.ctrl", &val) != 0)
514 scfg->sgmii_ctrl = val;
518 if (resource_int_value(device_get_name(sc->sc_dev),
519 device_get_unit(sc->sc_dev),
520 "sgmii.serdes_aen", &val) != 0)
522 scfg->serdes_aen = val;
528 * Fetch the LED configuration from the boot hints.
531 ar8327_fetch_pdata_led(struct arswitch_softc *sc,
532 struct ar8327_led_cfg *lcfg)
537 if (resource_int_value(device_get_name(sc->sc_dev),
538 device_get_unit(sc->sc_dev),
539 "led.ctrl0", &val) != 0)
541 lcfg->led_ctrl0 = val;
544 if (resource_int_value(device_get_name(sc->sc_dev),
545 device_get_unit(sc->sc_dev),
546 "led.ctrl1", &val) != 0)
548 lcfg->led_ctrl1 = val;
551 if (resource_int_value(device_get_name(sc->sc_dev),
552 device_get_unit(sc->sc_dev),
553 "led.ctrl2", &val) != 0)
555 lcfg->led_ctrl2 = val;
558 if (resource_int_value(device_get_name(sc->sc_dev),
559 device_get_unit(sc->sc_dev),
560 "led.ctrl3", &val) != 0)
562 lcfg->led_ctrl3 = val;
565 if (resource_int_value(device_get_name(sc->sc_dev),
566 device_get_unit(sc->sc_dev),
567 "led.open_drain", &val) != 0)
569 lcfg->open_drain = val;
575 * Initialise the ar8327 specific hardware features from
576 * the hints provided in the boot environment.
579 ar8327_init_pdata(struct arswitch_softc *sc)
581 struct ar8327_pad_cfg pc;
582 struct ar8327_port_cfg port_cfg;
583 struct ar8327_sgmii_cfg scfg;
584 struct ar8327_led_cfg lcfg;
585 uint32_t t, new_pos, pos;
588 bzero(&port_cfg, sizeof(port_cfg));
589 sc->ar8327.port0_status = 0;
590 if (ar8327_fetch_pdata_port(sc, &port_cfg, 0))
591 sc->ar8327.port0_status = ar8327_get_port_init_status(&port_cfg);
594 bzero(&port_cfg, sizeof(port_cfg));
595 sc->ar8327.port6_status = 0;
596 if (ar8327_fetch_pdata_port(sc, &port_cfg, 6))
597 sc->ar8327.port6_status = ar8327_get_port_init_status(&port_cfg);
600 bzero(&pc, sizeof(pc));
602 if (ar8327_fetch_pdata_pad(sc, &pc, 0))
603 t = ar8327_get_pad_cfg(&pc);
605 if (AR8X16_IS_SWITCH(sc, AR8337))
606 t |= AR8337_PAD_MAC06_EXCHANGE_EN;
608 arswitch_writereg(sc->sc_dev, AR8327_REG_PAD0_MODE, t);
611 bzero(&pc, sizeof(pc));
613 if (ar8327_fetch_pdata_pad(sc, &pc, 5))
614 t = ar8327_get_pad_cfg(&pc);
615 arswitch_writereg(sc->sc_dev, AR8327_REG_PAD5_MODE, t);
618 bzero(&pc, sizeof(pc));
620 if (ar8327_fetch_pdata_pad(sc, &pc, 6))
621 t = ar8327_get_pad_cfg(&pc);
622 arswitch_writereg(sc->sc_dev, AR8327_REG_PAD6_MODE, t);
624 pos = arswitch_readreg(sc->sc_dev, AR8327_REG_POWER_ON_STRIP);
628 bzero(&lcfg, sizeof(lcfg));
629 if (ar8327_fetch_pdata_led(sc, &lcfg)) {
631 new_pos |= AR8327_POWER_ON_STRIP_LED_OPEN_EN;
633 new_pos &= ~AR8327_POWER_ON_STRIP_LED_OPEN_EN;
635 arswitch_writereg(sc->sc_dev, AR8327_REG_LED_CTRL0,
637 arswitch_writereg(sc->sc_dev, AR8327_REG_LED_CTRL1,
639 arswitch_writereg(sc->sc_dev, AR8327_REG_LED_CTRL2,
641 arswitch_writereg(sc->sc_dev, AR8327_REG_LED_CTRL3,
645 new_pos |= AR8327_POWER_ON_STRIP_POWER_ON_SEL;
649 bzero(&scfg, sizeof(scfg));
650 if (ar8327_fetch_pdata_sgmii(sc, &scfg)) {
651 device_printf(sc->sc_dev, "%s: SGMII cfg?\n", __func__);
653 if (sc->chip_rev == 1)
654 t |= AR8327_SGMII_CTRL_EN_PLL |
655 AR8327_SGMII_CTRL_EN_RX |
656 AR8327_SGMII_CTRL_EN_TX;
658 t &= ~(AR8327_SGMII_CTRL_EN_PLL |
659 AR8327_SGMII_CTRL_EN_RX |
660 AR8327_SGMII_CTRL_EN_TX);
662 arswitch_writereg(sc->sc_dev, AR8327_REG_SGMII_CTRL, t);
665 new_pos &= ~AR8327_POWER_ON_STRIP_SERDES_AEN;
667 new_pos |= AR8327_POWER_ON_STRIP_SERDES_AEN;
670 arswitch_writereg(sc->sc_dev, AR8327_REG_POWER_ON_STRIP, new_pos);
676 ar8327_hw_setup(struct arswitch_softc *sc)
681 /* pdata fetch and setup */
682 err = ar8327_init_pdata(sc);
688 for (i = 0; i < AR8327_NUM_PHYS; i++) {
690 ar8327_phy_fixup(sc, i);
692 /* start PHY autonegotiation? */
693 /* XXX is this done as part of the normal PHY setup? */
697 /* Let things settle */
704 * Initialise other global values, for the AR8327.
707 ar8327_hw_global_setup(struct arswitch_softc *sc)
713 /* enable CPU port and disable mirror port */
714 t = AR8327_FWD_CTRL0_CPU_PORT_EN |
715 AR8327_FWD_CTRL0_MIRROR_PORT;
716 arswitch_writereg(sc->sc_dev, AR8327_REG_FWD_CTRL0, t);
718 /* forward multicast and broadcast frames to CPU */
719 t = (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_UC_FLOOD_S) |
720 (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_MC_FLOOD_S) |
721 (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_BC_FLOOD_S);
722 arswitch_writereg(sc->sc_dev, AR8327_REG_FWD_CTRL1, t);
724 /* enable jumbo frames */
725 /* XXX need to macro-shift the value! */
726 arswitch_modifyreg(sc->sc_dev, AR8327_REG_MAX_FRAME_SIZE,
727 AR8327_MAX_FRAME_SIZE_MTU, 9018 + 8 + 2);
729 /* Enable MIB counters */
730 arswitch_modifyreg(sc->sc_dev, AR8327_REG_MODULE_EN,
731 AR8327_MODULE_EN_MIB, AR8327_MODULE_EN_MIB);
733 /* Disable EEE on all ports due to stability issues */
734 t = arswitch_readreg(sc->sc_dev, AR8327_REG_EEE_CTRL);
735 t |= AR8327_EEE_CTRL_DISABLE_PHY(0) |
736 AR8327_EEE_CTRL_DISABLE_PHY(1) |
737 AR8327_EEE_CTRL_DISABLE_PHY(2) |
738 AR8327_EEE_CTRL_DISABLE_PHY(3) |
739 AR8327_EEE_CTRL_DISABLE_PHY(4);
740 arswitch_writereg(sc->sc_dev, AR8327_REG_EEE_CTRL, t);
742 /* Set the right number of ports */
743 /* GMAC0 (CPU), GMAC1..5 (PHYs), GMAC6 (CPU) */
744 sc->info.es_nports = 7;
751 * Port setup. Called at attach time.
754 ar8327_port_init(struct arswitch_softc *sc, int port)
759 /* For now, port can see all other ports */
762 if (port == AR8X16_PORT_CPU)
763 t = sc->ar8327.port0_status;
765 t = sc->ar8327.port6_status;
767 t = AR8X16_PORT_STS_LINK_AUTO;
769 arswitch_writereg(sc->sc_dev, AR8327_REG_PORT_STATUS(port), t);
770 arswitch_writereg(sc->sc_dev, AR8327_REG_PORT_HEADER(port), 0);
773 * Default to 1 port group.
775 t = 1 << AR8327_PORT_VLAN0_DEF_SVID_S;
776 t |= 1 << AR8327_PORT_VLAN0_DEF_CVID_S;
777 arswitch_writereg(sc->sc_dev, AR8327_REG_PORT_VLAN0(port), t);
779 t = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH << AR8327_PORT_VLAN1_OUT_MODE_S;
780 arswitch_writereg(sc->sc_dev, AR8327_REG_PORT_VLAN1(port), t);
783 * This doesn't configure any ports which this port can "see".
784 * bits 0-6 control which ports a frame coming into this port
785 * can be sent out to.
787 * So by doing this, we're making it impossible to send frames out
790 t = AR8327_PORT_LOOKUP_LEARN;
791 t |= AR8X16_PORT_CTRL_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S;
793 /* So this allows traffic to any port except ourselves */
794 t |= (ports & ~(1 << port));
795 arswitch_writereg(sc->sc_dev, AR8327_REG_PORT_LOOKUP(port), t);
799 ar8327_port_vlan_setup(struct arswitch_softc *sc, etherswitch_port_t *p)
802 /* Check: ADDTAG/STRIPTAG - exclusive */
808 sc->hal.arswitch_vlan_set_pvid(sc, p->es_port, p->es_pvid);
820 * Get the port VLAN configuration.
823 ar8327_port_vlan_get(struct arswitch_softc *sc, etherswitch_port_t *p)
828 /* Retrieve the PVID */
829 sc->hal.arswitch_vlan_get_pvid(sc, p->es_port, &p->es_pvid);
831 /* Retrieve the current port configuration from the VTU */
843 ar8327_port_disable_mirror(struct arswitch_softc *sc, int port)
846 arswitch_modifyreg(sc->sc_dev,
847 AR8327_REG_PORT_LOOKUP(port),
848 AR8327_PORT_LOOKUP_ING_MIRROR_EN,
850 arswitch_modifyreg(sc->sc_dev,
851 AR8327_REG_PORT_HOL_CTRL1(port),
852 AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN,
857 ar8327_reset_vlans(struct arswitch_softc *sc)
863 ARSWITCH_LOCK_ASSERT(sc, MA_NOTOWNED);
866 /* Clear the existing VLAN configuration */
867 memset(sc->vid, 0, sizeof(sc->vid));
872 arswitch_modifyreg(sc->sc_dev, AR8327_REG_FWD_CTRL0,
873 AR8327_FWD_CTRL0_MIRROR_PORT,
874 (0xF << AR8327_FWD_CTRL0_MIRROR_PORT_S));
877 * XXX TODO: disable any Q-in-Q port configuration,
878 * tagging, egress filters, etc.
882 * For now, let's default to one portgroup, just so traffic
883 * flows. All ports can see other ports. There are two CPU GMACs
884 * (GMAC0, GMAC6), GMAC1..GMAC5 are external PHYs.
886 * (ETHERSWITCH_VLAN_PORT)
891 * XXX TODO: set things up correctly for vlans!
893 for (i = 0; i < AR8327_NUM_PORTS; i++) {
896 if (sc->vlan_mode == ETHERSWITCH_VLAN_PORT) {
897 sc->vid[i] = i | ETHERSWITCH_VID_VALID;
898 /* set egress == out_keep */
899 ingress = AR8X16_PORT_VLAN_MODE_PORT_ONLY;
900 /* in_port_only, forward */
901 egress = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH;
902 } else if (sc->vlan_mode == ETHERSWITCH_VLAN_DOT1Q) {
903 ingress = AR8X16_PORT_VLAN_MODE_SECURE;
904 egress = AR8327_PORT_VLAN1_OUT_MODE_UNMOD;
906 /* set egress == out_keep */
907 ingress = AR8X16_PORT_VLAN_MODE_PORT_ONLY;
908 /* in_port_only, forward */
909 egress = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH;
912 /* set pvid = 1; there's only one vlangroup to start with */
913 t = 1 << AR8327_PORT_VLAN0_DEF_SVID_S;
914 t |= 1 << AR8327_PORT_VLAN0_DEF_CVID_S;
915 arswitch_writereg(sc->sc_dev, AR8327_REG_PORT_VLAN0(i), t);
917 t = AR8327_PORT_VLAN1_PORT_VLAN_PROP;
918 t |= egress << AR8327_PORT_VLAN1_OUT_MODE_S;
919 arswitch_writereg(sc->sc_dev, AR8327_REG_PORT_VLAN1(i), t);
921 /* Ports can see other ports */
922 /* XXX not entirely true for dot1q? */
923 t = (ports & ~(1 << i)); /* all ports besides us */
924 t |= AR8327_PORT_LOOKUP_LEARN;
926 t |= ingress << AR8327_PORT_LOOKUP_IN_MODE_S;
927 t |= AR8X16_PORT_CTRL_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S;
928 arswitch_writereg(sc->sc_dev, AR8327_REG_PORT_LOOKUP(i), t);
932 * Disable port mirroring entirely.
934 for (i = 0; i < AR8327_NUM_PORTS; i++) {
935 ar8327_port_disable_mirror(sc, i);
939 * If dot1q - set pvid; dot1q, etc.
941 if (sc->vlan_mode == ETHERSWITCH_VLAN_DOT1Q) {
943 for (i = 0; i < AR8327_NUM_PORTS; i++) {
944 /* Each port - pvid 1 */
945 sc->hal.arswitch_vlan_set_pvid(sc, i, sc->vid[0]);
947 /* Initialise vlan1 - all ports, untagged */
948 sc->hal.arswitch_set_dot1q_vlan(sc, ports, ports, sc->vid[0]);
949 sc->vid[0] |= ETHERSWITCH_VID_VALID;
956 ar8327_vlan_get_port(struct arswitch_softc *sc, uint32_t *ports, int vid)
961 ARSWITCH_LOCK_ASSERT(sc, MA_OWNED);
963 /* For port based vlans the vlanid is the same as the port index. */
964 port = vid & ETHERSWITCH_VID_MASK;
965 reg = arswitch_readreg(sc->sc_dev, AR8327_REG_PORT_LOOKUP(port));
971 ar8327_vlan_set_port(struct arswitch_softc *sc, uint32_t ports, int vid)
975 ARSWITCH_LOCK_ASSERT(sc, MA_OWNED);
977 /* For port based vlans the vlanid is the same as the port index. */
978 port = vid & ETHERSWITCH_VID_MASK;
980 err = arswitch_modifyreg(sc->sc_dev, AR8327_REG_PORT_LOOKUP(port),
981 0x7f, /* vlan membership mask */
990 ar8327_vlan_getvgroup(struct arswitch_softc *sc, etherswitch_vlangroup_t *vg)
993 return (ar8xxx_getvgroup(sc, vg));
997 ar8327_vlan_setvgroup(struct arswitch_softc *sc, etherswitch_vlangroup_t *vg)
1000 return (ar8xxx_setvgroup(sc, vg));
1004 ar8327_get_pvid(struct arswitch_softc *sc, int port, int *pvid)
1008 ARSWITCH_LOCK_ASSERT(sc, MA_OWNED);
1011 * XXX for now, assuming it's CVID; likely very wrong!
1013 port = port & ETHERSWITCH_VID_MASK;
1014 reg = arswitch_readreg(sc->sc_dev, AR8327_REG_PORT_VLAN0(port));
1015 reg = reg >> AR8327_PORT_VLAN0_DEF_CVID_S;
1023 ar8327_set_pvid(struct arswitch_softc *sc, int port, int pvid)
1027 /* Limit pvid to valid values */
1030 t = pvid << AR8327_PORT_VLAN0_DEF_SVID_S;
1031 t |= pvid << AR8327_PORT_VLAN0_DEF_CVID_S;
1032 arswitch_writereg(sc->sc_dev, AR8327_REG_PORT_VLAN0(port), t);
1038 ar8327_atu_flush(struct arswitch_softc *sc)
1043 ret = arswitch_waitreg(sc->sc_dev,
1044 AR8327_REG_ATU_FUNC,
1045 AR8327_ATU_FUNC_BUSY,
1050 device_printf(sc->sc_dev, "%s: waitreg failed\n", __func__);
1053 arswitch_writereg(sc->sc_dev,
1054 AR8327_REG_ATU_FUNC,
1055 AR8327_ATU_FUNC_OP_FLUSH);
1060 ar8327_flush_dot1q_vlan(struct arswitch_softc *sc)
1063 return (ar8327_vlan_op(sc, AR8327_VTU_FUNC1_OP_FLUSH, 0, 0));
1067 ar8327_purge_dot1q_vlan(struct arswitch_softc *sc, int vid)
1070 return (ar8327_vlan_op(sc, AR8327_VTU_FUNC1_OP_PURGE, vid, 0));
1074 ar8327_get_dot1q_vlan(struct arswitch_softc *sc, uint32_t *ports,
1075 uint32_t *untagged_ports, int vid)
1078 uint32_t op, reg, val;
1080 op = AR8327_VTU_FUNC1_OP_GET_ONE;
1082 /* Filter out the vid flags; only grab the VLAN ID */
1085 /* XXX TODO: the VTU here stores egress mode - keep, tag, untagged, none */
1086 r = ar8327_vlan_op(sc, op, vid, 0);
1088 device_printf(sc->sc_dev, "%s: %d: op failed\n", __func__, vid);
1091 reg = arswitch_readreg(sc->sc_dev, AR8327_REG_VTU_FUNC0);
1092 DPRINTF(sc, ARSWITCH_DBG_REGIO, "%s: %d: reg=0x%08x\n", __func__, vid, reg);
1095 * If any of the bits are set, update the port mask.
1096 * Worry about the port config itself when getport() is called.
1099 for (i = 0; i < AR8327_NUM_PORTS; i++) {
1100 val = reg >> AR8327_VTU_FUNC0_EG_MODE_S(i);
1102 /* XXX KEEP (unmodified?) */
1103 if (val == AR8327_VTU_FUNC0_EG_MODE_TAG) {
1105 } else if (val == AR8327_VTU_FUNC0_EG_MODE_UNTAG) {
1107 *untagged_ports |= (1 << i);
1115 ar8327_set_dot1q_vlan(struct arswitch_softc *sc, uint32_t ports,
1116 uint32_t untagged_ports, int vid)
1119 uint32_t op, val, mode;
1121 op = AR8327_VTU_FUNC1_OP_LOAD;
1124 DPRINTF(sc, ARSWITCH_DBG_VLAN,
1125 "%s: vid: %d, ports=0x%08x, untagged_ports=0x%08x\n",
1132 * Mark it as valid; and that it should use per-VLAN MAC table,
1133 * not VID=0 when doing MAC lookups
1135 val = AR8327_VTU_FUNC0_VALID | AR8327_VTU_FUNC0_IVL;
1137 for (i = 0; i < AR8327_NUM_PORTS; i++) {
1138 if ((ports & BIT(i)) == 0)
1139 mode = AR8327_VTU_FUNC0_EG_MODE_NOT;
1140 else if (untagged_ports & BIT(i))
1141 mode = AR8327_VTU_FUNC0_EG_MODE_UNTAG;
1143 mode = AR8327_VTU_FUNC0_EG_MODE_TAG;
1145 val |= mode << AR8327_VTU_FUNC0_EG_MODE_S(i);
1148 return (ar8327_vlan_op(sc, op, vid, val));
1152 ar8327_attach(struct arswitch_softc *sc)
1155 sc->hal.arswitch_hw_setup = ar8327_hw_setup;
1156 sc->hal.arswitch_hw_global_setup = ar8327_hw_global_setup;
1158 sc->hal.arswitch_port_init = ar8327_port_init;
1160 sc->hal.arswitch_vlan_getvgroup = ar8327_vlan_getvgroup;
1161 sc->hal.arswitch_vlan_setvgroup = ar8327_vlan_setvgroup;
1162 sc->hal.arswitch_port_vlan_setup = ar8327_port_vlan_setup;
1163 sc->hal.arswitch_port_vlan_get = ar8327_port_vlan_get;
1164 sc->hal.arswitch_flush_dot1q_vlan = ar8327_flush_dot1q_vlan;
1165 sc->hal.arswitch_purge_dot1q_vlan = ar8327_purge_dot1q_vlan;
1166 sc->hal.arswitch_set_dot1q_vlan = ar8327_set_dot1q_vlan;
1167 sc->hal.arswitch_get_dot1q_vlan = ar8327_get_dot1q_vlan;
1169 sc->hal.arswitch_vlan_init_hw = ar8327_reset_vlans;
1170 sc->hal.arswitch_vlan_get_pvid = ar8327_get_pvid;
1171 sc->hal.arswitch_vlan_set_pvid = ar8327_set_pvid;
1173 sc->hal.arswitch_get_port_vlan = ar8327_vlan_get_port;
1174 sc->hal.arswitch_set_port_vlan = ar8327_vlan_set_port;
1176 sc->hal.arswitch_atu_flush = ar8327_atu_flush;
1179 * Reading the PHY via the MDIO interface currently doesn't
1182 * So for now, just go direct to the PHY registers themselves.
1183 * This has always worked on external devices, but not internal
1184 * devices (AR934x, AR724x, AR933x.)
1186 sc->hal.arswitch_phy_read = arswitch_readphy_external;
1187 sc->hal.arswitch_phy_write = arswitch_writephy_external;
1189 /* Set the switch vlan capabilities. */
1190 sc->info.es_vlan_caps = ETHERSWITCH_VLAN_DOT1Q |
1191 ETHERSWITCH_VLAN_PORT | ETHERSWITCH_VLAN_DOUBLE_TAG;
1192 sc->info.es_nvlangroups = AR8X16_MAX_VLANS;