2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2011-2012 Stefan Bethke.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 #include <sys/param.h>
33 #include <sys/errno.h>
34 #include <sys/kernel.h>
35 #include <sys/module.h>
36 #include <sys/socket.h>
37 #include <sys/sockio.h>
38 #include <sys/sysctl.h>
39 #include <sys/systm.h>
42 #include <net/if_arp.h>
43 #include <net/ethernet.h>
44 #include <net/if_dl.h>
45 #include <net/if_media.h>
46 #include <net/if_types.h>
48 #include <machine/bus.h>
49 #include <dev/iicbus/iic.h>
50 #include <dev/iicbus/iiconf.h>
51 #include <dev/iicbus/iicbus.h>
52 #include <dev/mii/mii.h>
53 #include <dev/mii/miivar.h>
54 #include <dev/mdio/mdio.h>
56 #include <dev/etherswitch/etherswitch.h>
58 #include <dev/etherswitch/arswitch/arswitchreg.h>
59 #include <dev/etherswitch/arswitch/arswitchvar.h>
60 #include <dev/etherswitch/arswitch/arswitch_reg.h>
63 #include "miibus_if.h"
64 #include "etherswitch_if.h"
67 arswitch_split_setpage(device_t dev, uint32_t addr, uint16_t *phy,
70 struct arswitch_softc *sc = device_get_softc(dev);
73 page = (addr >> 9) & 0x1ff;
74 *phy = (addr >> 6) & 0x7;
75 *reg = (addr >> 1) & 0x1f;
77 if (sc->page != page) {
78 MDIO_WRITEREG(device_get_parent(dev), 0x18, 0, page);
85 * Read half a register. Some of the registers define control bits, and
86 * the sequence of half-word accesses matters. The register addresses
87 * are word-even (mod 4).
90 arswitch_readreg16(device_t dev, int addr)
94 arswitch_split_setpage(dev, addr, &phy, ®);
95 return (MDIO_READREG(device_get_parent(dev), 0x10 | phy, reg));
99 * Write half a register. See above!
102 arswitch_writereg16(device_t dev, int addr, int data)
106 arswitch_split_setpage(dev, addr, &phy, ®);
107 return (MDIO_WRITEREG(device_get_parent(dev), 0x10 | phy, reg, data));
113 * This may not work for AR7240 series embedded switches -
114 * the per-PHY register space doesn't seem to be exposed.
116 * In that instance, it may be required to speak via
117 * the internal switch PHY MDIO bus indirection.
120 arswitch_writedbg(device_t dev, int phy, uint16_t dbg_addr,
123 (void) MDIO_WRITEREG(device_get_parent(dev), phy,
124 MII_ATH_DBG_ADDR, dbg_addr);
125 (void) MDIO_WRITEREG(device_get_parent(dev), phy,
126 MII_ATH_DBG_DATA, dbg_data);
130 arswitch_writemmd(device_t dev, int phy, uint16_t dbg_addr,
133 (void) MDIO_WRITEREG(device_get_parent(dev), phy,
134 MII_ATH_MMD_ADDR, dbg_addr);
135 (void) MDIO_WRITEREG(device_get_parent(dev), phy,
136 MII_ATH_MMD_DATA, dbg_data);
140 arswitch_reg_read32(device_t dev, int phy, int reg)
143 lo = MDIO_READREG(device_get_parent(dev), phy, reg);
144 hi = MDIO_READREG(device_get_parent(dev), phy, reg + 1);
146 return (hi << 16) | lo;
150 arswitch_reg_write32(device_t dev, int phy, int reg, uint32_t value)
152 struct arswitch_softc *sc;
156 sc = device_get_softc(dev);
158 hi = (uint16_t) (value >> 16);
160 if (sc->mii_lo_first) {
161 r = MDIO_WRITEREG(device_get_parent(dev),
163 r |= MDIO_WRITEREG(device_get_parent(dev),
166 r = MDIO_WRITEREG(device_get_parent(dev),
168 r |= MDIO_WRITEREG(device_get_parent(dev),
176 arswitch_readreg(device_t dev, int addr)
180 arswitch_split_setpage(dev, addr, &phy, ®);
181 return arswitch_reg_read32(dev, 0x10 | phy, reg);
185 arswitch_writereg(device_t dev, int addr, int value)
187 struct arswitch_softc *sc;
190 sc = device_get_softc(dev);
192 arswitch_split_setpage(dev, addr, &phy, ®);
193 return (arswitch_reg_write32(dev, 0x10 | phy, reg, value));
197 * Read/write 16 bit values in the switch register space.
199 * Some of the registers are control registers (eg the MDIO
200 * data versus control space) and so need to be treated
204 arswitch_readreg_lsb(device_t dev, int addr)
207 return (arswitch_readreg16(dev, addr));
211 arswitch_readreg_msb(device_t dev, int addr)
214 return (arswitch_readreg16(dev, addr + 2) << 16);
218 arswitch_writereg_lsb(device_t dev, int addr, int data)
221 return (arswitch_writereg16(dev, addr, data & 0xffff));
225 arswitch_writereg_msb(device_t dev, int addr, int data)
228 return (arswitch_writereg16(dev, addr + 2, (data >> 16) & 0xffff));
232 arswitch_modifyreg(device_t dev, int addr, int mask, int set)
237 ARSWITCH_LOCK_ASSERT((struct arswitch_softc *)device_get_softc(dev),
240 arswitch_split_setpage(dev, addr, &phy, ®);
242 value = arswitch_reg_read32(dev, 0x10 | phy, reg);
245 return (arswitch_reg_write32(dev, 0x10 | phy, reg, value));
249 arswitch_waitreg(device_t dev, int addr, int mask, int val, int timeout)
251 struct arswitch_softc *sc = device_get_softc(dev);
255 ARSWITCH_LOCK_ASSERT(sc, MA_OWNED);
257 arswitch_split_setpage(dev, addr, &phy, ®);
261 v = arswitch_reg_read32(dev, 0x10 | phy, reg);
273 DPRINTF(sc, ARSWITCH_DBG_ANY,
274 "%s: waitreg failed; addr=0x%08x, mask=0x%08x, val=0x%08x\n",
275 __func__, addr, mask, val);