2 * Copyright (c) 2011-2012 Stefan Bethke.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 #include <sys/param.h>
31 #include <sys/errno.h>
32 #include <sys/kernel.h>
33 #include <sys/module.h>
34 #include <sys/socket.h>
35 #include <sys/sockio.h>
36 #include <sys/sysctl.h>
37 #include <sys/systm.h>
40 #include <net/if_arp.h>
41 #include <net/ethernet.h>
42 #include <net/if_dl.h>
43 #include <net/if_media.h>
44 #include <net/if_types.h>
46 #include <machine/bus.h>
47 #include <dev/iicbus/iic.h>
48 #include <dev/iicbus/iiconf.h>
49 #include <dev/iicbus/iicbus.h>
50 #include <dev/mii/mii.h>
51 #include <dev/mii/miivar.h>
52 #include <dev/mdio/mdio.h>
54 #include <dev/etherswitch/etherswitch.h>
56 #include <dev/etherswitch/arswitch/arswitchreg.h>
57 #include <dev/etherswitch/arswitch/arswitchvar.h>
58 #include <dev/etherswitch/arswitch/arswitch_reg.h>
61 #include "miibus_if.h"
62 #include "etherswitch_if.h"
65 arswitch_split_setpage(device_t dev, uint32_t addr, uint16_t *phy,
68 struct arswitch_softc *sc = device_get_softc(dev);
71 page = (addr >> 9) & 0x1ff;
72 *phy = (addr >> 6) & 0x7;
73 *reg = (addr >> 1) & 0x1f;
75 if (sc->page != page) {
76 MDIO_WRITEREG(device_get_parent(dev), 0x18, 0, page);
83 * Read half a register. Some of the registers define control bits, and
84 * the sequence of half-word accesses matters. The register addresses
85 * are word-even (mod 4).
88 arswitch_readreg16(device_t dev, int addr)
92 arswitch_split_setpage(dev, addr, &phy, ®);
93 return (MDIO_READREG(device_get_parent(dev), 0x10 | phy, reg));
97 * Write half a register. See above!
100 arswitch_writereg16(device_t dev, int addr, int data)
104 arswitch_split_setpage(dev, addr, &phy, ®);
105 return (MDIO_WRITEREG(device_get_parent(dev), 0x10 | phy, reg, data));
111 * This may not work for AR7240 series embedded switches -
112 * the per-PHY register space doesn't seem to be exposed.
114 * In that instance, it may be required to speak via
115 * the internal switch PHY MDIO bus indirection.
118 arswitch_writedbg(device_t dev, int phy, uint16_t dbg_addr,
121 (void) MDIO_WRITEREG(device_get_parent(dev), phy,
122 MII_ATH_DBG_ADDR, dbg_addr);
123 (void) MDIO_WRITEREG(device_get_parent(dev), phy,
124 MII_ATH_DBG_DATA, dbg_data);
128 arswitch_writemmd(device_t dev, int phy, uint16_t dbg_addr,
131 (void) MDIO_WRITEREG(device_get_parent(dev), phy,
132 MII_ATH_MMD_ADDR, dbg_addr);
133 (void) MDIO_WRITEREG(device_get_parent(dev), phy,
134 MII_ATH_MMD_DATA, dbg_data);
138 arswitch_reg_read32(device_t dev, int phy, int reg)
141 lo = MDIO_READREG(device_get_parent(dev), phy, reg);
142 hi = MDIO_READREG(device_get_parent(dev), phy, reg + 1);
144 return (hi << 16) | lo;
148 arswitch_reg_write32(device_t dev, int phy, int reg, uint32_t value)
150 struct arswitch_softc *sc;
154 sc = device_get_softc(dev);
156 hi = (uint16_t) (value >> 16);
158 if (sc->mii_lo_first) {
159 r = MDIO_WRITEREG(device_get_parent(dev),
161 r |= MDIO_WRITEREG(device_get_parent(dev),
164 r = MDIO_WRITEREG(device_get_parent(dev),
166 r |= MDIO_WRITEREG(device_get_parent(dev),
174 arswitch_readreg(device_t dev, int addr)
178 arswitch_split_setpage(dev, addr, &phy, ®);
179 return arswitch_reg_read32(dev, 0x10 | phy, reg);
183 arswitch_writereg(device_t dev, int addr, int value)
185 struct arswitch_softc *sc;
188 sc = device_get_softc(dev);
190 arswitch_split_setpage(dev, addr, &phy, ®);
191 return (arswitch_reg_write32(dev, 0x10 | phy, reg, value));
195 * Read/write 16 bit values in the switch register space.
197 * Some of the registers are control registers (eg the MDIO
198 * data versus control space) and so need to be treated
202 arswitch_readreg_lsb(device_t dev, int addr)
205 return (arswitch_readreg16(dev, addr));
209 arswitch_readreg_msb(device_t dev, int addr)
212 return (arswitch_readreg16(dev, addr + 2) << 16);
216 arswitch_writereg_lsb(device_t dev, int addr, int data)
219 return (arswitch_writereg16(dev, addr, data & 0xffff));
223 arswitch_writereg_msb(device_t dev, int addr, int data)
226 return (arswitch_writereg16(dev, addr + 2, (data >> 16) & 0xffff));
230 arswitch_modifyreg(device_t dev, int addr, int mask, int set)
235 ARSWITCH_LOCK_ASSERT((struct arswitch_softc *)device_get_softc(dev),
238 arswitch_split_setpage(dev, addr, &phy, ®);
240 value = arswitch_reg_read32(dev, 0x10 | phy, reg);
243 return (arswitch_reg_write32(dev, 0x10 | phy, reg, value));
247 arswitch_waitreg(device_t dev, int addr, int mask, int val, int timeout)
249 struct arswitch_softc *sc = device_get_softc(dev);
253 ARSWITCH_LOCK_ASSERT(sc, MA_OWNED);
255 arswitch_split_setpage(dev, addr, &phy, ®);
259 v = arswitch_reg_read32(dev, 0x10 | phy, reg);
271 DPRINTF(sc, ARSWITCH_DBG_ANY,
272 "%s: waitreg failed; addr=0x%08x, mask=0x%08x, val=0x%08x\n",
273 __func__, addr, mask, val);