2 * Copyright (c) 2011 Aleksandr Rybalko.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 #ifndef __AR8X16_SWITCHREG_H__
30 #define __AR8X16_SWITCHREG_H__
32 /* XXX doesn't belong here; stolen shamelessly from ath_hal/ah_internal.h */
34 * Register manipulation macros that expect bit field defines
35 * to follow the convention that an _S suffix is appended for
36 * a shift count, while the field mask has no suffix.
38 #define SM(_v, _f) (((_v) << _f##_S) & (_f))
39 #define MS(_v, _f) (((_v) & (_f)) >> _f##_S)
41 /* XXX Linux define compatibility stuff */
42 #define BIT(_m) (1UL << (_m))
43 #define BITM(_count) ((1UL << (_count)) - 1)
44 #define BITS(_shift, _count) (BITM(_count) << (_shift))
46 /* Atheros specific MII registers */
47 #define MII_ATH_MMD_ADDR 0x0d
48 #define MII_ATH_MMD_DATA 0x0e
49 #define MII_ATH_DBG_ADDR 0x1d
50 #define MII_ATH_DBG_DATA 0x1e
52 #define AR8X16_REG_MASK_CTRL 0x0000
53 #define AR8X16_MASK_CTRL_REV_MASK 0x000000ff
54 #define AR8X16_MASK_CTRL_VER_MASK 0x0000ff00
55 #define AR8X16_MASK_CTRL_VER_SHIFT 8
56 #define AR8X16_MASK_CTRL_SOFT_RESET (1U << 31)
58 #define AR8X16_REG_MODE 0x0008
59 /* DIR-615 E4 U-Boot */
60 #define AR8X16_MODE_DIR_615_UBOOT 0x8d1003e0
61 /* From Ubiquiti RSPRO */
62 #define AR8X16_MODE_RGMII_PORT4_ISO 0x81461bea
63 #define AR8X16_MODE_RGMII_PORT4_SWITCH 0x01261be2
64 /* AVM Fritz!Box 7390 */
65 #define AR8X16_MODE_GMII 0x010e5b71
66 /* from avm_cpmac/linux_ar_reg.h */
67 #define AR8X16_MODE_RESERVED 0x000e1b20
68 #define AR8X16_MODE_MAC0_GMII_EN (1u << 0)
69 #define AR8X16_MODE_MAC0_RGMII_EN (1u << 1)
70 #define AR8X16_MODE_PHY4_GMII_EN (1u << 2)
71 #define AR8X16_MODE_PHY4_RGMII_EN (1u << 3)
72 #define AR8X16_MODE_MAC0_MAC_MODE (1u << 4)
73 #define AR8X16_MODE_RGMII_RXCLK_DELAY_EN (1u << 6)
74 #define AR8X16_MODE_RGMII_TXCLK_DELAY_EN (1u << 7)
75 #define AR8X16_MODE_MAC5_MAC_MODE (1u << 14)
76 #define AR8X16_MODE_MAC5_PHY_MODE (1u << 15)
77 #define AR8X16_MODE_TXDELAY_S0 (1u << 21)
78 #define AR8X16_MODE_TXDELAY_S1 (1u << 22)
79 #define AR8X16_MODE_RXDELAY_S0 (1u << 23)
80 #define AR8X16_MODE_LED_OPEN_EN (1u << 24)
81 #define AR8X16_MODE_SPI_EN (1u << 25)
82 #define AR8X16_MODE_RXDELAY_S1 (1u << 26)
83 #define AR8X16_MODE_POWER_ON_SEL (1u << 31)
85 #define AR8X16_REG_ISR 0x0010
86 #define AR8X16_REG_IMR 0x0014
88 #define AR8X16_REG_SW_MAC_ADDR0 0x0020
89 #define AR8X16_REG_SW_MAC_ADDR1 0x0024
91 #define AR8X16_REG_FLOOD_MASK 0x002c
92 #define AR8X16_FLOOD_MASK_BCAST_TO_CPU (1 << 26)
94 #define AR8X16_REG_GLOBAL_CTRL 0x0030
95 #define AR8216_GLOBAL_CTRL_MTU_MASK 0x00000fff
96 #define AR8216_GLOBAL_CTRL_MTU_MASK_S 0
97 #define AR8316_GLOBAL_CTRL_MTU_MASK 0x00007fff
98 #define AR8316_GLOBAL_CTRL_MTU_MASK_S 0
99 #define AR8236_GLOBAL_CTRL_MTU_MASK 0x00007fff
100 #define AR8236_GLOBAL_CTRL_MTU_MASK_S 0
101 #define AR7240_GLOBAL_CTRL_MTU_MASK 0x00003fff
102 #define AR7240_GLOBAL_CTRL_MTU_MASK_S 0
104 #define AR8X16_REG_VLAN_CTRL 0x0040
105 #define AR8X16_VLAN_OP 0x00000007
106 #define AR8X16_VLAN_OP_NOOP 0x0
107 #define AR8X16_VLAN_OP_FLUSH 0x1
108 #define AR8X16_VLAN_OP_LOAD 0x2
109 #define AR8X16_VLAN_OP_PURGE 0x3
110 #define AR8X16_VLAN_OP_REMOVE_PORT 0x4
111 #define AR8X16_VLAN_OP_GET_NEXT 0x5
112 #define AR8X16_VLAN_OP_GET 0x6
113 #define AR8X16_VLAN_ACTIVE (1 << 3)
114 #define AR8X16_VLAN_FULL (1 << 4)
115 #define AR8X16_VLAN_PORT 0x00000f00
116 #define AR8X16_VLAN_PORT_SHIFT 8
117 #define AR8X16_VLAN_VID 0x0fff0000
118 #define AR8X16_VLAN_VID_SHIFT 16
119 #define AR8X16_VLAN_PRIO 0x70000000
120 #define AR8X16_VLAN_PRIO_SHIFT 28
121 #define AR8X16_VLAN_PRIO_EN (1U << 31)
123 #define AR8X16_REG_VLAN_DATA 0x0044
124 #define AR8X16_VLAN_MEMBER 0x0000003f
125 #define AR8X16_VLAN_VALID (1 << 11)
127 #define AR8216_REG_ATU 0x0050
128 #define AR8216_ATU_OP BITS(0, 3)
129 #define AR8216_ATU_OP_NOOP 0x0
130 #define AR8216_ATU_OP_FLUSH 0x1
131 #define AR8216_ATU_OP_LOAD 0x2
132 #define AR8216_ATU_OP_PURGE 0x3
133 #define AR8216_ATU_OP_FLUSH_LOCKED 0x4
134 #define AR8216_ATU_OP_FLUSH_UNICAST 0x5
135 #define AR8216_ATU_OP_GET_NEXT 0x6
136 #define AR8216_ATU_ACTIVE BIT(3)
137 #define AR8216_ATU_PORT_NUM BITS(8, 4)
138 #define AR8216_ATU_FULL_VIO BIT(12)
139 #define AR8216_ATU_ADDR4 BITS(16, 8)
140 #define AR8216_ATU_ADDR5 BITS(24, 8)
142 #define AR8216_REG_ATU_DATA 0x0054
143 #define AR8216_ATU_ADDR3 BITS(0, 8)
144 #define AR8216_ATU_ADDR2 BITS(8, 8)
145 #define AR8216_ATU_ADDR1 BITS(16, 8)
146 #define AR8216_ATU_ADDR0 BITS(24, 8)
148 #define AR8X16_REG_ARL_CTRL2 0x0058
150 #define AR8216_REG_ATU_CTRL 0x005C
151 #define AR8216_ATU_CTRL_AGE_EN BIT(17)
152 #define AR8216_ATU_CTRL_AGE_TIME BITS(0, 16)
153 #define AR8216_ATU_CTRL_AGE_TIME_S 0
155 #define AR8X16_REG_AT_CTRL 0x005c
156 #define AR8X16_AT_CTRL_ARP_EN (1 << 20)
158 #define AR8X16_REG_IP_PRIORITY_1 0x0060
159 #define AR8X16_REG_IP_PRIORITY_2 0x0064
160 #define AR8X16_REG_IP_PRIORITY_3 0x0068
161 #define AR8X16_REG_IP_PRIORITY_4 0x006C
163 #define AR8X16_REG_TAG_PRIO 0x0070
165 #define AR8X16_REG_SERVICE_TAG 0x0074
166 #define AR8X16_SERVICE_TAG_MASK 0x0000ffff
168 #define AR8X16_REG_CPU_PORT 0x0078
169 #define AR8X16_MIRROR_PORT_SHIFT 4
170 #define AR8X16_MIRROR_PORT_MASK (0xf << AR8X16_MIRROR_PORT_SHIFT)
171 #define AR8X16_CPU_MIRROR_PORT(_p) ((_p) << AR8X16_MIRROR_PORT_SHIFT)
172 #define AR8X16_CPU_MIRROR_DIS AR8X16_CPU_MIRROR_PORT(0xf)
173 #define AR8X16_CPU_PORT_EN (1 << 8)
175 #define AR8X16_REG_MIB_FUNC0 0x0080
176 #define AR8X16_MIB_TIMER_MASK 0x0000ffff
177 #define AR8X16_MIB_AT_HALF_EN (1 << 16)
178 #define AR8X16_MIB_BUSY (1 << 17)
179 #define AR8X16_MIB_FUNC_SHIFT 24
180 #define AR8X16_MIB_FUNC_NO_OP 0x0
181 #define AR8X16_MIB_FUNC_FLUSH 0x1
182 #define AR8X16_MIB_FUNC_CAPTURE 0x3
183 #define AR8X16_MIB_FUNC_XXX (1 << 30) /* 0x40000000 */
185 #define AR934X_MIB_ENABLE (1 << 30)
187 #define AR8X16_REG_MDIO_HIGH_ADDR 0x0094
189 #define AR8X16_REG_MDIO_CTRL 0x0098
190 #define AR8X16_MDIO_CTRL_DATA_MASK 0x0000ffff
191 #define AR8X16_MDIO_CTRL_REG_ADDR_SHIFT 16
192 #define AR8X16_MDIO_CTRL_PHY_ADDR_SHIFT 21
193 #define AR8X16_MDIO_CTRL_CMD_WRITE 0
194 #define AR8X16_MDIO_CTRL_CMD_READ (1 << 27)
195 #define AR8X16_MDIO_CTRL_MASTER_EN (1 << 30)
196 #define AR8X16_MDIO_CTRL_BUSY (1U << 31)
198 #define AR8X16_REG_PORT_BASE(_p) (0x0100 + (_p) * 0x0100)
200 #define AR8X16_REG_PORT_STS(_p) (AR8X16_REG_PORT_BASE((_p)) + 0x0000)
201 #define AR8X16_PORT_STS_SPEED_MASK 0x00000003
202 #define AR8X16_PORT_STS_SPEED_10 0
203 #define AR8X16_PORT_STS_SPEED_100 1
204 #define AR8X16_PORT_STS_SPEED_1000 2
205 #define AR8X16_PORT_STS_TXMAC (1 << 2)
206 #define AR8X16_PORT_STS_RXMAC (1 << 3)
207 #define AR8X16_PORT_STS_TXFLOW (1 << 4)
208 #define AR8X16_PORT_STS_RXFLOW (1 << 5)
209 #define AR8X16_PORT_STS_DUPLEX (1 << 6)
210 #define AR8X16_PORT_STS_LINK_UP (1 << 8)
211 #define AR8X16_PORT_STS_LINK_AUTO (1 << 9)
212 #define AR8X16_PORT_STS_LINK_PAUSE (1 << 10)
214 #define AR8X16_REG_PORT_CTRL(_p) (AR8X16_REG_PORT_BASE((_p)) + 0x0004)
215 #define AR8X16_PORT_CTRL_STATE_MASK 0x00000007
216 #define AR8X16_PORT_CTRL_STATE_DISABLED 0
217 #define AR8X16_PORT_CTRL_STATE_BLOCK 1
218 #define AR8X16_PORT_CTRL_STATE_LISTEN 2
219 #define AR8X16_PORT_CTRL_STATE_LEARN 3
220 #define AR8X16_PORT_CTRL_STATE_FORWARD 4
221 #define AR8X16_PORT_CTRL_LEARN_LOCK (1 << 7)
222 #define AR8X16_PORT_CTRL_EGRESS_VLAN_MODE_SHIFT 8
223 #define AR8X16_PORT_CTRL_EGRESS_VLAN_MODE_KEEP 0
224 #define AR8X16_PORT_CTRL_EGRESS_VLAN_MODE_STRIP 1
225 #define AR8X16_PORT_CTRL_EGRESS_VLAN_MODE_ADD 2
226 #define AR8X16_PORT_CTRL_EGRESS_VLAN_MODE_DOUBLE_TAG 3
227 #define AR8X16_PORT_CTRL_IGMP_SNOOP (1 << 10)
228 #define AR8X16_PORT_CTRL_HEADER (1 << 11)
229 #define AR8X16_PORT_CTRL_MAC_LOOP (1 << 12)
230 #define AR8X16_PORT_CTRL_SINGLE_VLAN (1 << 13)
231 #define AR8X16_PORT_CTRL_LEARN (1 << 14)
232 #define AR8X16_PORT_CTRL_DOUBLE_TAG (1 << 15)
233 #define AR8X16_PORT_CTRL_MIRROR_TX (1 << 16)
234 #define AR8X16_PORT_CTRL_MIRROR_RX (1 << 17)
236 #define AR8X16_REG_PORT_VLAN(_p) (AR8X16_REG_PORT_BASE((_p)) + 0x0008)
238 #define AR8X16_PORT_VLAN_DEFAULT_ID_SHIFT 0
239 #define AR8X16_PORT_VLAN_DEST_PORTS_SHIFT 16
240 #define AR8X16_PORT_VLAN_MODE_MASK 0xc0000000
241 #define AR8X16_PORT_VLAN_MODE_SHIFT 30
242 #define AR8X16_PORT_VLAN_MODE_PORT_ONLY 0
243 #define AR8X16_PORT_VLAN_MODE_PORT_FALLBACK 1
244 #define AR8X16_PORT_VLAN_MODE_VLAN_ONLY 2
245 #define AR8X16_PORT_VLAN_MODE_SECURE 3
247 #define AR8X16_REG_PORT_RATE_LIM(_p) (AR8X16_REG_PORT_BASE((_p)) + 0x000c)
248 #define AR8X16_PORT_RATE_LIM_128KB 0
249 #define AR8X16_PORT_RATE_LIM_256KB 1
250 #define AR8X16_PORT_RATE_LIM_512KB 2
251 #define AR8X16_PORT_RATE_LIM_1MB 3
252 #define AR8X16_PORT_RATE_LIM_2MB 4
253 #define AR8X16_PORT_RATE_LIM_4MB 5
254 #define AR8X16_PORT_RATE_LIM_8MB 6
255 #define AR8X16_PORT_RATE_LIM_16MB 7
256 #define AR8X16_PORT_RATE_LIM_32MB 8
257 #define AR8X16_PORT_RATE_LIM_64MB 9
258 #define AR8X16_PORT_RATE_LIM_IN_EN (1 << 24)
259 #define AR8X16_PORT_RATE_LIM_OUT_EN (1 << 23)
260 #define AR8X16_PORT_RATE_LIM_IN_MASK 0x000f0000
261 #define AR8X16_PORT_RATE_LIM_IN_SHIFT 16
262 #define AR8X16_PORT_RATE_LIM_OUT_MASK 0x0000000f
263 #define AR8X16_PORT_RATE_LIM_OUT_SHIFT 0
265 #define AR8X16_REG_PORT_PRIORITY(_p) (AR8X16_REG_PORT_BASE((_p)) + 0x0010)
267 #define AR8X16_REG_STATS_BASE(_p) (0x20000 + (_p) * 0x100)
269 #define AR8X16_STATS_RXBROAD 0x0000
270 #define AR8X16_STATS_RXPAUSE 0x0004
271 #define AR8X16_STATS_RXMULTI 0x0008
272 #define AR8X16_STATS_RXFCSERR 0x000c
273 #define AR8X16_STATS_RXALIGNERR 0x0010
274 #define AR8X16_STATS_RXRUNT 0x0014
275 #define AR8X16_STATS_RXFRAGMENT 0x0018
276 #define AR8X16_STATS_RX64BYTE 0x001c
277 #define AR8X16_STATS_RX128BYTE 0x0020
278 #define AR8X16_STATS_RX256BYTE 0x0024
279 #define AR8X16_STATS_RX512BYTE 0x0028
280 #define AR8X16_STATS_RX1024BYTE 0x002c
281 #define AR8X16_STATS_RX1518BYTE 0x0030
282 #define AR8X16_STATS_RXMAXBYTE 0x0034
283 #define AR8X16_STATS_RXTOOLONG 0x0038
284 #define AR8X16_STATS_RXGOODBYTE 0x003c
285 #define AR8X16_STATS_RXBADBYTE 0x0044
286 #define AR8X16_STATS_RXOVERFLOW 0x004c
287 #define AR8X16_STATS_FILTERED 0x0050
288 #define AR8X16_STATS_TXBROAD 0x0054
289 #define AR8X16_STATS_TXPAUSE 0x0058
290 #define AR8X16_STATS_TXMULTI 0x005c
291 #define AR8X16_STATS_TXUNDERRUN 0x0060
292 #define AR8X16_STATS_TX64BYTE 0x0064
293 #define AR8X16_STATS_TX128BYTE 0x0068
294 #define AR8X16_STATS_TX256BYTE 0x006c
295 #define AR8X16_STATS_TX512BYTE 0x0070
296 #define AR8X16_STATS_TX1024BYTE 0x0074
297 #define AR8X16_STATS_TX1518BYTE 0x0078
298 #define AR8X16_STATS_TXMAXBYTE 0x007c
299 #define AR8X16_STATS_TXOVERSIZE 0x0080
300 #define AR8X16_STATS_TXBYTE 0x0084
301 #define AR8X16_STATS_TXCOLLISION 0x008c
302 #define AR8X16_STATS_TXABORTCOL 0x0090
303 #define AR8X16_STATS_TXMULTICOL 0x0094
304 #define AR8X16_STATS_TXSINGLECOL 0x0098
305 #define AR8X16_STATS_TXEXCDEFER 0x009c
306 #define AR8X16_STATS_TXDEFER 0x00a0
307 #define AR8X16_STATS_TXLATECOL 0x00a4
309 #define AR8X16_PORT_CPU 0
310 #define AR8X16_NUM_PORTS 6
311 #define AR8X16_NUM_PHYS 5
312 #define AR8X16_MAGIC 0xc000050e
314 #define AR8X16_PHY_ID1 0x004d
315 #define AR8X16_PHY_ID2 0xd041
317 #define AR8X16_PORT_MASK(_port) (1 << (_port))
318 #define AR8X16_PORT_MASK_ALL ((1<<AR8X16_NUM_PORTS)-1)
319 #define AR8X16_PORT_MASK_BUT(_port) (AR8X16_PORT_MASK_ALL & ~(1 << (_port)))
321 #define AR8X16_MAX_VLANS 16
324 * AR9340 switch specific definitions.
327 #define AR934X_REG_OPER_MODE0 0x04
328 #define AR934X_OPER_MODE0_MAC_GMII_EN (1 << 6)
329 #define AR934X_OPER_MODE0_PHY_MII_EN (1 << 10)
331 #define AR934X_REG_OPER_MODE1 0x08
332 #define AR934X_REG_OPER_MODE1_PHY4_MII_EN (1 << 28)
334 #define AR934X_REG_FLOOD_MASK 0x2c
335 #define AR934X_FLOOD_MASK_MC_DP(_p) (1 << (16 + (_p)))
336 #define AR934X_FLOOD_MASK_BC_DP(_p) (1 << (25 + (_p)))
338 #define AR934X_REG_QM_CTRL 0x3c
339 #define AR934X_QM_CTRL_ARP_EN (1 << 15)
341 #define AR934X_REG_AT_CTRL 0x5c
342 #define AR934X_AT_CTRL_AGE_TIME BITS(0, 15)
343 #define AR934X_AT_CTRL_AGE_EN (1 << 17)
344 #define AR934X_AT_CTRL_LEARN_CHANGE (1 << 18)
346 #define AR934X_REG_PORT_BASE(_port) (0x100 + (_port) * 0x100)
348 #define AR934X_REG_PORT_VLAN1(_port) (AR934X_REG_PORT_BASE((_port)) + 0x08)
349 #define AR934X_PORT_VLAN1_DEFAULT_SVID_S 0
350 #define AR934X_PORT_VLAN1_FORCE_DEFAULT_VID_EN (1 << 12)
351 #define AR934X_PORT_VLAN1_PORT_TLS_MODE (1 << 13)
352 #define AR934X_PORT_VLAN1_PORT_VLAN_PROP_EN (1 << 14)
353 #define AR934X_PORT_VLAN1_PORT_CLONE_EN (1 << 15)
354 #define AR934X_PORT_VLAN1_DEFAULT_CVID_S 16
355 #define AR934X_PORT_VLAN1_FORCE_PORT_VLAN_EN (1 << 28)
356 #define AR934X_PORT_VLAN1_ING_PORT_PRI_S 29
358 #define AR934X_REG_PORT_VLAN2(_port) (AR934X_REG_PORT_BASE((_port)) + 0x0c)
359 #define AR934X_PORT_VLAN2_PORT_VID_MEM_S 16
360 #define AR934X_PORT_VLAN2_8021Q_MODE_S 30
361 #define AR934X_PORT_VLAN2_8021Q_MODE_PORT_ONLY 0
362 #define AR934X_PORT_VLAN2_8021Q_MODE_PORT_FALLBACK 1
363 #define AR934X_PORT_VLAN2_8021Q_MODE_VLAN_ONLY 2
364 #define AR934X_PORT_VLAN2_8021Q_MODE_SECURE 3
367 * AR8327 specific registers
369 #define AR8327_NUM_PORTS 7
370 #define AR8327_NUM_PHYS 5
371 #define AR8327_PORTS_ALL 0x7f
373 #define AR8327_REG_MASK 0x000
375 #define AR8327_REG_PAD0_MODE 0x004
376 #define AR8327_REG_PAD5_MODE 0x008
377 #define AR8327_REG_PAD6_MODE 0x00c
379 #define AR8327_PAD_MAC_MII_RXCLK_SEL (1 << 0)
380 #define AR8327_PAD_MAC_MII_TXCLK_SEL (1 << 1)
381 #define AR8327_PAD_MAC_MII_EN (1 << 2)
382 #define AR8327_PAD_MAC_GMII_RXCLK_SEL (1 << 4)
383 #define AR8327_PAD_MAC_GMII_TXCLK_SEL (1 << 5)
384 #define AR8327_PAD_MAC_GMII_EN (1 << 6)
385 #define AR8327_PAD_SGMII_EN (1 << 7)
386 #define AR8327_PAD_PHY_MII_RXCLK_SEL (1 << 8)
387 #define AR8327_PAD_PHY_MII_TXCLK_SEL (1 << 9)
388 #define AR8327_PAD_PHY_MII_EN (1 << 10)
389 #define AR8327_PAD_PHY_GMII_PIPE_RXCLK_SEL (1 << 11)
390 #define AR8327_PAD_PHY_GMII_RXCLK_SEL (1 << 12)
391 #define AR8327_PAD_PHY_GMII_TXCLK_SEL (1 << 13)
392 #define AR8327_PAD_PHY_GMII_EN (1 << 14)
393 #define AR8327_PAD_PHYX_GMII_EN (1 << 16)
394 #define AR8327_PAD_PHYX_RGMII_EN (1 << 17)
395 #define AR8327_PAD_PHYX_MII_EN (1 << 18)
396 #define AR8327_PAD_SGMII_DELAY_EN (1 << 19)
397 #define AR8327_PAD_RGMII_RXCLK_DELAY_SEL BITS(20, 2)
398 #define AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S 20
399 #define AR8327_PAD_RGMII_TXCLK_DELAY_SEL BITS(22, 2)
400 #define AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S 22
401 #define AR8327_PAD_RGMII_RXCLK_DELAY_EN (1 << 24)
402 #define AR8327_PAD_RGMII_TXCLK_DELAY_EN (1 << 25)
403 #define AR8327_PAD_RGMII_EN (1 << 26)
405 #define AR8327_REG_POWER_ON_STRIP 0x010
406 #define AR8327_POWER_ON_STRIP_POWER_ON_SEL (1U << 31)
407 #define AR8327_POWER_ON_STRIP_LED_OPEN_EN (1 << 24)
408 #define AR8327_POWER_ON_STRIP_SERDES_AEN (1 << 7)
410 #define AR8327_REG_INT_STATUS0 0x020
411 #define AR8327_INT0_VT_DONE (1 << 20)
413 #define AR8327_REG_INT_STATUS1 0x024
414 #define AR8327_REG_INT_MASK0 0x028
415 #define AR8327_REG_INT_MASK1 0x02c
417 #define AR8327_REG_MODULE_EN 0x030
418 #define AR8327_MODULE_EN_MIB (1 << 0)
420 #define AR8327_REG_MIB_FUNC 0x034
421 #define AR8327_MIB_CPU_KEEP (1 << 20)
423 #define AR8327_REG_MDIO_CTRL 0x03c
425 #define AR8327_REG_SERVICE_TAG 0x048
426 #define AR8327_REG_LED_CTRL0 0x050
427 #define AR8327_REG_LED_CTRL1 0x054
428 #define AR8327_REG_LED_CTRL2 0x058
429 #define AR8327_REG_LED_CTRL3 0x05c
430 #define AR8327_REG_MAC_ADDR0 0x060
431 #define AR8327_REG_MAC_ADDR1 0x064
433 #define AR8327_REG_MAX_FRAME_SIZE 0x078
434 #define AR8327_MAX_FRAME_SIZE_MTU BITS(0, 14)
436 #define AR8327_REG_PORT_STATUS(_i) (0x07c + (_i) * 4)
438 #define AR8327_REG_HEADER_CTRL 0x098
439 #define AR8327_REG_PORT_HEADER(_i) (0x09c + (_i) * 4)
441 #define AR8327_REG_SGMII_CTRL 0x0e0
442 #define AR8327_SGMII_CTRL_EN_PLL (1 << 1)
443 #define AR8327_SGMII_CTRL_EN_RX (1 << 2)
444 #define AR8327_SGMII_CTRL_EN_TX (1 << 3)
446 #define AR8327_REG_PORT_VLAN0(_i) (0x420 + (_i) * 0x8)
447 #define AR8327_PORT_VLAN0_DEF_SVID BITS(0, 12)
448 #define AR8327_PORT_VLAN0_DEF_SVID_S 0
449 #define AR8327_PORT_VLAN0_DEF_CVID BITS(16, 12)
450 #define AR8327_PORT_VLAN0_DEF_CVID_S 16
452 #define AR8327_REG_PORT_VLAN1(_i) (0x424 + (_i) * 0x8)
453 #define AR8327_PORT_VLAN1_PORT_VLAN_PROP (1 << 6)
454 #define AR8327_PORT_VLAN1_OUT_MODE BITS(12, 2)
455 #define AR8327_PORT_VLAN1_OUT_MODE_S 12
456 #define AR8327_PORT_VLAN1_OUT_MODE_UNMOD 0
457 #define AR8327_PORT_VLAN1_OUT_MODE_UNTAG 1
458 #define AR8327_PORT_VLAN1_OUT_MODE_TAG 2
459 #define AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH 3
461 #define AR8327_REG_ATU_DATA0 0x600
462 #define AR8327_REG_ATU_DATA1 0x604
463 #define AR8327_REG_ATU_DATA2 0x608
465 #define AR8327_REG_ATU_FUNC 0x60c
466 #define AR8327_ATU_FUNC_OP BITS(0, 4)
467 #define AR8327_ATU_FUNC_OP_NOOP 0x0
468 #define AR8327_ATU_FUNC_OP_FLUSH 0x1
469 #define AR8327_ATU_FUNC_OP_LOAD 0x2
470 #define AR8327_ATU_FUNC_OP_PURGE 0x3
471 #define AR8327_ATU_FUNC_OP_FLUSH_LOCKED 0x4
472 #define AR8327_ATU_FUNC_OP_FLUSH_UNICAST 0x5
473 #define AR8327_ATU_FUNC_OP_GET_NEXT 0x6
474 #define AR8327_ATU_FUNC_OP_SEARCH_MAC 0x7
475 #define AR8327_ATU_FUNC_OP_CHANGE_TRUNK 0x8
476 #define AR8327_ATU_FUNC_BUSY (1U << 31)
478 #define AR8327_REG_VTU_FUNC0 0x0610
479 #define AR8327_VTU_FUNC0_EG_MODE BITS(4, 14)
480 #define AR8327_VTU_FUNC0_EG_MODE_S(_i) (4 + (_i) * 2)
481 #define AR8327_VTU_FUNC0_EG_MODE_KEEP 0
482 #define AR8327_VTU_FUNC0_EG_MODE_UNTAG 1
483 #define AR8327_VTU_FUNC0_EG_MODE_TAG 2
484 #define AR8327_VTU_FUNC0_EG_MODE_NOT 3
485 #define AR8327_VTU_FUNC0_IVL (1 << 19)
486 #define AR8327_VTU_FUNC0_VALID (1 << 20)
488 #define AR8327_REG_VTU_FUNC1 0x0614
489 #define AR8327_VTU_FUNC1_OP BITS(0, 3)
490 #define AR8327_VTU_FUNC1_OP_NOOP 0
491 #define AR8327_VTU_FUNC1_OP_FLUSH 1
492 #define AR8327_VTU_FUNC1_OP_LOAD 2
493 #define AR8327_VTU_FUNC1_OP_PURGE 3
494 #define AR8327_VTU_FUNC1_OP_REMOVE_PORT 4
495 #define AR8327_VTU_FUNC1_OP_GET_NEXT 5
496 #define AR8327_VTU_FUNC1_OP_GET_ONE 6
497 #define AR8327_VTU_FUNC1_FULL (1 << 4)
498 #define AR8327_VTU_FUNC1_PORT (1 << 8, 4)
499 #define AR8327_VTU_FUNC1_PORT_S 8
500 #define AR8327_VTU_FUNC1_VID (1 << 16, 12)
501 #define AR8327_VTU_FUNC1_VID_S 16
502 #define AR8327_VTU_FUNC1_BUSY (1U << 31)
504 #define AR8327_REG_FWD_CTRL0 0x620
505 #define AR8327_FWD_CTRL0_CPU_PORT_EN (1 << 10)
506 #define AR8327_FWD_CTRL0_MIRROR_PORT BITS(4, 4)
507 #define AR8327_FWD_CTRL0_MIRROR_PORT_S 4
509 #define AR8327_REG_FWD_CTRL1 0x624
510 #define AR8327_FWD_CTRL1_UC_FLOOD BITS(0, 7)
511 #define AR8327_FWD_CTRL1_UC_FLOOD_S 0
512 #define AR8327_FWD_CTRL1_MC_FLOOD BITS(8, 7)
513 #define AR8327_FWD_CTRL1_MC_FLOOD_S 8
514 #define AR8327_FWD_CTRL1_BC_FLOOD BITS(16, 7)
515 #define AR8327_FWD_CTRL1_BC_FLOOD_S 16
516 #define AR8327_FWD_CTRL1_IGMP BITS(24, 7)
517 #define AR8327_FWD_CTRL1_IGMP_S 24
519 #define AR8327_REG_PORT_LOOKUP(_i) (0x660 + (_i) * 0xc)
520 #define AR8327_PORT_LOOKUP_MEMBER BITS(0, 7)
521 #define AR8327_PORT_LOOKUP_IN_MODE BITS(8, 2)
522 #define AR8327_PORT_LOOKUP_IN_MODE_S 8
523 #define AR8327_PORT_LOOKUP_STATE BITS(16, 3)
524 #define AR8327_PORT_LOOKUP_STATE_S 16
525 #define AR8327_PORT_LOOKUP_LEARN (1 << 20)
526 #define AR8327_PORT_LOOKUP_ING_MIRROR_EN (1 << 25)
528 #define AR8327_REG_PORT_PRIO(_i) (0x664 + (_i) * 0xc)
530 #define AR8327_REG_PORT_HOL_CTRL1(_i) (0x974 + (_i) * 0x8)
531 #define AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN (1 << 16)
533 #define AR8327_REG_PORT_STATS_BASE(_i) (0x1000 + (_i) * 0x100)
535 #endif /* __AR8X16_SWITCHREG_H__ */