2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2011 Aleksandr Rybalko.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 #ifndef __AR8X16_SWITCHREG_H__
32 #define __AR8X16_SWITCHREG_H__
34 /* XXX doesn't belong here; stolen shamelessly from ath_hal/ah_internal.h */
36 * Register manipulation macros that expect bit field defines
37 * to follow the convention that an _S suffix is appended for
38 * a shift count, while the field mask has no suffix.
40 #define SM(_v, _f) (((_v) << _f##_S) & (_f))
41 #define MS(_v, _f) (((_v) & (_f)) >> _f##_S)
43 /* XXX Linux define compatibility stuff */
44 #define BIT(_m) (1UL << (_m))
45 #define BITM(_count) ((1UL << (_count)) - 1)
46 #define BITS(_shift, _count) (BITM(_count) << (_shift))
48 /* Atheros specific MII registers */
49 #define MII_ATH_MMD_ADDR 0x0d
50 #define MII_ATH_MMD_DATA 0x0e
51 #define MII_ATH_DBG_ADDR 0x1d
52 #define MII_ATH_DBG_DATA 0x1e
54 #define AR8X16_REG_MASK_CTRL 0x0000
55 #define AR8X16_MASK_CTRL_REV_MASK 0x000000ff
56 #define AR8X16_MASK_CTRL_VER_MASK 0x0000ff00
57 #define AR8X16_MASK_CTRL_VER_SHIFT 8
58 #define AR8X16_MASK_CTRL_SOFT_RESET (1U << 31)
60 #define AR8X16_REG_MODE 0x0008
61 /* DIR-615 E4 U-Boot */
62 #define AR8X16_MODE_DIR_615_UBOOT 0x8d1003e0
63 /* From Ubiquiti RSPRO */
64 #define AR8X16_MODE_RGMII_PORT4_ISO 0x81461bea
65 #define AR8X16_MODE_RGMII_PORT4_SWITCH 0x01261be2
66 /* AVM Fritz!Box 7390 */
67 #define AR8X16_MODE_GMII 0x010e5b71
68 /* from avm_cpmac/linux_ar_reg.h */
69 #define AR8X16_MODE_RESERVED 0x000e1b20
70 #define AR8X16_MODE_MAC0_GMII_EN (1u << 0)
71 #define AR8X16_MODE_MAC0_RGMII_EN (1u << 1)
72 #define AR8X16_MODE_PHY4_GMII_EN (1u << 2)
73 #define AR8X16_MODE_PHY4_RGMII_EN (1u << 3)
74 #define AR8X16_MODE_MAC0_MAC_MODE (1u << 4)
75 #define AR8X16_MODE_RGMII_RXCLK_DELAY_EN (1u << 6)
76 #define AR8X16_MODE_RGMII_TXCLK_DELAY_EN (1u << 7)
77 #define AR8X16_MODE_MAC5_MAC_MODE (1u << 14)
78 #define AR8X16_MODE_MAC5_PHY_MODE (1u << 15)
79 #define AR8X16_MODE_TXDELAY_S0 (1u << 21)
80 #define AR8X16_MODE_TXDELAY_S1 (1u << 22)
81 #define AR8X16_MODE_RXDELAY_S0 (1u << 23)
82 #define AR8X16_MODE_LED_OPEN_EN (1u << 24)
83 #define AR8X16_MODE_SPI_EN (1u << 25)
84 #define AR8X16_MODE_RXDELAY_S1 (1u << 26)
85 #define AR8X16_MODE_POWER_ON_SEL (1u << 31)
87 #define AR8X16_REG_ISR 0x0010
88 #define AR8X16_REG_IMR 0x0014
90 #define AR8X16_REG_SW_MAC_ADDR0 0x0020
91 #define AR8X16_REG_SW_MAC_ADDR0_BYTE4 BITS(8, 8)
92 #define AR8X16_REG_SW_MAC_ADDR0_BYTE4_S 8
93 #define AR8X16_REG_SW_MAC_ADDR0_BYTE5 BITS(0, 8)
94 #define AR8X16_REG_SW_MAC_ADDR0_BYTE5_S 0
96 #define AR8X16_REG_SW_MAC_ADDR1 0x0024
97 #define AR8X16_REG_SW_MAC_ADDR1_BYTE0 BITS(24, 8)
98 #define AR8X16_REG_SW_MAC_ADDR1_BYTE0_S 24
99 #define AR8X16_REG_SW_MAC_ADDR1_BYTE1 BITS(16, 8)
100 #define AR8X16_REG_SW_MAC_ADDR1_BYTE1_S 16
101 #define AR8X16_REG_SW_MAC_ADDR1_BYTE2 BITS(8, 8)
102 #define AR8X16_REG_SW_MAC_ADDR1_BYTE2_S 8
103 #define AR8X16_REG_SW_MAC_ADDR1_BYTE3 BITS(0, 8)
104 #define AR8X16_REG_SW_MAC_ADDR1_BYTE3_S 0
106 #define AR8X16_REG_FLOOD_MASK 0x002c
107 #define AR8X16_FLOOD_MASK_BCAST_TO_CPU (1 << 26)
109 #define AR8X16_REG_GLOBAL_CTRL 0x0030
110 #define AR8216_GLOBAL_CTRL_MTU_MASK 0x00000fff
111 #define AR8216_GLOBAL_CTRL_MTU_MASK_S 0
112 #define AR8316_GLOBAL_CTRL_MTU_MASK 0x00007fff
113 #define AR8316_GLOBAL_CTRL_MTU_MASK_S 0
114 #define AR8236_GLOBAL_CTRL_MTU_MASK 0x00007fff
115 #define AR8236_GLOBAL_CTRL_MTU_MASK_S 0
116 #define AR7240_GLOBAL_CTRL_MTU_MASK 0x00003fff
117 #define AR7240_GLOBAL_CTRL_MTU_MASK_S 0
119 #define AR8X16_REG_VLAN_CTRL 0x0040
120 #define AR8X16_VLAN_OP 0x00000007
121 #define AR8X16_VLAN_OP_NOOP 0x0
122 #define AR8X16_VLAN_OP_FLUSH 0x1
123 #define AR8X16_VLAN_OP_LOAD 0x2
124 #define AR8X16_VLAN_OP_PURGE 0x3
125 #define AR8X16_VLAN_OP_REMOVE_PORT 0x4
126 #define AR8X16_VLAN_OP_GET_NEXT 0x5
127 #define AR8X16_VLAN_OP_GET 0x6
128 #define AR8X16_VLAN_ACTIVE (1 << 3)
129 #define AR8X16_VLAN_FULL (1 << 4)
130 #define AR8X16_VLAN_PORT 0x00000f00
131 #define AR8X16_VLAN_PORT_SHIFT 8
132 #define AR8X16_VLAN_VID 0x0fff0000
133 #define AR8X16_VLAN_VID_SHIFT 16
134 #define AR8X16_VLAN_PRIO 0x70000000
135 #define AR8X16_VLAN_PRIO_SHIFT 28
136 #define AR8X16_VLAN_PRIO_EN (1U << 31)
138 #define AR8X16_REG_VLAN_DATA 0x0044
139 #define AR8X16_VLAN_MEMBER 0x0000003f
140 #define AR8X16_VLAN_VALID (1 << 11)
142 #define AR8216_REG_ATU 0x0050
143 #define AR8216_ATU_OP BITS(0, 3)
144 #define AR8216_ATU_OP_NOOP 0x0
145 #define AR8216_ATU_OP_FLUSH 0x1
146 #define AR8216_ATU_OP_LOAD 0x2
147 #define AR8216_ATU_OP_PURGE 0x3
148 #define AR8216_ATU_OP_FLUSH_LOCKED 0x4
149 #define AR8216_ATU_OP_FLUSH_UNICAST 0x5
150 #define AR8216_ATU_OP_GET_NEXT 0x6
151 #define AR8216_ATU_ACTIVE BIT(3)
152 #define AR8216_ATU_PORT_NUM BITS(8, 4)
153 #define AR8216_ATU_PORT_NUM_S 8
154 #define AR8216_ATU_FULL_VIO BIT(12)
155 #define AR8216_ATU_ADDR5 BITS(16, 8)
156 #define AR8216_ATU_ADDR5_S 16
157 #define AR8216_ATU_ADDR4 BITS(24, 8)
158 #define AR8216_ATU_ADDR4_S 24
160 #define AR8216_REG_ATU_DATA 0x0054
161 #define AR8216_ATU_ADDR3 BITS(0, 8)
162 #define AR8216_ATU_ADDR3_S 0
163 #define AR8216_ATU_ADDR2 BITS(8, 8)
164 #define AR8216_ATU_ADDR2_S 8
165 #define AR8216_ATU_ADDR1 BITS(16, 8)
166 #define AR8216_ATU_ADDR1_S 16
167 #define AR8216_ATU_ADDR0 BITS(24, 8)
168 #define AR8216_ATU_ADDR0_S 24
170 #define AR8216_REG_ATU_CTRL2 0x0058
171 #define AR8216_ATU_CTRL2_DESPORT BITS(0, 5)
172 #define AR8216_ATU_CTRL2_DESPORT_S 0
173 #define AR934X_ATU_CROSS_STATE_PORT_EN BIT(8)
174 #define AR934X_ATU_HASH_HIGH_ADDR BIT(9) /* Used for CPU_FUNC (get_next_valid) */
175 #define AR8216_ATU_CTRL2_AT_PRIORITY BITS(10, 2)
176 #define AR8216_ATU_CTRL2_AT_PRIORITY_EN BIT(12)
177 #define AR8216_ATU_CTRL2_MIRROR_EN BIT(13)
178 #define AR8216_ATU_CTRL2_SA_DROP_EN BIT(14)
179 #define AR934X_ATU_CTRL2_MAC_CLONE BIT(15)
180 #define AR8216_ATU_CTRL2_AT_STATUS BITS(16, 4)
181 #define AR8216_ATU_CTRL2_AT_STATUS_S 16
183 * For at least the AR9340 -
185 * 1-7: dynamic, valid
186 * 15: static, won't be aged
188 #define AR8216_ATU_CTRL2_VLAN_LEAKY_EN BIT(24)
190 * This defines whether this MAC will leak between VLANs;
191 * controlled by ARL_UNI_LEAKY_EN and ARL_MULTI_LEAKY_EN.
193 #define AR8216_ATU_CTRL2_REDIRECT2CPU BIT(25)
194 #define AR8216_ATU_CTRL2_COPY2CPU BIT(26)
196 #define AR8216_REG_ATU_CTRL 0x005C
197 #define AR8216_ATU_CTRL_AGE_TIME BITS(0, 16)
198 #define AR8216_ATU_CTRL_AGE_TIME_S 0
199 #define AR8216_ATU_CTRL_AGE_EN BIT(17)
200 #define AR8216_ATU_CTRL_LEARN_CHANGE BIT(18)
201 #define AR8216_ATU_CTRL_ARP_EN BIT(20)
203 #define AR8X16_REG_IP_PRIORITY_1 0x0060
204 #define AR8X16_REG_IP_PRIORITY_2 0x0064
205 #define AR8X16_REG_IP_PRIORITY_3 0x0068
206 #define AR8X16_REG_IP_PRIORITY_4 0x006C
208 #define AR8X16_REG_TAG_PRIO 0x0070
210 #define AR8X16_REG_SERVICE_TAG 0x0074
211 #define AR8X16_SERVICE_TAG_MASK 0x0000ffff
213 #define AR8X16_REG_CPU_PORT 0x0078
214 #define AR8X16_MIRROR_PORT_SHIFT 4
215 #define AR8X16_MIRROR_PORT_MASK (0xf << AR8X16_MIRROR_PORT_SHIFT)
216 #define AR8X16_CPU_MIRROR_PORT(_p) ((_p) << AR8X16_MIRROR_PORT_SHIFT)
217 #define AR8X16_CPU_MIRROR_DIS AR8X16_CPU_MIRROR_PORT(0xf)
218 #define AR8X16_CPU_PORT_EN (1 << 8)
220 #define AR8X16_REG_MIB_FUNC0 0x0080
221 #define AR8X16_MIB_TIMER_MASK 0x0000ffff
222 #define AR8X16_MIB_AT_HALF_EN (1 << 16)
223 #define AR8X16_MIB_BUSY (1 << 17)
224 #define AR8X16_MIB_FUNC_SHIFT 24
225 #define AR8X16_MIB_FUNC_NO_OP 0x0
226 #define AR8X16_MIB_FUNC_FLUSH 0x1
227 #define AR8X16_MIB_FUNC_CAPTURE 0x3
228 #define AR8X16_MIB_FUNC_XXX (1 << 30) /* 0x40000000 */
230 #define AR934X_MIB_ENABLE (1 << 30)
232 #define AR8X16_REG_MDIO_HIGH_ADDR 0x0094
234 #define AR8X16_REG_MDIO_CTRL 0x0098
235 #define AR8X16_MDIO_CTRL_DATA_MASK 0x0000ffff
236 #define AR8X16_MDIO_CTRL_REG_ADDR_SHIFT 16
237 #define AR8X16_MDIO_CTRL_PHY_ADDR_SHIFT 21
238 #define AR8X16_MDIO_CTRL_CMD_WRITE 0
239 #define AR8X16_MDIO_CTRL_CMD_READ (1 << 27)
240 #define AR8X16_MDIO_CTRL_MASTER_EN (1 << 30)
241 #define AR8X16_MDIO_CTRL_BUSY (1U << 31)
243 #define AR8X16_REG_PORT_BASE(_p) (0x0100 + (_p) * 0x0100)
245 #define AR8X16_REG_PORT_STS(_p) (AR8X16_REG_PORT_BASE((_p)) + 0x0000)
246 #define AR8X16_PORT_STS_SPEED_MASK 0x00000003
247 #define AR8X16_PORT_STS_SPEED_10 0
248 #define AR8X16_PORT_STS_SPEED_100 1
249 #define AR8X16_PORT_STS_SPEED_1000 2
250 #define AR8X16_PORT_STS_TXMAC (1 << 2)
251 #define AR8X16_PORT_STS_RXMAC (1 << 3)
252 #define AR8X16_PORT_STS_TXFLOW (1 << 4)
253 #define AR8X16_PORT_STS_RXFLOW (1 << 5)
254 #define AR8X16_PORT_STS_DUPLEX (1 << 6)
255 #define AR8X16_PORT_STS_LINK_UP (1 << 8)
256 #define AR8X16_PORT_STS_LINK_AUTO (1 << 9)
257 #define AR8X16_PORT_STS_LINK_PAUSE (1 << 10)
259 #define AR8X16_REG_PORT_CTRL(_p) (AR8X16_REG_PORT_BASE((_p)) + 0x0004)
260 #define AR8X16_PORT_CTRL_STATE_MASK 0x00000007
261 #define AR8X16_PORT_CTRL_STATE_DISABLED 0
262 #define AR8X16_PORT_CTRL_STATE_BLOCK 1
263 #define AR8X16_PORT_CTRL_STATE_LISTEN 2
264 #define AR8X16_PORT_CTRL_STATE_LEARN 3
265 #define AR8X16_PORT_CTRL_STATE_FORWARD 4
266 #define AR8X16_PORT_CTRL_LEARN_LOCK (1 << 7)
267 #define AR8X16_PORT_CTRL_EGRESS_VLAN_MODE_SHIFT 8
268 #define AR8X16_PORT_CTRL_EGRESS_VLAN_MODE_KEEP 0
269 #define AR8X16_PORT_CTRL_EGRESS_VLAN_MODE_STRIP 1
270 #define AR8X16_PORT_CTRL_EGRESS_VLAN_MODE_ADD 2
271 #define AR8X16_PORT_CTRL_EGRESS_VLAN_MODE_DOUBLE_TAG 3
272 #define AR8X16_PORT_CTRL_IGMP_SNOOP (1 << 10)
273 #define AR8X16_PORT_CTRL_HEADER (1 << 11)
274 #define AR8X16_PORT_CTRL_MAC_LOOP (1 << 12)
275 #define AR8X16_PORT_CTRL_SINGLE_VLAN (1 << 13)
276 #define AR8X16_PORT_CTRL_LEARN (1 << 14)
277 #define AR8X16_PORT_CTRL_DOUBLE_TAG (1 << 15)
278 #define AR8X16_PORT_CTRL_MIRROR_TX (1 << 16)
279 #define AR8X16_PORT_CTRL_MIRROR_RX (1 << 17)
281 #define AR8X16_REG_PORT_VLAN(_p) (AR8X16_REG_PORT_BASE((_p)) + 0x0008)
283 #define AR8X16_PORT_VLAN_DEFAULT_ID_SHIFT 0
284 #define AR8X16_PORT_VLAN_DEST_PORTS_SHIFT 16
285 #define AR8X16_PORT_VLAN_MODE_MASK 0xc0000000
286 #define AR8X16_PORT_VLAN_MODE_SHIFT 30
287 #define AR8X16_PORT_VLAN_MODE_PORT_ONLY 0
288 #define AR8X16_PORT_VLAN_MODE_PORT_FALLBACK 1
289 #define AR8X16_PORT_VLAN_MODE_VLAN_ONLY 2
290 #define AR8X16_PORT_VLAN_MODE_SECURE 3
292 #define AR8X16_REG_PORT_RATE_LIM(_p) (AR8X16_REG_PORT_BASE((_p)) + 0x000c)
293 #define AR8X16_PORT_RATE_LIM_128KB 0
294 #define AR8X16_PORT_RATE_LIM_256KB 1
295 #define AR8X16_PORT_RATE_LIM_512KB 2
296 #define AR8X16_PORT_RATE_LIM_1MB 3
297 #define AR8X16_PORT_RATE_LIM_2MB 4
298 #define AR8X16_PORT_RATE_LIM_4MB 5
299 #define AR8X16_PORT_RATE_LIM_8MB 6
300 #define AR8X16_PORT_RATE_LIM_16MB 7
301 #define AR8X16_PORT_RATE_LIM_32MB 8
302 #define AR8X16_PORT_RATE_LIM_64MB 9
303 #define AR8X16_PORT_RATE_LIM_IN_EN (1 << 24)
304 #define AR8X16_PORT_RATE_LIM_OUT_EN (1 << 23)
305 #define AR8X16_PORT_RATE_LIM_IN_MASK 0x000f0000
306 #define AR8X16_PORT_RATE_LIM_IN_SHIFT 16
307 #define AR8X16_PORT_RATE_LIM_OUT_MASK 0x0000000f
308 #define AR8X16_PORT_RATE_LIM_OUT_SHIFT 0
310 #define AR8X16_REG_PORT_PRIORITY(_p) (AR8X16_REG_PORT_BASE((_p)) + 0x0010)
312 #define AR8X16_REG_STATS_BASE(_p) (0x20000 + (_p) * 0x100)
314 #define AR8X16_STATS_RXBROAD 0x0000
315 #define AR8X16_STATS_RXPAUSE 0x0004
316 #define AR8X16_STATS_RXMULTI 0x0008
317 #define AR8X16_STATS_RXFCSERR 0x000c
318 #define AR8X16_STATS_RXALIGNERR 0x0010
319 #define AR8X16_STATS_RXRUNT 0x0014
320 #define AR8X16_STATS_RXFRAGMENT 0x0018
321 #define AR8X16_STATS_RX64BYTE 0x001c
322 #define AR8X16_STATS_RX128BYTE 0x0020
323 #define AR8X16_STATS_RX256BYTE 0x0024
324 #define AR8X16_STATS_RX512BYTE 0x0028
325 #define AR8X16_STATS_RX1024BYTE 0x002c
326 #define AR8X16_STATS_RX1518BYTE 0x0030
327 #define AR8X16_STATS_RXMAXBYTE 0x0034
328 #define AR8X16_STATS_RXTOOLONG 0x0038
329 #define AR8X16_STATS_RXGOODBYTE 0x003c
330 #define AR8X16_STATS_RXBADBYTE 0x0044
331 #define AR8X16_STATS_RXOVERFLOW 0x004c
332 #define AR8X16_STATS_FILTERED 0x0050
333 #define AR8X16_STATS_TXBROAD 0x0054
334 #define AR8X16_STATS_TXPAUSE 0x0058
335 #define AR8X16_STATS_TXMULTI 0x005c
336 #define AR8X16_STATS_TXUNDERRUN 0x0060
337 #define AR8X16_STATS_TX64BYTE 0x0064
338 #define AR8X16_STATS_TX128BYTE 0x0068
339 #define AR8X16_STATS_TX256BYTE 0x006c
340 #define AR8X16_STATS_TX512BYTE 0x0070
341 #define AR8X16_STATS_TX1024BYTE 0x0074
342 #define AR8X16_STATS_TX1518BYTE 0x0078
343 #define AR8X16_STATS_TXMAXBYTE 0x007c
344 #define AR8X16_STATS_TXOVERSIZE 0x0080
345 #define AR8X16_STATS_TXBYTE 0x0084
346 #define AR8X16_STATS_TXCOLLISION 0x008c
347 #define AR8X16_STATS_TXABORTCOL 0x0090
348 #define AR8X16_STATS_TXMULTICOL 0x0094
349 #define AR8X16_STATS_TXSINGLECOL 0x0098
350 #define AR8X16_STATS_TXEXCDEFER 0x009c
351 #define AR8X16_STATS_TXDEFER 0x00a0
352 #define AR8X16_STATS_TXLATECOL 0x00a4
354 #define AR8X16_PORT_CPU 0
355 #define AR8X16_NUM_PORTS 6
356 #define AR8X16_NUM_PHYS 5
357 #define AR8X16_MAGIC 0xc000050e
359 #define AR8X16_PHY_ID1 0x004d
360 #define AR8X16_PHY_ID2 0xd041
362 #define AR8X16_PORT_MASK(_port) (1 << (_port))
363 #define AR8X16_PORT_MASK_ALL ((1<<AR8X16_NUM_PORTS)-1)
364 #define AR8X16_PORT_MASK_BUT(_port) (AR8X16_PORT_MASK_ALL & ~(1 << (_port)))
366 #define AR8X16_MAX_VLANS 16
369 * AR9340 switch specific definitions.
372 #define AR934X_REG_OPER_MODE0 0x04
373 #define AR934X_OPER_MODE0_MAC_GMII_EN (1 << 6)
374 #define AR934X_OPER_MODE0_PHY_MII_EN (1 << 10)
376 #define AR934X_REG_OPER_MODE1 0x08
377 #define AR934X_REG_OPER_MODE1_PHY4_MII_EN (1 << 28)
379 #define AR934X_REG_FLOOD_MASK 0x2c
380 #define AR934X_FLOOD_MASK_UC_DP(_p) (1 << (0 + (_p)))
381 #define AR934X_FLOOD_MASK_MC_DP(_p) (1 << (16 + (_p)))
382 #define AR934X_FLOOD_MASK_BC_DP(_p) (1 << (25 + (_p)))
384 #define AR934X_REG_QM_CTRL 0x3c
385 #define AR934X_QM_CTRL_ARP_EN (1 << 15)
386 #define AR934X_QM_CTRL_ARP_COPY_EN (1 << 14)
388 #define AR934X_REG_AT_CTRL 0x5c
389 #define AR934X_AT_CTRL_AGE_TIME BITS(0, 15)
390 #define AR934X_AT_CTRL_AGE_EN (1 << 17)
391 #define AR934X_AT_CTRL_LEARN_CHANGE (1 << 18)
393 #define AR934X_REG_PORT_BASE(_port) (0x100 + (_port) * 0x100)
395 #define AR934X_REG_PORT_VLAN1(_port) (AR934X_REG_PORT_BASE((_port)) + 0x08)
396 #define AR934X_PORT_VLAN1_DEFAULT_SVID_S 0
397 #define AR934X_PORT_VLAN1_FORCE_DEFAULT_VID_EN (1 << 12)
398 #define AR934X_PORT_VLAN1_PORT_TLS_MODE (1 << 13)
399 #define AR934X_PORT_VLAN1_PORT_VLAN_PROP_EN (1 << 14)
400 #define AR934X_PORT_VLAN1_PORT_CLONE_EN (1 << 15)
401 #define AR934X_PORT_VLAN1_DEFAULT_CVID_S 16
402 #define AR934X_PORT_VLAN1_FORCE_PORT_VLAN_EN (1 << 28)
403 #define AR934X_PORT_VLAN1_ING_PORT_PRI_S 29
405 #define AR934X_REG_PORT_VLAN2(_port) (AR934X_REG_PORT_BASE((_port)) + 0x0c)
406 #define AR934X_PORT_VLAN2_PORT_VID_MEM_S 16
407 #define AR934X_PORT_VLAN2_8021Q_MODE_S 30
408 #define AR934X_PORT_VLAN2_8021Q_MODE_PORT_ONLY 0
409 #define AR934X_PORT_VLAN2_8021Q_MODE_PORT_FALLBACK 1
410 #define AR934X_PORT_VLAN2_8021Q_MODE_VLAN_ONLY 2
411 #define AR934X_PORT_VLAN2_8021Q_MODE_SECURE 3
414 * AR8327 specific registers
416 #define AR8327_NUM_PORTS 7
417 #define AR8327_NUM_PHYS 5
418 #define AR8327_PORTS_ALL 0x7f
420 #define AR8327_PORT_GMAC0 0
421 #define AR8327_PORT_GMAC6 6
423 #define AR8327_REG_MASK 0x000
425 #define AR8327_REG_PAD0_MODE 0x004
426 #define AR8327_REG_PAD5_MODE 0x008
427 #define AR8327_REG_PAD6_MODE 0x00c
429 #define AR8327_PAD_MAC_MII_RXCLK_SEL (1 << 0)
430 #define AR8327_PAD_MAC_MII_TXCLK_SEL (1 << 1)
431 #define AR8327_PAD_MAC_MII_EN (1 << 2)
432 #define AR8327_PAD_MAC_GMII_RXCLK_SEL (1 << 4)
433 #define AR8327_PAD_MAC_GMII_TXCLK_SEL (1 << 5)
434 #define AR8327_PAD_MAC_GMII_EN (1 << 6)
435 #define AR8327_PAD_SGMII_EN (1 << 7)
436 #define AR8327_PAD_PHY_MII_RXCLK_SEL (1 << 8)
437 #define AR8327_PAD_PHY_MII_TXCLK_SEL (1 << 9)
438 #define AR8327_PAD_PHY_MII_EN (1 << 10)
439 #define AR8327_PAD_PHY_GMII_PIPE_RXCLK_SEL (1 << 11)
440 #define AR8327_PAD_PHY_GMII_RXCLK_SEL (1 << 12)
441 #define AR8327_PAD_PHY_GMII_TXCLK_SEL (1 << 13)
442 #define AR8327_PAD_PHY_GMII_EN (1 << 14)
443 #define AR8327_PAD_PHYX_GMII_EN (1 << 16)
444 #define AR8327_PAD_PHYX_RGMII_EN (1 << 17)
445 #define AR8327_PAD_PHYX_MII_EN (1 << 18)
446 #define AR8327_PAD_SGMII_DELAY_EN (1 << 19)
447 #define AR8327_PAD_RGMII_RXCLK_DELAY_SEL BITS(20, 2)
448 #define AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S 20
449 #define AR8327_PAD_RGMII_TXCLK_DELAY_SEL BITS(22, 2)
450 #define AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S 22
451 #define AR8327_PAD_RGMII_RXCLK_DELAY_EN (1 << 24)
452 #define AR8327_PAD_RGMII_TXCLK_DELAY_EN (1 << 25)
453 #define AR8327_PAD_RGMII_EN (1 << 26)
455 #define AR8327_REG_POWER_ON_STRIP 0x010
456 #define AR8327_POWER_ON_STRIP_POWER_ON_SEL (1U << 31)
457 #define AR8327_POWER_ON_STRIP_LED_OPEN_EN (1 << 24)
458 #define AR8327_POWER_ON_STRIP_SERDES_AEN (1 << 7)
460 #define AR8327_REG_INT_STATUS0 0x020
461 #define AR8327_INT0_VT_DONE (1 << 20)
463 #define AR8327_REG_INT_STATUS1 0x024
464 #define AR8327_REG_INT_MASK0 0x028
465 #define AR8327_REG_INT_MASK1 0x02c
467 #define AR8327_REG_MODULE_EN 0x030
468 #define AR8327_MODULE_EN_MIB (1 << 0)
470 #define AR8327_REG_MIB_FUNC 0x034
471 #define AR8327_MIB_CPU_KEEP (1 << 20)
473 #define AR8327_REG_MDIO_CTRL 0x03c
475 #define AR8327_REG_SERVICE_TAG 0x048
476 #define AR8327_REG_LED_CTRL0 0x050
477 #define AR8327_REG_LED_CTRL1 0x054
478 #define AR8327_REG_LED_CTRL2 0x058
479 #define AR8327_REG_LED_CTRL3 0x05c
480 #define AR8327_REG_MAC_ADDR0 0x060
481 #define AR8327_REG_MAC_ADDR1 0x064
483 #define AR8327_REG_MAX_FRAME_SIZE 0x078
484 #define AR8327_MAX_FRAME_SIZE_MTU BITS(0, 14)
486 #define AR8327_REG_PORT_STATUS(_i) (0x07c + (_i) * 4)
488 #define AR8327_REG_HEADER_CTRL 0x098
489 #define AR8327_REG_PORT_HEADER(_i) (0x09c + (_i) * 4)
491 #define AR8327_REG_SGMII_CTRL 0x0e0
492 #define AR8327_SGMII_CTRL_EN_PLL (1 << 1)
493 #define AR8327_SGMII_CTRL_EN_RX (1 << 2)
494 #define AR8327_SGMII_CTRL_EN_TX (1 << 3)
496 #define AR8327_REG_EEE_CTRL 0x100
497 #define AR8327_EEE_CTRL_DISABLE_PHY(_i) BIT(4 + (_i) * 2)
499 #define AR8327_REG_PORT_VLAN0(_i) (0x420 + (_i) * 0x8)
500 #define AR8327_PORT_VLAN0_DEF_SVID BITS(0, 12)
501 #define AR8327_PORT_VLAN0_DEF_SVID_S 0
502 #define AR8327_PORT_VLAN0_DEF_CVID BITS(16, 12)
503 #define AR8327_PORT_VLAN0_DEF_CVID_S 16
505 #define AR8327_REG_PORT_VLAN1(_i) (0x424 + (_i) * 0x8)
506 #define AR8327_PORT_VLAN1_PORT_VLAN_PROP (1 << 6)
507 #define AR8327_PORT_VLAN1_OUT_MODE BITS(12, 2)
508 #define AR8327_PORT_VLAN1_OUT_MODE_S 12
509 #define AR8327_PORT_VLAN1_OUT_MODE_UNMOD 0
510 #define AR8327_PORT_VLAN1_OUT_MODE_UNTAG 1
511 #define AR8327_PORT_VLAN1_OUT_MODE_TAG 2
512 #define AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH 3
514 #define AR8327_REG_ATU_DATA0 0x600
515 #define AR8327_ATU_DATA0_MAC_ADDR3 BITS(0, 8)
516 #define AR8327_ATU_DATA0_MAC_ADDR3_S 0
517 #define AR8327_ATU_DATA0_MAC_ADDR2 BITS(8, 8)
518 #define AR8327_ATU_DATA0_MAC_ADDR2_S 8
519 #define AR8327_ATU_DATA0_MAC_ADDR1 BITS(16, 8)
520 #define AR8327_ATU_DATA0_MAC_ADDR1_S 16
521 #define AR8327_ATU_DATA0_MAC_ADDR0 BITS(24, 8)
522 #define AR8327_ATU_DATA0_MAC_ADDR0_S 24
524 #define AR8327_REG_ATU_DATA1 0x604
525 #define AR8327_ATU_DATA1_MAC_ADDR4 BITS(0, 8)
526 #define AR8327_ATU_DATA1_MAC_ADDR4_S 0
527 #define AR8327_ATU_DATA1_MAC_ADDR5 BITS(8, 8)
528 #define AR8327_ATU_DATA1_MAC_ADDR5_S 8
529 #define AR8327_ATU_DATA1_DEST_PORT BITS(16, 7)
530 #define AR8327_ATU_DATA1_DEST_PORT_S 16
531 #define AR8327_ATU_DATA1_CROSS_PORT_STATE_EN BIT(23)
532 #define AR8327_ATU_DATA1_PRI BITS(24, 3)
533 #define AR8327_ATU_DATA1_SVL_ENTRY BIT(27)
534 #define AR8327_ATU_DATA1_PRI_OVER_EN BIT(28)
535 #define AR8327_ATU_DATA1_MIRROR_EN BIT(29)
536 #define AR8327_ATU_DATA1_SA_DROP_EN BIT(30)
537 #define AR8327_ATU_DATA1_HASH_HIGH_ADDR BIT(31)
539 #define AR8327_REG_ATU_DATA2 0x608
540 #define AR8327_ATU_FUNC_DATA2_STATUS BITS(0, 4)
541 #define AR8327_ATU_FUNC_DATA2_STATUS_S 0
542 #define AR8327_ATU_FUNC_DATA2_VLAN_LEAKY_EN BIT(4)
543 #define AR8327_ATU_FUNC_DATA2_REDIRECT_TO_CPU BIT(5)
544 #define AR8327_ATU_FUNC_DATA2_COPY_TO_CPU BIT(6)
545 #define AR8327_ATU_FUNC_DATA2_SHORT_LOOP BIT(7)
546 #define AR8327_ATU_FUNC_DATA2_ATU_VID BITS(8, 12)
547 #define AR8327_ATU_FUNC_DATA2_ATU_VID_S 8
549 #define AR8327_REG_ATU_FUNC 0x60c
550 #define AR8327_ATU_FUNC_OP BITS(0, 4)
551 #define AR8327_ATU_FUNC_OP_NOOP 0x0
552 #define AR8327_ATU_FUNC_OP_FLUSH 0x1
553 #define AR8327_ATU_FUNC_OP_LOAD 0x2
554 #define AR8327_ATU_FUNC_OP_PURGE 0x3
555 #define AR8327_ATU_FUNC_OP_FLUSH_LOCKED 0x4
556 #define AR8327_ATU_FUNC_OP_FLUSH_UNICAST 0x5
557 #define AR8327_ATU_FUNC_OP_GET_NEXT 0x6
558 #define AR8327_ATU_FUNC_OP_SEARCH_MAC 0x7
559 #define AR8327_ATU_FUNC_OP_CHANGE_TRUNK 0x8
560 #define AR8327_ATU_FUNC_FLUSH_STATIC_EN BIT(4)
561 #define AR8327_ATU_FUNC_ENTRY_TYPE BIT(5)
562 #define AR8327_ATU_FUNC_PORT_NUM BITS(8, 4)
563 #define AR8327_ATU_FUNC_PORT_NUM_S 8
564 #define AR8327_ATU_FUNC_FULL_VIOLATION BIT(12)
565 #define AR8327_ATU_FUNC_MULTI_EN BIT(13) /* for GET_NEXT */
566 #define AR8327_ATU_FUNC_PORT_EN BIT(14) /* for GET_NEXT */
567 #define AR8327_ATU_FUNC_VID_EN BIT(15) /* for GET_NEXT */
568 #define AR8327_ATU_FUNC_ATU_INDEX BITS(16, 5)
569 #define AR8327_ATU_FUNC_ATU_INDEX_S 16
570 #define AR8327_ATU_FUNC_TRUNK_PORT_NUM BITS(22, 3) /* for CHANGE_TRUNK */
571 #define AR8327_ATU_FUNC_TRUNK_PORT_NUM_S 22
572 #define AR8327_ATU_FUNC_BUSY BIT(31)
574 #define AR8327_REG_VTU_FUNC0 0x0610
575 #define AR8327_VTU_FUNC0_EG_MODE BITS(4, 14)
576 #define AR8327_VTU_FUNC0_EG_MODE_S(_i) (4 + (_i) * 2)
577 #define AR8327_VTU_FUNC0_EG_MODE_KEEP 0
578 #define AR8327_VTU_FUNC0_EG_MODE_UNTAG 1
579 #define AR8327_VTU_FUNC0_EG_MODE_TAG 2
580 #define AR8327_VTU_FUNC0_EG_MODE_NOT 3
581 #define AR8327_VTU_FUNC0_IVL (1 << 19)
582 #define AR8327_VTU_FUNC0_VALID (1 << 20)
584 #define AR8327_REG_VTU_FUNC1 0x0614
585 #define AR8327_VTU_FUNC1_OP BITS(0, 3)
586 #define AR8327_VTU_FUNC1_OP_NOOP 0
587 #define AR8327_VTU_FUNC1_OP_FLUSH 1
588 #define AR8327_VTU_FUNC1_OP_LOAD 2
589 #define AR8327_VTU_FUNC1_OP_PURGE 3
590 #define AR8327_VTU_FUNC1_OP_REMOVE_PORT 4
591 #define AR8327_VTU_FUNC1_OP_GET_NEXT 5
592 #define AR8327_VTU_FUNC1_OP_GET_ONE 6
593 #define AR8327_VTU_FUNC1_FULL (1 << 4)
594 #define AR8327_VTU_FUNC1_PORT (1 << 8, 4)
595 #define AR8327_VTU_FUNC1_PORT_S 8
596 #define AR8327_VTU_FUNC1_VID (1 << 16, 12)
597 #define AR8327_VTU_FUNC1_VID_S 16
598 #define AR8327_VTU_FUNC1_BUSY (1U << 31)
600 #define AR8327_REG_FWD_CTRL0 0x620
601 #define AR8327_FWD_CTRL0_CPU_PORT_EN (1 << 10)
602 #define AR8327_FWD_CTRL0_MIRROR_PORT BITS(4, 4)
603 #define AR8327_FWD_CTRL0_MIRROR_PORT_S 4
605 #define AR8327_REG_FWD_CTRL1 0x624
606 #define AR8327_FWD_CTRL1_UC_FLOOD BITS(0, 7)
607 #define AR8327_FWD_CTRL1_UC_FLOOD_S 0
608 #define AR8327_FWD_CTRL1_MC_FLOOD BITS(8, 7)
609 #define AR8327_FWD_CTRL1_MC_FLOOD_S 8
610 #define AR8327_FWD_CTRL1_BC_FLOOD BITS(16, 7)
611 #define AR8327_FWD_CTRL1_BC_FLOOD_S 16
612 #define AR8327_FWD_CTRL1_IGMP BITS(24, 7)
613 #define AR8327_FWD_CTRL1_IGMP_S 24
615 #define AR8327_REG_PORT_LOOKUP(_i) (0x660 + (_i) * 0xc)
616 #define AR8327_PORT_LOOKUP_MEMBER BITS(0, 7)
617 #define AR8327_PORT_LOOKUP_IN_MODE BITS(8, 2)
618 #define AR8327_PORT_LOOKUP_IN_MODE_S 8
619 #define AR8327_PORT_LOOKUP_STATE BITS(16, 3)
620 #define AR8327_PORT_LOOKUP_STATE_S 16
621 #define AR8327_PORT_LOOKUP_LEARN (1 << 20)
622 #define AR8327_PORT_LOOKUP_ING_MIRROR_EN (1 << 25)
624 #define AR8327_REG_PORT_PRIO(_i) (0x664 + (_i) * 0xc)
626 #define AR8327_REG_PORT_HOL_CTRL1(_i) (0x974 + (_i) * 0x8)
627 #define AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN (1 << 16)
629 #define AR8327_REG_PORT_STATS_BASE(_i) (0x1000 + (_i) * 0x100)
631 #endif /* __AR8X16_SWITCHREG_H__ */