2 * Copyright (c) 2013 Luiz Otavio O Souza.
3 * Copyright (c) 2011-2012 Stefan Bethke.
4 * Copyright (c) 2012 Adrian Chadd.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 #include <sys/param.h>
33 #include <sys/kernel.h>
35 #include <sys/mutex.h>
36 #include <sys/systm.h>
37 #include <sys/socket.h>
41 #include <dev/mii/mii.h>
43 #include <dev/etherswitch/etherswitch.h>
44 #include <dev/etherswitch/ip17x/ip17x_phy.h>
45 #include <dev/etherswitch/ip17x/ip17x_reg.h>
46 #include <dev/etherswitch/ip17x/ip17x_var.h>
47 #include <dev/etherswitch/ip17x/ip17x_vlans.h>
48 #include <dev/etherswitch/ip17x/ip175c.h>
51 * IP175C specific functions.
58 ip175c_reset(struct ip17x_softc *sc)
62 /* Reset all the switch settings. */
63 if (ip17x_writephy(sc->sc_dev, IP175C_RESET_PHY, IP175C_RESET_REG,
68 /* Force IP175C mode. */
69 data = ip17x_readphy(sc->sc_dev, IP175C_MODE_PHY, IP175C_MODE_REG);
71 if (ip17x_writephy(sc->sc_dev, IP175C_MODE_PHY, IP175C_MODE_REG,
80 ip175c_port_vlan_setup(struct ip17x_softc *sc)
83 uint32_t ports[IP175X_NUM_PORTS], reg[IP175X_NUM_PORTS/2];
86 KASSERT(sc->cpuport == 5, ("cpuport != 5 not supported for IP175C"));
87 KASSERT(sc->numports == 6, ("numports != 6 not supported for IP175C"));
89 /* Build the port access masks. */
90 memset(ports, 0, sizeof(ports));
91 for (i = 0; i < sc->info.es_nports; i++) {
94 ports[phy] = v->ports;
97 /* Move the cpuport bit to its correct place. */
98 for (i = 0; i < sc->numports; i++) {
99 if (ports[i] & (1 << sc->cpuport)) {
100 ports[i] |= (1 << 7);
101 ports[i] &= ~(1 << sc->cpuport);
105 /* And now build the switch register data. */
106 memset(reg, 0, sizeof(reg));
107 for (i = 0; i < (sc->numports / 2); i++)
108 reg[i] = ports[i * 2] << 8 | ports[i * 2 + 1];
110 /* Update the switch resgisters. */
111 err = ip17x_writephy(sc->sc_dev, 29, 19, reg[0]);
113 err = ip17x_writephy(sc->sc_dev, 29, 20, reg[1]);
115 err = ip17x_updatephy(sc->sc_dev, 29, 21, 0xff00, reg[2]);
117 err = ip17x_updatephy(sc->sc_dev, 30, 18, 0x00ff, reg[2]);
122 ip175c_dot1q_vlan_setup(struct ip17x_softc *sc)
124 struct ip17x_vlan *v;
126 uint32_t vlans[IP17X_MAX_VLANS];
129 KASSERT(sc->cpuport == 5, ("cpuport != 5 not supported for IP175C"));
130 KASSERT(sc->numports == 6, ("numports != 6 not supported for IP175C"));
132 /* Add and strip VLAN tags. */
133 data = (sc->addtag & ~(1 << IP175X_CPU_PORT)) << 11;
134 data |= (sc->striptag & ~(1 << IP175X_CPU_PORT)) << 6;
135 if (sc->addtag & (1 << IP175X_CPU_PORT))
137 if (sc->striptag & (1 << IP175X_CPU_PORT))
139 if (ip17x_writephy(sc->sc_dev, 29, 23, data))
142 /* Set the VID_IDX_SEL to 0. */
143 if (ip17x_updatephy(sc->sc_dev, 30, 9, 0x70, 0))
146 /* Calculate the port masks. */
147 memset(vlans, 0, sizeof(vlans));
148 for (i = 0; i < IP17X_MAX_VLANS; i++) {
150 if ((v->vlanid & ETHERSWITCH_VID_VALID) == 0)
152 vlans[v->vlanid & ETHERSWITCH_VID_MASK] = v->ports;
155 for (j = 0, i = 1; i <= IP17X_MAX_VLANS / 2; i++) {
156 data = vlans[j++] & 0x3f;
157 data |= (vlans[j++] & 0x3f) << 8;
158 if (ip17x_writephy(sc->sc_dev, 30, i, data))
162 /* Port default VLAN ID. */
163 for (i = 0; i < sc->numports; i++) {
164 if (i == IP175X_CPU_PORT) {
165 if (ip17x_writephy(sc->sc_dev, 29, 30, sc->pvid[i]))
168 if (ip17x_writephy(sc->sc_dev, 29, 24 + i, sc->pvid[i]))
177 * Set the Switch configuration.
180 ip175c_hw_setup(struct ip17x_softc *sc)
183 switch (sc->vlan_mode) {
184 case ETHERSWITCH_VLAN_PORT:
185 return (ip175c_port_vlan_setup(sc));
187 case ETHERSWITCH_VLAN_DOT1Q:
188 return (ip175c_dot1q_vlan_setup(sc));
195 * Set the switch VLAN mode.
198 ip175c_set_vlan_mode(struct ip17x_softc *sc, uint32_t mode)
202 case ETHERSWITCH_VLAN_DOT1Q:
203 /* Enable VLAN tag processing. */
204 ip17x_updatephy(sc->sc_dev, 30, 9, 0x80, 0x80);
205 sc->vlan_mode = mode;
207 case ETHERSWITCH_VLAN_PORT:
209 /* Disable VLAN tag processing. */
210 ip17x_updatephy(sc->sc_dev, 30, 9, 0x80, 0);
211 sc->vlan_mode = ETHERSWITCH_VLAN_PORT;
216 ip17x_reset_vlans(sc, sc->vlan_mode);
218 /* Update switch configuration. */
225 * Get the switch VLAN mode.
228 ip175c_get_vlan_mode(struct ip17x_softc *sc)
231 return (sc->vlan_mode);
235 ip175c_attach(struct ip17x_softc *sc)
239 data = ip17x_readphy(sc->sc_dev, IP175C_MII_PHY, IP175C_MII_CTL_REG);
240 device_printf(sc->sc_dev, "MII: %x\n", data);
241 /* check mii1 interface if disabled then phy4 and mac4 hold on switch */
242 if((data & (1 << IP175C_MII_MII1_RMII_EN)) == 0)
245 sc->hal.ip17x_reset = ip175c_reset;
246 sc->hal.ip17x_hw_setup = ip175c_hw_setup;
247 sc->hal.ip17x_get_vlan_mode = ip175c_get_vlan_mode;
248 sc->hal.ip17x_set_vlan_mode = ip175c_set_vlan_mode;
250 /* Defaults for IP175C. */
251 sc->cpuport = IP175X_CPU_PORT;
252 sc->numports = IP175X_NUM_PORTS;
253 sc->info.es_vlan_caps = ETHERSWITCH_VLAN_PORT | ETHERSWITCH_VLAN_DOT1Q;
255 device_printf(sc->sc_dev, "type: IP175C\n");