2 * Copyright (c) 2011-2012 Stefan Bethke.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 #ifndef _DEV_ETHERSWITCH_RTL8366RBVAR_H_
30 #define _DEV_ETHERSWITCH_RTL8366RBVAR_H_
32 #define RTL8366RB_IIC_ADDR 0xa8
33 #define RTL_IICBUS_TIMEOUT 100 /* us */
34 #define RTL_IICBUS_READ 1
35 #define RTL_IICBUS_WRITE 0
36 /* number of times to try and select the chip on the I2C bus */
37 #define RTL_IICBUS_RETRIES 3
38 #define RTL_IICBUS_RETRY_SLEEP (hz/1000)
40 /* Register definitions */
42 /* Switch Global Configuration */
43 #define RTL8366RB_SGCR 0x0000
44 #define RTL8366RB_SGCR_EN_BC_STORM_CTRL 0x0001
45 #define RTL8366RB_SGCR_MAX_LENGTH_MASK 0x0030
46 #define RTL8366RB_SGCR_MAX_LENGTH_1522 0x0000
47 #define RTL8366RB_SGCR_MAX_LENGTH_1536 0x0010
48 #define RTL8366RB_SGCR_MAX_LENGTH_1552 0x0020
49 #define RTL8366RB_SGCR_MAX_LENGTH_9216 0x0030
50 #define RTL8366RB_SGCR_EN_VLAN 0x2000
51 #define RTL8366RB_SGCR_EN_VLAN_4KTB 0x4000
52 #define RTL8366RB_SGCR_EN_QOS 0x8000
54 /* Port Enable Control: DISABLE_PORT[5:0] */
55 #define RTL8366RB_PECR 0x0001
57 /* Switch Security Control 0: DIS_LEARN[5:0] */
58 #define RTL8366RB_SSCR0 0x0002
60 /* Switch Security Control 1: DIS_AGE[5:0] */
61 #define RTL8366RB_SSCR1 0x0003
63 /* Switch Security Control 2 */
64 #define RTL8366RB_SSCR2 0x0004
65 #define RTL8366RB_SSCR2_DROP_UNKNOWN_DA 0x0001
67 /* Port Link Status: two ports per register */
68 #define RTL8366RB_PLSR_BASE 0x0014
69 #define RTL8366RB_PLSR_SPEED_MASK 0x03
70 #define RTL8366RB_PLSR_SPEED_10 0x00
71 #define RTL8366RB_PLSR_SPEED_100 0x01
72 #define RTL8366RB_PLSR_SPEED_1000 0x02
73 #define RTL8366RB_PLSR_FULLDUPLEX 0x08
74 #define RTL8366RB_PLSR_LINK 0x10
75 #define RTL8366RB_PLSR_TXPAUSE 0x20
76 #define RTL8366RB_PLSR_RXPAUSE 0x40
77 #define RTL8366RB_PLSR_NO_AUTO 0x80
79 /* VLAN Member Configuration, 3 registers per VLAN */
80 #define RTL8366RB_VMCR_BASE 0x0020
81 #define RTL8366RB_VMCR_MULT 3
82 #define RTL8366RB_VMCR_DOT1Q_REG 0
83 #define RTL8366RB_VMCR_DOT1Q_VID_SHIFT 0
84 #define RTL8366RB_VMCR_DOT1Q_VID_MASK 0x0fff
85 #define RTL8366RB_VMCR_DOT1Q_PCP_SHIFT 12
86 #define RTL8366RB_VMCR_DOT1Q_PCP_MASK 0x7000
87 #define RTL8366RB_VMCR_MU_REG 1
88 #define RTL8366RB_VMCR_MU_MEMBER_SHIFT 0
89 #define RTL8366RB_VMCR_MU_MEMBER_MASK 0x00ff
90 #define RTL8366RB_VMCR_MU_UNTAG_SHIFT 8
91 #define RTL8366RB_VMCR_MU_UNTAG_MASK 0xff00
92 #define RTL8366RB_VMCR_FID_REG 2
93 #define RTL8366RB_VMCR_FID_FID_SHIFT 0
94 #define RTL8366RB_VMCR_FID_FID_MASK 0x0007
95 #define RTL8366RB_VMCR(_reg, _vlan) \
96 (RTL8366RB_VMCR_BASE + _reg + _vlan * RTL8366RB_VMCR_MULT)
98 #define RTL8366RB_VMCR_VID(_r) \
99 (_r[RTL8366RB_VMCR_DOT1Q_REG] & RTL8366RB_VMCR_DOT1Q_VID_MASK)
100 /* Priority Code Point */
101 #define RTL8366RB_VMCR_PCP(_r) \
102 ((_r[RTL8366RB_VMCR_DOT1Q_REG] & RTL8366RB_VMCR_DOT1Q_PCP_MASK) \
103 >> RTL8366RB_VMCR_DOT1Q_PCP_SHIFT)
105 #define RTL8366RB_VMCR_MEMBER(_r) \
106 (_r[RTL8366RB_VMCR_MU_REG] & RTL8366RB_VMCR_MU_MEMBER_MASK)
108 #define RTL8366RB_VMCR_UNTAG(_r) \
109 ((_r[RTL8366RB_VMCR_MU_REG] & RTL8366RB_VMCR_MU_UNTAG_MASK) \
110 >> RTL8366RB_VMCR_MU_UNTAG_SHIFT)
112 #define RTL8366RB_VMCR_FID(_r) \
113 (_r[RTL8366RB_VMCR_FID_REG] & RTL8366RB_VMCR_FID_FID_MASK)
116 * Port VLAN Control, 4 ports per register
117 * Determines the VID for untagged ingress frames through
120 #define RTL8366RB_PVCR_BASE 0x0063
121 #define RTL8366RB_PVCR_PORT_SHIFT 4
122 #define RTL8366RB_PVCR_PORT_PERREG (16 / RTL8366RB_PVCR_PORT_SHIFT)
123 #define RTL8366RB_PVCR_PORT_MASK 0x000f
124 #define RTL8366RB_PVCR_REG(_port) \
125 (RTL8366RB_PVCR_BASE + _port / (RTL8366RB_PVCR_PORT_PERREG))
126 #define RTL8366RB_PVCR_VAL(_port, _pvlan) \
127 ((_pvlan & RTL8366RB_PVCR_PORT_MASK) << \
128 ((_port % RTL8366RB_PVCR_PORT_PERREG) * RTL8366RB_PVCR_PORT_SHIFT))
129 #define RTL8366RB_PVCR_GET(_port, _val) \
130 (((_val) >> ((_port % RTL8366RB_PVCR_PORT_PERREG) * RTL8366RB_PVCR_PORT_SHIFT)) & RTL8366RB_PVCR_PORT_MASK)
133 #define RTL8366RB_RCR 0x0100
134 #define RTL8366RB_RCR_HARD_RESET 0x0001
135 #define RTL8366RB_RCR_SOFT_RESET 0x0002
137 /* Chip Version Control: CHIP_VER[3:0] */
138 #define RTL8366RB_CVCR 0x050A
139 /* Chip Identifier */
140 #define RTL8366RB_CIR 0x0509
141 #define RTL8366RB_CIR_ID8366RB 0x5937
143 /* VLAN Ingress Control 2: [5:0] */
144 #define RTL8366RB_VIC2R 0x037f
147 #define RTL8366RB_MCNT_BASE 0x1000
148 #define RTL8366RB_MCTLR 0x13f0
149 #define RTL8366RB_MCTLR_BUSY 0x0001
150 #define RTL8366RB_MCTLR_RESET 0x0002
151 #define RTL8366RB_MCTLR_RESET_PORT_MASK 0x00fc
152 #define RTL8366RB_MCTLR_RESET_ALL 0x0800
154 #define RTL8366RB_MCNT(_port, _r) \
155 (RTL8366RB_MCNT_BASE + 0x50 * (_port) + (_r))
156 #define RTL8366RB_MCTLR_RESET_PORT(_p) \
159 /* PHY Access Control */
160 #define RTL8366RB_PACR 0x8000
161 #define RTL8366RB_PACR_WRITE 0x0000
162 #define RTL8366RB_PACR_READ 0x0001
164 /* PHY Access Data */
165 #define RTL8366RB_PADR 0x8002
167 #define RTL8366RB_PHYREG(phy, page, reg) \
168 (RTL8366RB_PACR | (1 << (((phy) & 0x1f) + 9)) | (((page) & 0xf) << 5) | ((reg) & 0x1f))
170 /* general characteristics of the chip */
171 #define RTL8366RB_NUM_PORTS 6
172 #define RTL8366RB_NUM_PHYS (RTL8366RB_NUM_PORTS-1)
173 #define RTL8366RB_NUM_VLANS 16
174 #define RTL8366RB_NUM_PHY_REG 32