2 * Copyright (c) 2015-2016 Hiroki Mori.
3 * Copyright (c) 2011-2012 Stefan Bethke.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #ifndef _DEV_ETHERSWITCH_RTL8366RBVAR_H_
31 #define _DEV_ETHERSWITCH_RTL8366RBVAR_H_
33 #define RTL8366_IIC_ADDR 0xa8
34 #define RTL_IICBUS_TIMEOUT 100 /* us */
35 #define RTL_IICBUS_READ 1
36 #define RTL_IICBUS_WRITE 0
37 /* number of times to try and select the chip on the I2C bus */
38 #define RTL_IICBUS_RETRIES 3
39 #define RTL_IICBUS_RETRY_SLEEP (hz/1000)
41 /* Register definitions */
43 /* Switch Global Configuration */
44 #define RTL8366_SGCR 0x0000
45 #define RTL8366_SGCR_EN_BC_STORM_CTRL 0x0001
46 #define RTL8366_SGCR_MAX_LENGTH_MASK 0x0030
47 #define RTL8366_SGCR_MAX_LENGTH_1522 0x0000
48 #define RTL8366_SGCR_MAX_LENGTH_1536 0x0010
49 #define RTL8366_SGCR_MAX_LENGTH_1552 0x0020
50 #define RTL8366_SGCR_MAX_LENGTH_9216 0x0030
51 #define RTL8366_SGCR_EN_VLAN 0x2000
52 #define RTL8366_SGCR_EN_VLAN_4KTB 0x4000
53 #define RTL8366_SGCR_EN_QOS 0x8000
55 /* Port Enable Control: DISABLE_PORT[5:0] */
56 #define RTL8366_PECR 0x0001
58 /* Switch Security Control 0: DIS_LEARN[5:0] */
59 #define RTL8366_SSCR0 0x0002
61 /* Switch Security Control 1: DIS_AGE[5:0] */
62 #define RTL8366_SSCR1 0x0003
64 /* Switch Security Control 2 */
65 #define RTL8366_SSCR2 0x0004
66 #define RTL8366_SSCR2_DROP_UNKNOWN_DA 0x0001
68 /* Port Link Status: two ports per register */
69 #define RTL8366_PLSR_BASE (sc->chip_type == 0 ? 0x0014 : 0x0060)
70 #define RTL8366_PLSR_SPEED_MASK 0x03
71 #define RTL8366_PLSR_SPEED_10 0x00
72 #define RTL8366_PLSR_SPEED_100 0x01
73 #define RTL8366_PLSR_SPEED_1000 0x02
74 #define RTL8366_PLSR_FULLDUPLEX 0x04
75 #define RTL8366_PLSR_LINK 0x10
76 #define RTL8366_PLSR_TXPAUSE 0x20
77 #define RTL8366_PLSR_RXPAUSE 0x40
78 #define RTL8366_PLSR_NO_AUTO 0x80
80 /* VLAN Member Configuration, 3 or 2 registers per VLAN */
81 #define RTL8366_VMCR_BASE (sc->chip_type == 0 ? 0x0020 : 0x0016)
82 #define RTL8366_VMCR_MULT (sc->chip_type == 0 ? 3 : 2)
83 #define RTL8366_VMCR_DOT1Q_REG 0
84 #define RTL8366_VMCR_DOT1Q_VID_SHIFT 0
85 #define RTL8366_VMCR_DOT1Q_VID_MASK 0x0fff
86 #define RTL8366_VMCR_DOT1Q_PCP_SHIFT 12
87 #define RTL8366_VMCR_DOT1Q_PCP_MASK 0x7000
88 #define RTL8366_VMCR_MU_REG 1
89 #define RTL8366_VMCR_MU_MEMBER_SHIFT 0
90 #define RTL8366_VMCR_MU_MEMBER_MASK (sc->chip_type == 0 ? 0x00ff : 0x003f)
91 #define RTL8366_VMCR_MU_UNTAG_SHIFT (sc->chip_type == 0 ? 8 : 6)
92 #define RTL8366_VMCR_MU_UNTAG_MASK (sc->chip_type == 0 ? 0xff00 : 0x0fc0)
93 #define RTL8366_VMCR_FID_REG (sc->chip_type == 0 ? 2 : 1)
94 #define RTL8366_VMCR_FID_FID_SHIFT (sc->chip_type == 0 ? 0 : 12)
95 #define RTL8366_VMCR_FID_FID_MASK (sc->chip_type == 0 ? 0x0007 : 0x7000)
96 #define RTL8366_VMCR(_reg, _vlan) \
97 (RTL8366_VMCR_BASE + _reg + _vlan * RTL8366_VMCR_MULT)
99 #define RTL8366_VMCR_VID(_r) \
100 (_r[RTL8366_VMCR_DOT1Q_REG] & RTL8366_VMCR_DOT1Q_VID_MASK)
101 /* Priority Code Point */
102 #define RTL8366_VMCR_PCP(_r) \
103 ((_r[RTL8366_VMCR_DOT1Q_REG] & RTL8366_VMCR_DOT1Q_PCP_MASK) \
104 >> RTL8366_VMCR_DOT1Q_PCP_SHIFT)
106 #define RTL8366_VMCR_MEMBER(_r) \
107 (_r[RTL8366_VMCR_MU_REG] & RTL8366_VMCR_MU_MEMBER_MASK)
109 #define RTL8366_VMCR_UNTAG(_r) \
110 ((_r[RTL8366_VMCR_MU_REG] & RTL8366_VMCR_MU_UNTAG_MASK) \
111 >> RTL8366_VMCR_MU_UNTAG_SHIFT)
113 #define RTL8366_VMCR_FID(_r) \
114 (sc->chip_type == 0 ? (_r[RTL8366_VMCR_FID_REG] & RTL8366_VMCR_FID_FID_MASK) : \
115 ((_r[RTL8366_VMCR_FID_REG] & RTL8366_VMCR_FID_FID_MASK) \
116 >> RTL8366_VMCR_FID_FID_SHIFT))
119 * Port VLAN Control, 4 ports per register
120 * Determines the VID for untagged ingress frames through
123 #define RTL8366_PVCR_BASE (sc->chip_type == 0 ? 0x0063 : 0x0058)
124 #define RTL8366_PVCR_PORT_SHIFT 4
125 #define RTL8366_PVCR_PORT_PERREG (16 / RTL8366_PVCR_PORT_SHIFT)
126 #define RTL8366_PVCR_PORT_MASK 0x000f
127 #define RTL8366_PVCR_REG(_port) \
128 (RTL8366_PVCR_BASE + _port / (RTL8366_PVCR_PORT_PERREG))
129 #define RTL8366_PVCR_VAL(_port, _pvlan) \
130 ((_pvlan & RTL8366_PVCR_PORT_MASK) << \
131 ((_port % RTL8366_PVCR_PORT_PERREG) * RTL8366_PVCR_PORT_SHIFT))
132 #define RTL8366_PVCR_GET(_port, _val) \
133 (((_val) >> ((_port % RTL8366_PVCR_PORT_PERREG) * RTL8366_PVCR_PORT_SHIFT)) & RTL8366_PVCR_PORT_MASK)
136 #define RTL8366_RCR 0x0100
137 #define RTL8366_RCR_HARD_RESET 0x0001
138 #define RTL8366_RCR_SOFT_RESET 0x0002
140 /* Chip Version Control: CHIP_VER[3:0] */
141 #define RTL8366_CVCR (sc->chip_type == 0 ? 0x050A : 0x0104)
142 /* Chip Identifier */
143 #define RTL8366RB_CIR 0x0509
144 #define RTL8366RB_CIR_ID8366RB 0x5937
145 #define RTL8366SR_CIR 0x0105
146 #define RTL8366SR_CIR_ID8366SR 0x8366
148 /* VLAN Ingress Control 2: [5:0] */
149 #define RTL8366_VIC2R 0x037f
152 #define RTL8366_MCNT_BASE 0x1000
153 #define RTL8366_MCTLR (sc->chip_type == 0 ? 0x13f0 : 0x11F0)
154 #define RTL8366_MCTLR_BUSY 0x0001
155 #define RTL8366_MCTLR_RESET 0x0002
156 #define RTL8366_MCTLR_RESET_PORT_MASK 0x00fc
157 #define RTL8366_MCTLR_RESET_ALL 0x0800
159 #define RTL8366_MCNT(_port, _r) \
160 (RTL8366_MCNT_BASE + 0x50 * (_port) + (_r))
161 #define RTL8366_MCTLR_RESET_PORT(_p) \
164 /* PHY Access Control */
165 #define RTL8366_PACR (sc->chip_type == 0 ? 0x8000 : 0x8028)
166 #define RTL8366_PACR_WRITE 0x0000
167 #define RTL8366_PACR_READ 0x0001
169 /* PHY Access Data */
170 #define RTL8366_PADR (sc->chip_type == 0 ? 0x8002 : 0x8029)
172 #define RTL8366_PHYREG(phy, page, reg) \
173 (0x8000 | (1 << (((phy) & 0x1f) + 9)) | (((page) & (sc->chip_type == 0 ? 0xf : 0x7)) << 5) | ((reg) & 0x1f))
175 /* general characteristics of the chip */
176 #define RTL8366_CPU_PORT 5
177 #define RTL8366_NUM_PORTS 6
178 #define RTL8366_NUM_PHYS (RTL8366_NUM_PORTS-1)
179 #define RTL8366_NUM_VLANS 16
180 #define RTL8366_NUM_PHY_REG 32