sys/dev/ex/if_ex.c

   1 /*-
   2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
   3  *
   4  * Copyright (c) 1996, Javier Martín Rueda (jmrueda@diatel.upm.es)
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice unmodified, this list of conditions, and the following
  12  *    disclaimer.
  13  * 2. Redistributions in binary form must reproduce the above copyright
  14  *    notice, this list of conditions and the following disclaimer in the
  15  *    documentation and/or other materials provided with the distribution.
  16  *
  17  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  18  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  19  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  20  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  21  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  22  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  23  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  24  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  25  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  26  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  27  * SUCH DAMAGE.
  28  *
  29  *
  30  * MAINTAINER: Matthew N. Dodd <winter@jurai.net>
  31  *                             <mdodd@FreeBSD.org>
  32  */
  33
  34 #include <sys/cdefs.h>
  35 __FBSDID("$FreeBSD$");
  36
  37 /*
  38  * Intel EtherExpress Pro/10, Pro/10+ Ethernet driver
  39  *
  40  * Revision history:
  41  *
  42  * dd-mmm-yyyy: Multicast support ported from NetBSD's if_iy driver.
  43  * 30-Oct-1996: first beta version. Inet and BPF supported, but no multicast.
  44  */
  45
  46 #include <sys/param.h>
  47 #include <sys/systm.h>
  48 #include <sys/kernel.h>
  49 #include <sys/sockio.h>
  50 #include <sys/mbuf.h>
  51 #include <sys/socket.h>
  52
  53 #include <sys/module.h>
  54 #include <sys/bus.h>
  55
  56 #include <machine/bus.h>
  57 #include <machine/resource.h>
  58 #include <sys/rman.h>
  59
  60 #include <net/if.h>
  61 #include <net/if_var.h>
  62 #include <net/if_arp.h>
  63 #include <net/if_dl.h>
  64 #include <net/if_media.h>
  65 #include <net/if_types.h>
  66 #include <net/ethernet.h>
  67 #include <net/bpf.h>
  68
  69 #include <netinet/in.h>
  70 #include <netinet/if_ether.h>
  71
  72
  73 #include <isa/isavar.h>
  74 #include <isa/pnpvar.h>
  75
  76 #include <dev/ex/if_exreg.h>
  77 #include <dev/ex/if_exvar.h>
  78
  79 #ifdef EXDEBUG
  80 # define Start_End 1
  81 # define Rcvd_Pkts 2
  82 # define Sent_Pkts 4
  83 # define Status    8
  84 static int debug_mask = 0;
  85 # define DODEBUG(level, action) if (level & debug_mask) action
  86 #else
  87 # define DODEBUG(level, action)
  88 #endif
  89
  90 devclass_t ex_devclass;
  91
  92 char irq2eemap[] =
  93         { -1, -1, 0, 1, -1, 2, -1, -1, -1, 0, 3, 4, -1, -1, -1, -1 };
  94 u_char ee2irqmap[] =
  95         { 9, 3, 5, 10, 11, 0, 0, 0 };
  96
  97 char plus_irq2eemap[] =
  98         { -1, -1, -1, 0, 1, 2, -1, 3, -1, 4, 5, 6, 7, -1, -1, -1 };
  99 u_char plus_ee2irqmap[] =
 100         { 3, 4, 5, 7, 9, 10, 11, 12 };
 101
 102 /* Network Interface Functions */
 103 static void     ex_init(void *);
 104 static void     ex_init_locked(struct ex_softc *);
 105 static void     ex_start(struct ifnet *);
 106 static void     ex_start_locked(struct ifnet *);
 107 static int      ex_ioctl(struct ifnet *, u_long, caddr_t);
 108 static void     ex_watchdog(void *);
 109
 110 /* ifmedia Functions    */
 111 static int      ex_ifmedia_upd(struct ifnet *);
 112 static void     ex_ifmedia_sts(struct ifnet *, struct ifmediareq *);
 113
 114 static int      ex_get_media(struct ex_softc *);
 115
 116 static void     ex_reset(struct ex_softc *);
 117 static void     ex_setmulti(struct ex_softc *);
 118
 119 static void     ex_tx_intr(struct ex_softc *);
 120 static void     ex_rx_intr(struct ex_softc *);
 121
 122 void
 123 ex_get_address(struct ex_softc *sc, u_char *enaddr)
 124 {
 125         uint16_t        eaddr_tmp;
 126
 127         eaddr_tmp = ex_eeprom_read(sc, EE_Eth_Addr_Lo);
 128         enaddr[5] = eaddr_tmp & 0xff;
 129         enaddr[4] = eaddr_tmp >> 8;
 130         eaddr_tmp = ex_eeprom_read(sc, EE_Eth_Addr_Mid);
 131         enaddr[3] = eaddr_tmp & 0xff;
 132         enaddr[2] = eaddr_tmp >> 8;
 133         eaddr_tmp = ex_eeprom_read(sc, EE_Eth_Addr_Hi);
 134         enaddr[1] = eaddr_tmp & 0xff;
 135         enaddr[0] = eaddr_tmp >> 8;
 136
 137         return;
 138 }
 139
 140 int
 141 ex_card_type(u_char *enaddr)
 142 {
 143         if ((enaddr[0] == 0x00) && (enaddr[1] == 0xA0) && (enaddr[2] == 0xC9))
 144                 return (CARD_TYPE_EX_10_PLUS);
 145
 146         return (CARD_TYPE_EX_10);
 147 }
 148
 149 /*
 150  * Caller is responsible for eventually calling
 151  * ex_release_resources() on failure.
 152  */
 153 int
 154 ex_alloc_resources(device_t dev)
 155 {
 156         struct ex_softc *       sc = device_get_softc(dev);
 157         int                     error = 0;
 158
 159         sc->ioport = bus_alloc_resource_any(dev, SYS_RES_IOPORT,
 160                                             &sc->ioport_rid, RF_ACTIVE);
 161         if (!sc->ioport) {
 162                 device_printf(dev, "No I/O space?!\n");
 163                 error = ENOMEM;
 164                 goto bad;
 165         }
 166
 167         sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irq_rid,
 168                                         RF_ACTIVE);
 169
 170         if (!sc->irq) {
 171                 device_printf(dev, "No IRQ?!\n");
 172                 error = ENOMEM;
 173                 goto bad;
 174         }
 175
 176 bad:
 177         return (error);
 178 }
 179
 180 void
 181 ex_release_resources(device_t dev)
 182 {
 183         struct ex_softc *       sc = device_get_softc(dev);
 184
 185         if (sc->ih) {
 186                 bus_teardown_intr(dev, sc->irq, sc->ih);
 187                 sc->ih = NULL;
 188         }
 189
 190         if (sc->ioport) {
 191                 bus_release_resource(dev, SYS_RES_IOPORT,
 192                                         sc->ioport_rid, sc->ioport);
 193                 sc->ioport = NULL;
 194         }
 195
 196         if (sc->irq) {
 197                 bus_release_resource(dev, SYS_RES_IRQ,
 198                                         sc->irq_rid, sc->irq);
 199                 sc->irq = NULL;
 200         }
 201
 202         if (sc->ifp)
 203                 if_free(sc->ifp);
 204
 205         return;
 206 }
 207
 208 int
 209 ex_attach(device_t dev)
 210 {
 211         struct ex_softc *       sc = device_get_softc(dev);
 212         struct ifnet *          ifp;
 213         struct ifmedia *        ifm;
 214         int                     error;
 215         uint16_t                temp;
 216
 217         ifp = sc->ifp = if_alloc(IFT_ETHER);
 218         if (ifp == NULL) {
 219                 device_printf(dev, "can not if_alloc()\n");
 220                 return (ENOSPC);
 221         }
 222         /* work out which set of irq <-> internal tables to use */
 223         if (ex_card_type(sc->enaddr) == CARD_TYPE_EX_10_PLUS) {
 224                 sc->irq2ee = plus_irq2eemap;
 225                 sc->ee2irq = plus_ee2irqmap;
 226         } else {
 227                 sc->irq2ee = irq2eemap;
 228                 sc->ee2irq = ee2irqmap;
 229         }
 230
 231         sc->mem_size = CARD_RAM_SIZE;   /* XXX This should be read from the card itself. */
 232
 233         /*
 234          * Initialize the ifnet structure.
 235          */
 236         ifp->if_softc = sc;
 237         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
 238         ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST;
 239         ifp->if_start = ex_start;
 240         ifp->if_ioctl = ex_ioctl;
 241         ifp->if_init = ex_init;
 242         IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen);
 243
 244         ifmedia_init(&sc->ifmedia, 0, ex_ifmedia_upd, ex_ifmedia_sts);
 245         mtx_init(&sc->lock, device_get_nameunit(dev), MTX_NETWORK_LOCK,
 246             MTX_DEF);
 247         callout_init_mtx(&sc->timer, &sc->lock, 0);
 248
 249         temp = ex_eeprom_read(sc, EE_W5);
 250         if (temp & EE_W5_PORT_TPE)
 251                 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL);
 252         if (temp & EE_W5_PORT_BNC)
 253                 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_2, 0, NULL);
 254         if (temp & EE_W5_PORT_AUI)
 255                 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_5, 0, NULL);
 256
 257         ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
 258         ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_NONE, 0, NULL);
 259         ifmedia_set(&sc->ifmedia, ex_get_media(sc));
 260
 261         ifm = &sc->ifmedia;
 262         ifm->ifm_media = ifm->ifm_cur->ifm_media;
 263         ex_ifmedia_upd(ifp);
 264
 265         /*
 266          * Attach the interface.
 267          */
 268         ether_ifattach(ifp, sc->enaddr);
 269
 270         error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET | INTR_MPSAFE,
 271                                 NULL, ex_intr, (void *)sc, &sc->ih);
 272         if (error) {
 273                 device_printf(dev, "bus_setup_intr() failed!\n");
 274                 ether_ifdetach(ifp);
 275                 mtx_destroy(&sc->lock);
 276                 return (error);
 277         }
 278
 279         gone_by_fcp101_dev(dev);
 280
 281         return(0);
 282 }
 283
 284 int
 285 ex_detach(device_t dev)
 286 {
 287         struct ex_softc *sc;
 288         struct ifnet    *ifp;
 289
 290         sc = device_get_softc(dev);
 291         ifp = sc->ifp;
 292
 293         EX_LOCK(sc);
 294         ex_stop(sc);
 295         EX_UNLOCK(sc);
 296
 297         ether_ifdetach(ifp);
 298         callout_drain(&sc->timer);
 299
 300         ex_release_resources(dev);
 301         mtx_destroy(&sc->lock);
 302
 303         return (0);
 304 }
 305
 306 static void
 307 ex_init(void *xsc)
 308 {
 309         struct ex_softc *       sc = (struct ex_softc *) xsc;
 310
 311         EX_LOCK(sc);
 312         ex_init_locked(sc);
 313         EX_UNLOCK(sc);
 314 }
 315
 316 static void
 317 ex_init_locked(struct ex_softc *sc)
 318 {
 319         struct ifnet *          ifp = sc->ifp;
 320         int                     i;
 321         unsigned short          temp_reg;
 322
 323         DODEBUG(Start_End, printf("%s: ex_init: start\n", ifp->if_xname););
 324
 325         sc->tx_timeout = 0;
 326
 327         /*
 328          * Load the ethernet address into the card.
 329          */
 330         CSR_WRITE_1(sc, CMD_REG, Bank2_Sel);
 331         temp_reg = CSR_READ_1(sc, EEPROM_REG);
 332         if (temp_reg & Trnoff_Enable)
 333                 CSR_WRITE_1(sc, EEPROM_REG, temp_reg & ~Trnoff_Enable);
 334         for (i = 0; i < ETHER_ADDR_LEN; i++)
 335                 CSR_WRITE_1(sc, I_ADDR_REG0 + i, IF_LLADDR(sc->ifp)[i]);
 336
 337         /*
 338          * - Setup transmit chaining and discard bad received frames.
 339          * - Match broadcast.
 340          * - Clear test mode.
 341          * - Set receiving mode.
 342          */
 343         CSR_WRITE_1(sc, REG1, CSR_READ_1(sc, REG1) | Tx_Chn_Int_Md | Tx_Chn_ErStp | Disc_Bad_Fr);
 344         CSR_WRITE_1(sc, REG2, CSR_READ_1(sc, REG2) | No_SA_Ins | RX_CRC_InMem);
 345         CSR_WRITE_1(sc, REG3, CSR_READ_1(sc, REG3) & 0x3f /* XXX constants. */ );
 346         /*
 347          * - Set IRQ number, if this part has it.  ISA devices have this,
 348          * while PC Card devices don't seem to.  Either way, we have to
 349          * switch to Bank1 as the rest of this code relies on that.
 350          */
 351         CSR_WRITE_1(sc, CMD_REG, Bank1_Sel);
 352         if (sc->flags & HAS_INT_NO_REG)
 353                 CSR_WRITE_1(sc, INT_NO_REG,
 354                     (CSR_READ_1(sc, INT_NO_REG) & 0xf8) |
 355                     sc->irq2ee[sc->irq_no]);
 356
 357         /*
 358          * Divide the available memory in the card into rcv and xmt buffers.
 359          * By default, I use the first 3/4 of the memory for the rcv buffer,
 360          * and the remaining 1/4 of the memory for the xmt buffer.
 361          */
 362         sc->rx_mem_size = sc->mem_size * 3 / 4;
 363         sc->tx_mem_size = sc->mem_size - sc->rx_mem_size;
 364         sc->rx_lower_limit = 0x0000;
 365         sc->rx_upper_limit = sc->rx_mem_size - 2;
 366         sc->tx_lower_limit = sc->rx_mem_size;
 367         sc->tx_upper_limit = sc->mem_size - 2;
 368         CSR_WRITE_1(sc, RCV_LOWER_LIMIT_REG, sc->rx_lower_limit >> 8);
 369         CSR_WRITE_1(sc, RCV_UPPER_LIMIT_REG, sc->rx_upper_limit >> 8);
 370         CSR_WRITE_1(sc, XMT_LOWER_LIMIT_REG, sc->tx_lower_limit >> 8);
 371         CSR_WRITE_1(sc, XMT_UPPER_LIMIT_REG, sc->tx_upper_limit >> 8);
 372
 373         /*
 374          * Enable receive and transmit interrupts, and clear any pending int.
 375          */
 376         CSR_WRITE_1(sc, REG1, CSR_READ_1(sc, REG1) | TriST_INT);
 377         CSR_WRITE_1(sc, CMD_REG, Bank0_Sel);
 378         CSR_WRITE_1(sc, MASK_REG, All_Int & ~(Rx_Int | Tx_Int));
 379         CSR_WRITE_1(sc, STATUS_REG, All_Int);
 380
 381         /*
 382          * Initialize receive and transmit ring buffers.
 383          */
 384         CSR_WRITE_2(sc, RCV_BAR, sc->rx_lower_limit);
 385         sc->rx_head = sc->rx_lower_limit;
 386         CSR_WRITE_2(sc, RCV_STOP_REG, sc->rx_upper_limit | 0xfe);
 387         CSR_WRITE_2(sc, XMT_BAR, sc->tx_lower_limit);
 388         sc->tx_head = sc->tx_tail = sc->tx_lower_limit;
 389
 390         ifp->if_drv_flags |= IFF_DRV_RUNNING;
 391         ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
 392         DODEBUG(Status, printf("OIDLE init\n"););
 393         callout_reset(&sc->timer, hz, ex_watchdog, sc);
 394
 395         ex_setmulti(sc);
 396
 397         /*
 398          * Final reset of the board, and enable operation.
 399          */
 400         CSR_WRITE_1(sc, CMD_REG, Sel_Reset_CMD);
 401         DELAY(2);
 402         CSR_WRITE_1(sc, CMD_REG, Rcv_Enable_CMD);
 403
 404         ex_start_locked(ifp);
 405
 406         DODEBUG(Start_End, printf("%s: ex_init: finish\n", ifp->if_xname););
 407 }
 408
 409 static void
 410 ex_start(struct ifnet *ifp)
 411 {
 412         struct ex_softc *       sc = ifp->if_softc;
 413
 414         EX_LOCK(sc);
 415         ex_start_locked(ifp);
 416         EX_UNLOCK(sc);
 417 }
 418
 419 static void
 420 ex_start_locked(struct ifnet *ifp)
 421 {
 422         struct ex_softc *       sc = ifp->if_softc;
 423         int                     i, len, data_len, avail, dest, next;
 424         unsigned char           tmp16[2];
 425         struct mbuf *           opkt;
 426         struct mbuf *           m;
 427
 428         DODEBUG(Start_End, printf("ex_start%d: start\n", unit););
 429
 430         /*
 431          * Main loop: send outgoing packets to network card until there are no
 432          * more packets left, or the card cannot accept any more yet.
 433          */
 434         while (((opkt = ifp->if_snd.ifq_head) != NULL) &&
 435                !(ifp->if_drv_flags & IFF_DRV_OACTIVE)) {
 436
 437                 /*
 438                  * Ensure there is enough free transmit buffer space for
 439                  * this packet, including its header. Note: the header
 440                  * cannot wrap around the end of the transmit buffer and
 441                  * must be kept together, so we allow space for twice the
 442                  * length of the header, just in case.
 443                  */
 444
 445                 for (len = 0, m = opkt; m != NULL; m = m->m_next) {
 446                         len += m->m_len;
 447                 }
 448
 449                 data_len = len;
 450
 451                 DODEBUG(Sent_Pkts, printf("1. Sending packet with %d data bytes. ", data_len););
 452
 453                 if (len & 1) {
 454                         len += XMT_HEADER_LEN + 1;
 455                 } else {
 456                         len += XMT_HEADER_LEN;
 457                 }
 458
 459                 if ((i = sc->tx_tail - sc->tx_head) >= 0) {
 460                         avail = sc->tx_mem_size - i;
 461                 } else {
 462                         avail = -i;
 463                 }
 464
 465                 DODEBUG(Sent_Pkts, printf("i=%d, avail=%d\n", i, avail););
 466
 467                 if (avail >= len + XMT_HEADER_LEN) {
 468                         IF_DEQUEUE(&ifp->if_snd, opkt);
 469
 470 #ifdef EX_PSA_INTR
 471                         /*
 472                          * Disable rx and tx interrupts, to avoid corruption
 473                          * of the host address register by interrupt service
 474                          * routines.
 475                          * XXX Is this necessary with splimp() enabled?
 476                          */
 477                         CSR_WRITE_1(sc, MASK_REG, All_Int);
 478 #endif
 479
 480                         /*
 481                          * Compute the start and end addresses of this
 482                          * frame in the tx buffer.
 483                          */
 484                         dest = sc->tx_tail;
 485                         next = dest + len;
 486
 487                         if (next > sc->tx_upper_limit) {
 488                                 if ((sc->tx_upper_limit + 2 - sc->tx_tail) <=
 489                                     XMT_HEADER_LEN) {
 490                                         dest = sc->tx_lower_limit;
 491                                         next = dest + len;
 492                                 } else {
 493                                         next = sc->tx_lower_limit +
 494                                                 next - sc->tx_upper_limit - 2;
 495                                 }
 496                         }
 497
 498                         /*
 499                          * Build the packet frame in the card's ring buffer.
 500                          */
 501                         DODEBUG(Sent_Pkts, printf("2. dest=%d, next=%d. ", dest, next););
 502
 503                         CSR_WRITE_2(sc, HOST_ADDR_REG, dest);
 504                         CSR_WRITE_2(sc, IO_PORT_REG, Transmit_CMD);
 505                         CSR_WRITE_2(sc, IO_PORT_REG, 0);
 506                         CSR_WRITE_2(sc, IO_PORT_REG, next);
 507                         CSR_WRITE_2(sc, IO_PORT_REG, data_len);
 508
 509                         /*
 510                          * Output the packet data to the card. Ensure all
 511                          * transfers are 16-bit wide, even if individual
 512                          * mbufs have odd length.
 513                          */
 514                         for (m = opkt, i = 0; m != NULL; m = m->m_next) {
 515                                 DODEBUG(Sent_Pkts, printf("[%d]", m->m_len););
 516                                 if (i) {
 517                                         tmp16[1] = *(mtod(m, caddr_t));
 518                                         CSR_WRITE_MULTI_2(sc, IO_PORT_REG,
 519                                             (uint16_t *) tmp16, 1);
 520                                 }
 521                                 CSR_WRITE_MULTI_2(sc, IO_PORT_REG,
 522                                     (uint16_t *) (mtod(m, caddr_t) + i),
 523                                     (m->m_len - i) / 2);
 524                                 if ((i = (m->m_len - i) & 1) != 0) {
 525                                         tmp16[0] = *(mtod(m, caddr_t) +
 526                                                    m->m_len - 1);
 527                                 }
 528                         }
 529                         if (i)
 530                                 CSR_WRITE_MULTI_2(sc, IO_PORT_REG,
 531                                     (uint16_t *) tmp16, 1);
 532                         /*
 533                          * If there were other frames chained, update the
 534                          * chain in the last one.
 535                          */
 536                         if (sc->tx_head != sc->tx_tail) {
 537                                 if (sc->tx_tail != dest) {
 538                                         CSR_WRITE_2(sc, HOST_ADDR_REG,
 539                                              sc->tx_last + XMT_Chain_Point);
 540                                         CSR_WRITE_2(sc, IO_PORT_REG, dest);
 541                                 }
 542                                 CSR_WRITE_2(sc, HOST_ADDR_REG,
 543                                      sc->tx_last + XMT_Byte_Count);
 544                                 i = CSR_READ_2(sc, IO_PORT_REG);
 545                                 CSR_WRITE_2(sc, HOST_ADDR_REG,
 546                                      sc->tx_last + XMT_Byte_Count);
 547                                 CSR_WRITE_2(sc, IO_PORT_REG, i | Ch_bit);
 548                         }
 549
 550                         /*
 551                          * Resume normal operation of the card:
 552                          * - Make a dummy read to flush the DRAM write
 553                          *   pipeline.
 554                          * - Enable receive and transmit interrupts.
 555                          * - Send Transmit or Resume_XMT command, as
 556                          *   appropriate.
 557                          */
 558                         CSR_READ_2(sc, IO_PORT_REG);
 559 #ifdef EX_PSA_INTR
 560                         CSR_WRITE_1(sc, MASK_REG, All_Int & ~(Rx_Int | Tx_Int));
 561 #endif
 562                         if (sc->tx_head == sc->tx_tail) {
 563                                 CSR_WRITE_2(sc, XMT_BAR, dest);
 564                                 CSR_WRITE_1(sc, CMD_REG, Transmit_CMD);
 565                                 sc->tx_head = dest;
 566                                 DODEBUG(Sent_Pkts, printf("Transmit\n"););
 567                         } else {
 568                                 CSR_WRITE_1(sc, CMD_REG, Resume_XMT_List_CMD);
 569                                 DODEBUG(Sent_Pkts, printf("Resume\n"););
 570                         }
 571
 572                         sc->tx_last = dest;
 573                         sc->tx_tail = next;
 574
 575                         BPF_MTAP(ifp, opkt);
 576
 577                         sc->tx_timeout = 2;
 578                         if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
 579                         m_freem(opkt);
 580                 } else {
 581                         ifp->if_drv_flags |= IFF_DRV_OACTIVE;
 582                         DODEBUG(Status, printf("OACTIVE start\n"););
 583                 }
 584         }
 585
 586         DODEBUG(Start_End, printf("ex_start%d: finish\n", unit););
 587 }
 588
 589 void
 590 ex_stop(struct ex_softc *sc)
 591 {
 592
 593         DODEBUG(Start_End, printf("ex_stop%d: start\n", unit););
 594
 595         EX_ASSERT_LOCKED(sc);
 596         /*
 597          * Disable card operation:
 598          * - Disable the interrupt line.
 599          * - Flush transmission and disable reception.
 600          * - Mask and clear all interrupts.
 601          * - Reset the 82595.
 602          */
 603         CSR_WRITE_1(sc, CMD_REG, Bank1_Sel);
 604         CSR_WRITE_1(sc, REG1, CSR_READ_1(sc, REG1) & ~TriST_INT);
 605         CSR_WRITE_1(sc, CMD_REG, Bank0_Sel);
 606         CSR_WRITE_1(sc, CMD_REG, Rcv_Stop);
 607         sc->tx_head = sc->tx_tail = sc->tx_lower_limit;
 608         sc->tx_last = 0; /* XXX I think these two lines are not necessary, because ex_init will always be called again to reinit the interface. */
 609         CSR_WRITE_1(sc, MASK_REG, All_Int);
 610         CSR_WRITE_1(sc, STATUS_REG, All_Int);
 611         CSR_WRITE_1(sc, CMD_REG, Reset_CMD);
 612         DELAY(200);
 613         sc->ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
 614         sc->tx_timeout = 0;
 615         callout_stop(&sc->timer);
 616
 617         DODEBUG(Start_End, printf("ex_stop%d: finish\n", unit););
 618
 619         return;
 620 }
 621
 622 void
 623 ex_intr(void *arg)
 624 {
 625         struct ex_softc *sc = (struct ex_softc *)arg;
 626         struct ifnet    *ifp = sc->ifp;
 627         int             int_status, send_pkts;
 628         int             loops = 100;
 629
 630         DODEBUG(Start_End, printf("ex_intr%d: start\n", unit););
 631
 632         EX_LOCK(sc);
 633         send_pkts = 0;
 634         while (loops-- > 0 &&
 635             (int_status = CSR_READ_1(sc, STATUS_REG)) & (Tx_Int | Rx_Int)) {
 636                 /* don't loop forever */
 637                 if (int_status == 0xff)
 638                         break;
 639                 if (int_status & Rx_Int) {
 640                         CSR_WRITE_1(sc, STATUS_REG, Rx_Int);
 641                         ex_rx_intr(sc);
 642                 } else if (int_status & Tx_Int) {
 643                         CSR_WRITE_1(sc, STATUS_REG, Tx_Int);
 644                         ex_tx_intr(sc);
 645                         send_pkts = 1;
 646                 }
 647         }
 648         if (loops == 0)
 649                 printf("100 loops are not enough\n");
 650
 651         /*
 652          * If any packet has been transmitted, and there are queued packets to
 653          * be sent, attempt to send more packets to the network card.
 654          */
 655         if (send_pkts && (ifp->if_snd.ifq_head != NULL))
 656                 ex_start_locked(ifp);
 657         EX_UNLOCK(sc);
 658
 659         DODEBUG(Start_End, printf("ex_intr%d: finish\n", unit););
 660
 661         return;
 662 }
 663
 664 static void
 665 ex_tx_intr(struct ex_softc *sc)
 666 {
 667         struct ifnet *  ifp = sc->ifp;
 668         int             tx_status;
 669
 670         DODEBUG(Start_End, printf("ex_tx_intr%d: start\n", unit););
 671
 672         /*
 673          * - Cancel the watchdog.
 674          * For all packets transmitted since last transmit interrupt:
 675          * - Advance chain pointer to next queued packet.
 676          * - Update statistics.
 677          */
 678
 679         sc->tx_timeout = 0;
 680
 681         while (sc->tx_head != sc->tx_tail) {
 682                 CSR_WRITE_2(sc, HOST_ADDR_REG, sc->tx_head);
 683
 684                 if (!(CSR_READ_2(sc, IO_PORT_REG) & Done_bit))
 685                         break;
 686
 687                 tx_status = CSR_READ_2(sc, IO_PORT_REG);
 688                 sc->tx_head = CSR_READ_2(sc, IO_PORT_REG);
 689
 690                 if (tx_status & TX_OK_bit) {
 691                         if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
 692                 } else {
 693                         if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
 694                 }
 695
 696                 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, tx_status & No_Collisions_bits);
 697         }
 698
 699         /*
 700          * The card should be ready to accept more packets now.
 701          */
 702
 703         ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
 704
 705         DODEBUG(Status, printf("OIDLE tx_intr\n"););
 706         DODEBUG(Start_End, printf("ex_tx_intr%d: finish\n", unit););
 707
 708         return;
 709 }
 710
 711 static void
 712 ex_rx_intr(struct ex_softc *sc)
 713 {
 714         struct ifnet *          ifp = sc->ifp;
 715         int                     rx_status;
 716         int                     pkt_len;
 717         int                     QQQ;
 718         struct mbuf *           m;
 719         struct mbuf *           ipkt;
 720         struct ether_header *   eh;
 721
 722         DODEBUG(Start_End, printf("ex_rx_intr%d: start\n", unit););
 723
 724         /*
 725          * For all packets received since last receive interrupt:
 726          * - If packet ok, read it into a new mbuf and queue it to interface,
 727          *   updating statistics.
 728          * - If packet bad, just discard it, and update statistics.
 729          * Finally, advance receive stop limit in card's memory to new location.
 730          */
 731
 732         CSR_WRITE_2(sc, HOST_ADDR_REG, sc->rx_head);
 733
 734         while (CSR_READ_2(sc, IO_PORT_REG) == RCV_Done) {
 735
 736                 rx_status = CSR_READ_2(sc, IO_PORT_REG);
 737                 sc->rx_head = CSR_READ_2(sc, IO_PORT_REG);
 738                 QQQ = pkt_len = CSR_READ_2(sc, IO_PORT_REG);
 739
 740                 if (rx_status & RCV_OK_bit) {
 741                         MGETHDR(m, M_NOWAIT, MT_DATA);
 742                         ipkt = m;
 743                         if (ipkt == NULL) {
 744                                 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
 745                         } else {
 746                                 ipkt->m_pkthdr.rcvif = ifp;
 747                                 ipkt->m_pkthdr.len = pkt_len;
 748                                 ipkt->m_len = MHLEN;
 749
 750                                 while (pkt_len > 0) {
 751                                         if (pkt_len >= MINCLSIZE) {
 752                                                 if (MCLGET(m, M_NOWAIT)) {
 753                                                         m->m_len = MCLBYTES;
 754                                                 } else {
 755                                                         m_freem(ipkt);
 756                                                         if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
 757                                                         goto rx_another;
 758                                                 }
 759                                         }
 760                                         m->m_len = min(m->m_len, pkt_len);
 761
 762           /*
 763            * NOTE: I'm assuming that all mbufs allocated are of even length,
 764            * except for the last one in an odd-length packet.
 765            */
 766
 767                                         CSR_READ_MULTI_2(sc, IO_PORT_REG,
 768                                             mtod(m, uint16_t *), m->m_len / 2);
 769
 770                                         if (m->m_len & 1) {
 771                                                 *(mtod(m, caddr_t) + m->m_len - 1) = CSR_READ_1(sc, IO_PORT_REG);
 772                                         }
 773                                         pkt_len -= m->m_len;
 774
 775                                         if (pkt_len > 0) {
 776                                                 MGET(m->m_next, M_NOWAIT, MT_DATA);
 777                                                 if (m->m_next == NULL) {
 778                                                         m_freem(ipkt);
 779                                                         if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
 780                                                         goto rx_another;
 781                                                 }
 782                                                 m = m->m_next;
 783                                                 m->m_len = MLEN;
 784                                         }
 785                                 }
 786                                 eh = mtod(ipkt, struct ether_header *);
 787 #ifdef EXDEBUG
 788         if (debug_mask & Rcvd_Pkts) {
 789                 if ((eh->ether_dhost[5] != 0xff) || (eh->ether_dhost[0] != 0xff)) {
 790                         printf("Receive packet with %d data bytes: %6D -> ", QQQ, eh->ether_shost, ":");
 791                         printf("%6D\n", eh->ether_dhost, ":");
 792                 } /* QQQ */
 793         }
 794 #endif
 795                                 EX_UNLOCK(sc);
 796                                 (*ifp->if_input)(ifp, ipkt);
 797                                 EX_LOCK(sc);
 798                                 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
 799                         }
 800                 } else {
 801                         if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
 802                 }
 803                 CSR_WRITE_2(sc, HOST_ADDR_REG, sc->rx_head);
 804 rx_another: ;
 805         }
 806
 807         if (sc->rx_head < sc->rx_lower_limit + 2)
 808                 CSR_WRITE_2(sc, RCV_STOP_REG, sc->rx_upper_limit);
 809         else
 810                 CSR_WRITE_2(sc, RCV_STOP_REG, sc->rx_head - 2);
 811
 812         DODEBUG(Start_End, printf("ex_rx_intr%d: finish\n", unit););
 813
 814         return;
 815 }
 816
 817
 818 static int
 819 ex_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
 820 {
 821         struct ex_softc *       sc = ifp->if_softc;
 822         struct ifreq *          ifr = (struct ifreq *)data;
 823         int                     error = 0;
 824
 825         DODEBUG(Start_End, printf("%s: ex_ioctl: start ", ifp->if_xname););
 826
 827         switch(cmd) {
 828                 case SIOCSIFFLAGS:
 829                         DODEBUG(Start_End, printf("SIOCSIFFLAGS"););
 830                         EX_LOCK(sc);
 831                         if ((ifp->if_flags & IFF_UP) == 0 &&
 832                             (ifp->if_drv_flags & IFF_DRV_RUNNING)) {
 833                                 ex_stop(sc);
 834                         } else {
 835                                 ex_init_locked(sc);
 836                         }
 837                         EX_UNLOCK(sc);
 838                         break;
 839                 case SIOCADDMULTI:
 840                 case SIOCDELMULTI:
 841                         ex_init(sc);
 842                         error = 0;
 843                         break;
 844                 case SIOCSIFMEDIA:
 845                 case SIOCGIFMEDIA:
 846                         error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, cmd);
 847                         break;
 848                 default:
 849                         error = ether_ioctl(ifp, cmd, data);
 850                         break;
 851         }
 852
 853         DODEBUG(Start_End, printf("\n%s: ex_ioctl: finish\n", ifp->if_xname););
 854
 855         return(error);
 856 }
 857
 858 static void
 859 ex_setmulti(struct ex_softc *sc)
 860 {
 861         struct ifnet *ifp;
 862         struct ifmultiaddr *maddr;
 863         uint16_t *addr;
 864         int count;
 865         int timeout, status;
 866
 867         ifp = sc->ifp;
 868
 869         count = 0;
 870         if_maddr_rlock(ifp);
 871         CK_STAILQ_FOREACH(maddr, &ifp->if_multiaddrs, ifma_link) {
 872                 if (maddr->ifma_addr->sa_family != AF_LINK)
 873                         continue;
 874                 count++;
 875         }
 876         if_maddr_runlock(ifp);
 877
 878         if ((ifp->if_flags & IFF_PROMISC) || (ifp->if_flags & IFF_ALLMULTI)
 879                         || count > 63) {
 880                 /* Interface is in promiscuous mode or there are too many
 881                  * multicast addresses for the card to handle */
 882                 CSR_WRITE_1(sc, CMD_REG, Bank2_Sel);
 883                 CSR_WRITE_1(sc, REG2, CSR_READ_1(sc, REG2) | Promisc_Mode);
 884                 CSR_WRITE_1(sc, REG3, CSR_READ_1(sc, REG3));
 885                 CSR_WRITE_1(sc, CMD_REG, Bank0_Sel);
 886         }
 887         else if ((ifp->if_flags & IFF_MULTICAST) && (count > 0)) {
 888                 /* Program multicast addresses plus our MAC address
 889                  * into the filter */
 890                 CSR_WRITE_1(sc, CMD_REG, Bank2_Sel);
 891                 CSR_WRITE_1(sc, REG2, CSR_READ_1(sc, REG2) | Multi_IA);
 892                 CSR_WRITE_1(sc, REG3, CSR_READ_1(sc, REG3));
 893                 CSR_WRITE_1(sc, CMD_REG, Bank0_Sel);
 894
 895                 /* Borrow space from TX buffer; this should be safe
 896                  * as this is only called from ex_init */
 897
 898                 CSR_WRITE_2(sc, HOST_ADDR_REG, sc->tx_lower_limit);
 899                 CSR_WRITE_2(sc, IO_PORT_REG, MC_Setup_CMD);
 900                 CSR_WRITE_2(sc, IO_PORT_REG, 0);
 901                 CSR_WRITE_2(sc, IO_PORT_REG, 0);
 902                 CSR_WRITE_2(sc, IO_PORT_REG, (count + 1) * 6);
 903
 904                 if_maddr_rlock(ifp);
 905                 CK_STAILQ_FOREACH(maddr, &ifp->if_multiaddrs, ifma_link) {
 906                         if (maddr->ifma_addr->sa_family != AF_LINK)
 907                                 continue;
 908
 909                         addr = (uint16_t*)LLADDR((struct sockaddr_dl *)
 910                                         maddr->ifma_addr);
 911                         CSR_WRITE_2(sc, IO_PORT_REG, *addr++);
 912                         CSR_WRITE_2(sc, IO_PORT_REG, *addr++);
 913                         CSR_WRITE_2(sc, IO_PORT_REG, *addr++);
 914                 }
 915                 if_maddr_runlock(ifp);
 916
 917                 /* Program our MAC address as well */
 918                 /* XXX: Is this necessary?  The Linux driver does this
 919                  * but the NetBSD driver does not */
 920                 addr = (uint16_t*)IF_LLADDR(sc->ifp);
 921                 CSR_WRITE_2(sc, IO_PORT_REG, *addr++);
 922                 CSR_WRITE_2(sc, IO_PORT_REG, *addr++);
 923                 CSR_WRITE_2(sc, IO_PORT_REG, *addr++);
 924
 925                 CSR_READ_2(sc, IO_PORT_REG);
 926                 CSR_WRITE_2(sc, XMT_BAR, sc->tx_lower_limit);
 927                 CSR_WRITE_1(sc, CMD_REG, MC_Setup_CMD);
 928
 929                 sc->tx_head = sc->tx_lower_limit;
 930                 sc->tx_tail = sc->tx_head + XMT_HEADER_LEN + (count + 1) * 6;
 931
 932                 for (timeout=0; timeout<100; timeout++) {
 933                         DELAY(2);
 934                         if ((CSR_READ_1(sc, STATUS_REG) & Exec_Int) == 0)
 935                                 continue;
 936
 937                         status = CSR_READ_1(sc, CMD_REG);
 938                         CSR_WRITE_1(sc, STATUS_REG, Exec_Int);
 939                         break;
 940                 }
 941
 942                 sc->tx_head = sc->tx_tail;
 943         }
 944         else
 945         {
 946                 /* No multicast or promiscuous mode */
 947                 CSR_WRITE_1(sc, CMD_REG, Bank2_Sel);
 948                 CSR_WRITE_1(sc, REG2, CSR_READ_1(sc, REG2) & 0xDE);
 949                         /* ~(Multi_IA | Promisc_Mode) */
 950                 CSR_WRITE_1(sc, REG3, CSR_READ_1(sc, REG3));
 951                 CSR_WRITE_1(sc, CMD_REG, Bank0_Sel);
 952         }
 953 }
 954
 955 static void
 956 ex_reset(struct ex_softc *sc)
 957 {
 958
 959         DODEBUG(Start_End, printf("ex_reset%d: start\n", unit););
 960
 961         EX_ASSERT_LOCKED(sc);
 962         ex_stop(sc);
 963         ex_init_locked(sc);
 964
 965         DODEBUG(Start_End, printf("ex_reset%d: finish\n", unit););
 966
 967         return;
 968 }
 969
 970 static void
 971 ex_watchdog(void *arg)
 972 {
 973         struct ex_softc *       sc = arg;
 974         struct ifnet *ifp = sc->ifp;
 975
 976         if (sc->tx_timeout && --sc->tx_timeout == 0) {
 977                 DODEBUG(Start_End, if_printf(ifp, "ex_watchdog: start\n"););
 978
 979                 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
 980
 981                 DODEBUG(Status, printf("OIDLE watchdog\n"););
 982
 983                 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
 984                 ex_reset(sc);
 985                 ex_start_locked(ifp);
 986
 987                 DODEBUG(Start_End, if_printf(ifp, "ex_watchdog: finish\n"););
 988         }
 989
 990         callout_reset(&sc->timer, hz, ex_watchdog, sc);
 991 }
 992
 993 static int
 994 ex_get_media(struct ex_softc *sc)
 995 {
 996         int     current;
 997         int     media;
 998
 999         media = ex_eeprom_read(sc, EE_W5);
1000
1001         CSR_WRITE_1(sc, CMD_REG, Bank2_Sel);
1002         current = CSR_READ_1(sc, REG3);
1003         CSR_WRITE_1(sc, CMD_REG, Bank0_Sel);
1004
1005         if ((current & TPE_bit) && (media & EE_W5_PORT_TPE))
1006                 return(IFM_ETHER|IFM_10_T);
1007         if ((current & BNC_bit) && (media & EE_W5_PORT_BNC))
1008                 return(IFM_ETHER|IFM_10_2);
1009
1010         if (media & EE_W5_PORT_AUI)
1011                 return (IFM_ETHER|IFM_10_5);
1012
1013         return (IFM_ETHER|IFM_AUTO);
1014 }
1015
1016 static int
1017 ex_ifmedia_upd(ifp)
1018         struct ifnet *          ifp;
1019 {
1020         struct ex_softc *       sc = ifp->if_softc;
1021
1022         if (IFM_TYPE(sc->ifmedia.ifm_media) != IFM_ETHER)
1023                 return EINVAL;
1024
1025         return (0);
1026 }
1027
1028 static void
1029 ex_ifmedia_sts(ifp, ifmr)
1030         struct ifnet *          ifp;
1031         struct ifmediareq *     ifmr;
1032 {
1033         struct ex_softc *       sc = ifp->if_softc;
1034
1035         EX_LOCK(sc);
1036         ifmr->ifm_active = ex_get_media(sc);
1037         ifmr->ifm_status = IFM_AVALID | IFM_ACTIVE;
1038         EX_UNLOCK(sc);
1039
1040         return;
1041 }
1042
1043 u_short
1044 ex_eeprom_read(struct ex_softc *sc, int location)
1045 {
1046         int i;
1047         u_short data = 0;
1048         int read_cmd = location | EE_READ_CMD;
1049         short ctrl_val = EECS;
1050
1051         CSR_WRITE_1(sc, CMD_REG, Bank2_Sel);
1052         CSR_WRITE_1(sc, EEPROM_REG, EECS);
1053         for (i = 8; i >= 0; i--) {
1054                 short outval = (read_cmd & (1 << i)) ? ctrl_val | EEDI : ctrl_val;
1055                 CSR_WRITE_1(sc, EEPROM_REG, outval);
1056                 CSR_WRITE_1(sc, EEPROM_REG, outval | EESK);
1057                 DELAY(3);
1058                 CSR_WRITE_1(sc, EEPROM_REG, outval);
1059                 DELAY(2);
1060         }
1061         CSR_WRITE_1(sc, EEPROM_REG, ctrl_val);
1062
1063         for (i = 16; i > 0; i--) {
1064                 CSR_WRITE_1(sc, EEPROM_REG, ctrl_val | EESK);
1065                 DELAY(3);
1066                 data = (data << 1) |
1067                     ((CSR_READ_1(sc, EEPROM_REG) & EEDO) ? 1 : 0);
1068                 CSR_WRITE_1(sc, EEPROM_REG, ctrl_val);
1069                 DELAY(2);
1070         }
1071
1072         ctrl_val &= ~EECS;
1073         CSR_WRITE_1(sc, EEPROM_REG, ctrl_val | EESK);
1074         DELAY(3);
1075         CSR_WRITE_1(sc, EEPROM_REG, ctrl_val);
1076         DELAY(2);
1077         CSR_WRITE_1(sc, CMD_REG, Bank0_Sel);
1078         return(data);
1079 }