sys/dev/ex/if_ex.c

   1 /*-
   2  * Copyright (c) 1996, Javier Martín Rueda (jmrueda@diatel.upm.es)
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice unmodified, this list of conditions, and the following
  10  *    disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  *
  15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  18  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  25  * SUCH DAMAGE.
  26  *
  27  *
  28  * MAINTAINER: Matthew N. Dodd <winter@jurai.net>
  29  *                             <mdodd@FreeBSD.org>
  30  */
  31
  32 #include <sys/cdefs.h>
  33 __FBSDID("$FreeBSD$");
  34
  35 /*
  36  * Intel EtherExpress Pro/10, Pro/10+ Ethernet driver
  37  *
  38  * Revision history:
  39  *
  40  * dd-mmm-yyyy: Multicast support ported from NetBSD's if_iy driver.
  41  * 30-Oct-1996: first beta version. Inet and BPF supported, but no multicast.
  42  */
  43
  44 #include <sys/param.h>
  45 #include <sys/systm.h>
  46 #include <sys/kernel.h>
  47 #include <sys/sockio.h>
  48 #include <sys/mbuf.h>
  49 #include <sys/socket.h>
  50
  51 #include <sys/module.h>
  52 #include <sys/bus.h>
  53
  54 #include <machine/bus.h>
  55 #include <machine/resource.h>
  56 #include <sys/rman.h>
  57
  58 #include <net/if.h>
  59 #include <net/if_var.h>
  60 #include <net/if_arp.h>
  61 #include <net/if_dl.h>
  62 #include <net/if_media.h>
  63 #include <net/if_types.h>
  64 #include <net/ethernet.h>
  65 #include <net/bpf.h>
  66
  67 #include <netinet/in.h>
  68 #include <netinet/if_ether.h>
  69
  70
  71 #include <isa/isavar.h>
  72 #include <isa/pnpvar.h>
  73
  74 #include <dev/ex/if_exreg.h>
  75 #include <dev/ex/if_exvar.h>
  76
  77 #ifdef EXDEBUG
  78 # define Start_End 1
  79 # define Rcvd_Pkts 2
  80 # define Sent_Pkts 4
  81 # define Status    8
  82 static int debug_mask = 0;
  83 # define DODEBUG(level, action) if (level & debug_mask) action
  84 #else
  85 # define DODEBUG(level, action)
  86 #endif
  87
  88 devclass_t ex_devclass;
  89
  90 char irq2eemap[] =
  91         { -1, -1, 0, 1, -1, 2, -1, -1, -1, 0, 3, 4, -1, -1, -1, -1 };
  92 u_char ee2irqmap[] =
  93         { 9, 3, 5, 10, 11, 0, 0, 0 };
  94
  95 char plus_irq2eemap[] =
  96         { -1, -1, -1, 0, 1, 2, -1, 3, -1, 4, 5, 6, 7, -1, -1, -1 };
  97 u_char plus_ee2irqmap[] =
  98         { 3, 4, 5, 7, 9, 10, 11, 12 };
  99
 100 /* Network Interface Functions */
 101 static void     ex_init(void *);
 102 static void     ex_init_locked(struct ex_softc *);
 103 static void     ex_start(struct ifnet *);
 104 static void     ex_start_locked(struct ifnet *);
 105 static int      ex_ioctl(struct ifnet *, u_long, caddr_t);
 106 static void     ex_watchdog(void *);
 107
 108 /* ifmedia Functions    */
 109 static int      ex_ifmedia_upd(struct ifnet *);
 110 static void     ex_ifmedia_sts(struct ifnet *, struct ifmediareq *);
 111
 112 static int      ex_get_media(struct ex_softc *);
 113
 114 static void     ex_reset(struct ex_softc *);
 115 static void     ex_setmulti(struct ex_softc *);
 116
 117 static void     ex_tx_intr(struct ex_softc *);
 118 static void     ex_rx_intr(struct ex_softc *);
 119
 120 void
 121 ex_get_address(struct ex_softc *sc, u_char *enaddr)
 122 {
 123         uint16_t        eaddr_tmp;
 124
 125         eaddr_tmp = ex_eeprom_read(sc, EE_Eth_Addr_Lo);
 126         enaddr[5] = eaddr_tmp & 0xff;
 127         enaddr[4] = eaddr_tmp >> 8;
 128         eaddr_tmp = ex_eeprom_read(sc, EE_Eth_Addr_Mid);
 129         enaddr[3] = eaddr_tmp & 0xff;
 130         enaddr[2] = eaddr_tmp >> 8;
 131         eaddr_tmp = ex_eeprom_read(sc, EE_Eth_Addr_Hi);
 132         enaddr[1] = eaddr_tmp & 0xff;
 133         enaddr[0] = eaddr_tmp >> 8;
 134
 135         return;
 136 }
 137
 138 int
 139 ex_card_type(u_char *enaddr)
 140 {
 141         if ((enaddr[0] == 0x00) && (enaddr[1] == 0xA0) && (enaddr[2] == 0xC9))
 142                 return (CARD_TYPE_EX_10_PLUS);
 143
 144         return (CARD_TYPE_EX_10);
 145 }
 146
 147 /*
 148  * Caller is responsible for eventually calling
 149  * ex_release_resources() on failure.
 150  */
 151 int
 152 ex_alloc_resources(device_t dev)
 153 {
 154         struct ex_softc *       sc = device_get_softc(dev);
 155         int                     error = 0;
 156
 157         sc->ioport = bus_alloc_resource_any(dev, SYS_RES_IOPORT,
 158                                             &sc->ioport_rid, RF_ACTIVE);
 159         if (!sc->ioport) {
 160                 device_printf(dev, "No I/O space?!\n");
 161                 error = ENOMEM;
 162                 goto bad;
 163         }
 164
 165         sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irq_rid,
 166                                         RF_ACTIVE);
 167
 168         if (!sc->irq) {
 169                 device_printf(dev, "No IRQ?!\n");
 170                 error = ENOMEM;
 171                 goto bad;
 172         }
 173
 174 bad:
 175         return (error);
 176 }
 177
 178 void
 179 ex_release_resources(device_t dev)
 180 {
 181         struct ex_softc *       sc = device_get_softc(dev);
 182
 183         if (sc->ih) {
 184                 bus_teardown_intr(dev, sc->irq, sc->ih);
 185                 sc->ih = NULL;
 186         }
 187
 188         if (sc->ioport) {
 189                 bus_release_resource(dev, SYS_RES_IOPORT,
 190                                         sc->ioport_rid, sc->ioport);
 191                 sc->ioport = NULL;
 192         }
 193
 194         if (sc->irq) {
 195                 bus_release_resource(dev, SYS_RES_IRQ,
 196                                         sc->irq_rid, sc->irq);
 197                 sc->irq = NULL;
 198         }
 199
 200         if (sc->ifp)
 201                 if_free(sc->ifp);
 202
 203         return;
 204 }
 205
 206 int
 207 ex_attach(device_t dev)
 208 {
 209         struct ex_softc *       sc = device_get_softc(dev);
 210         struct ifnet *          ifp;
 211         struct ifmedia *        ifm;
 212         int                     error;
 213         uint16_t                temp;
 214
 215         ifp = sc->ifp = if_alloc(IFT_ETHER);
 216         if (ifp == NULL) {
 217                 device_printf(dev, "can not if_alloc()\n");
 218                 return (ENOSPC);
 219         }
 220         /* work out which set of irq <-> internal tables to use */
 221         if (ex_card_type(sc->enaddr) == CARD_TYPE_EX_10_PLUS) {
 222                 sc->irq2ee = plus_irq2eemap;
 223                 sc->ee2irq = plus_ee2irqmap;
 224         } else {
 225                 sc->irq2ee = irq2eemap;
 226                 sc->ee2irq = ee2irqmap;
 227         }
 228
 229         sc->mem_size = CARD_RAM_SIZE;   /* XXX This should be read from the card itself. */
 230
 231         /*
 232          * Initialize the ifnet structure.
 233          */
 234         ifp->if_softc = sc;
 235         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
 236         ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST;
 237         ifp->if_start = ex_start;
 238         ifp->if_ioctl = ex_ioctl;
 239         ifp->if_init = ex_init;
 240         IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen);
 241
 242         ifmedia_init(&sc->ifmedia, 0, ex_ifmedia_upd, ex_ifmedia_sts);
 243         mtx_init(&sc->lock, device_get_nameunit(dev), MTX_NETWORK_LOCK,
 244             MTX_DEF);
 245         callout_init_mtx(&sc->timer, &sc->lock, 0);
 246
 247         temp = ex_eeprom_read(sc, EE_W5);
 248         if (temp & EE_W5_PORT_TPE)
 249                 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL);
 250         if (temp & EE_W5_PORT_BNC)
 251                 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_2, 0, NULL);
 252         if (temp & EE_W5_PORT_AUI)
 253                 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_5, 0, NULL);
 254
 255         ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
 256         ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_NONE, 0, NULL);
 257         ifmedia_set(&sc->ifmedia, ex_get_media(sc));
 258
 259         ifm = &sc->ifmedia;
 260         ifm->ifm_media = ifm->ifm_cur->ifm_media;
 261         ex_ifmedia_upd(ifp);
 262
 263         /*
 264          * Attach the interface.
 265          */
 266         ether_ifattach(ifp, sc->enaddr);
 267
 268         error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET | INTR_MPSAFE,
 269                                 NULL, ex_intr, (void *)sc, &sc->ih);
 270         if (error) {
 271                 device_printf(dev, "bus_setup_intr() failed!\n");
 272                 ether_ifdetach(ifp);
 273                 mtx_destroy(&sc->lock);
 274                 return (error);
 275         }
 276
 277         gone_by_fcp101_dev(dev);
 278
 279         return(0);
 280 }
 281
 282 int
 283 ex_detach(device_t dev)
 284 {
 285         struct ex_softc *sc;
 286         struct ifnet    *ifp;
 287
 288         sc = device_get_softc(dev);
 289         ifp = sc->ifp;
 290
 291         EX_LOCK(sc);
 292         ex_stop(sc);
 293         EX_UNLOCK(sc);
 294
 295         ether_ifdetach(ifp);
 296         callout_drain(&sc->timer);
 297
 298         ex_release_resources(dev);
 299         mtx_destroy(&sc->lock);
 300
 301         return (0);
 302 }
 303
 304 static void
 305 ex_init(void *xsc)
 306 {
 307         struct ex_softc *       sc = (struct ex_softc *) xsc;
 308
 309         EX_LOCK(sc);
 310         ex_init_locked(sc);
 311         EX_UNLOCK(sc);
 312 }
 313
 314 static void
 315 ex_init_locked(struct ex_softc *sc)
 316 {
 317         struct ifnet *          ifp = sc->ifp;
 318         int                     i;
 319         unsigned short          temp_reg;
 320
 321         DODEBUG(Start_End, printf("%s: ex_init: start\n", ifp->if_xname););
 322
 323         sc->tx_timeout = 0;
 324
 325         /*
 326          * Load the ethernet address into the card.
 327          */
 328         CSR_WRITE_1(sc, CMD_REG, Bank2_Sel);
 329         temp_reg = CSR_READ_1(sc, EEPROM_REG);
 330         if (temp_reg & Trnoff_Enable)
 331                 CSR_WRITE_1(sc, EEPROM_REG, temp_reg & ~Trnoff_Enable);
 332         for (i = 0; i < ETHER_ADDR_LEN; i++)
 333                 CSR_WRITE_1(sc, I_ADDR_REG0 + i, IF_LLADDR(sc->ifp)[i]);
 334
 335         /*
 336          * - Setup transmit chaining and discard bad received frames.
 337          * - Match broadcast.
 338          * - Clear test mode.
 339          * - Set receiving mode.
 340          */
 341         CSR_WRITE_1(sc, REG1, CSR_READ_1(sc, REG1) | Tx_Chn_Int_Md | Tx_Chn_ErStp | Disc_Bad_Fr);
 342         CSR_WRITE_1(sc, REG2, CSR_READ_1(sc, REG2) | No_SA_Ins | RX_CRC_InMem);
 343         CSR_WRITE_1(sc, REG3, CSR_READ_1(sc, REG3) & 0x3f /* XXX constants. */ );
 344         /*
 345          * - Set IRQ number, if this part has it.  ISA devices have this,
 346          * while PC Card devices don't seem to.  Either way, we have to
 347          * switch to Bank1 as the rest of this code relies on that.
 348          */
 349         CSR_WRITE_1(sc, CMD_REG, Bank1_Sel);
 350         if (sc->flags & HAS_INT_NO_REG)
 351                 CSR_WRITE_1(sc, INT_NO_REG,
 352                     (CSR_READ_1(sc, INT_NO_REG) & 0xf8) |
 353                     sc->irq2ee[sc->irq_no]);
 354
 355         /*
 356          * Divide the available memory in the card into rcv and xmt buffers.
 357          * By default, I use the first 3/4 of the memory for the rcv buffer,
 358          * and the remaining 1/4 of the memory for the xmt buffer.
 359          */
 360         sc->rx_mem_size = sc->mem_size * 3 / 4;
 361         sc->tx_mem_size = sc->mem_size - sc->rx_mem_size;
 362         sc->rx_lower_limit = 0x0000;
 363         sc->rx_upper_limit = sc->rx_mem_size - 2;
 364         sc->tx_lower_limit = sc->rx_mem_size;
 365         sc->tx_upper_limit = sc->mem_size - 2;
 366         CSR_WRITE_1(sc, RCV_LOWER_LIMIT_REG, sc->rx_lower_limit >> 8);
 367         CSR_WRITE_1(sc, RCV_UPPER_LIMIT_REG, sc->rx_upper_limit >> 8);
 368         CSR_WRITE_1(sc, XMT_LOWER_LIMIT_REG, sc->tx_lower_limit >> 8);
 369         CSR_WRITE_1(sc, XMT_UPPER_LIMIT_REG, sc->tx_upper_limit >> 8);
 370
 371         /*
 372          * Enable receive and transmit interrupts, and clear any pending int.
 373          */
 374         CSR_WRITE_1(sc, REG1, CSR_READ_1(sc, REG1) | TriST_INT);
 375         CSR_WRITE_1(sc, CMD_REG, Bank0_Sel);
 376         CSR_WRITE_1(sc, MASK_REG, All_Int & ~(Rx_Int | Tx_Int));
 377         CSR_WRITE_1(sc, STATUS_REG, All_Int);
 378
 379         /*
 380          * Initialize receive and transmit ring buffers.
 381          */
 382         CSR_WRITE_2(sc, RCV_BAR, sc->rx_lower_limit);
 383         sc->rx_head = sc->rx_lower_limit;
 384         CSR_WRITE_2(sc, RCV_STOP_REG, sc->rx_upper_limit | 0xfe);
 385         CSR_WRITE_2(sc, XMT_BAR, sc->tx_lower_limit);
 386         sc->tx_head = sc->tx_tail = sc->tx_lower_limit;
 387
 388         ifp->if_drv_flags |= IFF_DRV_RUNNING;
 389         ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
 390         DODEBUG(Status, printf("OIDLE init\n"););
 391         callout_reset(&sc->timer, hz, ex_watchdog, sc);
 392
 393         ex_setmulti(sc);
 394
 395         /*
 396          * Final reset of the board, and enable operation.
 397          */
 398         CSR_WRITE_1(sc, CMD_REG, Sel_Reset_CMD);
 399         DELAY(2);
 400         CSR_WRITE_1(sc, CMD_REG, Rcv_Enable_CMD);
 401
 402         ex_start_locked(ifp);
 403
 404         DODEBUG(Start_End, printf("%s: ex_init: finish\n", ifp->if_xname););
 405 }
 406
 407 static void
 408 ex_start(struct ifnet *ifp)
 409 {
 410         struct ex_softc *       sc = ifp->if_softc;
 411
 412         EX_LOCK(sc);
 413         ex_start_locked(ifp);
 414         EX_UNLOCK(sc);
 415 }
 416
 417 static void
 418 ex_start_locked(struct ifnet *ifp)
 419 {
 420         struct ex_softc *       sc = ifp->if_softc;
 421         int                     i, len, data_len, avail, dest, next;
 422         unsigned char           tmp16[2];
 423         struct mbuf *           opkt;
 424         struct mbuf *           m;
 425
 426         DODEBUG(Start_End, printf("ex_start%d: start\n", unit););
 427
 428         /*
 429          * Main loop: send outgoing packets to network card until there are no
 430          * more packets left, or the card cannot accept any more yet.
 431          */
 432         while (((opkt = ifp->if_snd.ifq_head) != NULL) &&
 433                !(ifp->if_drv_flags & IFF_DRV_OACTIVE)) {
 434
 435                 /*
 436                  * Ensure there is enough free transmit buffer space for
 437                  * this packet, including its header. Note: the header
 438                  * cannot wrap around the end of the transmit buffer and
 439                  * must be kept together, so we allow space for twice the
 440                  * length of the header, just in case.
 441                  */
 442
 443                 for (len = 0, m = opkt; m != NULL; m = m->m_next) {
 444                         len += m->m_len;
 445                 }
 446
 447                 data_len = len;
 448
 449                 DODEBUG(Sent_Pkts, printf("1. Sending packet with %d data bytes. ", data_len););
 450
 451                 if (len & 1) {
 452                         len += XMT_HEADER_LEN + 1;
 453                 } else {
 454                         len += XMT_HEADER_LEN;
 455                 }
 456
 457                 if ((i = sc->tx_tail - sc->tx_head) >= 0) {
 458                         avail = sc->tx_mem_size - i;
 459                 } else {
 460                         avail = -i;
 461                 }
 462
 463                 DODEBUG(Sent_Pkts, printf("i=%d, avail=%d\n", i, avail););
 464
 465                 if (avail >= len + XMT_HEADER_LEN) {
 466                         IF_DEQUEUE(&ifp->if_snd, opkt);
 467
 468 #ifdef EX_PSA_INTR
 469                         /*
 470                          * Disable rx and tx interrupts, to avoid corruption
 471                          * of the host address register by interrupt service
 472                          * routines.
 473                          * XXX Is this necessary with splimp() enabled?
 474                          */
 475                         CSR_WRITE_1(sc, MASK_REG, All_Int);
 476 #endif
 477
 478                         /*
 479                          * Compute the start and end addresses of this
 480                          * frame in the tx buffer.
 481                          */
 482                         dest = sc->tx_tail;
 483                         next = dest + len;
 484
 485                         if (next > sc->tx_upper_limit) {
 486                                 if ((sc->tx_upper_limit + 2 - sc->tx_tail) <=
 487                                     XMT_HEADER_LEN) {
 488                                         dest = sc->tx_lower_limit;
 489                                         next = dest + len;
 490                                 } else {
 491                                         next = sc->tx_lower_limit +
 492                                                 next - sc->tx_upper_limit - 2;
 493                                 }
 494                         }
 495
 496                         /*
 497                          * Build the packet frame in the card's ring buffer.
 498                          */
 499                         DODEBUG(Sent_Pkts, printf("2. dest=%d, next=%d. ", dest, next););
 500
 501                         CSR_WRITE_2(sc, HOST_ADDR_REG, dest);
 502                         CSR_WRITE_2(sc, IO_PORT_REG, Transmit_CMD);
 503                         CSR_WRITE_2(sc, IO_PORT_REG, 0);
 504                         CSR_WRITE_2(sc, IO_PORT_REG, next);
 505                         CSR_WRITE_2(sc, IO_PORT_REG, data_len);
 506
 507                         /*
 508                          * Output the packet data to the card. Ensure all
 509                          * transfers are 16-bit wide, even if individual
 510                          * mbufs have odd length.
 511                          */
 512                         for (m = opkt, i = 0; m != NULL; m = m->m_next) {
 513                                 DODEBUG(Sent_Pkts, printf("[%d]", m->m_len););
 514                                 if (i) {
 515                                         tmp16[1] = *(mtod(m, caddr_t));
 516                                         CSR_WRITE_MULTI_2(sc, IO_PORT_REG,
 517                                             (uint16_t *) tmp16, 1);
 518                                 }
 519                                 CSR_WRITE_MULTI_2(sc, IO_PORT_REG,
 520                                     (uint16_t *) (mtod(m, caddr_t) + i),
 521                                     (m->m_len - i) / 2);
 522                                 if ((i = (m->m_len - i) & 1) != 0) {
 523                                         tmp16[0] = *(mtod(m, caddr_t) +
 524                                                    m->m_len - 1);
 525                                 }
 526                         }
 527                         if (i)
 528                                 CSR_WRITE_MULTI_2(sc, IO_PORT_REG,
 529                                     (uint16_t *) tmp16, 1);
 530                         /*
 531                          * If there were other frames chained, update the
 532                          * chain in the last one.
 533                          */
 534                         if (sc->tx_head != sc->tx_tail) {
 535                                 if (sc->tx_tail != dest) {
 536                                         CSR_WRITE_2(sc, HOST_ADDR_REG,
 537                                              sc->tx_last + XMT_Chain_Point);
 538                                         CSR_WRITE_2(sc, IO_PORT_REG, dest);
 539                                 }
 540                                 CSR_WRITE_2(sc, HOST_ADDR_REG,
 541                                      sc->tx_last + XMT_Byte_Count);
 542                                 i = CSR_READ_2(sc, IO_PORT_REG);
 543                                 CSR_WRITE_2(sc, HOST_ADDR_REG,
 544                                      sc->tx_last + XMT_Byte_Count);
 545                                 CSR_WRITE_2(sc, IO_PORT_REG, i | Ch_bit);
 546                         }
 547
 548                         /*
 549                          * Resume normal operation of the card:
 550                          * - Make a dummy read to flush the DRAM write
 551                          *   pipeline.
 552                          * - Enable receive and transmit interrupts.
 553                          * - Send Transmit or Resume_XMT command, as
 554                          *   appropriate.
 555                          */
 556                         CSR_READ_2(sc, IO_PORT_REG);
 557 #ifdef EX_PSA_INTR
 558                         CSR_WRITE_1(sc, MASK_REG, All_Int & ~(Rx_Int | Tx_Int));
 559 #endif
 560                         if (sc->tx_head == sc->tx_tail) {
 561                                 CSR_WRITE_2(sc, XMT_BAR, dest);
 562                                 CSR_WRITE_1(sc, CMD_REG, Transmit_CMD);
 563                                 sc->tx_head = dest;
 564                                 DODEBUG(Sent_Pkts, printf("Transmit\n"););
 565                         } else {
 566                                 CSR_WRITE_1(sc, CMD_REG, Resume_XMT_List_CMD);
 567                                 DODEBUG(Sent_Pkts, printf("Resume\n"););
 568                         }
 569
 570                         sc->tx_last = dest;
 571                         sc->tx_tail = next;
 572
 573                         BPF_MTAP(ifp, opkt);
 574
 575                         sc->tx_timeout = 2;
 576                         if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
 577                         m_freem(opkt);
 578                 } else {
 579                         ifp->if_drv_flags |= IFF_DRV_OACTIVE;
 580                         DODEBUG(Status, printf("OACTIVE start\n"););
 581                 }
 582         }
 583
 584         DODEBUG(Start_End, printf("ex_start%d: finish\n", unit););
 585 }
 586
 587 void
 588 ex_stop(struct ex_softc *sc)
 589 {
 590
 591         DODEBUG(Start_End, printf("ex_stop%d: start\n", unit););
 592
 593         EX_ASSERT_LOCKED(sc);
 594         /*
 595          * Disable card operation:
 596          * - Disable the interrupt line.
 597          * - Flush transmission and disable reception.
 598          * - Mask and clear all interrupts.
 599          * - Reset the 82595.
 600          */
 601         CSR_WRITE_1(sc, CMD_REG, Bank1_Sel);
 602         CSR_WRITE_1(sc, REG1, CSR_READ_1(sc, REG1) & ~TriST_INT);
 603         CSR_WRITE_1(sc, CMD_REG, Bank0_Sel);
 604         CSR_WRITE_1(sc, CMD_REG, Rcv_Stop);
 605         sc->tx_head = sc->tx_tail = sc->tx_lower_limit;
 606         sc->tx_last = 0; /* XXX I think these two lines are not necessary, because ex_init will always be called again to reinit the interface. */
 607         CSR_WRITE_1(sc, MASK_REG, All_Int);
 608         CSR_WRITE_1(sc, STATUS_REG, All_Int);
 609         CSR_WRITE_1(sc, CMD_REG, Reset_CMD);
 610         DELAY(200);
 611         sc->ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
 612         sc->tx_timeout = 0;
 613         callout_stop(&sc->timer);
 614
 615         DODEBUG(Start_End, printf("ex_stop%d: finish\n", unit););
 616
 617         return;
 618 }
 619
 620 void
 621 ex_intr(void *arg)
 622 {
 623         struct ex_softc *sc = (struct ex_softc *)arg;
 624         struct ifnet    *ifp = sc->ifp;
 625         int             int_status, send_pkts;
 626         int             loops = 100;
 627
 628         DODEBUG(Start_End, printf("ex_intr%d: start\n", unit););
 629
 630         EX_LOCK(sc);
 631         send_pkts = 0;
 632         while (loops-- > 0 &&
 633             (int_status = CSR_READ_1(sc, STATUS_REG)) & (Tx_Int | Rx_Int)) {
 634                 /* don't loop forever */
 635                 if (int_status == 0xff)
 636                         break;
 637                 if (int_status & Rx_Int) {
 638                         CSR_WRITE_1(sc, STATUS_REG, Rx_Int);
 639                         ex_rx_intr(sc);
 640                 } else if (int_status & Tx_Int) {
 641                         CSR_WRITE_1(sc, STATUS_REG, Tx_Int);
 642                         ex_tx_intr(sc);
 643                         send_pkts = 1;
 644                 }
 645         }
 646         if (loops == 0)
 647                 printf("100 loops are not enough\n");
 648
 649         /*
 650          * If any packet has been transmitted, and there are queued packets to
 651          * be sent, attempt to send more packets to the network card.
 652          */
 653         if (send_pkts && (ifp->if_snd.ifq_head != NULL))
 654                 ex_start_locked(ifp);
 655         EX_UNLOCK(sc);
 656
 657         DODEBUG(Start_End, printf("ex_intr%d: finish\n", unit););
 658
 659         return;
 660 }
 661
 662 static void
 663 ex_tx_intr(struct ex_softc *sc)
 664 {
 665         struct ifnet *  ifp = sc->ifp;
 666         int             tx_status;
 667
 668         DODEBUG(Start_End, printf("ex_tx_intr%d: start\n", unit););
 669
 670         /*
 671          * - Cancel the watchdog.
 672          * For all packets transmitted since last transmit interrupt:
 673          * - Advance chain pointer to next queued packet.
 674          * - Update statistics.
 675          */
 676
 677         sc->tx_timeout = 0;
 678
 679         while (sc->tx_head != sc->tx_tail) {
 680                 CSR_WRITE_2(sc, HOST_ADDR_REG, sc->tx_head);
 681
 682                 if (!(CSR_READ_2(sc, IO_PORT_REG) & Done_bit))
 683                         break;
 684
 685                 tx_status = CSR_READ_2(sc, IO_PORT_REG);
 686                 sc->tx_head = CSR_READ_2(sc, IO_PORT_REG);
 687
 688                 if (tx_status & TX_OK_bit) {
 689                         if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
 690                 } else {
 691                         if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
 692                 }
 693
 694                 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, tx_status & No_Collisions_bits);
 695         }
 696
 697         /*
 698          * The card should be ready to accept more packets now.
 699          */
 700
 701         ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
 702
 703         DODEBUG(Status, printf("OIDLE tx_intr\n"););
 704         DODEBUG(Start_End, printf("ex_tx_intr%d: finish\n", unit););
 705
 706         return;
 707 }
 708
 709 static void
 710 ex_rx_intr(struct ex_softc *sc)
 711 {
 712         struct ifnet *          ifp = sc->ifp;
 713         int                     rx_status;
 714         int                     pkt_len;
 715         int                     QQQ;
 716         struct mbuf *           m;
 717         struct mbuf *           ipkt;
 718         struct ether_header *   eh;
 719
 720         DODEBUG(Start_End, printf("ex_rx_intr%d: start\n", unit););
 721
 722         /*
 723          * For all packets received since last receive interrupt:
 724          * - If packet ok, read it into a new mbuf and queue it to interface,
 725          *   updating statistics.
 726          * - If packet bad, just discard it, and update statistics.
 727          * Finally, advance receive stop limit in card's memory to new location.
 728          */
 729
 730         CSR_WRITE_2(sc, HOST_ADDR_REG, sc->rx_head);
 731
 732         while (CSR_READ_2(sc, IO_PORT_REG) == RCV_Done) {
 733
 734                 rx_status = CSR_READ_2(sc, IO_PORT_REG);
 735                 sc->rx_head = CSR_READ_2(sc, IO_PORT_REG);
 736                 QQQ = pkt_len = CSR_READ_2(sc, IO_PORT_REG);
 737
 738                 if (rx_status & RCV_OK_bit) {
 739                         MGETHDR(m, M_NOWAIT, MT_DATA);
 740                         ipkt = m;
 741                         if (ipkt == NULL) {
 742                                 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
 743                         } else {
 744                                 ipkt->m_pkthdr.rcvif = ifp;
 745                                 ipkt->m_pkthdr.len = pkt_len;
 746                                 ipkt->m_len = MHLEN;
 747
 748                                 while (pkt_len > 0) {
 749                                         if (pkt_len >= MINCLSIZE) {
 750                                                 if (MCLGET(m, M_NOWAIT)) {
 751                                                         m->m_len = MCLBYTES;
 752                                                 } else {
 753                                                         m_freem(ipkt);
 754                                                         if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
 755                                                         goto rx_another;
 756                                                 }
 757                                         }
 758                                         m->m_len = min(m->m_len, pkt_len);
 759
 760           /*
 761            * NOTE: I'm assuming that all mbufs allocated are of even length,
 762            * except for the last one in an odd-length packet.
 763            */
 764
 765                                         CSR_READ_MULTI_2(sc, IO_PORT_REG,
 766                                             mtod(m, uint16_t *), m->m_len / 2);
 767
 768                                         if (m->m_len & 1) {
 769                                                 *(mtod(m, caddr_t) + m->m_len - 1) = CSR_READ_1(sc, IO_PORT_REG);
 770                                         }
 771                                         pkt_len -= m->m_len;
 772
 773                                         if (pkt_len > 0) {
 774                                                 MGET(m->m_next, M_NOWAIT, MT_DATA);
 775                                                 if (m->m_next == NULL) {
 776                                                         m_freem(ipkt);
 777                                                         if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
 778                                                         goto rx_another;
 779                                                 }
 780                                                 m = m->m_next;
 781                                                 m->m_len = MLEN;
 782                                         }
 783                                 }
 784                                 eh = mtod(ipkt, struct ether_header *);
 785 #ifdef EXDEBUG
 786         if (debug_mask & Rcvd_Pkts) {
 787                 if ((eh->ether_dhost[5] != 0xff) || (eh->ether_dhost[0] != 0xff)) {
 788                         printf("Receive packet with %d data bytes: %6D -> ", QQQ, eh->ether_shost, ":");
 789                         printf("%6D\n", eh->ether_dhost, ":");
 790                 } /* QQQ */
 791         }
 792 #endif
 793                                 EX_UNLOCK(sc);
 794                                 (*ifp->if_input)(ifp, ipkt);
 795                                 EX_LOCK(sc);
 796                                 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
 797                         }
 798                 } else {
 799                         if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
 800                 }
 801                 CSR_WRITE_2(sc, HOST_ADDR_REG, sc->rx_head);
 802 rx_another: ;
 803         }
 804
 805         if (sc->rx_head < sc->rx_lower_limit + 2)
 806                 CSR_WRITE_2(sc, RCV_STOP_REG, sc->rx_upper_limit);
 807         else
 808                 CSR_WRITE_2(sc, RCV_STOP_REG, sc->rx_head - 2);
 809
 810         DODEBUG(Start_End, printf("ex_rx_intr%d: finish\n", unit););
 811
 812         return;
 813 }
 814
 815
 816 static int
 817 ex_ioctl(register struct ifnet *ifp, u_long cmd, caddr_t data)
 818 {
 819         struct ex_softc *       sc = ifp->if_softc;
 820         struct ifreq *          ifr = (struct ifreq *)data;
 821         int                     error = 0;
 822
 823         DODEBUG(Start_End, printf("%s: ex_ioctl: start ", ifp->if_xname););
 824
 825         switch(cmd) {
 826                 case SIOCSIFADDR:
 827                 case SIOCGIFADDR:
 828                 case SIOCSIFMTU:
 829                         error = ether_ioctl(ifp, cmd, data);
 830                         break;
 831
 832                 case SIOCSIFFLAGS:
 833                         DODEBUG(Start_End, printf("SIOCSIFFLAGS"););
 834                         EX_LOCK(sc);
 835                         if ((ifp->if_flags & IFF_UP) == 0 &&
 836                             (ifp->if_drv_flags & IFF_DRV_RUNNING)) {
 837                                 ex_stop(sc);
 838                         } else {
 839                                 ex_init_locked(sc);
 840                         }
 841                         EX_UNLOCK(sc);
 842                         break;
 843                 case SIOCADDMULTI:
 844                 case SIOCDELMULTI:
 845                         ex_init(sc);
 846                         error = 0;
 847                         break;
 848                 case SIOCSIFMEDIA:
 849                 case SIOCGIFMEDIA:
 850                         error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, cmd);
 851                         break;
 852                 default:
 853                         DODEBUG(Start_End, printf("unknown"););
 854                         error = EINVAL;
 855         }
 856
 857         DODEBUG(Start_End, printf("\n%s: ex_ioctl: finish\n", ifp->if_xname););
 858
 859         return(error);
 860 }
 861
 862 static void
 863 ex_setmulti(struct ex_softc *sc)
 864 {
 865         struct ifnet *ifp;
 866         struct ifmultiaddr *maddr;
 867         uint16_t *addr;
 868         int count;
 869         int timeout, status;
 870
 871         ifp = sc->ifp;
 872
 873         count = 0;
 874         if_maddr_rlock(ifp);
 875         TAILQ_FOREACH(maddr, &ifp->if_multiaddrs, ifma_link) {
 876                 if (maddr->ifma_addr->sa_family != AF_LINK)
 877                         continue;
 878                 count++;
 879         }
 880         if_maddr_runlock(ifp);
 881
 882         if ((ifp->if_flags & IFF_PROMISC) || (ifp->if_flags & IFF_ALLMULTI)
 883                         || count > 63) {
 884                 /* Interface is in promiscuous mode or there are too many
 885                  * multicast addresses for the card to handle */
 886                 CSR_WRITE_1(sc, CMD_REG, Bank2_Sel);
 887                 CSR_WRITE_1(sc, REG2, CSR_READ_1(sc, REG2) | Promisc_Mode);
 888                 CSR_WRITE_1(sc, REG3, CSR_READ_1(sc, REG3));
 889                 CSR_WRITE_1(sc, CMD_REG, Bank0_Sel);
 890         }
 891         else if ((ifp->if_flags & IFF_MULTICAST) && (count > 0)) {
 892                 /* Program multicast addresses plus our MAC address
 893                  * into the filter */
 894                 CSR_WRITE_1(sc, CMD_REG, Bank2_Sel);
 895                 CSR_WRITE_1(sc, REG2, CSR_READ_1(sc, REG2) | Multi_IA);
 896                 CSR_WRITE_1(sc, REG3, CSR_READ_1(sc, REG3));
 897                 CSR_WRITE_1(sc, CMD_REG, Bank0_Sel);
 898
 899                 /* Borrow space from TX buffer; this should be safe
 900                  * as this is only called from ex_init */
 901
 902                 CSR_WRITE_2(sc, HOST_ADDR_REG, sc->tx_lower_limit);
 903                 CSR_WRITE_2(sc, IO_PORT_REG, MC_Setup_CMD);
 904                 CSR_WRITE_2(sc, IO_PORT_REG, 0);
 905                 CSR_WRITE_2(sc, IO_PORT_REG, 0);
 906                 CSR_WRITE_2(sc, IO_PORT_REG, (count + 1) * 6);
 907
 908                 if_maddr_rlock(ifp);
 909                 TAILQ_FOREACH(maddr, &ifp->if_multiaddrs, ifma_link) {
 910                         if (maddr->ifma_addr->sa_family != AF_LINK)
 911                                 continue;
 912
 913                         addr = (uint16_t*)LLADDR((struct sockaddr_dl *)
 914                                         maddr->ifma_addr);
 915                         CSR_WRITE_2(sc, IO_PORT_REG, *addr++);
 916                         CSR_WRITE_2(sc, IO_PORT_REG, *addr++);
 917                         CSR_WRITE_2(sc, IO_PORT_REG, *addr++);
 918                 }
 919                 if_maddr_runlock(ifp);
 920
 921                 /* Program our MAC address as well */
 922                 /* XXX: Is this necessary?  The Linux driver does this
 923                  * but the NetBSD driver does not */
 924                 addr = (uint16_t*)IF_LLADDR(sc->ifp);
 925                 CSR_WRITE_2(sc, IO_PORT_REG, *addr++);
 926                 CSR_WRITE_2(sc, IO_PORT_REG, *addr++);
 927                 CSR_WRITE_2(sc, IO_PORT_REG, *addr++);
 928
 929                 CSR_READ_2(sc, IO_PORT_REG);
 930                 CSR_WRITE_2(sc, XMT_BAR, sc->tx_lower_limit);
 931                 CSR_WRITE_1(sc, CMD_REG, MC_Setup_CMD);
 932
 933                 sc->tx_head = sc->tx_lower_limit;
 934                 sc->tx_tail = sc->tx_head + XMT_HEADER_LEN + (count + 1) * 6;
 935
 936                 for (timeout=0; timeout<100; timeout++) {
 937                         DELAY(2);
 938                         if ((CSR_READ_1(sc, STATUS_REG) & Exec_Int) == 0)
 939                                 continue;
 940
 941                         status = CSR_READ_1(sc, CMD_REG);
 942                         CSR_WRITE_1(sc, STATUS_REG, Exec_Int);
 943                         break;
 944                 }
 945
 946                 sc->tx_head = sc->tx_tail;
 947         }
 948         else
 949         {
 950                 /* No multicast or promiscuous mode */
 951                 CSR_WRITE_1(sc, CMD_REG, Bank2_Sel);
 952                 CSR_WRITE_1(sc, REG2, CSR_READ_1(sc, REG2) & 0xDE);
 953                         /* ~(Multi_IA | Promisc_Mode) */
 954                 CSR_WRITE_1(sc, REG3, CSR_READ_1(sc, REG3));
 955                 CSR_WRITE_1(sc, CMD_REG, Bank0_Sel);
 956         }
 957 }
 958
 959 static void
 960 ex_reset(struct ex_softc *sc)
 961 {
 962
 963         DODEBUG(Start_End, printf("ex_reset%d: start\n", unit););
 964
 965         EX_ASSERT_LOCKED(sc);
 966         ex_stop(sc);
 967         ex_init_locked(sc);
 968
 969         DODEBUG(Start_End, printf("ex_reset%d: finish\n", unit););
 970
 971         return;
 972 }
 973
 974 static void
 975 ex_watchdog(void *arg)
 976 {
 977         struct ex_softc *       sc = arg;
 978         struct ifnet *ifp = sc->ifp;
 979
 980         if (sc->tx_timeout && --sc->tx_timeout == 0) {
 981                 DODEBUG(Start_End, if_printf(ifp, "ex_watchdog: start\n"););
 982
 983                 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
 984
 985                 DODEBUG(Status, printf("OIDLE watchdog\n"););
 986
 987                 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
 988                 ex_reset(sc);
 989                 ex_start_locked(ifp);
 990
 991                 DODEBUG(Start_End, if_printf(ifp, "ex_watchdog: finish\n"););
 992         }
 993
 994         callout_reset(&sc->timer, hz, ex_watchdog, sc);
 995 }
 996
 997 static int
 998 ex_get_media(struct ex_softc *sc)
 999 {
1000         int     current;
1001         int     media;
1002
1003         media = ex_eeprom_read(sc, EE_W5);
1004
1005         CSR_WRITE_1(sc, CMD_REG, Bank2_Sel);
1006         current = CSR_READ_1(sc, REG3);
1007         CSR_WRITE_1(sc, CMD_REG, Bank0_Sel);
1008
1009         if ((current & TPE_bit) && (media & EE_W5_PORT_TPE))
1010                 return(IFM_ETHER|IFM_10_T);
1011         if ((current & BNC_bit) && (media & EE_W5_PORT_BNC))
1012                 return(IFM_ETHER|IFM_10_2);
1013
1014         if (media & EE_W5_PORT_AUI)
1015                 return (IFM_ETHER|IFM_10_5);
1016
1017         return (IFM_ETHER|IFM_AUTO);
1018 }
1019
1020 static int
1021 ex_ifmedia_upd(ifp)
1022         struct ifnet *          ifp;
1023 {
1024         struct ex_softc *       sc = ifp->if_softc;
1025
1026         if (IFM_TYPE(sc->ifmedia.ifm_media) != IFM_ETHER)
1027                 return EINVAL;
1028
1029         return (0);
1030 }
1031
1032 static void
1033 ex_ifmedia_sts(ifp, ifmr)
1034         struct ifnet *          ifp;
1035         struct ifmediareq *     ifmr;
1036 {
1037         struct ex_softc *       sc = ifp->if_softc;
1038
1039         EX_LOCK(sc);
1040         ifmr->ifm_active = ex_get_media(sc);
1041         ifmr->ifm_status = IFM_AVALID | IFM_ACTIVE;
1042         EX_UNLOCK(sc);
1043
1044         return;
1045 }
1046
1047 u_short
1048 ex_eeprom_read(struct ex_softc *sc, int location)
1049 {
1050         int i;
1051         u_short data = 0;
1052         int read_cmd = location | EE_READ_CMD;
1053         short ctrl_val = EECS;
1054
1055         CSR_WRITE_1(sc, CMD_REG, Bank2_Sel);
1056         CSR_WRITE_1(sc, EEPROM_REG, EECS);
1057         for (i = 8; i >= 0; i--) {
1058                 short outval = (read_cmd & (1 << i)) ? ctrl_val | EEDI : ctrl_val;
1059                 CSR_WRITE_1(sc, EEPROM_REG, outval);
1060                 CSR_WRITE_1(sc, EEPROM_REG, outval | EESK);
1061                 DELAY(3);
1062                 CSR_WRITE_1(sc, EEPROM_REG, outval);
1063                 DELAY(2);
1064         }
1065         CSR_WRITE_1(sc, EEPROM_REG, ctrl_val);
1066
1067         for (i = 16; i > 0; i--) {
1068                 CSR_WRITE_1(sc, EEPROM_REG, ctrl_val | EESK);
1069                 DELAY(3);
1070                 data = (data << 1) |
1071                     ((CSR_READ_1(sc, EEPROM_REG) & EEDO) ? 1 : 0);
1072                 CSR_WRITE_1(sc, EEPROM_REG, ctrl_val);
1073                 DELAY(2);
1074         }
1075
1076         ctrl_val &= ~EECS;
1077         CSR_WRITE_1(sc, EEPROM_REG, ctrl_val | EESK);
1078         DELAY(3);
1079         CSR_WRITE_1(sc, EEPROM_REG, ctrl_val);
1080         DELAY(2);
1081         CSR_WRITE_1(sc, CMD_REG, Bank0_Sel);
1082         return(data);
1083 }