2 * Copyright (c) 1996, Javier MartÃn Rueda (jmrueda@diatel.upm.es)
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 * Intel EtherExpress Pro/10 Ethernet driver
38 /* Length of an ethernet address. */
39 #define ETHER_ADDR_LEN 6
40 /* Default RAM size in board. */
41 #define CARD_RAM_SIZE 0x8000
42 /* Number of I/O ports used. */
46 * Intel EtherExpress Pro (i82595 based) registers
49 /* Common registers to all banks. */
68 /* Definitions for command register (CMD_REG). */
70 #define Switch_Bank_CMD 0
71 #define MC_Setup_CMD 3
72 #define Transmit_CMD 4
73 #define Diagnose_CMD 7
74 #define Rcv_Enable_CMD 8
77 #define Resume_XMT_List_CMD 28
78 #define Sel_Reset_CMD 30
80 #define Bank0_Sel 0x00
81 #define Bank1_Sel 0x40
82 #define Bank2_Sel 0x80
84 /* Bank 0 specific registers. */
90 #define Counter_bits 0xc0
95 #define Rx_Stp_Int 0x01
100 #define RCV_STOP_REG 6
102 #define HOST_ADDR_REG 12 /* 16-bit register */
103 #define IO_PORT_REG 14 /* 16-bit register */
105 /* Bank 1 specific registers. */
107 #define TriST_INT 0x80
109 #define RCV_LOWER_LIMIT_REG 8
110 #define RCV_UPPER_LIMIT_REG 9
111 #define XMT_LOWER_LIMIT_REG 10
112 #define XMT_UPPER_LIMIT_REG 11
114 /* Bank 2 specific registers. */
116 #define Disc_Bad_Fr 0x80
117 #define Tx_Chn_ErStp 0x40
118 #define Tx_Chn_Int_Md 0x20
119 #define No_SA_Ins 0x10
120 #define RX_CRC_InMem 0x04
123 #define I_ADDR_REG0 4
124 #define EEPROM_REG 10
125 #define Trnoff_Enable 0x10
127 /* EEPROM memory positions (16-bit wide). */
130 # define EE_W0_PNP 0x0001
131 # define EE_W0_BUS16 0x0004
132 # define EE_W0_FLASH_ADDR_MASK 0x0038
133 # define EE_W0_FLASH_ADDR_SHIFT 3
134 # define EE_W0_AUTO_IO 0x0040
135 # define EE_W0_FLASH 0x0100
136 # define EE_W0_AUTO_NEG 0x0200
137 # define EE_W0_IO_MASK 0xFC00
138 # define EE_W0_IO_SHIFT 10
141 #define IRQ_No_Mask 0x07
144 # define EE_W1_INT_SEL 0x0007
145 # define EE_W1_NO_LINK_INT 0x0008 /* Link Integrity Off */
146 # define EE_W1_NO_POLARITY 0x0010 /* Polarity Correction Off */
147 # define EE_W1_TPE_AUI 0x0020 /* 1 = TPE, 0 = AUI */
148 # define EE_W1_NO_JABBER_PREV 0x0040 /* Jabber prevention Off */
149 # define EE_W1_NO_AUTO_SELECT 0x0080 /* Auto Port Selection Off */
150 # define EE_W1_SMOUT 0x0100 /* SMout Pin Control 0= Input */
151 # define EE_W1_PROM 0x0200 /* Flash = 0, PROM = 1 */
152 # define EE_W1_ALT_READY 0x2000 /* Alternate Ready, 0=normal */
153 # define EE_W1_FULL_DUPLEX 0x8000
159 #define EE_Eth_Addr_Lo 2
160 #define EE_Eth_Addr_Mid 3
161 #define EE_Eth_Addr_Hi 4
164 # define EE_W5_BNC_TPE 0x0001 /* 0 = TPE, 1 = BNC */
165 # define EE_W5_BOOT_IPX 0x0002
166 # define EE_W5_BOOT_ODI 0x0004
167 # define EE_W5_BOOT_NDIS (EE_W5_BOOT_IPX|EE_W5_BOOT_ODI)
168 # define EE_W5_NUM_CONN 0x0008 /* 0 = 2, 1 = 3 */
169 # define EE_W5_NOFLASH 0x0010 /* No flash socket present */
170 # define EE_W5_PORT_TPE 0x0020 /* TPE present */
171 # define EE_W5_PORT_BNC 0x0040 /* BNC present */
172 # define EE_W5_PORT_AUI 0x0080 /* AUI present */
173 # define EE_W5_PWR_MGT 0x0100 /* Power Management */
174 # define EE_W5_CP 0x0200 /* COncurrent Processing */
177 # define EE_W6_STEP_MASK 0x000F
178 # define EE_W6_BOARD_MASK 0xFFF0
179 # define EE_W6_BOARD_SHIFT 4
181 /* EEPROM serial interface. */
187 #define EE_READ_CMD (6 << 6)
189 /* Frame chain constants. */
191 /* Transmit header length (in board's ring buffer). */
192 #define XMT_HEADER_LEN 8
193 #define XMT_Chain_Point 4
194 #define XMT_Byte_Count 6
195 #define Done_bit 0x0080
196 #define Ch_bit 0x8000
197 /* Transmit result bits. */
198 #define No_Collisions_bits 0x000f
199 #define TX_OK_bit 0x2000
200 /* Receive result bits. */
202 #define RCV_OK_bit 0x2000