2 * Copyright (c) 2001-2003
3 * Fraunhofer Institute for Open Communication Systems (FhG Fokus).
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * Author: Hartmut Brandt <harti@freebsd.org>
31 * Fore PCA200E hardware definitions.
35 * Fore implements some additional PCI registers. One of them is the
36 * master control register. One of the bits allow to automatically byte
37 * swap accesses to the on-board RAM.
39 #define FATM_PCIR_MCTL 0x41
40 #define FATM_PCIM_SWAB 0x100
43 * Operations codes for commands.
46 FATM_OP_INITIALIZE = 0x01, /* Initialize the card */
47 FATM_OP_ACTIVATE_VCIN = 0x02, /* Start reassembly on a channel */
48 FATM_OP_ACTIVATE_VCOUT = 0x03, /* (not used) */
49 FATM_OP_DEACTIVATE_VCIN = 0x04, /* Stop reassembly on a channel */
50 FATM_OP_DEACTIVATE_VCOUT= 0x05, /* (not used) */
51 FATM_OP_REQUEST_STATS = 0x06, /* Get statistics */
52 FATM_OP_OC3_SET_REG = 0x07, /* Set OC3 chip register */
53 FATM_OP_OC3_GET_REG = 0x08, /* Get OC3 chip registers */
54 FATM_OP_ZERO_STATS = 0x09, /* Zero out statistics */
55 FATM_OP_GET_PROM_DATA = 0x0a, /* Return expansion ROM data */
56 FATM_OP_SETVPI_BITS = 0x0b, /* (not used, not implemented) */
58 FATM_OP_INTERRUPT_SEL = 0x80, /* Request interrupt on completion */
62 * Status word definitions. Before initiating an operation the host sets the
63 * status word to PENDING. The card sets it to COMPLETE upon completion of
64 * the transmit/receive or command. An unused queue entry contains FREE.
65 * The ERROR can be ored into the COMPLETE. Note, that there are circumstances
66 * when ERROR is set without COMPLETE being set (when you try to activate
67 * a bad VCI like, for example, VCI 0).
70 FATM_STAT_PENDING = 0x01,
71 FATM_STAT_COMPLETE = 0x02,
72 FATM_STAT_FREE = 0x04,
73 FATM_STAT_ERROR = 0x08,
77 * On board queue offsets. There are two fundamentally different queue types:
78 * the command queue and all other queues. The command queue has 32 byte
79 * entries on the card which contain the operation code, parameters and the
80 * DMA pointer to the status word. All other queues have 8 byte entries, which
81 * contain a DMA pointer to the i/o block, that contains the parameters, and
82 * a DMA pointer to the status word.
84 #define FATMOC_OP 0 /* cmd queue: offset to op code */
85 #define FATMOC_PARAM 4 /* cmd queue: offset to parameters */
86 #define FATMOC_STATP 16 /* cmd queue: offset to status ptr */
87 #define FATMOC_END 32 /* cmd queue: element size */
89 #define FATMOC_ACTIN_VPVC (FATMOC_PARAM + 0)
90 #define FATMOC_ACTIN_MTU (FATMOC_PARAM + 4)
91 #define FATMOC_DEACTIN_VPVC (FATMOC_PARAM + 0)
92 #define FATMOC_GETOC3_BUF (FATMOC_PARAM + 0)
93 #define FATMOC_GSTAT_BUF (FATMOC_PARAM + 0)
94 #define FATMOC_GPROM_BUF (FATMOC_PARAM + 0)
96 #define FATMOS_IOBLK 0 /* other queues: offset to ioblk ptr */
97 #define FATMOS_STATP 4 /* other queues: offset to status ptr */
99 #define FATM_MAKE_SETOC3(REG,VAL,MASK) \
100 (FATM_OP_OC3_SET_REG | (((REG) & 0xff) << 8) | \
101 (((VAL) & 0xff) << 16) | (((MASK) & 0xff) << 24))
102 #define FATM_NREGS 128
106 * On board memory layout.
108 * The card contains up to 2MByte memory that is mapped at virtual offset 0.
109 * It is followed by three registers. The memory contains two areas at
110 * fixed addresses: the mon960 area that is used for communication with
111 * the card's operating system and the common block that is used by the
112 * firmware to communicate with the driver.
114 #define FATM_RAM_SIZE (256 * 1024) /* normal RAM size */
116 #define FATMO_RAM (0x0) /* virtual RAM start */
117 #define FATMO_MON960 (0x400) /* mon960 communication area */
118 #define FATMO_COMMON_ORIGIN (0x4d40) /* firmware comm. area */
120 #define FATMO_HCR (0x100000) /* host control registers */
121 #define FATMO_HIMR (0x100004) /* host interrupt mask */
122 #define FATMO_PSR (0x100008) /* PCI control register */
124 #define FATMO_END (0x200000) /* end of mapped area */
127 * The mon960 area contains two cells that are used as a virtual serial
128 * interface, a status word, the base for loading the application (i.e.
129 * firmware) and a version number.
131 #define FATMO_UART_TO_960 (FATMO_MON960 + 0)
132 #define FATMO_UART_TO_HOST (FATMO_MON960 + 4)
133 #define FATMO_BOOT_STATUS (FATMO_MON960 + 8)
134 #define FATMO_APP_BASE (FATMO_MON960 + 12)
135 #define FATMO_VERSION (FATMO_MON960 + 16)
139 * The host control register allows to hold the i960 or send it interrupts.
140 * The bits have different meaning on read and write.
142 #define FATM_HCR_RESET 0x01 /* (W) reset the card */
143 #define FATM_HCR_LOCK_HOLD 0x02 /* (W) hold the i960 */
144 #define FATM_HCR_I960FAIL 0x04 /* (R) internal self-test failed */
145 #define FATM_HCR_INTR2 0x04 /* (W) assert i960 interrupt 2 */
146 #define FATM_HCR_HOLDA 0x08 /* (R) hold ack from i960 */
147 #define FATM_HCR_INTR1 0x08 /* (W) assert i960 interrupt 1 */
148 #define FATM_HCR_OFIFO 0x10 /* (R) DMA request FIFO full */
149 #define FATM_HCR_CLRIRQ 0x10 /* (W) clear interrupt request */
150 #define FATM_HCR_ESP_HOLD 0x20 /* (R) SAR chip holds i960 */
151 #define FATM_HCR_IFIFO 0x40 /* (R) input FIFO full */
152 #define FATM_HCR_TESTMODE 0x80 /* (R) board is in test mode */
155 * The mon960 area contains a virtual UART and a status word.
156 * The UART uses a simple protocol: a zero means, that there is no
157 * character available from the i960 or that one can write the next
158 * character to the i960. This character has to be ored with 0x1000000
159 * to signal to the i960 that there is a new character.
160 * The cold_start values must be written to the status word, the others
161 * denote certain stages of initializing.
164 #define CHAR_AVAIL 0x1000000
166 #define COLD_START 0xc01dc01d
167 #define SELF_TEST_OK 0x02201958
168 #define SELF_TEST_FAIL 0xadbadbad
169 #define CP_RUNNING 0xce11feed
170 #define MON906_TOO_BIG 0x10aded00
173 * The firmware communication area contains a big structure most of which
174 * is used only during initialisation.
177 * These are the offsets to the onboard queues that are valid after the
178 * initialisation command has completed.
180 #define FATMO_COMMAND_QUEUE (FATMO_COMMON_ORIGIN + 0)
181 #define FATMO_TRANSMIT_QUEUE (FATMO_COMMON_ORIGIN + 4)
182 #define FATMO_RECEIVE_QUEUE (FATMO_COMMON_ORIGIN + 8)
183 #define FATMO_SMALL_B1_QUEUE (FATMO_COMMON_ORIGIN + 12)
184 #define FATMO_LARGE_B1_QUEUE (FATMO_COMMON_ORIGIN + 16)
185 #define FATMO_SMALL_B2_QUEUE (FATMO_COMMON_ORIGIN + 20)
186 #define FATMO_LARGE_B2_QUEUE (FATMO_COMMON_ORIGIN + 24)
189 * If the interrupt mask is set to 1, interrupts to the host are queued, but
190 * inhbited. The istat variable is set, when this card has posted an interrupt.
192 #define FATMO_IMASK (FATMO_COMMON_ORIGIN + 28)
193 #define FATMO_ISTAT (FATMO_COMMON_ORIGIN + 32)
196 * This is the offset and the size of the queue area. Could be used to
197 * dynamically compute queue sizes.
199 #define FATMO_HEAP_BASE (FATMO_COMMON_ORIGIN + 36)
200 #define FATMO_HEAP_SIZE (FATMO_COMMON_ORIGIN + 40)
202 #define FATMO_HLOGGER (FATMO_COMMON_ORIGIN + 44)
205 * The heartbeat variable is incremented in each loop of the normal processing.
206 * If it is stuck this means, that the card had a fatal error. In this case
207 * it may set the word to a number of values of the form 0xdeadXXXX where
208 * XXXX is an error code.
210 #define FATMO_HEARTBEAT (FATMO_COMMON_ORIGIN + 48)
212 #define FATMO_FIRMWARE_RELEASE (FATMO_COMMON_ORIGIN + 52)
213 #define FATMO_MON960_RELEASE (FATMO_COMMON_ORIGIN + 56)
214 #define FATMO_TQ_PLEN (FATMO_COMMON_ORIGIN + 60)
217 * At this offset the init command block is located. The init command cannot
218 * use the normal queue mechanism because it is used to initialize the
219 * queues. For this reason it is located at this fixed offset.
221 #define FATMO_INIT (FATMO_COMMON_ORIGIN + 64)
224 * physical media type
226 #define FATMO_MEDIA_TYPE (FATMO_COMMON_ORIGIN + 176)
227 #define FATMO_OC3_REVISION (FATMO_COMMON_ORIGIN + 180)
230 * End of the common block
232 #define FATMO_COMMON_END (FATMO_COMMON_ORIGIN + 184)
235 * The INITIALIZE command block. This is embedded into the above common
236 * block. The offsets are from the beginning of the command block.
238 #define FATMOI_OP 0 /* operation code */
239 #define FATMOI_STATUS 4 /* status word */
240 #define FATMOI_RECEIVE_TRESHOLD 8 /* when to start interrupting */
241 #define FATMOI_NUM_CONNECT 12 /* max number of VCIs */
242 #define FATMOI_CQUEUE_LEN 16 /* length of command queue */
243 #define FATMOI_TQUEUE_LEN 20 /* length of transmit queue */
244 #define FATMOI_RQUEUE_LEN 24 /* length of receive queue */
245 #define FATMOI_RPD_EXTENSION 28 /* additional 32 byte blocks */
246 #define FATMOI_TPD_EXTENSION 32 /* additional 32 byte blocks */
247 #define FATMOI_CONLESS_VPVC 36 /* (not used) */
248 #define FATMOI_SMALL_B1 48 /* small buffer 1 pool */
249 #define FATMOI_LARGE_B1 64 /* small buffer 2 pool */
250 #define FATMOI_SMALL_B2 80 /* large buffer 1 pool */
251 #define FATMOI_LARGE_B2 96 /* large buffer 2 pool */
252 #define FATMOI_END 112 /* size of init block */
255 * Each of the four buffer schemes is initialized with a block that
256 * contains four words:
258 #define FATMOB_QUEUE_LENGTH 0 /* supply queue length */
259 #define FATMOB_BUFFER_SIZE 4 /* size of each buffer */
260 #define FATMOB_POOL_SIZE 8 /* size of on-board pool */
261 #define FATMOB_SUPPLY_BLKSIZE 12 /* number of buffers/supply */
264 * The fore firmware is a binary file, that starts with a header. The
265 * header contains the offset to where the file must be loaded and the
266 * entry for execution. The header must also be loaded onto the card!
269 uint32_t id; /* "FORE" */
270 uint32_t version; /* firmware version */
271 uint32_t offset; /* load offset */
272 uint32_t entry; /* entry point */
274 #define FATM_FWID 0x65726f66 /* "FORE" */
275 #define FATM_FWVERSION 0x100 /* supported version */
278 * PDUs to be transmitted are described by Transmit PDU Descriptors.
279 * These descriptors are held in host memory, but referenced from the ioblk
280 * member of the queue structure on the card. The card DMAs the descriptor
281 * and than gather-DMAs the PDU transmitting it on-the-fly. Tpds are variable
282 * length in blocks of 32 byte (8 words). The minimum length is one block,
283 * maximum 15. The number of blocks beyond 1 is configured during the
284 * initialisation command (tpd_extension).
285 * Each gather-DMA segment is described by a segment descriptor. The buffer
286 * address and the length must be a multiple of four.
287 * Tpd must also be 4 byte aligned.
288 * Because of the minimum length of 32 byte, the first blocks contains already
289 * 2 segement descriptors. Each extension block holds four descriptors.
292 #define SEGS_PER_BLOCK 4 /* segment descriptors per extension block */
294 uint32_t buffer; /* DMA buffer address */
295 uint32_t length; /* and length */
298 uint32_t atm_header; /* header for the transmitted cells */
299 uint32_t spec; /* PDU description */
300 uint32_t stream; /* traffic shaping word */
302 struct txseg segment[TXD_FIXED];
305 #define TDX_MKSPEC(INTR,AAL,NSEG,LEN) \
306 (((INTR) << 28) | ((AAL) << 24) | ((NSEG) << 16) | (LEN))
307 #define TDX_MKSTR(DATA,IDLE) \
308 (((DATA) << 16) | (IDLE))
309 #define TDX_MKHDR(VPI,VCI,PT,CLP) \
310 (((VPI) << 20) | ((VCI) << 4) | ((PT) << 1) | (CLP))
311 #define TDX_SEGS2BLKS(SEGS) \
312 (1 + ((SEGS)-TXD_FIXED+SEGS_PER_BLOCK-1)/SEGS_PER_BLOCK)
315 * We want probably support scatter transmission, so we use the maximum
316 * transmit descriptor extension that is possible. Because the size of the
317 * Tpd is encoded in 32-byte blocks in a 4-bit field, the maximum extension
318 * is 14 such blocks. The value for the init command is the number of
319 * additional descriptor entries NOT the number of 32 byte blocks.
321 #define TPD_EXTENSION_BLOCKS 14
322 #define TPD_EXTENSIONS (TPD_EXTENSION_BLOCKS * 4)
323 #define TPD_SIZE ((size_t)((TPD_EXTENSION_BLOCKS+1) * 32))
326 * Received PDUs are handed from the card to the host by means of Receive
327 * PDU descriptors. Each segment describes on part of the PDU. The buffer
328 * handle is a 32 bit value that is supplied by the host and passed
329 * transparently back to the host by the card. It is used to locate the buffer.
330 * The length field is the number of actual bytes in that buffer.
334 uint32_t handle; /* buffer handle */
335 uint32_t length; /* number of bytes */
340 struct rxseg segment[RXD_FIXED];
344 * PDUs received are stored in buffers supplied to the card. We use only
345 * buffer scheme 1: small buffers are normal mbuf's which can hold three
346 * cells in their default size (256 byte) and mbuf clusters which can
347 * hold 42 cells (2 kbyte).
348 * The number of receive segments can be computed from these sizes:
350 #define FATM_MAXPDU 65535
351 #define MAXPDU_CELLS ((FATM_MAXPDU+47)/48)
353 #define SMALL_BUFFER_CELLS (MHLEN/48)
354 #define LARGE_BUFFER_CELLS (MCLBYTES/48)
356 #define SMALL_BUFFER_LEN (SMALL_BUFFER_CELLS * 48)
357 #define LARGE_BUFFER_LEN (LARGE_BUFFER_CELLS * 48)
360 * The card first alloctes a small buffer and the switches to large
361 * buffers. So the number of large buffers needed to store the maximum
364 #define MAX_LARGE_BUFFERS ((MAXPDU_CELLS - SMALL_BUFFER_CELLS \
365 + LARGE_BUFFER_CELLS - 1) \
366 / LARGE_BUFFER_CELLS) \
369 * From this we get the number of extension blocks for the Rpds as:
371 #define RPD_EXTENSION_BLOCKS ((MAX_LARGE_BUFFERS + 1 - RXD_FIXED \
372 + SEGS_PER_BLOCK - 1) \
374 #define RPD_EXTENSIONS (RPD_EXTENSION_BLOCKS * 4)
375 #define RPD_SIZE ((size_t)((RPD_EXTENSION_BLOCKS+1) * 32))
378 * Buffers are supplied to the card prior receiving by the supply queues.
379 * We use two queues: scheme 1 small buffers and scheme 1 large buffers.
380 * The queues and on-card pools are initialized by the initialize command.
381 * Buffers are supplied in chunks. Each chunk can contain from 4 to 124
382 * buffers in multiples of four. The chunk sizes are configured by the
383 * initialize command. Each buffer in a chunk is described by a Receive
384 * Buffer Descriptor that is held in host memory and given as the ioblk
387 #define BSUP_BLK2SIZE(CHUNK) (8 * (CHUNK))
391 uint32_t buffer; /* DMA address for card */
395 * The PCA200E has an expansion ROM that contains version information and
396 * the FORE-assigned MAC address. It can be read via the get_prom_data
406 * The media type member of the firmware communication block contains a
407 * code that describes the physical medium and physical protocol.
409 #define FORE_MT_TAXI_100 0x04
410 #define FORE_MT_TAXI_140 0x05
411 #define FORE_MT_UTP_SONET 0x06
412 #define FORE_MT_MM_OC3_ST 0x16
413 #define FORE_MT_MM_OC3_SC 0x26
414 #define FORE_MT_SM_OC3_ST 0x36
415 #define FORE_MT_SM_OC3_SC 0x46
420 #define FORE_MAX_VCC 1024 /* max. number of VCIs supported */
421 #define FORE_VCIBITS 10
423 #define FATM_STATE_TIMEOUT 500 /* msec */
426 * Statistics as delivered by the FORE cards
430 uint32_t crc_header_errors;
431 uint32_t framing_errors;
436 uint32_t section_bip8_errors;
437 uint32_t path_bip8_errors;
438 uint32_t line_bip24_errors;
439 uint32_t line_febe_errors;
440 uint32_t path_febe_errors;
441 uint32_t corr_hcs_errors;
442 uint32_t ucorr_hcs_errors;
447 uint32_t cells_transmitted;
448 uint32_t cells_received;
449 uint32_t vpi_bad_range;
450 uint32_t vpi_no_conn;
451 uint32_t vci_bad_range;
452 uint32_t vci_no_conn;
457 uint32_t cells_transmitted;
458 uint32_t cells_received;
459 uint32_t cells_dropped;
464 uint32_t cells_transmitted;
465 uint32_t cells_received;
466 uint32_t cells_crc_errors;
467 uint32_t cels_protocol_errors;
468 uint32_t cells_dropped;
469 uint32_t cspdus_transmitted;
470 uint32_t cspdus_received;
471 uint32_t cspdus_protocol_errors;
472 uint32_t cspdus_dropped;
477 uint32_t cells_transmitted;
478 uint32_t cells_received;
479 uint32_t congestion_experienced;
480 uint32_t cells_dropped;
481 uint32_t cspdus_transmitted;
482 uint32_t cspdus_received;
483 uint32_t cspdus_crc_errors;
484 uint32_t cspdus_protocol_errors;
485 uint32_t cspdus_dropped;
490 uint32_t small_b1_failed;
491 uint32_t large_b1_failed;
492 uint32_t small_b2_failed;
493 uint32_t large_b2_failed;
494 uint32_t rpd_alloc_failed;
495 uint32_t receive_carrier;
499 #define FATM_NSTATS 42