2 * Copyright (c) 1995, 1996 Carnegie-Mellon University.
5 * Author: Chris G. Demetriou
7 * Permission to use, copy, modify and distribute this software and
8 * its documentation is hereby granted, provided that both the copyright
9 * notice and this permission notice appear in all copies of the
10 * software, derivative works or modified versions, and any portions
11 * thereof, and that both notices appear in supporting documentation.
13 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
14 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
15 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
17 * Carnegie Mellon requests users of this software to return to
19 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
20 * School of Computer Science
21 * Carnegie Mellon University
22 * Pittsburgh PA 15213-3890
24 * any improvements or extensions that they make and grant Carnegie the
25 * rights to redistribute these changes.
27 * Copyright (c) 2000 Andrew Miklic
35 /* TGA-specific FB stuff */
41 * Register definitions for the Brooktree Bt463 135MHz Monolithic
46 * Directly-accessible registers. Note the address register is
49 #define BT463_REG_ADDR_LOW 0x00 /* C1,C0 == 0,0 */
50 #define BT463_REG_ADDR_HIGH 0x01 /* C1,C0 == 0,1 */
51 #define BT463_REG_IREG_DATA 0x02 /* C1,C0 == 1,0 */
52 #define BT463_REG_CMAP_DATA 0x03 /* C1,C0 == 1,1 */
54 #define BT463_REG_MAX BT463_REG_CMAP_DATA
57 * All internal register access to the Bt463 is done indirectly via the
58 * Address Register (mapped into the host bus in a device-specific
59 * fashion). The following register definitions are in terms of
60 * their address register address values.
63 /* C1,C0 must be 1,0 */
64 #define BT463_IREG_CURSOR_COLOR_0 0x0100 /* 3 r/w cycles */
65 #define BT463_IREG_CURSOR_COLOR_1 0x0101 /* 3 r/w cycles */
66 #define BT463_IREG_ID 0x0200
67 #define BT463_IREG_COMMAND_0 0x0201
68 #define BT463_IREG_COMMAND_1 0x0202
69 #define BT463_IREG_COMMAND_2 0x0203
70 #define BT463_IREG_READ_MASK_P0_P7 0x0205
71 #define BT463_IREG_READ_MASK_P8_P15 0x0206
72 #define BT463_IREG_READ_MASK_P16_P23 0x0207
73 #define BT463_IREG_READ_MASK_P24_P27 0x0208
74 #define BT463_IREG_BLINK_MASK_P0_P7 0x0209
75 #define BT463_IREG_BLINK_MASK_P8_P15 0x020a
76 #define BT463_IREG_BLINK_MASK_P16_P23 0x020b
77 #define BT463_IREG_BLINK_MASK_P24_P27 0x020c
78 #define BT463_IREG_TEST 0x020d
79 #define BT463_IREG_INPUT_SIG 0x020e /* 2 of 3 r/w cycles */
80 #define BT463_IREG_OUTPUT_SIG 0x020f /* 3 r/w cycles */
81 #define BT463_IREG_REVISION 0x0220
82 #define BT463_IREG_WINDOW_TYPE_TABLE 0x0300 /* 3 r/w cycles */
84 #define BT463_NWTYPE_ENTRIES 0x10 /* 16 window type entries */
86 /* C1,C0 must be 1,1 */
87 #define BT463_IREG_CPALETTE_RAM 0x0000 /* 3 r/w cycles */
89 #define BT463_NCMAP_ENTRIES 0x210 /* 528 CMAP entries */
91 #define BT463_DATA_CURCMAP_CHANGED 0x01 /* cursor colormap changed */
92 #define BT463_DATA_CMAP_CHANGED 0x02 /* colormap changed */
93 #define BT463_DATA_WTYPE_CHANGED 0x04 /* window type table changed */
94 #define BT463_DATA_ALL_CHANGED 0x07
97 * Register definitions for the Brooktree Bt485A 170MHz Monolithic
98 * CMOS True-Color RAMDAC.
102 * Directly-addressed registers.
105 #define BT485_REG_PCRAM_WRADDR 0x00
106 #define BT485_REG_PALETTE 0x01
107 #define BT485_REG_PIXMASK 0x02
108 #define BT485_REG_PCRAM_RDADDR 0x03
109 #define BT485_REG_COC_WRADDR 0x04
110 #define BT485_REG_COCDATA 0x05
111 #define BT485_REG_COMMAND_0 0x06
112 #define BT485_REG_COC_RDADDR 0x07
113 #define BT485_REG_COMMAND_1 0x08
114 #define BT485_REG_COMMAND_2 0x09
115 #define BT485_REG_STATUS 0x0a
116 #define BT485_REG_EXTENDED BT485_REG_STATUS
117 #define BT485_REG_CURSOR_RAM 0x0b
118 #define BT485_REG_CURSOR_X_LOW 0x0c
119 #define BT485_REG_CURSOR_X_HIGH 0x0d
120 #define BT485_REG_CURSOR_Y_LOW 0x0e
121 #define BT485_REG_CURSOR_Y_HIGH 0x0f
123 #define BT485_REG_MAX 0x0f
125 #define BT485_IREG_STATUS 0x00
126 #define BT485_IREG_COMMAND_3 0x01
127 #define BT485_IREG_COMMAND_4 0x02
128 #define BT485_IREG_RSA 0x20
129 #define BT485_IREG_GSA 0x21
130 #define BT485_IREG_BSA 0x22
132 #define BT485_DATA_ENB_CHANGED 0x01 /* cursor enable changed */
133 #define BT485_DATA_CURCMAP_CHANGED 0x02 /* cursor colormap changed */
134 #define BT485_DATA_CURSHAPE_CHANGED 0x04 /* cursor size, image, mask changed */
135 #define BT485_DATA_CMAP_CHANGED 0x08 /* colormap changed */
136 #define BT485_DATA_ALL_CHANGED 0x0f
137 #define CURSOR_MAX_SIZE 64
139 #define TGA_DRIVER_NAME "tga"
140 #define TGA2_DRIVER_NAME "tga2"
142 #define BTWREG(sc, addr, val) \
143 sc->gfbc->ramdac_wr((sc), BT463_REG_ADDR_LOW, (addr) & 0xff); \
144 sc->gfbc->ramdac_wr((sc), BT463_REG_ADDR_HIGH, ((addr) >> 8) & 0xff);\
145 (sc)->gfbc->ramdac_wr((sc), BT463_REG_IREG_DATA, (val))
146 #define BTWNREG(sc, val) \
147 (sc)->gfbc->ramdac_wr((sc), BT463_REG_IREG_DATA, (val))
148 #define BTRREG(sc, addr) \
149 sc->gfbc->ramdac_wr((sc), BT463_REG_ADDR_LOW, (addr) & 0xff); \
150 sc->gfbc->ramdac_wr((sc), BT463_REG_ADDR_HIGH, ((addr) >> 8) & 0xff);\
151 (sc)->gfbc->ramdac_rd((sc), BT463_REG_IREG_DATA)
152 #define BTRNREG(sc) \
153 (sc)->gfbc->ramdac_rd((sc), BT463_REG_IREG_DATA)
155 #endif /* _FB_TGA_H_ */