2 * All Rights Reserved, Copyright (C) Fujitsu Limited 1995
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12 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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15 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
16 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
17 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
18 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
19 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * Registers of Fujitsu MB86960A/MB86965A series Ethernet controllers.
27 * Written and contributed by M.S. <seki@sysrap.cs.fujitsu.co.jp>
31 * Notes on register naming:
33 * Fujitsu documents for MB86960A/MB86965A uses no mnemorable names
34 * for their registers. They defined only three names for 32
35 * registers and appended numbers to distinguish registers of
36 * same name. Surprisingly, the numbers represent I/O address
37 * offsets of the registers from the base addresses, and their
38 * names correspond to the "bank" the registers are allocated.
39 * All this means that, for example, to say "read DLCR8" has no more
40 * than to say "read a register at offset 8 on bank DLCR."
42 * The following definitions may look silly, but that's what Fujitsu
43 * did, and it is necessary to know these names to read Fujitsu
47 /* Data Link Control Registrs, on invaliant port addresses. */
57 /* More DLCRs, on register bank #0. */
67 /* Malticast Address Registers. On register bank #1. */
77 /* Buffer Memory Port Registers. On register back #2. */
87 /* More BMPRs, only on 86965, accessible only when JLI mode. */
94 * Definitions of registers.
95 * I don't have Fujitsu documents of MB86960A/MB86965A, so I don't
96 * know the official names for each flags and fields. The following
97 * names are assigned by me (the author of this file,) since I cannot
98 * mnemorize hexadecimal constants for all of these functions.
101 * I've got documents from Fujitsu web site, recently. However, it's
102 * too late. Names for some fields (bits) are kept different from
103 * those used in the Fujitsu documents...
106 /* DLCR0 -- transmitter status */
107 #define FE_D0_BUSERR 0x01 /* Bus write error? */
108 #define FE_D0_COLL16 0x02 /* Collision limit (16) encountered */
109 #define FE_D0_COLLID 0x04 /* Collision on last transmission */
110 #define FE_D0_JABBER 0x08 /* Jabber */
111 #define FE_D0_CRLOST 0x10 /* Carrier lost on last transmission */
112 #define FE_D0_PKTRCD 0x20 /* Last packet looped back correctly */
113 #define FE_D0_NETBSY 0x40 /* Network Busy (Carrier Detected) */
114 #define FE_D0_TXDONE 0x80 /* Transmission complete */
116 /* DLCR1 -- receiver status */
117 #define FE_D1_OVRFLO 0x01 /* Receiver buffer overflow */
118 #define FE_D1_CRCERR 0x02 /* CRC error on last packet */
119 #define FE_D1_ALGERR 0x04 /* Alignment error on last packet */
120 #define FE_D1_SRTPKT 0x08 /* Short (RUNT) packet is received */
121 #define FE_D1_RMTRST 0x10 /* Remote reset packet (type = 0x0900) */
122 #define FE_D1_DMAEOP 0x20 /* Host asserted End of DMA OPeration */
123 #define FE_D1_BUSERR 0x40 /* Bus read error */
124 #define FE_D1_PKTRDY 0x80 /* Packet(s) ready on receive buffer */
126 /* DLCR2 -- transmitter interrupt control; same layout as DLCR0 */
127 #define FE_D2_BUSERR FE_D0_BUSERR
128 #define FE_D2_COLL16 FE_D0_COLL16
129 #define FE_D2_COLLID FE_D0_COLLID
130 #define FE_D2_JABBER FE_D0_JABBER
131 #define FE_D2_TXDONE FE_D0_TXDONE
133 #define FE_D2_RESERVED 0x70
135 /* DLCR3 -- receiver interrupt control; same layout as DLCR1 */
136 #define FE_D3_OVRFLO FE_D1_OVRFLO
137 #define FE_D3_CRCERR FE_D1_CRCERR
138 #define FE_D3_ALGERR FE_D1_ALGERR
139 #define FE_D3_SRTPKT FE_D1_SRTPKT
140 #define FE_D3_RMTRST FE_D1_RMTRST
141 #define FE_D3_DMAEOP FE_D1_DMAEOP
142 #define FE_D3_BUSERR FE_D1_BUSERR
143 #define FE_D3_PKTRDY FE_D1_PKTRDY
145 /* DLCR4 -- transmitter operation mode */
146 #define FE_D4_DSC 0x01 /* Disable carrier sense on trans. */
147 #define FE_D4_LBC 0x02 /* Loop back test control */
148 #define FE_D4_CNTRL 0x04 /* - tied to CNTRL pin of the chip */
149 #define FE_D4_TEST1 0x08 /* Test output #1 */
150 #define FE_D4_COL 0xF0 /* Collision counter */
152 #define FE_D4_LBC_ENABLE 0x00 /* Perform loop back test */
153 #define FE_D4_LBC_DISABLE 0x02 /* Normal operation */
155 #define FE_D4_COL_SHIFT 4
157 /* DLCR5 -- receiver operation mode */
158 #define FE_D5_AFM0 0x01 /* Receive packets for other stations */
159 #define FE_D5_AFM1 0x02 /* Receive packets for this station */
160 #define FE_D5_RMTRST 0x04 /* Enable remote reset operation */
161 #define FE_D5_SRTPKT 0x08 /* Accept short (RUNT) packets */
162 #define FE_D5_SRTADR 0x10 /* Short (16 bits?) MAC address */
163 #define FE_D5_BADPKT 0x20 /* Accept packets with error */
164 #define FE_D5_BUFEMP 0x40 /* Receive buffer is empty */
165 #define FE_D5_TEST2 0x80 /* Test output #2 */
167 /* DLCR6 -- hardware configuration #0 */
168 #define FE_D6_BUFSIZ 0x03 /* Size of NIC buffer SRAM */
169 #define FE_D6_TXBSIZ 0x0C /* Size (and config)of trans. buffer */
170 #define FE_D6_BBW 0x10 /* Buffer SRAM bus width */
171 #define FE_D6_SBW 0x20 /* System bus width */
172 #define FE_D6_SRAM 0x40 /* Buffer SRAM access time */
173 #define FE_D6_DLC 0x80 /* Disable DLC (recever/transmitter) */
175 #define FE_D6_BUFSIZ_8KB 0x00 /* The board has 8KB SRAM */
176 #define FE_D6_BUFSIZ_16KB 0x01 /* The board has 16KB SRAM */
177 #define FE_D6_BUFSIZ_32KB 0x02 /* The board has 32KB SRAM */
178 #define FE_D6_BUFSIZ_64KB 0x03 /* The board has 64KB SRAM */
180 #define FE_D6_TXBSIZ_1x2KB 0x00 /* Single 2KB buffer for trans. */
181 #define FE_D6_TXBSIZ_2x2KB 0x04 /* Double 2KB buffers */
182 #define FE_D6_TXBSIZ_2x4KB 0x08 /* Double 4KB buffers */
183 #define FE_D6_TXBSIZ_2x8KB 0x0C /* Double 8KB buffers */
185 #define FE_D6_BBW_WORD 0x00 /* SRAM has 16 bit data line */
186 #define FE_D6_BBW_BYTE 0x10 /* SRAM has 8 bit data line */
188 #define FE_D6_SBW_WORD 0x00 /* Access with 16 bit (AT) bus */
189 #define FE_D6_SBW_BYTE 0x20 /* Access with 8 bit (XT) bus */
191 #define FE_D6_SRAM_150ns 0x00 /* The board has slow SRAM */
192 #define FE_D6_SRAM_100ns 0x40 /* The board has fast SRAM */
194 #define FE_D6_DLC_ENABLE 0x00 /* Normal operation */
195 #define FE_D6_DLC_DISABLE 0x80 /* Stop sending/receiving */
197 /* DLC7 -- hardware configuration #1 */
198 #define FE_D7_BYTSWP 0x01 /* Host byte order control */
199 #define FE_D7_EOPPOL 0x02 /* Polarity of DMA EOP signal */
200 #define FE_D7_RBS 0x0C /* Register bank select */
201 #define FE_D7_RDYPNS 0x10 /* Senses RDYPNSEL input signal */
202 #define FE_D7_POWER 0x20 /* Stand-by (power down) mode control */
203 #define FE_D7_IDENT 0xC0 /* Chip identification */
205 #define FE_D7_BYTSWP_LH 0x00 /* DEC/Intel byte order */
206 #define FE_D7_BYTSWP_HL 0x01 /* IBM/Motorolla byte order */
208 #define FE_D7_RBS_DLCR 0x00 /* Select DLCR8-15 */
209 #define FE_D7_RBS_MAR 0x04 /* Select MAR8-15 */
210 #define FE_D7_RBS_BMPR 0x08 /* Select BMPR8-15 */
212 #define FE_D7_POWER_DOWN 0x00 /* Power down (stand-by) mode */
213 #define FE_D7_POWER_UP 0x20 /* Normal operation */
215 #define FE_D7_IDENT_TDK 0x00 /* TDK chips? */
216 #define FE_D7_IDENT_NICE 0x80 /* Fujitsu NICE (86960) */
217 #define FE_D7_IDENT_EC 0xC0 /* Fujitsu EtherCoupler (86965) */
219 /* DLCR8 thru DLCR13 are for Ethernet station address. */
221 /* DLCR14 and DLCR15 are for TDR. (TDR is used for cable diagnostic.) */
223 /* MAR8 thru MAR15 are for Multicast address filter. */
225 /* BMPR8 and BMPR9 are for packet data. */
227 /* BMPR10 -- transmitter start trigger */
228 #define FE_B10_START 0x80 /* Start transmitter */
229 #define FE_B10_COUNT 0x7F /* Packet count */
231 /* BMPR11 -- 16 collisions control */
232 #define FE_B11_CTRL 0x01 /* Skip or resend errored packets */
233 #define FE_B11_MODE1 0x02 /* Restart transmitter after COLL16 */
234 #define FE_B11_MODE2 0x04 /* Automatic restart enable */
236 #define FE_B11_CTRL_RESEND 0x00 /* Re-send the collided packet */
237 #define FE_B11_CTRL_SKIP 0x01 /* Skip the collided packet */
239 /* BMPR12 -- DMA enable */
240 #define FE_B12_TXDMA 0x01 /* Enable transmitter DMA */
241 #define FE_B12_RXDMA 0x02 /* Enable receiver DMA */
243 /* BMPR13 -- DMA control */
244 #define FE_B13_BSTCTL 0x03 /* DMA burst mode control */
245 #define FE_B13_TPTYPE 0x04 /* Twisted pair cable impedance */
246 #define FE_B13_PORT 0x18 /* Port (TP/AUI) selection */
247 #define FE_B13_LNKTST 0x20 /* Link test enable */
248 #define FE_B13_SQTHLD 0x40 /* Lower squelch threshold */
249 #define FE_B13_IOUNLK 0x80 /* Change I/O base address, on JLI mode */
251 #define FE_B13_BSTCTL_1 0x00
252 #define FE_B13_BSTCTL_4 0x01
253 #define FE_B13_BSTCTL_8 0x02
254 #define FE_B13_BSTCLT_12 0x03
256 #define FE_B13_TPTYPE_UTP 0x00 /* Unshielded (standard) cable */
257 #define FE_B13_TPTYPE_STP 0x04 /* Shielded (IBM) cable */
259 #define FE_B13_PORT_AUTO 0x00 /* Auto detected */
260 #define FE_B13_PORT_TP 0x08 /* Force TP */
261 #define FE_B13_PORT_AUI 0x18 /* Force AUI */
263 /* BMPR14 -- More receiver control and more transmission interrupts */
264 #define FE_B14_FILTER 0x01 /* Filter out self-originated packets */
265 #define FE_B14_SQE 0x02 /* SQE interrupt enable */
266 #define FE_B14_SKIP 0x04 /* Skip a received packet */
267 #define FE_B14_RJAB 0x20 /* RJAB interrupt enable */
268 #define FE_B14_LLD 0x40 /* Local-link-down interrupt enable */
269 #define FE_B14_RLD 0x80 /* Remote-link-down interrupt enable */
271 /* BMPR15 -- More transmitter status; basically same layout as BMPR14 */
272 #define FE_B15_SQE FE_B14_SQE
273 #define FE_B15_RCVPOL 0x08 /* Reversed receive line polarity */
274 #define FE_B15_RMTPRT 0x10 /* ??? */
275 #define FE_B15_RAJB FE_B14_RJAB
276 #define FE_B15_LLD FE_B14_LLD
277 #define FE_B15_RLD FE_B14_RLD
279 /* BMPR16 -- EEPROM control */
280 #define FE_B16_DOUT 0x04 /* EEPROM Data in (CPU to EEPROM) */
281 #define FE_B16_SELECT 0x20 /* EEPROM chip select */
282 #define FE_B16_CLOCK 0x40 /* EEPROM shift clock */
283 #define FE_B16_DIN 0x80 /* EEPROM data out (EEPROM to CPU) */
285 /* BMPR17 -- EEPROM data */
286 #define FE_B17_DATA 0x80 /* EEPROM data bit */
288 /* BMPR18 -- cycle I/O address setting in JLI mode */
290 /* BMPR19 -- ISA interface configuration in JLI mode */
291 #define FE_B19_IRQ 0xC0
292 #define FE_B19_IRQ_SHIFT 6
294 #define FE_B19_ROM 0x38
295 #define FE_B19_ROM_SHIFT 3
297 #define FE_B19_ADDR 0x07
298 #define FE_B19_ADDR_SHIFT 0
301 * An extra I/O port address to reset 86965. This location is called
302 * "ID ROM area" by Fujitsu document.
306 * Flags in Receive Packet Header... Basically same layout as DLCR1.
308 #define FE_RPH_OVRFLO FE_D1_OVRFLO
309 #define FE_RPH_CRCERR FE_D1_CRCERR
310 #define FE_RPH_ALGERR FE_D1_ALGERR
311 #define FE_RPH_SRTPKT FE_D1_SRTPKT
312 #define FE_RPH_RMTRST FE_D1_RMTRST
313 #define FE_RPH_GOOD 0x20 /* Good packet follows */
316 * EEPROM specification (of JLI mode).
319 /* Number of bytes in an EEPROM accessible through 86965. */
320 #define FE_EEPROM_SIZE 32
322 /* Offset for JLI config; automatically copied into BMPR19 at startup. */
323 #define FE_EEPROM_CONF 0
326 * Some 8696x specific constants.
329 /* Length (in bytes) of a Multicast Address Filter. */
330 #define FE_FILTER_LEN 8
332 /* How many packets we can put in the transmission buffer on NIC memory. */
333 #define FE_QUEUEING_MAX 127
335 /* Length (in bytes) of a "packet length" word in transmission buffer. */
336 #define FE_DATA_LEN_LEN 2
338 /* Special Multicast Address Filter value. */
339 #define FE_FILTER_NOTHING { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 }
340 #define FE_FILTER_ALL { 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF }