2 * Copyright (c) 2013 Ian Lepore <ian@freebsd.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
32 * Driver for Freescale Fast Ethernet Controller, found on imx-series SoCs among
33 * others. Also works for the ENET Gigibit controller found on imx6 and imx28,
34 * but the driver doesn't currently use any of the ENET advanced features other
35 * than enabling gigabit.
37 * The interface name 'fec' is already taken by netgraph's Fast Etherchannel
38 * (netgraph/ng_fec.c), so we use 'ffec'.
40 * Requires an FDT entry with at least these properties:
41 * fec: ethernet@02188000 {
42 * compatible = "fsl,imxNN-fec";
43 * reg = <0x02188000 0x4000>;
44 * interrupts = <150 151>;
46 * phy-disable-preamble; // optional
48 * The second interrupt number is for IEEE-1588, and is not currently used; it
49 * need not be present. phy-mode must be one of: "mii", "rmii", "rgmii".
50 * There is also an optional property, phy-disable-preamble, which if present
51 * will disable the preamble bits, cutting the size of each mdio transaction
52 * (and thus the busy-wait time) in half.
55 #include <sys/param.h>
56 #include <sys/systm.h>
58 #include <sys/endian.h>
59 #include <sys/kernel.h>
61 #include <sys/malloc.h>
63 #include <sys/module.h>
64 #include <sys/mutex.h>
66 #include <sys/socket.h>
67 #include <sys/sockio.h>
68 #include <sys/sysctl.h>
70 #include <machine/bus.h>
74 #include <net/ethernet.h>
75 #include <net/if_dl.h>
76 #include <net/if_media.h>
77 #include <net/if_types.h>
78 #include <net/if_var.h>
79 #include <net/if_vlan_var.h>
81 #include <dev/fdt/fdt_common.h>
82 #include <dev/ffec/if_ffecreg.h>
83 #include <dev/ofw/ofw_bus.h>
84 #include <dev/ofw/ofw_bus_subr.h>
85 #include <dev/mii/mii.h>
86 #include <dev/mii/miivar.h>
87 #include <dev/mii/mii_fdt.h>
88 #include "miibus_if.h"
91 * There are small differences in the hardware on various SoCs. Not every SoC
92 * we support has its own FECTYPE; most work as GENERIC and only the ones that
93 * need different handling get their own entry. In addition to the types in
94 * this list, there are some flags below that can be ORed into the upper bits.
100 FECTYPE_IMX6, /* imx6 and imx7 */
105 * Flags that describe general differences between the FEC hardware in various
106 * SoCs. These are ORed into the FECTYPE enum values.
108 #define FECTYPE_MASK 0x0000ffff
109 #define FECFLAG_GBE (1 << 16)
110 #define FECFLAG_AVB (1 << 17)
113 * Table of supported FDT compat strings and their associated FECTYPE values.
115 static struct ofw_compat_data compat_data[] = {
116 {"fsl,imx51-fec", FECTYPE_GENERIC},
117 {"fsl,imx53-fec", FECTYPE_IMX53},
118 {"fsl,imx6q-fec", FECTYPE_IMX6 | FECFLAG_GBE},
119 {"fsl,imx6ul-fec", FECTYPE_IMX6},
120 {"fsl,imx7d-fec", FECTYPE_IMX6 | FECFLAG_GBE | FECFLAG_AVB},
121 {"fsl,mvf600-fec", FECTYPE_MVF},
122 {"fsl,mvf-fec", FECTYPE_MVF},
123 {NULL, FECTYPE_NONE},
127 * Driver data and defines.
129 #define RX_DESC_COUNT 64
130 #define RX_DESC_SIZE (sizeof(struct ffec_hwdesc) * RX_DESC_COUNT)
131 #define TX_DESC_COUNT 64
132 #define TX_DESC_SIZE (sizeof(struct ffec_hwdesc) * TX_DESC_COUNT)
134 #define WATCHDOG_TIMEOUT_SECS 5
144 struct mii_data * mii_softc;
148 struct resource *irq_res;
149 struct resource *mem_res;
151 struct callout ffec_callout;
152 mii_contype_t phy_conn_type;
154 boolean_t link_is_up;
155 boolean_t is_attached;
156 boolean_t is_detaching;
157 int tx_watchdog_count;
161 bus_dma_tag_t rxdesc_tag;
162 bus_dmamap_t rxdesc_map;
163 struct ffec_hwdesc *rxdesc_ring;
164 bus_addr_t rxdesc_ring_paddr;
165 bus_dma_tag_t rxbuf_tag;
166 struct ffec_bufmap rxbuf_map[RX_DESC_COUNT];
169 bus_dma_tag_t txdesc_tag;
170 bus_dmamap_t txdesc_map;
171 struct ffec_hwdesc *txdesc_ring;
172 bus_addr_t txdesc_ring_paddr;
173 bus_dma_tag_t txbuf_tag;
174 struct ffec_bufmap txbuf_map[TX_DESC_COUNT];
175 uint32_t tx_idx_head;
176 uint32_t tx_idx_tail;
180 #define FFEC_LOCK(sc) mtx_lock(&(sc)->mtx)
181 #define FFEC_UNLOCK(sc) mtx_unlock(&(sc)->mtx)
182 #define FFEC_LOCK_INIT(sc) mtx_init(&(sc)->mtx, \
183 device_get_nameunit((sc)->dev), MTX_NETWORK_LOCK, MTX_DEF)
184 #define FFEC_LOCK_DESTROY(sc) mtx_destroy(&(sc)->mtx);
185 #define FFEC_ASSERT_LOCKED(sc) mtx_assert(&(sc)->mtx, MA_OWNED);
186 #define FFEC_ASSERT_UNLOCKED(sc) mtx_assert(&(sc)->mtx, MA_NOTOWNED);
188 static void ffec_init_locked(struct ffec_softc *sc);
189 static void ffec_stop_locked(struct ffec_softc *sc);
190 static void ffec_txstart_locked(struct ffec_softc *sc);
191 static void ffec_txfinish_locked(struct ffec_softc *sc);
193 static inline uint16_t
194 RD2(struct ffec_softc *sc, bus_size_t off)
197 return (bus_read_2(sc->mem_res, off));
201 WR2(struct ffec_softc *sc, bus_size_t off, uint16_t val)
204 bus_write_2(sc->mem_res, off, val);
207 static inline uint32_t
208 RD4(struct ffec_softc *sc, bus_size_t off)
211 return (bus_read_4(sc->mem_res, off));
215 WR4(struct ffec_softc *sc, bus_size_t off, uint32_t val)
218 bus_write_4(sc->mem_res, off, val);
221 static inline uint32_t
222 next_rxidx(struct ffec_softc *sc, uint32_t curidx)
225 return ((curidx == RX_DESC_COUNT - 1) ? 0 : curidx + 1);
228 static inline uint32_t
229 next_txidx(struct ffec_softc *sc, uint32_t curidx)
232 return ((curidx == TX_DESC_COUNT - 1) ? 0 : curidx + 1);
236 ffec_get1paddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
241 *(bus_addr_t *)arg = segs[0].ds_addr;
245 ffec_miigasket_setup(struct ffec_softc *sc)
250 * We only need the gasket for MII and RMII connections on certain SoCs.
253 switch (sc->fectype & FECTYPE_MASK)
261 switch (sc->phy_conn_type)
263 case MII_CONTYPE_MII:
266 case MII_CONTYPE_RMII:
267 ifmode = FEC_MIIGSK_CFGR_IF_MODE_RMII;
274 * Disable the gasket, configure for either MII or RMII, then enable.
277 WR2(sc, FEC_MIIGSK_ENR, 0);
278 while (RD2(sc, FEC_MIIGSK_ENR) & FEC_MIIGSK_ENR_READY)
281 WR2(sc, FEC_MIIGSK_CFGR, ifmode);
283 WR2(sc, FEC_MIIGSK_ENR, FEC_MIIGSK_ENR_EN);
284 while (!(RD2(sc, FEC_MIIGSK_ENR) & FEC_MIIGSK_ENR_READY))
289 ffec_miibus_iowait(struct ffec_softc *sc)
293 for (timeout = 10000; timeout != 0; --timeout)
294 if (RD4(sc, FEC_IER_REG) & FEC_IER_MII)
301 ffec_miibus_readreg(device_t dev, int phy, int reg)
303 struct ffec_softc *sc;
306 sc = device_get_softc(dev);
308 WR4(sc, FEC_IER_REG, FEC_IER_MII);
310 WR4(sc, FEC_MMFR_REG, FEC_MMFR_OP_READ |
311 FEC_MMFR_ST_VALUE | FEC_MMFR_TA_VALUE |
312 ((phy << FEC_MMFR_PA_SHIFT) & FEC_MMFR_PA_MASK) |
313 ((reg << FEC_MMFR_RA_SHIFT) & FEC_MMFR_RA_MASK));
315 if (!ffec_miibus_iowait(sc)) {
316 device_printf(dev, "timeout waiting for mii read\n");
317 return (-1); /* All-ones is a symptom of bad mdio. */
320 val = RD4(sc, FEC_MMFR_REG) & FEC_MMFR_DATA_MASK;
326 ffec_miibus_writereg(device_t dev, int phy, int reg, int val)
328 struct ffec_softc *sc;
330 sc = device_get_softc(dev);
332 WR4(sc, FEC_IER_REG, FEC_IER_MII);
334 WR4(sc, FEC_MMFR_REG, FEC_MMFR_OP_WRITE |
335 FEC_MMFR_ST_VALUE | FEC_MMFR_TA_VALUE |
336 ((phy << FEC_MMFR_PA_SHIFT) & FEC_MMFR_PA_MASK) |
337 ((reg << FEC_MMFR_RA_SHIFT) & FEC_MMFR_RA_MASK) |
338 (val & FEC_MMFR_DATA_MASK));
340 if (!ffec_miibus_iowait(sc)) {
341 device_printf(dev, "timeout waiting for mii write\n");
349 ffec_miibus_statchg(device_t dev)
351 struct ffec_softc *sc;
352 struct mii_data *mii;
353 uint32_t ecr, rcr, tcr;
356 * Called by the MII bus driver when the PHY establishes link to set the
357 * MAC interface registers.
360 sc = device_get_softc(dev);
362 FFEC_ASSERT_LOCKED(sc);
366 if (mii->mii_media_status & IFM_ACTIVE)
367 sc->link_is_up = true;
369 sc->link_is_up = false;
371 ecr = RD4(sc, FEC_ECR_REG) & ~FEC_ECR_SPEED;
372 rcr = RD4(sc, FEC_RCR_REG) & ~(FEC_RCR_RMII_10T | FEC_RCR_RMII_MODE |
373 FEC_RCR_RGMII_EN | FEC_RCR_DRT | FEC_RCR_FCE);
374 tcr = RD4(sc, FEC_TCR_REG) & ~FEC_TCR_FDEN;
376 rcr |= FEC_RCR_MII_MODE; /* Must always be on even for R[G]MII. */
377 switch (sc->phy_conn_type) {
378 case MII_CONTYPE_RMII:
379 rcr |= FEC_RCR_RMII_MODE;
381 case MII_CONTYPE_RGMII:
382 case MII_CONTYPE_RGMII_ID:
383 case MII_CONTYPE_RGMII_RXID:
384 case MII_CONTYPE_RGMII_TXID:
385 rcr |= FEC_RCR_RGMII_EN;
391 switch (IFM_SUBTYPE(mii->mii_media_active)) {
394 ecr |= FEC_ECR_SPEED;
397 /* Not-FEC_ECR_SPEED + not-FEC_RCR_RMII_10T means 100TX */
400 rcr |= FEC_RCR_RMII_10T;
403 sc->link_is_up = false;
406 sc->link_is_up = false;
407 device_printf(dev, "Unsupported media %u\n",
408 IFM_SUBTYPE(mii->mii_media_active));
412 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0)
417 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FLOW) != 0)
420 WR4(sc, FEC_RCR_REG, rcr);
421 WR4(sc, FEC_TCR_REG, tcr);
422 WR4(sc, FEC_ECR_REG, ecr);
426 ffec_media_status(struct ifnet * ifp, struct ifmediareq *ifmr)
428 struct ffec_softc *sc;
429 struct mii_data *mii;
436 ifmr->ifm_active = mii->mii_media_active;
437 ifmr->ifm_status = mii->mii_media_status;
442 ffec_media_change_locked(struct ffec_softc *sc)
445 return (mii_mediachg(sc->mii_softc));
449 ffec_media_change(struct ifnet * ifp)
451 struct ffec_softc *sc;
457 error = ffec_media_change_locked(sc);
462 static void ffec_clear_stats(struct ffec_softc *sc)
466 mibc = RD4(sc, FEC_MIBC_REG);
469 * On newer hardware the statistic regs are cleared by toggling a bit in
470 * the mib control register. On older hardware the clear procedure is
471 * to disable statistics collection, zero the regs, then re-enable.
473 if (sc->fectype == FECTYPE_IMX6 || sc->fectype == FECTYPE_MVF) {
474 WR4(sc, FEC_MIBC_REG, mibc | FEC_MIBC_CLEAR);
475 WR4(sc, FEC_MIBC_REG, mibc & ~FEC_MIBC_CLEAR);
477 WR4(sc, FEC_MIBC_REG, mibc | FEC_MIBC_DIS);
479 WR4(sc, FEC_IEEE_R_DROP, 0);
480 WR4(sc, FEC_IEEE_R_MACERR, 0);
481 WR4(sc, FEC_RMON_R_CRC_ALIGN, 0);
482 WR4(sc, FEC_RMON_R_FRAG, 0);
483 WR4(sc, FEC_RMON_R_JAB, 0);
484 WR4(sc, FEC_RMON_R_MC_PKT, 0);
485 WR4(sc, FEC_RMON_R_OVERSIZE, 0);
486 WR4(sc, FEC_RMON_R_PACKETS, 0);
487 WR4(sc, FEC_RMON_R_UNDERSIZE, 0);
488 WR4(sc, FEC_RMON_T_COL, 0);
489 WR4(sc, FEC_RMON_T_CRC_ALIGN, 0);
490 WR4(sc, FEC_RMON_T_FRAG, 0);
491 WR4(sc, FEC_RMON_T_JAB, 0);
492 WR4(sc, FEC_RMON_T_MC_PKT, 0);
493 WR4(sc, FEC_RMON_T_OVERSIZE , 0);
494 WR4(sc, FEC_RMON_T_PACKETS, 0);
495 WR4(sc, FEC_RMON_T_UNDERSIZE, 0);
497 WR4(sc, FEC_MIBC_REG, mibc);
502 ffec_harvest_stats(struct ffec_softc *sc)
509 * - FEC_IEEE_R_DROP is "dropped due to invalid start frame delimiter"
510 * so it's really just another type of input error.
511 * - FEC_IEEE_R_MACERR is "no receive fifo space"; count as input drops.
513 if_inc_counter(ifp, IFCOUNTER_IPACKETS, RD4(sc, FEC_RMON_R_PACKETS));
514 if_inc_counter(ifp, IFCOUNTER_IMCASTS, RD4(sc, FEC_RMON_R_MC_PKT));
515 if_inc_counter(ifp, IFCOUNTER_IERRORS,
516 RD4(sc, FEC_RMON_R_CRC_ALIGN) + RD4(sc, FEC_RMON_R_UNDERSIZE) +
517 RD4(sc, FEC_RMON_R_OVERSIZE) + RD4(sc, FEC_RMON_R_FRAG) +
518 RD4(sc, FEC_RMON_R_JAB) + RD4(sc, FEC_IEEE_R_DROP));
520 if_inc_counter(ifp, IFCOUNTER_IQDROPS, RD4(sc, FEC_IEEE_R_MACERR));
522 if_inc_counter(ifp, IFCOUNTER_OPACKETS, RD4(sc, FEC_RMON_T_PACKETS));
523 if_inc_counter(ifp, IFCOUNTER_OMCASTS, RD4(sc, FEC_RMON_T_MC_PKT));
524 if_inc_counter(ifp, IFCOUNTER_OERRORS,
525 RD4(sc, FEC_RMON_T_CRC_ALIGN) + RD4(sc, FEC_RMON_T_UNDERSIZE) +
526 RD4(sc, FEC_RMON_T_OVERSIZE) + RD4(sc, FEC_RMON_T_FRAG) +
527 RD4(sc, FEC_RMON_T_JAB));
529 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, RD4(sc, FEC_RMON_T_COL));
531 ffec_clear_stats(sc);
537 struct ffec_softc *sc;
543 FFEC_ASSERT_LOCKED(sc);
547 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING))
551 * Typical tx watchdog. If this fires it indicates that we enqueued
552 * packets for output and never got a txdone interrupt for them. Maybe
553 * it's a missed interrupt somehow, just pretend we got one.
555 if (sc->tx_watchdog_count > 0) {
556 if (--sc->tx_watchdog_count == 0) {
557 ffec_txfinish_locked(sc);
561 /* Gather stats from hardware counters. */
562 ffec_harvest_stats(sc);
564 /* Check the media status. */
565 link_was_up = sc->link_is_up;
566 mii_tick(sc->mii_softc);
567 if (sc->link_is_up && !link_was_up)
568 ffec_txstart_locked(sc);
570 /* Schedule another check one second from now. */
571 callout_reset(&sc->ffec_callout, hz, ffec_tick, sc);
574 inline static uint32_t
575 ffec_setup_txdesc(struct ffec_softc *sc, int idx, bus_addr_t paddr,
581 nidx = next_txidx(sc, idx);
583 /* Addr/len 0 means we're clearing the descriptor after xmit done. */
584 if (paddr == 0 || len == 0) {
588 flags = FEC_TXDESC_READY | FEC_TXDESC_L | FEC_TXDESC_TC;
592 flags |= FEC_TXDESC_WRAP;
595 * The hardware requires 32-bit physical addresses. We set up the dma
596 * tag to indicate that, so the cast to uint32_t should never lose
599 sc->txdesc_ring[idx].buf_paddr = (uint32_t)paddr;
600 sc->txdesc_ring[idx].flags_len = flags | len; /* Must be set last! */
606 ffec_setup_txbuf(struct ffec_softc *sc, int idx, struct mbuf **mp)
610 struct bus_dma_segment seg;
612 if ((m = m_defrag(*mp, M_NOWAIT)) == NULL)
616 error = bus_dmamap_load_mbuf_sg(sc->txbuf_tag, sc->txbuf_map[idx].map,
621 bus_dmamap_sync(sc->txbuf_tag, sc->txbuf_map[idx].map,
622 BUS_DMASYNC_PREWRITE);
624 sc->txbuf_map[idx].mbuf = m;
625 ffec_setup_txdesc(sc, idx, seg.ds_addr, seg.ds_len);
632 ffec_txstart_locked(struct ffec_softc *sc)
638 FFEC_ASSERT_LOCKED(sc);
645 if (ifp->if_drv_flags & IFF_DRV_OACTIVE)
651 if (sc->txcount == (TX_DESC_COUNT-1)) {
652 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
655 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
658 if (ffec_setup_txbuf(sc, sc->tx_idx_head, &m) != 0) {
659 IFQ_DRV_PREPEND(&ifp->if_snd, m);
663 sc->tx_idx_head = next_txidx(sc, sc->tx_idx_head);
668 bus_dmamap_sync(sc->txdesc_tag, sc->txdesc_map, BUS_DMASYNC_PREWRITE);
669 WR4(sc, FEC_TDAR_REG, FEC_TDAR_TDAR);
670 bus_dmamap_sync(sc->txdesc_tag, sc->txdesc_map, BUS_DMASYNC_POSTWRITE);
671 sc->tx_watchdog_count = WATCHDOG_TIMEOUT_SECS;
676 ffec_txstart(struct ifnet *ifp)
678 struct ffec_softc *sc = ifp->if_softc;
681 ffec_txstart_locked(sc);
686 ffec_txfinish_locked(struct ffec_softc *sc)
689 struct ffec_hwdesc *desc;
690 struct ffec_bufmap *bmap;
691 boolean_t retired_buffer;
693 FFEC_ASSERT_LOCKED(sc);
695 /* XXX Can't set PRE|POST right now, but we need both. */
696 bus_dmamap_sync(sc->txdesc_tag, sc->txdesc_map, BUS_DMASYNC_PREREAD);
697 bus_dmamap_sync(sc->txdesc_tag, sc->txdesc_map, BUS_DMASYNC_POSTREAD);
699 retired_buffer = false;
700 while (sc->tx_idx_tail != sc->tx_idx_head) {
701 desc = &sc->txdesc_ring[sc->tx_idx_tail];
702 if (desc->flags_len & FEC_TXDESC_READY)
704 retired_buffer = true;
705 bmap = &sc->txbuf_map[sc->tx_idx_tail];
706 bus_dmamap_sync(sc->txbuf_tag, bmap->map,
707 BUS_DMASYNC_POSTWRITE);
708 bus_dmamap_unload(sc->txbuf_tag, bmap->map);
711 ffec_setup_txdesc(sc, sc->tx_idx_tail, 0, 0);
712 sc->tx_idx_tail = next_txidx(sc, sc->tx_idx_tail);
716 * If we retired any buffers, there will be open tx slots available in
717 * the descriptor ring, go try to start some new output.
719 if (retired_buffer) {
720 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
721 ffec_txstart_locked(sc);
724 /* If there are no buffers outstanding, muzzle the watchdog. */
725 if (sc->tx_idx_tail == sc->tx_idx_head) {
726 sc->tx_watchdog_count = 0;
730 inline static uint32_t
731 ffec_setup_rxdesc(struct ffec_softc *sc, int idx, bus_addr_t paddr)
736 * The hardware requires 32-bit physical addresses. We set up the dma
737 * tag to indicate that, so the cast to uint32_t should never lose
740 nidx = next_rxidx(sc, idx);
741 sc->rxdesc_ring[idx].buf_paddr = (uint32_t)paddr;
742 sc->rxdesc_ring[idx].flags_len = FEC_RXDESC_EMPTY |
743 ((nidx == 0) ? FEC_RXDESC_WRAP : 0);
749 ffec_setup_rxbuf(struct ffec_softc *sc, int idx, struct mbuf * m)
752 struct bus_dma_segment seg;
755 * We need to leave at least ETHER_ALIGN bytes free at the beginning of
756 * the buffer to allow the data to be re-aligned after receiving it (by
757 * copying it backwards ETHER_ALIGN bytes in the same buffer). We also
758 * have to ensure that the beginning of the buffer is aligned to the
759 * hardware's requirements.
761 m_adj(m, roundup(ETHER_ALIGN, sc->rxbuf_align));
763 error = bus_dmamap_load_mbuf_sg(sc->rxbuf_tag, sc->rxbuf_map[idx].map,
769 bus_dmamap_sync(sc->rxbuf_tag, sc->rxbuf_map[idx].map,
770 BUS_DMASYNC_PREREAD);
772 sc->rxbuf_map[idx].mbuf = m;
773 ffec_setup_rxdesc(sc, idx, seg.ds_addr);
779 ffec_alloc_mbufcl(struct ffec_softc *sc)
783 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
784 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size;
790 ffec_rxfinish_onebuf(struct ffec_softc *sc, int len)
792 struct mbuf *m, *newmbuf;
793 struct ffec_bufmap *bmap;
798 * First try to get a new mbuf to plug into this slot in the rx ring.
799 * If that fails, drop the current packet and recycle the current
800 * mbuf, which is still mapped and loaded.
802 if ((newmbuf = ffec_alloc_mbufcl(sc)) == NULL) {
803 if_inc_counter(sc->ifp, IFCOUNTER_IQDROPS, 1);
804 ffec_setup_rxdesc(sc, sc->rx_idx,
805 sc->rxdesc_ring[sc->rx_idx].buf_paddr);
810 * Unfortunately, the protocol headers need to be aligned on a 32-bit
811 * boundary for the upper layers. The hardware requires receive
812 * buffers to be 16-byte aligned. The ethernet header is 14 bytes,
813 * leaving the protocol header unaligned. We used m_adj() after
814 * allocating the buffer to leave empty space at the start of the
815 * buffer, now we'll use the alignment agnostic bcopy() routine to
816 * shuffle all the data backwards 2 bytes and adjust m_data.
818 * XXX imx6 hardware is able to do this 2-byte alignment by setting the
819 * SHIFT16 bit in the RACC register. Older hardware doesn't have that
820 * feature, but for them could we speed this up by copying just the
821 * protocol headers into their own small mbuf then chaining the cluster
822 * to it? That way we'd only need to copy like 64 bytes or whatever
823 * the biggest header is, instead of the whole 1530ish-byte frame.
828 bmap = &sc->rxbuf_map[sc->rx_idx];
829 len -= ETHER_CRC_LEN;
830 bus_dmamap_sync(sc->rxbuf_tag, bmap->map, BUS_DMASYNC_POSTREAD);
831 bus_dmamap_unload(sc->rxbuf_tag, bmap->map);
835 m->m_pkthdr.len = len;
836 m->m_pkthdr.rcvif = sc->ifp;
838 src = mtod(m, uint8_t*);
839 dst = src - ETHER_ALIGN;
840 bcopy(src, dst, len);
842 sc->ifp->if_input(sc->ifp, m);
846 if ((error = ffec_setup_rxbuf(sc, sc->rx_idx, newmbuf)) != 0) {
847 device_printf(sc->dev, "ffec_setup_rxbuf error %d\n", error);
848 /* XXX Now what? We've got a hole in the rx ring. */
854 ffec_rxfinish_locked(struct ffec_softc *sc)
856 struct ffec_hwdesc *desc;
858 boolean_t produced_empty_buffer;
860 FFEC_ASSERT_LOCKED(sc);
862 /* XXX Can't set PRE|POST right now, but we need both. */
863 bus_dmamap_sync(sc->rxdesc_tag, sc->rxdesc_map, BUS_DMASYNC_PREREAD);
864 bus_dmamap_sync(sc->rxdesc_tag, sc->rxdesc_map, BUS_DMASYNC_POSTREAD);
865 produced_empty_buffer = false;
867 desc = &sc->rxdesc_ring[sc->rx_idx];
868 if (desc->flags_len & FEC_RXDESC_EMPTY)
870 produced_empty_buffer = true;
871 len = (desc->flags_len & FEC_RXDESC_LEN_MASK);
874 * Just recycle the descriptor and continue. .
876 ffec_setup_rxdesc(sc, sc->rx_idx,
877 sc->rxdesc_ring[sc->rx_idx].buf_paddr);
878 } else if ((desc->flags_len & FEC_RXDESC_L) == 0) {
880 * The entire frame is not in this buffer. Impossible.
881 * Recycle the descriptor and continue.
883 * XXX what's the right way to handle this? Probably we
884 * should stop/init the hardware because this should
885 * just really never happen when we have buffers bigger
886 * than the maximum frame size.
888 device_printf(sc->dev,
889 "fec_rxfinish: received frame without LAST bit set");
890 ffec_setup_rxdesc(sc, sc->rx_idx,
891 sc->rxdesc_ring[sc->rx_idx].buf_paddr);
892 } else if (desc->flags_len & FEC_RXDESC_ERROR_BITS) {
894 * Something went wrong with receiving the frame, we
895 * don't care what (the hardware has counted the error
896 * in the stats registers already), we just reuse the
897 * same mbuf, which is still dma-mapped, by resetting
900 ffec_setup_rxdesc(sc, sc->rx_idx,
901 sc->rxdesc_ring[sc->rx_idx].buf_paddr);
904 * Normal case: a good frame all in one buffer.
906 ffec_rxfinish_onebuf(sc, len);
908 sc->rx_idx = next_rxidx(sc, sc->rx_idx);
911 if (produced_empty_buffer) {
912 bus_dmamap_sync(sc->rxdesc_tag, sc->rxdesc_map, BUS_DMASYNC_PREWRITE);
913 WR4(sc, FEC_RDAR_REG, FEC_RDAR_RDAR);
914 bus_dmamap_sync(sc->rxdesc_tag, sc->rxdesc_map, BUS_DMASYNC_POSTWRITE);
919 ffec_get_hwaddr(struct ffec_softc *sc, uint8_t *hwaddr)
921 uint32_t palr, paur, rnd;
924 * Try to recover a MAC address from the running hardware. If there's
925 * something non-zero there, assume the bootloader did the right thing
928 * Otherwise, set the address to a convenient locally assigned address,
929 * 'bsd' + random 24 low-order bits. 'b' is 0x62, which has the locally
930 * assigned bit set, and the broadcast/multicast bit clear.
932 palr = RD4(sc, FEC_PALR_REG);
933 paur = RD4(sc, FEC_PAUR_REG) & FEC_PAUR_PADDR2_MASK;
934 if ((palr | paur) != 0) {
935 hwaddr[0] = palr >> 24;
936 hwaddr[1] = palr >> 16;
937 hwaddr[2] = palr >> 8;
938 hwaddr[3] = palr >> 0;
939 hwaddr[4] = paur >> 24;
940 hwaddr[5] = paur >> 16;
942 rnd = arc4random() & 0x00ffffff;
946 hwaddr[3] = rnd >> 16;
947 hwaddr[4] = rnd >> 8;
948 hwaddr[5] = rnd >> 0;
952 device_printf(sc->dev,
953 "MAC address %02x:%02x:%02x:%02x:%02x:%02x:\n",
954 hwaddr[0], hwaddr[1], hwaddr[2],
955 hwaddr[3], hwaddr[4], hwaddr[5]);
960 ffec_setup_rxfilter(struct ffec_softc *sc)
963 struct ifmultiaddr *ifma;
966 uint64_t ghash, ihash;
968 FFEC_ASSERT_LOCKED(sc);
973 * Set the multicast (group) filter hash.
975 if ((ifp->if_flags & IFF_ALLMULTI))
976 ghash = 0xffffffffffffffffLLU;
980 TAILQ_FOREACH(ifma, &sc->ifp->if_multiaddrs, ifma_link) {
981 if (ifma->ifma_addr->sa_family != AF_LINK)
983 /* 6 bits from MSB in LE CRC32 are used for hash. */
984 crc = ether_crc32_le(LLADDR((struct sockaddr_dl *)
985 ifma->ifma_addr), ETHER_ADDR_LEN);
986 ghash |= 1LLU << (((uint8_t *)&crc)[3] >> 2);
988 if_maddr_runlock(ifp);
990 WR4(sc, FEC_GAUR_REG, (uint32_t)(ghash >> 32));
991 WR4(sc, FEC_GALR_REG, (uint32_t)ghash);
994 * Set the individual address filter hash.
996 * XXX Is 0 the right value when promiscuous is off? This hw feature
997 * seems to support the concept of MAC address aliases, does such a
1000 if ((ifp->if_flags & IFF_PROMISC))
1001 ihash = 0xffffffffffffffffLLU;
1005 WR4(sc, FEC_IAUR_REG, (uint32_t)(ihash >> 32));
1006 WR4(sc, FEC_IALR_REG, (uint32_t)ihash);
1009 * Set the primary address.
1011 eaddr = IF_LLADDR(ifp);
1012 WR4(sc, FEC_PALR_REG, (eaddr[0] << 24) | (eaddr[1] << 16) |
1013 (eaddr[2] << 8) | eaddr[3]);
1014 WR4(sc, FEC_PAUR_REG, (eaddr[4] << 24) | (eaddr[5] << 16));
1018 ffec_stop_locked(struct ffec_softc *sc)
1021 struct ffec_hwdesc *desc;
1022 struct ffec_bufmap *bmap;
1025 FFEC_ASSERT_LOCKED(sc);
1028 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1029 sc->tx_watchdog_count = 0;
1032 * Stop the hardware, mask all interrupts, and clear all current
1033 * interrupt status bits.
1035 WR4(sc, FEC_ECR_REG, RD4(sc, FEC_ECR_REG) & ~FEC_ECR_ETHEREN);
1036 WR4(sc, FEC_IEM_REG, 0x00000000);
1037 WR4(sc, FEC_IER_REG, 0xffffffff);
1040 * Stop the media-check callout. Do not use callout_drain() because
1041 * we're holding a mutex the callout acquires, and if it's currently
1042 * waiting to acquire it, we'd deadlock. If it is waiting now, the
1043 * ffec_tick() routine will return without doing anything when it sees
1044 * that IFF_DRV_RUNNING is not set, so avoiding callout_drain() is safe.
1046 callout_stop(&sc->ffec_callout);
1049 * Discard all untransmitted buffers. Each buffer is simply freed;
1050 * it's as if the bits were transmitted and then lost on the wire.
1052 * XXX Is this right? Or should we use IFQ_DRV_PREPEND() to put them
1053 * back on the queue for when we get restarted later?
1055 idx = sc->tx_idx_tail;
1056 while (idx != sc->tx_idx_head) {
1057 desc = &sc->txdesc_ring[idx];
1058 bmap = &sc->txbuf_map[idx];
1059 if (desc->buf_paddr != 0) {
1060 bus_dmamap_unload(sc->txbuf_tag, bmap->map);
1061 m_freem(bmap->mbuf);
1063 ffec_setup_txdesc(sc, idx, 0, 0);
1065 idx = next_txidx(sc, idx);
1069 * Discard all unprocessed receive buffers. This amounts to just
1070 * pretending that nothing ever got received into them. We reuse the
1071 * mbuf already mapped for each desc, simply turning the EMPTY flags
1072 * back on so they'll get reused when we start up again.
1074 for (idx = 0; idx < RX_DESC_COUNT; ++idx) {
1075 desc = &sc->rxdesc_ring[idx];
1076 ffec_setup_rxdesc(sc, idx, desc->buf_paddr);
1081 ffec_init_locked(struct ffec_softc *sc)
1083 struct ifnet *ifp = sc->ifp;
1084 uint32_t maxbuf, maxfl, regval;
1086 FFEC_ASSERT_LOCKED(sc);
1089 * The hardware has a limit of 0x7ff as the max frame length (see
1090 * comments for MRBR below), and we use mbuf clusters as receive
1091 * buffers, and we currently are designed to receive an entire frame
1092 * into a single buffer.
1094 * We start with a MCLBYTES-sized cluster, but we have to offset into
1095 * the buffer by ETHER_ALIGN to make room for post-receive re-alignment,
1096 * and then that value has to be rounded up to the hardware's DMA
1097 * alignment requirements, so all in all our buffer is that much smaller
1100 * The resulting value is used as the frame truncation length and the
1101 * max buffer receive buffer size for now. It'll become more complex
1102 * when we support jumbo frames and receiving fragments of them into
1105 maxbuf = MCLBYTES - roundup(ETHER_ALIGN, sc->rxbuf_align);
1106 maxfl = min(maxbuf, 0x7ff);
1108 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1111 /* Mask all interrupts and clear all current interrupt status bits. */
1112 WR4(sc, FEC_IEM_REG, 0x00000000);
1113 WR4(sc, FEC_IER_REG, 0xffffffff);
1116 * Go set up palr/puar, galr/gaur, ialr/iaur.
1118 ffec_setup_rxfilter(sc);
1121 * TFWR - Transmit FIFO watermark register.
1123 * Set the transmit fifo watermark register to "store and forward" mode
1124 * and also set a threshold of 128 bytes in the fifo before transmission
1125 * of a frame begins (to avoid dma underruns). Recent FEC hardware
1126 * supports STRFWD and when that bit is set, the watermark level in the
1127 * low bits is ignored. Older hardware doesn't have STRFWD, but writing
1128 * to that bit is innocuous, and the TWFR bits get used instead.
1130 WR4(sc, FEC_TFWR_REG, FEC_TFWR_STRFWD | FEC_TFWR_TWFR_128BYTE);
1132 /* RCR - Receive control register.
1134 * Set max frame length + clean out anything left from u-boot.
1136 WR4(sc, FEC_RCR_REG, (maxfl << FEC_RCR_MAX_FL_SHIFT));
1139 * TCR - Transmit control register.
1141 * Clean out anything left from u-boot. Any necessary values are set in
1142 * ffec_miibus_statchg() based on the media type.
1144 WR4(sc, FEC_TCR_REG, 0);
1147 * OPD - Opcode/pause duration.
1149 * XXX These magic numbers come from u-boot.
1151 WR4(sc, FEC_OPD_REG, 0x00010020);
1154 * FRSR - Fifo receive start register.
1156 * This register does not exist on imx6, it is present on earlier
1157 * hardware. The u-boot code sets this to a non-default value that's 32
1158 * bytes larger than the default, with no clue as to why. The default
1159 * value should work fine, so there's no code to init it here.
1163 * MRBR - Max RX buffer size.
1165 * Note: For hardware prior to imx6 this value cannot exceed 0x07ff,
1166 * but the datasheet says no such thing for imx6. On the imx6, setting
1167 * this to 2K without setting EN1588 resulted in a crazy runaway
1168 * receive loop in the hardware, where every rx descriptor in the ring
1169 * had its EMPTY flag cleared, no completion or error flags set, and a
1170 * length of zero. I think maybe you can only exceed it when EN1588 is
1171 * set, like maybe that's what enables jumbo frames, because in general
1172 * the EN1588 flag seems to be the "enable new stuff" vs. "be legacy-
1175 WR4(sc, FEC_MRBR_REG, maxfl << FEC_MRBR_R_BUF_SIZE_SHIFT);
1178 * FTRL - Frame truncation length.
1180 * Must be greater than or equal to the value set in FEC_RCR_MAXFL.
1182 WR4(sc, FEC_FTRL_REG, maxfl);
1185 * RDSR / TDSR descriptor ring pointers.
1187 * When we turn on ECR_ETHEREN at the end, the hardware zeroes its
1188 * internal current descriptor index values for both rings, so we zero
1189 * our index values as well.
1192 sc->tx_idx_head = sc->tx_idx_tail = 0;
1194 WR4(sc, FEC_RDSR_REG, sc->rxdesc_ring_paddr);
1195 WR4(sc, FEC_TDSR_REG, sc->txdesc_ring_paddr);
1198 * EIM - interrupt mask register.
1200 * We always enable the same set of interrupts while running; unlike
1201 * some drivers there's no need to change the mask on the fly depending
1202 * on what operations are in progress.
1204 WR4(sc, FEC_IEM_REG, FEC_IER_TXF | FEC_IER_RXF | FEC_IER_EBERR);
1207 * MIBC - MIB control (hardware stats); clear all statistics regs, then
1208 * enable collection of statistics.
1210 regval = RD4(sc, FEC_MIBC_REG);
1211 WR4(sc, FEC_MIBC_REG, regval | FEC_MIBC_DIS);
1212 ffec_clear_stats(sc);
1213 WR4(sc, FEC_MIBC_REG, regval & ~FEC_MIBC_DIS);
1216 * ECR - Ethernet control register.
1218 * This must happen after all the other config registers are set. If
1219 * we're running on little-endian hardware, also set the flag for byte-
1220 * swapping descriptor ring entries. This flag doesn't exist on older
1221 * hardware, but it can be safely set -- the bit position it occupies
1224 regval = RD4(sc, FEC_ECR_REG);
1225 #if _BYTE_ORDER == _LITTLE_ENDIAN
1226 regval |= FEC_ECR_DBSWP;
1228 regval |= FEC_ECR_ETHEREN;
1229 WR4(sc, FEC_ECR_REG, regval);
1231 ifp->if_drv_flags |= IFF_DRV_RUNNING;
1234 * Call mii_mediachg() which will call back into ffec_miibus_statchg() to
1235 * set up the remaining config registers based on the current media.
1237 mii_mediachg(sc->mii_softc);
1238 callout_reset(&sc->ffec_callout, hz, ffec_tick, sc);
1241 * Tell the hardware that receive buffers are available. They were made
1242 * available in ffec_attach() or ffec_stop().
1244 WR4(sc, FEC_RDAR_REG, FEC_RDAR_RDAR);
1248 ffec_init(void *if_softc)
1250 struct ffec_softc *sc = if_softc;
1253 ffec_init_locked(sc);
1258 ffec_intr(void *arg)
1260 struct ffec_softc *sc;
1267 ier = RD4(sc, FEC_IER_REG);
1269 if (ier & FEC_IER_TXF) {
1270 WR4(sc, FEC_IER_REG, FEC_IER_TXF);
1271 ffec_txfinish_locked(sc);
1274 if (ier & FEC_IER_RXF) {
1275 WR4(sc, FEC_IER_REG, FEC_IER_RXF);
1276 ffec_rxfinish_locked(sc);
1280 * We actually don't care about most errors, because the hardware copes
1281 * with them just fine, discarding the incoming bad frame, or forcing a
1282 * bad CRC onto an outgoing bad frame, and counting the errors in the
1283 * stats registers. The one that really matters is EBERR (DMA bus
1284 * error) because the hardware automatically clears ECR[ETHEREN] and we
1285 * have to restart it here. It should never happen.
1287 if (ier & FEC_IER_EBERR) {
1288 WR4(sc, FEC_IER_REG, FEC_IER_EBERR);
1289 device_printf(sc->dev,
1290 "Ethernet DMA error, restarting controller.\n");
1291 ffec_stop_locked(sc);
1292 ffec_init_locked(sc);
1300 ffec_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
1302 struct ffec_softc *sc;
1303 struct mii_data *mii;
1308 ifr = (struct ifreq *)data;
1314 if (ifp->if_flags & IFF_UP) {
1315 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1316 if ((ifp->if_flags ^ sc->if_flags) &
1317 (IFF_PROMISC | IFF_ALLMULTI))
1318 ffec_setup_rxfilter(sc);
1320 if (!sc->is_detaching)
1321 ffec_init_locked(sc);
1324 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1325 ffec_stop_locked(sc);
1327 sc->if_flags = ifp->if_flags;
1333 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1335 ffec_setup_rxfilter(sc);
1342 mii = sc->mii_softc;
1343 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
1347 mask = ifp->if_capenable ^ ifr->ifr_reqcap;
1348 if (mask & IFCAP_VLAN_MTU) {
1349 /* No work to do except acknowledge the change took. */
1350 ifp->if_capenable ^= IFCAP_VLAN_MTU;
1355 error = ether_ioctl(ifp, cmd, data);
1363 ffec_detach(device_t dev)
1365 struct ffec_softc *sc;
1370 * NB: This function can be called internally to unwind a failure to
1371 * attach. Make sure a resource got allocated/created before destroying.
1374 sc = device_get_softc(dev);
1376 if (sc->is_attached) {
1378 sc->is_detaching = true;
1379 ffec_stop_locked(sc);
1381 callout_drain(&sc->ffec_callout);
1382 ether_ifdetach(sc->ifp);
1385 /* XXX no miibus detach? */
1387 /* Clean up RX DMA resources and free mbufs. */
1388 for (idx = 0; idx < RX_DESC_COUNT; ++idx) {
1389 if ((map = sc->rxbuf_map[idx].map) != NULL) {
1390 bus_dmamap_unload(sc->rxbuf_tag, map);
1391 bus_dmamap_destroy(sc->rxbuf_tag, map);
1392 m_freem(sc->rxbuf_map[idx].mbuf);
1395 if (sc->rxbuf_tag != NULL)
1396 bus_dma_tag_destroy(sc->rxbuf_tag);
1397 if (sc->rxdesc_map != NULL) {
1398 bus_dmamap_unload(sc->rxdesc_tag, sc->rxdesc_map);
1399 bus_dmamap_destroy(sc->rxdesc_tag, sc->rxdesc_map);
1401 if (sc->rxdesc_tag != NULL)
1402 bus_dma_tag_destroy(sc->rxdesc_tag);
1404 /* Clean up TX DMA resources. */
1405 for (idx = 0; idx < TX_DESC_COUNT; ++idx) {
1406 if ((map = sc->txbuf_map[idx].map) != NULL) {
1407 /* TX maps are already unloaded. */
1408 bus_dmamap_destroy(sc->txbuf_tag, map);
1411 if (sc->txbuf_tag != NULL)
1412 bus_dma_tag_destroy(sc->txbuf_tag);
1413 if (sc->txdesc_map != NULL) {
1414 bus_dmamap_unload(sc->txdesc_tag, sc->txdesc_map);
1415 bus_dmamap_destroy(sc->txdesc_tag, sc->txdesc_map);
1417 if (sc->txdesc_tag != NULL)
1418 bus_dma_tag_destroy(sc->txdesc_tag);
1420 /* Release bus resources. */
1421 if (sc->intr_cookie)
1422 bus_teardown_intr(dev, sc->irq_res, sc->intr_cookie);
1424 if (sc->irq_res != NULL)
1425 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq_res);
1427 if (sc->mem_res != NULL)
1428 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->mem_res);
1430 FFEC_LOCK_DESTROY(sc);
1435 ffec_attach(device_t dev)
1437 struct ffec_softc *sc;
1438 struct ifnet *ifp = NULL;
1442 int error, phynum, rid;
1443 uint8_t eaddr[ETHER_ADDR_LEN];
1446 sc = device_get_softc(dev);
1452 * There are differences in the implementation and features of the FEC
1453 * hardware on different SoCs, so figure out what type we are.
1455 sc->fectype = ofw_bus_search_compatible(dev, compat_data)->ocd_data;
1457 if (sc->fectype & FECFLAG_AVB) {
1458 sc->rxbuf_align = 64;
1459 sc->txbuf_align = 1;
1461 sc->rxbuf_align = 16;
1462 sc->txbuf_align = 16;
1466 * We have to be told what kind of electrical connection exists between
1467 * the MAC and PHY or we can't operate correctly.
1469 if ((ofw_node = ofw_bus_get_node(dev)) == -1) {
1470 device_printf(dev, "Impossible: Can't find ofw bus node\n");
1474 sc->phy_conn_type = mii_fdt_get_contype(ofw_node);
1475 if (sc->phy_conn_type == MII_CONTYPE_UNKNOWN) {
1476 device_printf(sc->dev, "No valid 'phy-mode' "
1477 "property found in FDT data for device.\n");
1482 callout_init_mtx(&sc->ffec_callout, &sc->mtx, 0);
1484 /* Allocate bus resources for accessing the hardware. */
1486 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1488 if (sc->mem_res == NULL) {
1489 device_printf(dev, "could not allocate memory resources.\n");
1494 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1496 if (sc->irq_res == NULL) {
1497 device_printf(dev, "could not allocate interrupt resources.\n");
1503 * Set up TX descriptor ring, descriptors, and dma maps.
1505 error = bus_dma_tag_create(
1506 bus_get_dma_tag(dev), /* Parent tag. */
1507 FEC_DESC_RING_ALIGN, 0, /* alignment, boundary */
1508 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
1509 BUS_SPACE_MAXADDR, /* highaddr */
1510 NULL, NULL, /* filter, filterarg */
1511 TX_DESC_SIZE, 1, /* maxsize, nsegments */
1512 TX_DESC_SIZE, /* maxsegsize */
1514 NULL, NULL, /* lockfunc, lockarg */
1517 device_printf(sc->dev,
1518 "could not create TX ring DMA tag.\n");
1522 error = bus_dmamem_alloc(sc->txdesc_tag, (void**)&sc->txdesc_ring,
1523 BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO, &sc->txdesc_map);
1525 device_printf(sc->dev,
1526 "could not allocate TX descriptor ring.\n");
1530 error = bus_dmamap_load(sc->txdesc_tag, sc->txdesc_map, sc->txdesc_ring,
1531 TX_DESC_SIZE, ffec_get1paddr, &sc->txdesc_ring_paddr, 0);
1533 device_printf(sc->dev,
1534 "could not load TX descriptor ring map.\n");
1538 error = bus_dma_tag_create(
1539 bus_get_dma_tag(dev), /* Parent tag. */
1540 sc->txbuf_align, 0, /* alignment, boundary */
1541 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
1542 BUS_SPACE_MAXADDR, /* highaddr */
1543 NULL, NULL, /* filter, filterarg */
1544 MCLBYTES, 1, /* maxsize, nsegments */
1545 MCLBYTES, /* maxsegsize */
1547 NULL, NULL, /* lockfunc, lockarg */
1550 device_printf(sc->dev,
1551 "could not create TX ring DMA tag.\n");
1555 for (idx = 0; idx < TX_DESC_COUNT; ++idx) {
1556 error = bus_dmamap_create(sc->txbuf_tag, 0,
1557 &sc->txbuf_map[idx].map);
1559 device_printf(sc->dev,
1560 "could not create TX buffer DMA map.\n");
1563 ffec_setup_txdesc(sc, idx, 0, 0);
1567 * Set up RX descriptor ring, descriptors, dma maps, and mbufs.
1569 error = bus_dma_tag_create(
1570 bus_get_dma_tag(dev), /* Parent tag. */
1571 FEC_DESC_RING_ALIGN, 0, /* alignment, boundary */
1572 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
1573 BUS_SPACE_MAXADDR, /* highaddr */
1574 NULL, NULL, /* filter, filterarg */
1575 RX_DESC_SIZE, 1, /* maxsize, nsegments */
1576 RX_DESC_SIZE, /* maxsegsize */
1578 NULL, NULL, /* lockfunc, lockarg */
1581 device_printf(sc->dev,
1582 "could not create RX ring DMA tag.\n");
1586 error = bus_dmamem_alloc(sc->rxdesc_tag, (void **)&sc->rxdesc_ring,
1587 BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO, &sc->rxdesc_map);
1589 device_printf(sc->dev,
1590 "could not allocate RX descriptor ring.\n");
1594 error = bus_dmamap_load(sc->rxdesc_tag, sc->rxdesc_map, sc->rxdesc_ring,
1595 RX_DESC_SIZE, ffec_get1paddr, &sc->rxdesc_ring_paddr, 0);
1597 device_printf(sc->dev,
1598 "could not load RX descriptor ring map.\n");
1602 error = bus_dma_tag_create(
1603 bus_get_dma_tag(dev), /* Parent tag. */
1604 1, 0, /* alignment, boundary */
1605 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
1606 BUS_SPACE_MAXADDR, /* highaddr */
1607 NULL, NULL, /* filter, filterarg */
1608 MCLBYTES, 1, /* maxsize, nsegments */
1609 MCLBYTES, /* maxsegsize */
1611 NULL, NULL, /* lockfunc, lockarg */
1614 device_printf(sc->dev,
1615 "could not create RX buf DMA tag.\n");
1619 for (idx = 0; idx < RX_DESC_COUNT; ++idx) {
1620 error = bus_dmamap_create(sc->rxbuf_tag, 0,
1621 &sc->rxbuf_map[idx].map);
1623 device_printf(sc->dev,
1624 "could not create RX buffer DMA map.\n");
1627 if ((m = ffec_alloc_mbufcl(sc)) == NULL) {
1628 device_printf(dev, "Could not alloc mbuf\n");
1632 if ((error = ffec_setup_rxbuf(sc, idx, m)) != 0) {
1633 device_printf(sc->dev,
1634 "could not create new RX buffer.\n");
1639 /* Try to get the MAC address from the hardware before resetting it. */
1640 ffec_get_hwaddr(sc, eaddr);
1643 * Reset the hardware. Disables all interrupts.
1645 * When the FEC is connected to the AXI bus (indicated by AVB flag), a
1646 * MAC reset while a bus transaction is pending can hang the bus.
1647 * Instead of resetting, turn off the ENABLE bit, which allows the
1648 * hardware to complete any in-progress transfers (appending a bad CRC
1649 * to any partial packet) and release the AXI bus. This could probably
1650 * be done unconditionally for all hardware variants, but that hasn't
1653 if (sc->fectype & FECFLAG_AVB)
1654 WR4(sc, FEC_ECR_REG, 0);
1656 WR4(sc, FEC_ECR_REG, FEC_ECR_RESET);
1658 /* Setup interrupt handler. */
1659 error = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_NET | INTR_MPSAFE,
1660 NULL, ffec_intr, sc, &sc->intr_cookie);
1662 device_printf(dev, "could not setup interrupt handler.\n");
1667 * Set up the PHY control register.
1669 * Speed formula for ENET is md_clock = mac_clock / ((N + 1) * 2).
1670 * Speed formula for FEC is md_clock = mac_clock / (N * 2)
1672 * XXX - Revisit this...
1674 * For a Wandboard imx6 (ENET) I was originally using 4, but the uboot
1675 * code uses 10. Both values seem to work, but I suspect many modern
1676 * PHY parts can do mdio at speeds far above the standard 2.5 MHz.
1678 * Different imx manuals use confusingly different terminology (things
1679 * like "system clock" and "internal module clock") with examples that
1680 * use frequencies that have nothing to do with ethernet, giving the
1681 * vague impression that maybe the clock in question is the periphclock
1682 * or something. In fact, on an imx53 development board (FEC),
1683 * measuring the mdio clock at the pin on the PHY and playing with
1684 * various divisors showed that the root speed was 66 MHz (clk_ipg_root
1685 * aka periphclock) and 13 was the right divisor.
1687 * All in all, it seems likely that 13 is a safe divisor for now,
1688 * because if we really do need to base it on the peripheral clock
1689 * speed, then we need a platform-independant get-clock-freq API.
1691 mscr = 13 << FEC_MSCR_MII_SPEED_SHIFT;
1692 if (OF_hasprop(ofw_node, "phy-disable-preamble")) {
1693 mscr |= FEC_MSCR_DIS_PRE;
1695 device_printf(dev, "PHY preamble disabled\n");
1697 WR4(sc, FEC_MSCR_REG, mscr);
1699 /* Set up the ethernet interface. */
1700 sc->ifp = ifp = if_alloc(IFT_ETHER);
1703 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1704 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1705 ifp->if_capabilities = IFCAP_VLAN_MTU;
1706 ifp->if_capenable = ifp->if_capabilities;
1707 ifp->if_start = ffec_txstart;
1708 ifp->if_ioctl = ffec_ioctl;
1709 ifp->if_init = ffec_init;
1710 IFQ_SET_MAXLEN(&ifp->if_snd, TX_DESC_COUNT - 1);
1711 ifp->if_snd.ifq_drv_maxlen = TX_DESC_COUNT - 1;
1712 IFQ_SET_READY(&ifp->if_snd);
1713 ifp->if_hdrlen = sizeof(struct ether_vlan_header);
1715 #if 0 /* XXX The hardware keeps stats we could use for these. */
1716 ifp->if_linkmib = &sc->mibdata;
1717 ifp->if_linkmiblen = sizeof(sc->mibdata);
1720 /* Set up the miigasket hardware (if any). */
1721 ffec_miigasket_setup(sc);
1723 /* Attach the mii driver. */
1724 if (fdt_get_phyaddr(ofw_node, dev, &phynum, &dummy) != 0) {
1725 phynum = MII_PHY_ANY;
1727 error = mii_attach(dev, &sc->miibus, ifp, ffec_media_change,
1728 ffec_media_status, BMSR_DEFCAPMASK, phynum, MII_OFFSET_ANY,
1729 (sc->fectype & FECTYPE_MVF) ? MIIF_FORCEANEG : 0);
1731 device_printf(dev, "PHY attach failed\n");
1734 sc->mii_softc = device_get_softc(sc->miibus);
1736 /* All ready to run, attach the ethernet interface. */
1737 ether_ifattach(ifp, eaddr);
1738 sc->is_attached = true;
1750 ffec_probe(device_t dev)
1754 if (!ofw_bus_status_okay(dev))
1757 fectype = ofw_bus_search_compatible(dev, compat_data)->ocd_data;
1758 if (fectype == FECTYPE_NONE)
1761 device_set_desc(dev, (fectype & FECFLAG_GBE) ?
1762 "Freescale Gigabit Ethernet Controller" :
1763 "Freescale Fast Ethernet Controller");
1765 return (BUS_PROBE_DEFAULT);
1769 static device_method_t ffec_methods[] = {
1770 /* Device interface. */
1771 DEVMETHOD(device_probe, ffec_probe),
1772 DEVMETHOD(device_attach, ffec_attach),
1773 DEVMETHOD(device_detach, ffec_detach),
1776 DEVMETHOD(device_shutdown, ffec_shutdown),
1777 DEVMETHOD(device_suspend, ffec_suspend),
1778 DEVMETHOD(device_resume, ffec_resume),
1781 /* MII interface. */
1782 DEVMETHOD(miibus_readreg, ffec_miibus_readreg),
1783 DEVMETHOD(miibus_writereg, ffec_miibus_writereg),
1784 DEVMETHOD(miibus_statchg, ffec_miibus_statchg),
1789 static driver_t ffec_driver = {
1792 sizeof(struct ffec_softc)
1795 static devclass_t ffec_devclass;
1797 DRIVER_MODULE(ffec, simplebus, ffec_driver, ffec_devclass, 0, 0);
1798 DRIVER_MODULE(miibus, ffec, miibus_driver, miibus_devclass, 0, 0);
1800 MODULE_DEPEND(ffec, ether, 1, 1, 1);
1801 MODULE_DEPEND(ffec, miibus, 1, 1, 1);