2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2013 Ian Lepore <ian@freebsd.org>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
34 * Driver for Freescale Fast Ethernet Controller, found on imx-series SoCs among
35 * others. Also works for the ENET Gigibit controller found on imx6 and imx28,
36 * but the driver doesn't currently use any of the ENET advanced features other
37 * than enabling gigabit.
39 * The interface name 'fec' is already taken by netgraph's Fast Etherchannel
40 * (netgraph/ng_fec.c), so we use 'ffec'.
42 * Requires an FDT entry with at least these properties:
43 * fec: ethernet@02188000 {
44 * compatible = "fsl,imxNN-fec";
45 * reg = <0x02188000 0x4000>;
46 * interrupts = <150 151>;
48 * phy-disable-preamble; // optional
50 * The second interrupt number is for IEEE-1588, and is not currently used; it
51 * need not be present. phy-mode must be one of: "mii", "rmii", "rgmii".
52 * There is also an optional property, phy-disable-preamble, which if present
53 * will disable the preamble bits, cutting the size of each mdio transaction
54 * (and thus the busy-wait time) in half.
57 #include <sys/param.h>
58 #include <sys/systm.h>
60 #include <sys/endian.h>
61 #include <sys/kernel.h>
63 #include <sys/malloc.h>
65 #include <sys/module.h>
66 #include <sys/mutex.h>
68 #include <sys/socket.h>
69 #include <sys/sockio.h>
70 #include <sys/sysctl.h>
72 #include <machine/bus.h>
76 #include <net/ethernet.h>
77 #include <net/if_dl.h>
78 #include <net/if_media.h>
79 #include <net/if_types.h>
80 #include <net/if_var.h>
81 #include <net/if_vlan_var.h>
83 #include <dev/fdt/fdt_common.h>
84 #include <dev/ffec/if_ffecreg.h>
85 #include <dev/ofw/ofw_bus.h>
86 #include <dev/ofw/ofw_bus_subr.h>
87 #include <dev/mii/mii.h>
88 #include <dev/mii/miivar.h>
89 #include <dev/mii/mii_fdt.h>
90 #include "miibus_if.h"
93 * There are small differences in the hardware on various SoCs. Not every SoC
94 * we support has its own FECTYPE; most work as GENERIC and only the ones that
95 * need different handling get their own entry. In addition to the types in
96 * this list, there are some flags below that can be ORed into the upper bits.
102 FECTYPE_IMX6, /* imx6 and imx7 */
107 * Flags that describe general differences between the FEC hardware in various
108 * SoCs. These are ORed into the FECTYPE enum values in the ofw_compat_data, so
109 * the low 8 bits are reserved for the type enum. In the softc, the type and
110 * flags are put into separate members, so that you don't need to mask the flags
111 * out of the type to compare it.
113 #define FECTYPE_MASK 0x000000ff
114 #define FECFLAG_GBE (1 << 8)
115 #define FECFLAG_AVB (1 << 9)
116 #define FECFLAG_RACC (1 << 10)
119 * Table of supported FDT compat strings and their associated FECTYPE values.
121 static struct ofw_compat_data compat_data[] = {
122 {"fsl,imx51-fec", FECTYPE_GENERIC},
123 {"fsl,imx53-fec", FECTYPE_IMX53},
124 {"fsl,imx6q-fec", FECTYPE_IMX6 | FECFLAG_RACC | FECFLAG_GBE },
125 {"fsl,imx6ul-fec", FECTYPE_IMX6 | FECFLAG_RACC },
126 {"fsl,imx6sx-fec", FECTYPE_IMX6 | FECFLAG_RACC },
127 {"fsl,imx7d-fec", FECTYPE_IMX6 | FECFLAG_RACC | FECFLAG_GBE |
129 {"fsl,mvf600-fec", FECTYPE_MVF | FECFLAG_RACC },
130 {"fsl,mvf-fec", FECTYPE_MVF},
131 {NULL, FECTYPE_NONE},
135 * Driver data and defines.
137 #define RX_DESC_COUNT 64
138 #define RX_DESC_SIZE (sizeof(struct ffec_hwdesc) * RX_DESC_COUNT)
139 #define TX_DESC_COUNT 64
140 #define TX_DESC_SIZE (sizeof(struct ffec_hwdesc) * TX_DESC_COUNT)
142 #define WATCHDOG_TIMEOUT_SECS 5
144 #define MAX_IRQ_COUNT 3
154 struct mii_data * mii_softc;
158 struct resource *irq_res[MAX_IRQ_COUNT];
159 struct resource *mem_res;
160 void * intr_cookie[MAX_IRQ_COUNT];
161 struct callout ffec_callout;
162 mii_contype_t phy_conn_type;
165 boolean_t link_is_up;
166 boolean_t is_attached;
167 boolean_t is_detaching;
168 int tx_watchdog_count;
172 bus_dma_tag_t rxdesc_tag;
173 bus_dmamap_t rxdesc_map;
174 struct ffec_hwdesc *rxdesc_ring;
175 bus_addr_t rxdesc_ring_paddr;
176 bus_dma_tag_t rxbuf_tag;
177 struct ffec_bufmap rxbuf_map[RX_DESC_COUNT];
180 bus_dma_tag_t txdesc_tag;
181 bus_dmamap_t txdesc_map;
182 struct ffec_hwdesc *txdesc_ring;
183 bus_addr_t txdesc_ring_paddr;
184 bus_dma_tag_t txbuf_tag;
185 struct ffec_bufmap txbuf_map[TX_DESC_COUNT];
186 uint32_t tx_idx_head;
187 uint32_t tx_idx_tail;
191 static struct resource_spec irq_res_spec[MAX_IRQ_COUNT + 1] = {
192 { SYS_RES_IRQ, 0, RF_ACTIVE },
193 { SYS_RES_IRQ, 1, RF_ACTIVE | RF_OPTIONAL },
194 { SYS_RES_IRQ, 2, RF_ACTIVE | RF_OPTIONAL },
198 #define FFEC_LOCK(sc) mtx_lock(&(sc)->mtx)
199 #define FFEC_UNLOCK(sc) mtx_unlock(&(sc)->mtx)
200 #define FFEC_LOCK_INIT(sc) mtx_init(&(sc)->mtx, \
201 device_get_nameunit((sc)->dev), MTX_NETWORK_LOCK, MTX_DEF)
202 #define FFEC_LOCK_DESTROY(sc) mtx_destroy(&(sc)->mtx);
203 #define FFEC_ASSERT_LOCKED(sc) mtx_assert(&(sc)->mtx, MA_OWNED);
204 #define FFEC_ASSERT_UNLOCKED(sc) mtx_assert(&(sc)->mtx, MA_NOTOWNED);
206 static void ffec_init_locked(struct ffec_softc *sc);
207 static void ffec_stop_locked(struct ffec_softc *sc);
208 static void ffec_txstart_locked(struct ffec_softc *sc);
209 static void ffec_txfinish_locked(struct ffec_softc *sc);
211 static inline uint16_t
212 RD2(struct ffec_softc *sc, bus_size_t off)
215 return (bus_read_2(sc->mem_res, off));
219 WR2(struct ffec_softc *sc, bus_size_t off, uint16_t val)
222 bus_write_2(sc->mem_res, off, val);
225 static inline uint32_t
226 RD4(struct ffec_softc *sc, bus_size_t off)
229 return (bus_read_4(sc->mem_res, off));
233 WR4(struct ffec_softc *sc, bus_size_t off, uint32_t val)
236 bus_write_4(sc->mem_res, off, val);
239 static inline uint32_t
240 next_rxidx(struct ffec_softc *sc, uint32_t curidx)
243 return ((curidx == RX_DESC_COUNT - 1) ? 0 : curidx + 1);
246 static inline uint32_t
247 next_txidx(struct ffec_softc *sc, uint32_t curidx)
250 return ((curidx == TX_DESC_COUNT - 1) ? 0 : curidx + 1);
254 ffec_get1paddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
259 *(bus_addr_t *)arg = segs[0].ds_addr;
263 ffec_miigasket_setup(struct ffec_softc *sc)
268 * We only need the gasket for MII and RMII connections on certain SoCs.
279 switch (sc->phy_conn_type)
281 case MII_CONTYPE_MII:
284 case MII_CONTYPE_RMII:
285 ifmode = FEC_MIIGSK_CFGR_IF_MODE_RMII;
292 * Disable the gasket, configure for either MII or RMII, then enable.
295 WR2(sc, FEC_MIIGSK_ENR, 0);
296 while (RD2(sc, FEC_MIIGSK_ENR) & FEC_MIIGSK_ENR_READY)
299 WR2(sc, FEC_MIIGSK_CFGR, ifmode);
301 WR2(sc, FEC_MIIGSK_ENR, FEC_MIIGSK_ENR_EN);
302 while (!(RD2(sc, FEC_MIIGSK_ENR) & FEC_MIIGSK_ENR_READY))
307 ffec_miibus_iowait(struct ffec_softc *sc)
311 for (timeout = 10000; timeout != 0; --timeout)
312 if (RD4(sc, FEC_IER_REG) & FEC_IER_MII)
319 ffec_miibus_readreg(device_t dev, int phy, int reg)
321 struct ffec_softc *sc;
324 sc = device_get_softc(dev);
326 WR4(sc, FEC_IER_REG, FEC_IER_MII);
328 WR4(sc, FEC_MMFR_REG, FEC_MMFR_OP_READ |
329 FEC_MMFR_ST_VALUE | FEC_MMFR_TA_VALUE |
330 ((phy << FEC_MMFR_PA_SHIFT) & FEC_MMFR_PA_MASK) |
331 ((reg << FEC_MMFR_RA_SHIFT) & FEC_MMFR_RA_MASK));
333 if (!ffec_miibus_iowait(sc)) {
334 device_printf(dev, "timeout waiting for mii read\n");
335 return (-1); /* All-ones is a symptom of bad mdio. */
338 val = RD4(sc, FEC_MMFR_REG) & FEC_MMFR_DATA_MASK;
344 ffec_miibus_writereg(device_t dev, int phy, int reg, int val)
346 struct ffec_softc *sc;
348 sc = device_get_softc(dev);
350 WR4(sc, FEC_IER_REG, FEC_IER_MII);
352 WR4(sc, FEC_MMFR_REG, FEC_MMFR_OP_WRITE |
353 FEC_MMFR_ST_VALUE | FEC_MMFR_TA_VALUE |
354 ((phy << FEC_MMFR_PA_SHIFT) & FEC_MMFR_PA_MASK) |
355 ((reg << FEC_MMFR_RA_SHIFT) & FEC_MMFR_RA_MASK) |
356 (val & FEC_MMFR_DATA_MASK));
358 if (!ffec_miibus_iowait(sc)) {
359 device_printf(dev, "timeout waiting for mii write\n");
367 ffec_miibus_statchg(device_t dev)
369 struct ffec_softc *sc;
370 struct mii_data *mii;
371 uint32_t ecr, rcr, tcr;
374 * Called by the MII bus driver when the PHY establishes link to set the
375 * MAC interface registers.
378 sc = device_get_softc(dev);
380 FFEC_ASSERT_LOCKED(sc);
384 if (mii->mii_media_status & IFM_ACTIVE)
385 sc->link_is_up = true;
387 sc->link_is_up = false;
389 ecr = RD4(sc, FEC_ECR_REG) & ~FEC_ECR_SPEED;
390 rcr = RD4(sc, FEC_RCR_REG) & ~(FEC_RCR_RMII_10T | FEC_RCR_RMII_MODE |
391 FEC_RCR_RGMII_EN | FEC_RCR_DRT | FEC_RCR_FCE);
392 tcr = RD4(sc, FEC_TCR_REG) & ~FEC_TCR_FDEN;
394 rcr |= FEC_RCR_MII_MODE; /* Must always be on even for R[G]MII. */
395 switch (sc->phy_conn_type) {
396 case MII_CONTYPE_RMII:
397 rcr |= FEC_RCR_RMII_MODE;
399 case MII_CONTYPE_RGMII:
400 case MII_CONTYPE_RGMII_ID:
401 case MII_CONTYPE_RGMII_RXID:
402 case MII_CONTYPE_RGMII_TXID:
403 rcr |= FEC_RCR_RGMII_EN;
409 switch (IFM_SUBTYPE(mii->mii_media_active)) {
412 ecr |= FEC_ECR_SPEED;
415 /* Not-FEC_ECR_SPEED + not-FEC_RCR_RMII_10T means 100TX */
418 rcr |= FEC_RCR_RMII_10T;
421 sc->link_is_up = false;
424 sc->link_is_up = false;
425 device_printf(dev, "Unsupported media %u\n",
426 IFM_SUBTYPE(mii->mii_media_active));
430 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0)
435 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FLOW) != 0)
438 WR4(sc, FEC_RCR_REG, rcr);
439 WR4(sc, FEC_TCR_REG, tcr);
440 WR4(sc, FEC_ECR_REG, ecr);
444 ffec_media_status(struct ifnet * ifp, struct ifmediareq *ifmr)
446 struct ffec_softc *sc;
447 struct mii_data *mii;
454 ifmr->ifm_active = mii->mii_media_active;
455 ifmr->ifm_status = mii->mii_media_status;
460 ffec_media_change_locked(struct ffec_softc *sc)
463 return (mii_mediachg(sc->mii_softc));
467 ffec_media_change(struct ifnet * ifp)
469 struct ffec_softc *sc;
475 error = ffec_media_change_locked(sc);
480 static void ffec_clear_stats(struct ffec_softc *sc)
484 mibc = RD4(sc, FEC_MIBC_REG);
487 * On newer hardware the statistic regs are cleared by toggling a bit in
488 * the mib control register. On older hardware the clear procedure is
489 * to disable statistics collection, zero the regs, then re-enable.
491 if (sc->fectype == FECTYPE_IMX6 || sc->fectype == FECTYPE_MVF) {
492 WR4(sc, FEC_MIBC_REG, mibc | FEC_MIBC_CLEAR);
493 WR4(sc, FEC_MIBC_REG, mibc & ~FEC_MIBC_CLEAR);
495 WR4(sc, FEC_MIBC_REG, mibc | FEC_MIBC_DIS);
497 WR4(sc, FEC_IEEE_R_DROP, 0);
498 WR4(sc, FEC_IEEE_R_MACERR, 0);
499 WR4(sc, FEC_RMON_R_CRC_ALIGN, 0);
500 WR4(sc, FEC_RMON_R_FRAG, 0);
501 WR4(sc, FEC_RMON_R_JAB, 0);
502 WR4(sc, FEC_RMON_R_MC_PKT, 0);
503 WR4(sc, FEC_RMON_R_OVERSIZE, 0);
504 WR4(sc, FEC_RMON_R_PACKETS, 0);
505 WR4(sc, FEC_RMON_R_UNDERSIZE, 0);
506 WR4(sc, FEC_RMON_T_COL, 0);
507 WR4(sc, FEC_RMON_T_CRC_ALIGN, 0);
508 WR4(sc, FEC_RMON_T_FRAG, 0);
509 WR4(sc, FEC_RMON_T_JAB, 0);
510 WR4(sc, FEC_RMON_T_MC_PKT, 0);
511 WR4(sc, FEC_RMON_T_OVERSIZE , 0);
512 WR4(sc, FEC_RMON_T_PACKETS, 0);
513 WR4(sc, FEC_RMON_T_UNDERSIZE, 0);
515 WR4(sc, FEC_MIBC_REG, mibc);
520 ffec_harvest_stats(struct ffec_softc *sc)
527 * - FEC_IEEE_R_DROP is "dropped due to invalid start frame delimiter"
528 * so it's really just another type of input error.
529 * - FEC_IEEE_R_MACERR is "no receive fifo space"; count as input drops.
531 if_inc_counter(ifp, IFCOUNTER_IPACKETS, RD4(sc, FEC_RMON_R_PACKETS));
532 if_inc_counter(ifp, IFCOUNTER_IMCASTS, RD4(sc, FEC_RMON_R_MC_PKT));
533 if_inc_counter(ifp, IFCOUNTER_IERRORS,
534 RD4(sc, FEC_RMON_R_CRC_ALIGN) + RD4(sc, FEC_RMON_R_UNDERSIZE) +
535 RD4(sc, FEC_RMON_R_OVERSIZE) + RD4(sc, FEC_RMON_R_FRAG) +
536 RD4(sc, FEC_RMON_R_JAB) + RD4(sc, FEC_IEEE_R_DROP));
538 if_inc_counter(ifp, IFCOUNTER_IQDROPS, RD4(sc, FEC_IEEE_R_MACERR));
540 if_inc_counter(ifp, IFCOUNTER_OPACKETS, RD4(sc, FEC_RMON_T_PACKETS));
541 if_inc_counter(ifp, IFCOUNTER_OMCASTS, RD4(sc, FEC_RMON_T_MC_PKT));
542 if_inc_counter(ifp, IFCOUNTER_OERRORS,
543 RD4(sc, FEC_RMON_T_CRC_ALIGN) + RD4(sc, FEC_RMON_T_UNDERSIZE) +
544 RD4(sc, FEC_RMON_T_OVERSIZE) + RD4(sc, FEC_RMON_T_FRAG) +
545 RD4(sc, FEC_RMON_T_JAB));
547 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, RD4(sc, FEC_RMON_T_COL));
549 ffec_clear_stats(sc);
555 struct ffec_softc *sc;
561 FFEC_ASSERT_LOCKED(sc);
565 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING))
569 * Typical tx watchdog. If this fires it indicates that we enqueued
570 * packets for output and never got a txdone interrupt for them. Maybe
571 * it's a missed interrupt somehow, just pretend we got one.
573 if (sc->tx_watchdog_count > 0) {
574 if (--sc->tx_watchdog_count == 0) {
575 ffec_txfinish_locked(sc);
579 /* Gather stats from hardware counters. */
580 ffec_harvest_stats(sc);
582 /* Check the media status. */
583 link_was_up = sc->link_is_up;
584 mii_tick(sc->mii_softc);
585 if (sc->link_is_up && !link_was_up)
586 ffec_txstart_locked(sc);
588 /* Schedule another check one second from now. */
589 callout_reset(&sc->ffec_callout, hz, ffec_tick, sc);
592 inline static uint32_t
593 ffec_setup_txdesc(struct ffec_softc *sc, int idx, bus_addr_t paddr,
599 nidx = next_txidx(sc, idx);
601 /* Addr/len 0 means we're clearing the descriptor after xmit done. */
602 if (paddr == 0 || len == 0) {
606 flags = FEC_TXDESC_READY | FEC_TXDESC_L | FEC_TXDESC_TC;
610 flags |= FEC_TXDESC_WRAP;
613 * The hardware requires 32-bit physical addresses. We set up the dma
614 * tag to indicate that, so the cast to uint32_t should never lose
617 sc->txdesc_ring[idx].buf_paddr = (uint32_t)paddr;
618 sc->txdesc_ring[idx].flags_len = flags | len; /* Must be set last! */
624 ffec_setup_txbuf(struct ffec_softc *sc, int idx, struct mbuf **mp)
628 struct bus_dma_segment seg;
630 if ((m = m_defrag(*mp, M_NOWAIT)) == NULL)
634 error = bus_dmamap_load_mbuf_sg(sc->txbuf_tag, sc->txbuf_map[idx].map,
639 bus_dmamap_sync(sc->txbuf_tag, sc->txbuf_map[idx].map,
640 BUS_DMASYNC_PREWRITE);
642 sc->txbuf_map[idx].mbuf = m;
643 ffec_setup_txdesc(sc, idx, seg.ds_addr, seg.ds_len);
650 ffec_txstart_locked(struct ffec_softc *sc)
656 FFEC_ASSERT_LOCKED(sc);
663 if (ifp->if_drv_flags & IFF_DRV_OACTIVE)
669 if (sc->txcount == (TX_DESC_COUNT-1)) {
670 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
673 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
676 if (ffec_setup_txbuf(sc, sc->tx_idx_head, &m) != 0) {
677 IFQ_DRV_PREPEND(&ifp->if_snd, m);
681 sc->tx_idx_head = next_txidx(sc, sc->tx_idx_head);
686 bus_dmamap_sync(sc->txdesc_tag, sc->txdesc_map, BUS_DMASYNC_PREWRITE);
687 WR4(sc, FEC_TDAR_REG, FEC_TDAR_TDAR);
688 bus_dmamap_sync(sc->txdesc_tag, sc->txdesc_map, BUS_DMASYNC_POSTWRITE);
689 sc->tx_watchdog_count = WATCHDOG_TIMEOUT_SECS;
694 ffec_txstart(struct ifnet *ifp)
696 struct ffec_softc *sc = ifp->if_softc;
699 ffec_txstart_locked(sc);
704 ffec_txfinish_locked(struct ffec_softc *sc)
707 struct ffec_hwdesc *desc;
708 struct ffec_bufmap *bmap;
709 boolean_t retired_buffer;
711 FFEC_ASSERT_LOCKED(sc);
713 /* XXX Can't set PRE|POST right now, but we need both. */
714 bus_dmamap_sync(sc->txdesc_tag, sc->txdesc_map, BUS_DMASYNC_PREREAD);
715 bus_dmamap_sync(sc->txdesc_tag, sc->txdesc_map, BUS_DMASYNC_POSTREAD);
717 retired_buffer = false;
718 while (sc->tx_idx_tail != sc->tx_idx_head) {
719 desc = &sc->txdesc_ring[sc->tx_idx_tail];
720 if (desc->flags_len & FEC_TXDESC_READY)
722 retired_buffer = true;
723 bmap = &sc->txbuf_map[sc->tx_idx_tail];
724 bus_dmamap_sync(sc->txbuf_tag, bmap->map,
725 BUS_DMASYNC_POSTWRITE);
726 bus_dmamap_unload(sc->txbuf_tag, bmap->map);
729 ffec_setup_txdesc(sc, sc->tx_idx_tail, 0, 0);
730 sc->tx_idx_tail = next_txidx(sc, sc->tx_idx_tail);
734 * If we retired any buffers, there will be open tx slots available in
735 * the descriptor ring, go try to start some new output.
737 if (retired_buffer) {
738 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
739 ffec_txstart_locked(sc);
742 /* If there are no buffers outstanding, muzzle the watchdog. */
743 if (sc->tx_idx_tail == sc->tx_idx_head) {
744 sc->tx_watchdog_count = 0;
748 inline static uint32_t
749 ffec_setup_rxdesc(struct ffec_softc *sc, int idx, bus_addr_t paddr)
754 * The hardware requires 32-bit physical addresses. We set up the dma
755 * tag to indicate that, so the cast to uint32_t should never lose
758 nidx = next_rxidx(sc, idx);
759 sc->rxdesc_ring[idx].buf_paddr = (uint32_t)paddr;
760 sc->rxdesc_ring[idx].flags_len = FEC_RXDESC_EMPTY |
761 ((nidx == 0) ? FEC_RXDESC_WRAP : 0);
767 ffec_setup_rxbuf(struct ffec_softc *sc, int idx, struct mbuf * m)
770 struct bus_dma_segment seg;
772 if (!(sc->fecflags & FECFLAG_RACC)) {
774 * The RACC[SHIFT16] feature is not available. So, we need to
775 * leave at least ETHER_ALIGN bytes free at the beginning of the
776 * buffer to allow the data to be re-aligned after receiving it
777 * (by copying it backwards ETHER_ALIGN bytes in the same
778 * buffer). We also have to ensure that the beginning of the
779 * buffer is aligned to the hardware's requirements.
781 m_adj(m, roundup(ETHER_ALIGN, sc->rxbuf_align));
784 error = bus_dmamap_load_mbuf_sg(sc->rxbuf_tag, sc->rxbuf_map[idx].map,
790 bus_dmamap_sync(sc->rxbuf_tag, sc->rxbuf_map[idx].map,
791 BUS_DMASYNC_PREREAD);
793 sc->rxbuf_map[idx].mbuf = m;
794 ffec_setup_rxdesc(sc, idx, seg.ds_addr);
800 ffec_alloc_mbufcl(struct ffec_softc *sc)
804 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
806 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size;
812 ffec_rxfinish_onebuf(struct ffec_softc *sc, int len)
814 struct mbuf *m, *newmbuf;
815 struct ffec_bufmap *bmap;
820 * First try to get a new mbuf to plug into this slot in the rx ring.
821 * If that fails, drop the current packet and recycle the current
822 * mbuf, which is still mapped and loaded.
824 if ((newmbuf = ffec_alloc_mbufcl(sc)) == NULL) {
825 if_inc_counter(sc->ifp, IFCOUNTER_IQDROPS, 1);
826 ffec_setup_rxdesc(sc, sc->rx_idx,
827 sc->rxdesc_ring[sc->rx_idx].buf_paddr);
833 bmap = &sc->rxbuf_map[sc->rx_idx];
834 len -= ETHER_CRC_LEN;
835 bus_dmamap_sync(sc->rxbuf_tag, bmap->map, BUS_DMASYNC_POSTREAD);
836 bus_dmamap_unload(sc->rxbuf_tag, bmap->map);
840 m->m_pkthdr.len = len;
841 m->m_pkthdr.rcvif = sc->ifp;
844 * Align the protocol headers in the receive buffer on a 32-bit
845 * boundary. Newer hardware does the alignment for us. On hardware
846 * that doesn't support this feature, we have to copy-align the data.
848 * XXX for older hardware, could we speed this up by copying just the
849 * protocol headers into their own small mbuf then chaining the cluster
850 * to it? That way we'd only need to copy like 64 bytes or whatever the
851 * biggest header is, instead of the whole 1530ish-byte frame.
853 if (sc->fecflags & FECFLAG_RACC) {
854 m->m_data = mtod(m, uint8_t *) + 2;
856 src = mtod(m, uint8_t*);
857 dst = src - ETHER_ALIGN;
858 bcopy(src, dst, len);
861 sc->ifp->if_input(sc->ifp, m);
865 if ((error = ffec_setup_rxbuf(sc, sc->rx_idx, newmbuf)) != 0) {
866 device_printf(sc->dev, "ffec_setup_rxbuf error %d\n", error);
867 /* XXX Now what? We've got a hole in the rx ring. */
873 ffec_rxfinish_locked(struct ffec_softc *sc)
875 struct ffec_hwdesc *desc;
877 boolean_t produced_empty_buffer;
879 FFEC_ASSERT_LOCKED(sc);
881 /* XXX Can't set PRE|POST right now, but we need both. */
882 bus_dmamap_sync(sc->rxdesc_tag, sc->rxdesc_map, BUS_DMASYNC_PREREAD);
883 bus_dmamap_sync(sc->rxdesc_tag, sc->rxdesc_map, BUS_DMASYNC_POSTREAD);
884 produced_empty_buffer = false;
886 desc = &sc->rxdesc_ring[sc->rx_idx];
887 if (desc->flags_len & FEC_RXDESC_EMPTY)
889 produced_empty_buffer = true;
890 len = (desc->flags_len & FEC_RXDESC_LEN_MASK);
893 * Just recycle the descriptor and continue. .
895 ffec_setup_rxdesc(sc, sc->rx_idx,
896 sc->rxdesc_ring[sc->rx_idx].buf_paddr);
897 } else if ((desc->flags_len & FEC_RXDESC_L) == 0) {
899 * The entire frame is not in this buffer. Impossible.
900 * Recycle the descriptor and continue.
902 * XXX what's the right way to handle this? Probably we
903 * should stop/init the hardware because this should
904 * just really never happen when we have buffers bigger
905 * than the maximum frame size.
907 device_printf(sc->dev,
908 "fec_rxfinish: received frame without LAST bit set");
909 ffec_setup_rxdesc(sc, sc->rx_idx,
910 sc->rxdesc_ring[sc->rx_idx].buf_paddr);
911 } else if (desc->flags_len & FEC_RXDESC_ERROR_BITS) {
913 * Something went wrong with receiving the frame, we
914 * don't care what (the hardware has counted the error
915 * in the stats registers already), we just reuse the
916 * same mbuf, which is still dma-mapped, by resetting
919 ffec_setup_rxdesc(sc, sc->rx_idx,
920 sc->rxdesc_ring[sc->rx_idx].buf_paddr);
923 * Normal case: a good frame all in one buffer.
925 ffec_rxfinish_onebuf(sc, len);
927 sc->rx_idx = next_rxidx(sc, sc->rx_idx);
930 if (produced_empty_buffer) {
931 bus_dmamap_sync(sc->rxdesc_tag, sc->rxdesc_map, BUS_DMASYNC_PREWRITE);
932 WR4(sc, FEC_RDAR_REG, FEC_RDAR_RDAR);
933 bus_dmamap_sync(sc->rxdesc_tag, sc->rxdesc_map, BUS_DMASYNC_POSTWRITE);
938 ffec_get_hwaddr(struct ffec_softc *sc, uint8_t *hwaddr)
940 uint32_t palr, paur, rnd;
943 * Try to recover a MAC address from the running hardware. If there's
944 * something non-zero there, assume the bootloader did the right thing
947 * Otherwise, set the address to a convenient locally assigned address,
948 * 'bsd' + random 24 low-order bits. 'b' is 0x62, which has the locally
949 * assigned bit set, and the broadcast/multicast bit clear.
951 palr = RD4(sc, FEC_PALR_REG);
952 paur = RD4(sc, FEC_PAUR_REG) & FEC_PAUR_PADDR2_MASK;
953 if ((palr | paur) != 0) {
954 hwaddr[0] = palr >> 24;
955 hwaddr[1] = palr >> 16;
956 hwaddr[2] = palr >> 8;
957 hwaddr[3] = palr >> 0;
958 hwaddr[4] = paur >> 24;
959 hwaddr[5] = paur >> 16;
961 rnd = arc4random() & 0x00ffffff;
965 hwaddr[3] = rnd >> 16;
966 hwaddr[4] = rnd >> 8;
967 hwaddr[5] = rnd >> 0;
971 device_printf(sc->dev,
972 "MAC address %02x:%02x:%02x:%02x:%02x:%02x:\n",
973 hwaddr[0], hwaddr[1], hwaddr[2],
974 hwaddr[3], hwaddr[4], hwaddr[5]);
979 ffec_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt)
981 uint64_t *ghash = arg;
984 /* 6 bits from MSB in LE CRC32 are used for hash. */
985 crc = ether_crc32_le(LLADDR(sdl), ETHER_ADDR_LEN);
986 *ghash |= 1LLU << (((uint8_t *)&crc)[3] >> 2);
992 ffec_setup_rxfilter(struct ffec_softc *sc)
996 uint64_t ghash, ihash;
998 FFEC_ASSERT_LOCKED(sc);
1003 * Set the multicast (group) filter hash.
1005 if ((ifp->if_flags & IFF_ALLMULTI))
1006 ghash = 0xffffffffffffffffLLU;
1009 if_foreach_llmaddr(ifp, ffec_hash_maddr, &ghash);
1011 WR4(sc, FEC_GAUR_REG, (uint32_t)(ghash >> 32));
1012 WR4(sc, FEC_GALR_REG, (uint32_t)ghash);
1015 * Set the individual address filter hash.
1017 * XXX Is 0 the right value when promiscuous is off? This hw feature
1018 * seems to support the concept of MAC address aliases, does such a
1021 if ((ifp->if_flags & IFF_PROMISC))
1022 ihash = 0xffffffffffffffffLLU;
1026 WR4(sc, FEC_IAUR_REG, (uint32_t)(ihash >> 32));
1027 WR4(sc, FEC_IALR_REG, (uint32_t)ihash);
1030 * Set the primary address.
1032 eaddr = IF_LLADDR(ifp);
1033 WR4(sc, FEC_PALR_REG, (eaddr[0] << 24) | (eaddr[1] << 16) |
1034 (eaddr[2] << 8) | eaddr[3]);
1035 WR4(sc, FEC_PAUR_REG, (eaddr[4] << 24) | (eaddr[5] << 16));
1039 ffec_stop_locked(struct ffec_softc *sc)
1042 struct ffec_hwdesc *desc;
1043 struct ffec_bufmap *bmap;
1046 FFEC_ASSERT_LOCKED(sc);
1049 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1050 sc->tx_watchdog_count = 0;
1053 * Stop the hardware, mask all interrupts, and clear all current
1054 * interrupt status bits.
1056 WR4(sc, FEC_ECR_REG, RD4(sc, FEC_ECR_REG) & ~FEC_ECR_ETHEREN);
1057 WR4(sc, FEC_IEM_REG, 0x00000000);
1058 WR4(sc, FEC_IER_REG, 0xffffffff);
1061 * Stop the media-check callout. Do not use callout_drain() because
1062 * we're holding a mutex the callout acquires, and if it's currently
1063 * waiting to acquire it, we'd deadlock. If it is waiting now, the
1064 * ffec_tick() routine will return without doing anything when it sees
1065 * that IFF_DRV_RUNNING is not set, so avoiding callout_drain() is safe.
1067 callout_stop(&sc->ffec_callout);
1070 * Discard all untransmitted buffers. Each buffer is simply freed;
1071 * it's as if the bits were transmitted and then lost on the wire.
1073 * XXX Is this right? Or should we use IFQ_DRV_PREPEND() to put them
1074 * back on the queue for when we get restarted later?
1076 idx = sc->tx_idx_tail;
1077 while (idx != sc->tx_idx_head) {
1078 desc = &sc->txdesc_ring[idx];
1079 bmap = &sc->txbuf_map[idx];
1080 if (desc->buf_paddr != 0) {
1081 bus_dmamap_unload(sc->txbuf_tag, bmap->map);
1082 m_freem(bmap->mbuf);
1084 ffec_setup_txdesc(sc, idx, 0, 0);
1086 idx = next_txidx(sc, idx);
1090 * Discard all unprocessed receive buffers. This amounts to just
1091 * pretending that nothing ever got received into them. We reuse the
1092 * mbuf already mapped for each desc, simply turning the EMPTY flags
1093 * back on so they'll get reused when we start up again.
1095 for (idx = 0; idx < RX_DESC_COUNT; ++idx) {
1096 desc = &sc->rxdesc_ring[idx];
1097 ffec_setup_rxdesc(sc, idx, desc->buf_paddr);
1102 ffec_init_locked(struct ffec_softc *sc)
1104 struct ifnet *ifp = sc->ifp;
1105 uint32_t maxbuf, maxfl, regval;
1107 FFEC_ASSERT_LOCKED(sc);
1110 * The hardware has a limit of 0x7ff as the max frame length (see
1111 * comments for MRBR below), and we use mbuf clusters as receive
1112 * buffers, and we currently are designed to receive an entire frame
1113 * into a single buffer.
1115 * We start with a MCLBYTES-sized cluster, but we have to offset into
1116 * the buffer by ETHER_ALIGN to make room for post-receive re-alignment,
1117 * and then that value has to be rounded up to the hardware's DMA
1118 * alignment requirements, so all in all our buffer is that much smaller
1121 * The resulting value is used as the frame truncation length and the
1122 * max buffer receive buffer size for now. It'll become more complex
1123 * when we support jumbo frames and receiving fragments of them into
1126 maxbuf = MCLBYTES - roundup(ETHER_ALIGN, sc->rxbuf_align);
1127 maxfl = min(maxbuf, 0x7ff);
1129 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1132 /* Mask all interrupts and clear all current interrupt status bits. */
1133 WR4(sc, FEC_IEM_REG, 0x00000000);
1134 WR4(sc, FEC_IER_REG, 0xffffffff);
1137 * Go set up palr/puar, galr/gaur, ialr/iaur.
1139 ffec_setup_rxfilter(sc);
1142 * TFWR - Transmit FIFO watermark register.
1144 * Set the transmit fifo watermark register to "store and forward" mode
1145 * and also set a threshold of 128 bytes in the fifo before transmission
1146 * of a frame begins (to avoid dma underruns). Recent FEC hardware
1147 * supports STRFWD and when that bit is set, the watermark level in the
1148 * low bits is ignored. Older hardware doesn't have STRFWD, but writing
1149 * to that bit is innocuous, and the TWFR bits get used instead.
1151 WR4(sc, FEC_TFWR_REG, FEC_TFWR_STRFWD | FEC_TFWR_TWFR_128BYTE);
1153 /* RCR - Receive control register.
1155 * Set max frame length + clean out anything left from u-boot.
1157 WR4(sc, FEC_RCR_REG, (maxfl << FEC_RCR_MAX_FL_SHIFT));
1160 * TCR - Transmit control register.
1162 * Clean out anything left from u-boot. Any necessary values are set in
1163 * ffec_miibus_statchg() based on the media type.
1165 WR4(sc, FEC_TCR_REG, 0);
1168 * OPD - Opcode/pause duration.
1170 * XXX These magic numbers come from u-boot.
1172 WR4(sc, FEC_OPD_REG, 0x00010020);
1175 * FRSR - Fifo receive start register.
1177 * This register does not exist on imx6, it is present on earlier
1178 * hardware. The u-boot code sets this to a non-default value that's 32
1179 * bytes larger than the default, with no clue as to why. The default
1180 * value should work fine, so there's no code to init it here.
1184 * MRBR - Max RX buffer size.
1186 * Note: For hardware prior to imx6 this value cannot exceed 0x07ff,
1187 * but the datasheet says no such thing for imx6. On the imx6, setting
1188 * this to 2K without setting EN1588 resulted in a crazy runaway
1189 * receive loop in the hardware, where every rx descriptor in the ring
1190 * had its EMPTY flag cleared, no completion or error flags set, and a
1191 * length of zero. I think maybe you can only exceed it when EN1588 is
1192 * set, like maybe that's what enables jumbo frames, because in general
1193 * the EN1588 flag seems to be the "enable new stuff" vs. "be legacy-
1196 WR4(sc, FEC_MRBR_REG, maxfl << FEC_MRBR_R_BUF_SIZE_SHIFT);
1199 * FTRL - Frame truncation length.
1201 * Must be greater than or equal to the value set in FEC_RCR_MAXFL.
1203 WR4(sc, FEC_FTRL_REG, maxfl);
1206 * RDSR / TDSR descriptor ring pointers.
1208 * When we turn on ECR_ETHEREN at the end, the hardware zeroes its
1209 * internal current descriptor index values for both rings, so we zero
1210 * our index values as well.
1213 sc->tx_idx_head = sc->tx_idx_tail = 0;
1215 WR4(sc, FEC_RDSR_REG, sc->rxdesc_ring_paddr);
1216 WR4(sc, FEC_TDSR_REG, sc->txdesc_ring_paddr);
1219 * EIM - interrupt mask register.
1221 * We always enable the same set of interrupts while running; unlike
1222 * some drivers there's no need to change the mask on the fly depending
1223 * on what operations are in progress.
1225 WR4(sc, FEC_IEM_REG, FEC_IER_TXF | FEC_IER_RXF | FEC_IER_EBERR);
1228 * MIBC - MIB control (hardware stats); clear all statistics regs, then
1229 * enable collection of statistics.
1231 regval = RD4(sc, FEC_MIBC_REG);
1232 WR4(sc, FEC_MIBC_REG, regval | FEC_MIBC_DIS);
1233 ffec_clear_stats(sc);
1234 WR4(sc, FEC_MIBC_REG, regval & ~FEC_MIBC_DIS);
1236 if (sc->fecflags & FECFLAG_RACC) {
1238 * RACC - Receive Accelerator Function Configuration.
1240 regval = RD4(sc, FEC_RACC_REG);
1241 WR4(sc, FEC_RACC_REG, regval | FEC_RACC_SHIFT16);
1245 * ECR - Ethernet control register.
1247 * This must happen after all the other config registers are set. If
1248 * we're running on little-endian hardware, also set the flag for byte-
1249 * swapping descriptor ring entries. This flag doesn't exist on older
1250 * hardware, but it can be safely set -- the bit position it occupies
1253 regval = RD4(sc, FEC_ECR_REG);
1254 #if _BYTE_ORDER == _LITTLE_ENDIAN
1255 regval |= FEC_ECR_DBSWP;
1257 regval |= FEC_ECR_ETHEREN;
1258 WR4(sc, FEC_ECR_REG, regval);
1260 ifp->if_drv_flags |= IFF_DRV_RUNNING;
1263 * Call mii_mediachg() which will call back into ffec_miibus_statchg() to
1264 * set up the remaining config registers based on the current media.
1266 mii_mediachg(sc->mii_softc);
1267 callout_reset(&sc->ffec_callout, hz, ffec_tick, sc);
1270 * Tell the hardware that receive buffers are available. They were made
1271 * available in ffec_attach() or ffec_stop().
1273 WR4(sc, FEC_RDAR_REG, FEC_RDAR_RDAR);
1277 ffec_init(void *if_softc)
1279 struct ffec_softc *sc = if_softc;
1282 ffec_init_locked(sc);
1287 ffec_intr(void *arg)
1289 struct ffec_softc *sc;
1296 ier = RD4(sc, FEC_IER_REG);
1298 if (ier & FEC_IER_TXF) {
1299 WR4(sc, FEC_IER_REG, FEC_IER_TXF);
1300 ffec_txfinish_locked(sc);
1303 if (ier & FEC_IER_RXF) {
1304 WR4(sc, FEC_IER_REG, FEC_IER_RXF);
1305 ffec_rxfinish_locked(sc);
1309 * We actually don't care about most errors, because the hardware copes
1310 * with them just fine, discarding the incoming bad frame, or forcing a
1311 * bad CRC onto an outgoing bad frame, and counting the errors in the
1312 * stats registers. The one that really matters is EBERR (DMA bus
1313 * error) because the hardware automatically clears ECR[ETHEREN] and we
1314 * have to restart it here. It should never happen.
1316 if (ier & FEC_IER_EBERR) {
1317 WR4(sc, FEC_IER_REG, FEC_IER_EBERR);
1318 device_printf(sc->dev,
1319 "Ethernet DMA error, restarting controller.\n");
1320 ffec_stop_locked(sc);
1321 ffec_init_locked(sc);
1329 ffec_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
1331 struct ffec_softc *sc;
1332 struct mii_data *mii;
1337 ifr = (struct ifreq *)data;
1343 if (ifp->if_flags & IFF_UP) {
1344 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1345 if ((ifp->if_flags ^ sc->if_flags) &
1346 (IFF_PROMISC | IFF_ALLMULTI))
1347 ffec_setup_rxfilter(sc);
1349 if (!sc->is_detaching)
1350 ffec_init_locked(sc);
1353 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1354 ffec_stop_locked(sc);
1356 sc->if_flags = ifp->if_flags;
1362 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1364 ffec_setup_rxfilter(sc);
1371 mii = sc->mii_softc;
1372 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
1376 mask = ifp->if_capenable ^ ifr->ifr_reqcap;
1377 if (mask & IFCAP_VLAN_MTU) {
1378 /* No work to do except acknowledge the change took. */
1379 ifp->if_capenable ^= IFCAP_VLAN_MTU;
1384 error = ether_ioctl(ifp, cmd, data);
1392 ffec_detach(device_t dev)
1394 struct ffec_softc *sc;
1399 * NB: This function can be called internally to unwind a failure to
1400 * attach. Make sure a resource got allocated/created before destroying.
1403 sc = device_get_softc(dev);
1405 if (sc->is_attached) {
1407 sc->is_detaching = true;
1408 ffec_stop_locked(sc);
1410 callout_drain(&sc->ffec_callout);
1411 ether_ifdetach(sc->ifp);
1414 /* XXX no miibus detach? */
1416 /* Clean up RX DMA resources and free mbufs. */
1417 for (idx = 0; idx < RX_DESC_COUNT; ++idx) {
1418 if ((map = sc->rxbuf_map[idx].map) != NULL) {
1419 bus_dmamap_unload(sc->rxbuf_tag, map);
1420 bus_dmamap_destroy(sc->rxbuf_tag, map);
1421 m_freem(sc->rxbuf_map[idx].mbuf);
1424 if (sc->rxbuf_tag != NULL)
1425 bus_dma_tag_destroy(sc->rxbuf_tag);
1426 if (sc->rxdesc_map != NULL) {
1427 bus_dmamap_unload(sc->rxdesc_tag, sc->rxdesc_map);
1428 bus_dmamap_destroy(sc->rxdesc_tag, sc->rxdesc_map);
1430 if (sc->rxdesc_tag != NULL)
1431 bus_dma_tag_destroy(sc->rxdesc_tag);
1433 /* Clean up TX DMA resources. */
1434 for (idx = 0; idx < TX_DESC_COUNT; ++idx) {
1435 if ((map = sc->txbuf_map[idx].map) != NULL) {
1436 /* TX maps are already unloaded. */
1437 bus_dmamap_destroy(sc->txbuf_tag, map);
1440 if (sc->txbuf_tag != NULL)
1441 bus_dma_tag_destroy(sc->txbuf_tag);
1442 if (sc->txdesc_map != NULL) {
1443 bus_dmamap_unload(sc->txdesc_tag, sc->txdesc_map);
1444 bus_dmamap_destroy(sc->txdesc_tag, sc->txdesc_map);
1446 if (sc->txdesc_tag != NULL)
1447 bus_dma_tag_destroy(sc->txdesc_tag);
1449 /* Release bus resources. */
1450 for (irq = 0; irq < MAX_IRQ_COUNT; ++irq) {
1451 if (sc->intr_cookie[irq] != NULL) {
1452 bus_teardown_intr(dev, sc->irq_res[irq],
1453 sc->intr_cookie[irq]);
1456 bus_release_resources(dev, irq_res_spec, sc->irq_res);
1458 if (sc->mem_res != NULL)
1459 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->mem_res);
1461 FFEC_LOCK_DESTROY(sc);
1466 ffec_attach(device_t dev)
1468 struct ffec_softc *sc;
1469 struct ifnet *ifp = NULL;
1472 uintptr_t typeflags;
1475 int error, phynum, rid, irq;
1476 uint8_t eaddr[ETHER_ADDR_LEN];
1478 sc = device_get_softc(dev);
1484 * There are differences in the implementation and features of the FEC
1485 * hardware on different SoCs, so figure out what type we are.
1487 typeflags = ofw_bus_search_compatible(dev, compat_data)->ocd_data;
1488 sc->fectype = (uint8_t)(typeflags & FECTYPE_MASK);
1489 sc->fecflags = (uint32_t)(typeflags & ~FECTYPE_MASK);
1491 if (sc->fecflags & FECFLAG_AVB) {
1492 sc->rxbuf_align = 64;
1493 sc->txbuf_align = 1;
1495 sc->rxbuf_align = 16;
1496 sc->txbuf_align = 16;
1500 * We have to be told what kind of electrical connection exists between
1501 * the MAC and PHY or we can't operate correctly.
1503 if ((ofw_node = ofw_bus_get_node(dev)) == -1) {
1504 device_printf(dev, "Impossible: Can't find ofw bus node\n");
1508 sc->phy_conn_type = mii_fdt_get_contype(ofw_node);
1509 if (sc->phy_conn_type == MII_CONTYPE_UNKNOWN) {
1510 device_printf(sc->dev, "No valid 'phy-mode' "
1511 "property found in FDT data for device.\n");
1516 callout_init_mtx(&sc->ffec_callout, &sc->mtx, 0);
1518 /* Allocate bus resources for accessing the hardware. */
1520 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1522 if (sc->mem_res == NULL) {
1523 device_printf(dev, "could not allocate memory resources.\n");
1528 error = bus_alloc_resources(dev, irq_res_spec, sc->irq_res);
1530 device_printf(dev, "could not allocate interrupt resources\n");
1535 * Set up TX descriptor ring, descriptors, and dma maps.
1537 error = bus_dma_tag_create(
1538 bus_get_dma_tag(dev), /* Parent tag. */
1539 FEC_DESC_RING_ALIGN, 0, /* alignment, boundary */
1540 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
1541 BUS_SPACE_MAXADDR, /* highaddr */
1542 NULL, NULL, /* filter, filterarg */
1543 TX_DESC_SIZE, 1, /* maxsize, nsegments */
1544 TX_DESC_SIZE, /* maxsegsize */
1546 NULL, NULL, /* lockfunc, lockarg */
1549 device_printf(sc->dev,
1550 "could not create TX ring DMA tag.\n");
1554 error = bus_dmamem_alloc(sc->txdesc_tag, (void**)&sc->txdesc_ring,
1555 BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO, &sc->txdesc_map);
1557 device_printf(sc->dev,
1558 "could not allocate TX descriptor ring.\n");
1562 error = bus_dmamap_load(sc->txdesc_tag, sc->txdesc_map, sc->txdesc_ring,
1563 TX_DESC_SIZE, ffec_get1paddr, &sc->txdesc_ring_paddr, 0);
1565 device_printf(sc->dev,
1566 "could not load TX descriptor ring map.\n");
1570 error = bus_dma_tag_create(
1571 bus_get_dma_tag(dev), /* Parent tag. */
1572 sc->txbuf_align, 0, /* alignment, boundary */
1573 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
1574 BUS_SPACE_MAXADDR, /* highaddr */
1575 NULL, NULL, /* filter, filterarg */
1576 MCLBYTES, 1, /* maxsize, nsegments */
1577 MCLBYTES, /* maxsegsize */
1579 NULL, NULL, /* lockfunc, lockarg */
1582 device_printf(sc->dev,
1583 "could not create TX ring DMA tag.\n");
1587 for (idx = 0; idx < TX_DESC_COUNT; ++idx) {
1588 error = bus_dmamap_create(sc->txbuf_tag, 0,
1589 &sc->txbuf_map[idx].map);
1591 device_printf(sc->dev,
1592 "could not create TX buffer DMA map.\n");
1595 ffec_setup_txdesc(sc, idx, 0, 0);
1599 * Set up RX descriptor ring, descriptors, dma maps, and mbufs.
1601 error = bus_dma_tag_create(
1602 bus_get_dma_tag(dev), /* Parent tag. */
1603 FEC_DESC_RING_ALIGN, 0, /* alignment, boundary */
1604 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
1605 BUS_SPACE_MAXADDR, /* highaddr */
1606 NULL, NULL, /* filter, filterarg */
1607 RX_DESC_SIZE, 1, /* maxsize, nsegments */
1608 RX_DESC_SIZE, /* maxsegsize */
1610 NULL, NULL, /* lockfunc, lockarg */
1613 device_printf(sc->dev,
1614 "could not create RX ring DMA tag.\n");
1618 error = bus_dmamem_alloc(sc->rxdesc_tag, (void **)&sc->rxdesc_ring,
1619 BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO, &sc->rxdesc_map);
1621 device_printf(sc->dev,
1622 "could not allocate RX descriptor ring.\n");
1626 error = bus_dmamap_load(sc->rxdesc_tag, sc->rxdesc_map, sc->rxdesc_ring,
1627 RX_DESC_SIZE, ffec_get1paddr, &sc->rxdesc_ring_paddr, 0);
1629 device_printf(sc->dev,
1630 "could not load RX descriptor ring map.\n");
1634 error = bus_dma_tag_create(
1635 bus_get_dma_tag(dev), /* Parent tag. */
1636 1, 0, /* alignment, boundary */
1637 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
1638 BUS_SPACE_MAXADDR, /* highaddr */
1639 NULL, NULL, /* filter, filterarg */
1640 MCLBYTES, 1, /* maxsize, nsegments */
1641 MCLBYTES, /* maxsegsize */
1643 NULL, NULL, /* lockfunc, lockarg */
1646 device_printf(sc->dev,
1647 "could not create RX buf DMA tag.\n");
1651 for (idx = 0; idx < RX_DESC_COUNT; ++idx) {
1652 error = bus_dmamap_create(sc->rxbuf_tag, 0,
1653 &sc->rxbuf_map[idx].map);
1655 device_printf(sc->dev,
1656 "could not create RX buffer DMA map.\n");
1659 if ((m = ffec_alloc_mbufcl(sc)) == NULL) {
1660 device_printf(dev, "Could not alloc mbuf\n");
1664 if ((error = ffec_setup_rxbuf(sc, idx, m)) != 0) {
1665 device_printf(sc->dev,
1666 "could not create new RX buffer.\n");
1671 /* Try to get the MAC address from the hardware before resetting it. */
1672 ffec_get_hwaddr(sc, eaddr);
1675 * Reset the hardware. Disables all interrupts.
1677 * When the FEC is connected to the AXI bus (indicated by AVB flag), a
1678 * MAC reset while a bus transaction is pending can hang the bus.
1679 * Instead of resetting, turn off the ENABLE bit, which allows the
1680 * hardware to complete any in-progress transfers (appending a bad CRC
1681 * to any partial packet) and release the AXI bus. This could probably
1682 * be done unconditionally for all hardware variants, but that hasn't
1685 if (sc->fecflags & FECFLAG_AVB)
1686 WR4(sc, FEC_ECR_REG, 0);
1688 WR4(sc, FEC_ECR_REG, FEC_ECR_RESET);
1690 /* Setup interrupt handler. */
1691 for (irq = 0; irq < MAX_IRQ_COUNT; ++irq) {
1692 if (sc->irq_res[irq] != NULL) {
1693 error = bus_setup_intr(dev, sc->irq_res[irq],
1694 INTR_TYPE_NET | INTR_MPSAFE, NULL, ffec_intr, sc,
1695 &sc->intr_cookie[irq]);
1698 "could not setup interrupt handler.\n");
1705 * Set up the PHY control register.
1707 * Speed formula for ENET is md_clock = mac_clock / ((N + 1) * 2).
1708 * Speed formula for FEC is md_clock = mac_clock / (N * 2)
1710 * XXX - Revisit this...
1712 * For a Wandboard imx6 (ENET) I was originally using 4, but the uboot
1713 * code uses 10. Both values seem to work, but I suspect many modern
1714 * PHY parts can do mdio at speeds far above the standard 2.5 MHz.
1716 * Different imx manuals use confusingly different terminology (things
1717 * like "system clock" and "internal module clock") with examples that
1718 * use frequencies that have nothing to do with ethernet, giving the
1719 * vague impression that maybe the clock in question is the periphclock
1720 * or something. In fact, on an imx53 development board (FEC),
1721 * measuring the mdio clock at the pin on the PHY and playing with
1722 * various divisors showed that the root speed was 66 MHz (clk_ipg_root
1723 * aka periphclock) and 13 was the right divisor.
1725 * All in all, it seems likely that 13 is a safe divisor for now,
1726 * because if we really do need to base it on the peripheral clock
1727 * speed, then we need a platform-independant get-clock-freq API.
1729 mscr = 13 << FEC_MSCR_MII_SPEED_SHIFT;
1730 if (OF_hasprop(ofw_node, "phy-disable-preamble")) {
1731 mscr |= FEC_MSCR_DIS_PRE;
1733 device_printf(dev, "PHY preamble disabled\n");
1735 WR4(sc, FEC_MSCR_REG, mscr);
1737 /* Set up the ethernet interface. */
1738 sc->ifp = ifp = if_alloc(IFT_ETHER);
1741 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1742 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1743 ifp->if_capabilities = IFCAP_VLAN_MTU;
1744 ifp->if_capenable = ifp->if_capabilities;
1745 ifp->if_start = ffec_txstart;
1746 ifp->if_ioctl = ffec_ioctl;
1747 ifp->if_init = ffec_init;
1748 IFQ_SET_MAXLEN(&ifp->if_snd, TX_DESC_COUNT - 1);
1749 ifp->if_snd.ifq_drv_maxlen = TX_DESC_COUNT - 1;
1750 IFQ_SET_READY(&ifp->if_snd);
1751 ifp->if_hdrlen = sizeof(struct ether_vlan_header);
1753 #if 0 /* XXX The hardware keeps stats we could use for these. */
1754 ifp->if_linkmib = &sc->mibdata;
1755 ifp->if_linkmiblen = sizeof(sc->mibdata);
1758 /* Set up the miigasket hardware (if any). */
1759 ffec_miigasket_setup(sc);
1761 /* Attach the mii driver. */
1762 if (fdt_get_phyaddr(ofw_node, dev, &phynum, &dummy) != 0) {
1763 phynum = MII_PHY_ANY;
1765 error = mii_attach(dev, &sc->miibus, ifp, ffec_media_change,
1766 ffec_media_status, BMSR_DEFCAPMASK, phynum, MII_OFFSET_ANY,
1767 (sc->fecflags & FECTYPE_MVF) ? MIIF_FORCEANEG : 0);
1769 device_printf(dev, "PHY attach failed\n");
1772 sc->mii_softc = device_get_softc(sc->miibus);
1774 /* All ready to run, attach the ethernet interface. */
1775 ether_ifattach(ifp, eaddr);
1776 sc->is_attached = true;
1788 ffec_probe(device_t dev)
1792 if (!ofw_bus_status_okay(dev))
1795 fectype = ofw_bus_search_compatible(dev, compat_data)->ocd_data;
1796 if (fectype == FECTYPE_NONE)
1799 device_set_desc(dev, (fectype & FECFLAG_GBE) ?
1800 "Freescale Gigabit Ethernet Controller" :
1801 "Freescale Fast Ethernet Controller");
1803 return (BUS_PROBE_DEFAULT);
1807 static device_method_t ffec_methods[] = {
1808 /* Device interface. */
1809 DEVMETHOD(device_probe, ffec_probe),
1810 DEVMETHOD(device_attach, ffec_attach),
1811 DEVMETHOD(device_detach, ffec_detach),
1814 DEVMETHOD(device_shutdown, ffec_shutdown),
1815 DEVMETHOD(device_suspend, ffec_suspend),
1816 DEVMETHOD(device_resume, ffec_resume),
1819 /* MII interface. */
1820 DEVMETHOD(miibus_readreg, ffec_miibus_readreg),
1821 DEVMETHOD(miibus_writereg, ffec_miibus_writereg),
1822 DEVMETHOD(miibus_statchg, ffec_miibus_statchg),
1827 static driver_t ffec_driver = {
1830 sizeof(struct ffec_softc)
1833 static devclass_t ffec_devclass;
1835 DRIVER_MODULE(ffec, simplebus, ffec_driver, ffec_devclass, 0, 0);
1836 DRIVER_MODULE(miibus, ffec, miibus_driver, miibus_devclass, 0, 0);
1838 MODULE_DEPEND(ffec, ether, 1, 1, 1);
1839 MODULE_DEPEND(ffec, miibus, 1, 1, 1);