2 * Copyright (c) 2003 Hidetoshi Shimokawa
3 * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the acknowledgement as bellow:
17 * This product includes software developed by K. Kobayashi and H. Shimokawa
19 * 4. The name of the author may not be used to endorse or promote products
20 * derived from this software without specific prior written permission.
22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
25 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
26 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
27 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
30 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
31 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
32 * POSSIBILITY OF SUCH DAMAGE.
45 #include <sys/param.h>
46 #include <sys/systm.h>
48 #include <sys/malloc.h>
49 #include <sys/sockio.h>
50 #include <sys/sysctl.h>
52 #include <sys/kernel.h>
54 #include <sys/endian.h>
57 #include <machine/bus.h>
59 #if defined(__DragonFly__) || __FreeBSD_version < 500000
60 #include <machine/clock.h> /* for DELAY() */
65 #include "firewirereg.h"
67 #include "fwohcireg.h"
68 #include "fwohcivar.h"
69 #include "firewire_phy.h"
71 #include <dev/firewire/firewire.h>
72 #include <dev/firewire/firewirereg.h>
73 #include <dev/firewire/fwdma.h>
74 #include <dev/firewire/fwohcireg.h>
75 #include <dev/firewire/fwohcivar.h>
76 #include <dev/firewire/firewire_phy.h>
81 static int nocyclemaster = 0;
82 int firewire_phydma_enable = 1;
83 SYSCTL_DECL(_hw_firewire);
84 SYSCTL_INT(_hw_firewire, OID_AUTO, nocyclemaster, CTLFLAG_RW, &nocyclemaster, 0,
85 "Do not send cycle start packets");
86 SYSCTL_INT(_hw_firewire, OID_AUTO, phydma_enable, CTLFLAG_RW,
87 &firewire_phydma_enable, 1, "Allow physical request DMA from firewire");
88 TUNABLE_INT("hw.firewire.phydma_enable", &firewire_phydma_enable);
90 static char dbcode[16][0x10]={"OUTM", "OUTL","INPM","INPL",
91 "STOR","LOAD","NOP ","STOP",};
93 static char dbkey[8][0x10]={"ST0", "ST1","ST2","ST3",
94 "UNDEF","REG","SYS","DEV"};
95 static char dbcond[4][0x10]={"NEV","C=1", "C=0", "ALL"};
96 char fwohcicode[32][0x20]={
97 "No stat","Undef","long","miss Ack err",
98 "FIFO underrun","FIFO overrun","desc err", "data read err",
99 "data write err","bus reset","timeout","tcode err",
100 "Undef","Undef","unknown event","flushed",
101 "Undef","ack complete","ack pend","Undef",
102 "ack busy_X","ack busy_A","ack busy_B","Undef",
103 "Undef","Undef","Undef","ack tardy",
104 "Undef","ack data_err","ack type_err",""};
107 extern char *linkspeed[];
108 uint32_t tagbit[4] = { 1 << 28, 1 << 29, 1 << 30, 1 << 31};
110 static struct tcode_info tinfo[] = {
111 /* hdr_len block flag valid_response */
112 /* 0 WREQQ */ {16, FWTI_REQ | FWTI_TLABEL, FWTCODE_WRES},
113 /* 1 WREQB */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY, FWTCODE_WRES},
114 /* 2 WRES */ {12, FWTI_RES, 0xff},
115 /* 3 XXX */ { 0, 0, 0xff},
116 /* 4 RREQQ */ {12, FWTI_REQ | FWTI_TLABEL, FWTCODE_RRESQ},
117 /* 5 RREQB */ {16, FWTI_REQ | FWTI_TLABEL, FWTCODE_RRESB},
118 /* 6 RRESQ */ {16, FWTI_RES, 0xff},
119 /* 7 RRESB */ {16, FWTI_RES | FWTI_BLOCK_ASY, 0xff},
120 /* 8 CYCS */ { 0, 0, 0xff},
121 /* 9 LREQ */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY, FWTCODE_LRES},
122 /* a STREAM */ { 4, FWTI_REQ | FWTI_BLOCK_STR, 0xff},
123 /* b LRES */ {16, FWTI_RES | FWTI_BLOCK_ASY, 0xff},
124 /* c XXX */ { 0, 0, 0xff},
125 /* d XXX */ { 0, 0, 0xff},
126 /* e PHY */ {12, FWTI_REQ, 0xff},
127 /* f XXX */ { 0, 0, 0xff}
130 #define OHCI_WRITE_SIGMASK 0xffff0000
131 #define OHCI_READ_SIGMASK 0xffff0000
133 #define OWRITE(sc, r, x) bus_space_write_4((sc)->bst, (sc)->bsh, (r), (x))
134 #define OREAD(sc, r) bus_space_read_4((sc)->bst, (sc)->bsh, (r))
136 static void fwohci_ibr (struct firewire_comm *);
137 static void fwohci_db_init (struct fwohci_softc *, struct fwohci_dbch *);
138 static void fwohci_db_free (struct fwohci_dbch *);
139 static void fwohci_arcv (struct fwohci_softc *, struct fwohci_dbch *, int);
140 static void fwohci_txd (struct fwohci_softc *, struct fwohci_dbch *);
141 static void fwohci_start_atq (struct firewire_comm *);
142 static void fwohci_start_ats (struct firewire_comm *);
143 static void fwohci_start (struct fwohci_softc *, struct fwohci_dbch *);
144 static uint32_t fwphy_wrdata ( struct fwohci_softc *, uint32_t, uint32_t);
145 static uint32_t fwphy_rddata ( struct fwohci_softc *, uint32_t);
146 static int fwohci_rx_enable (struct fwohci_softc *, struct fwohci_dbch *);
147 static int fwohci_tx_enable (struct fwohci_softc *, struct fwohci_dbch *);
148 static int fwohci_irx_enable (struct firewire_comm *, int);
149 static int fwohci_irx_disable (struct firewire_comm *, int);
150 #if BYTE_ORDER == BIG_ENDIAN
151 static void fwohci_irx_post (struct firewire_comm *, uint32_t *);
153 static int fwohci_itxbuf_enable (struct firewire_comm *, int);
154 static int fwohci_itx_disable (struct firewire_comm *, int);
155 static void fwohci_timeout (void *);
156 static void fwohci_set_intr (struct firewire_comm *, int);
158 static int fwohci_add_rx_buf (struct fwohci_dbch *, struct fwohcidb_tr *, int, struct fwdma_alloc *);
159 static int fwohci_add_tx_buf (struct fwohci_dbch *, struct fwohcidb_tr *, int);
160 static void dump_db (struct fwohci_softc *, uint32_t);
161 static void print_db (struct fwohcidb_tr *, struct fwohcidb *, uint32_t , uint32_t);
162 static void dump_dma (struct fwohci_softc *, uint32_t);
163 static uint32_t fwohci_cyctimer (struct firewire_comm *);
164 static void fwohci_rbuf_update (struct fwohci_softc *, int);
165 static void fwohci_tbuf_update (struct fwohci_softc *, int);
166 void fwohci_txbufdb (struct fwohci_softc *, int , struct fw_bulkxfer *);
167 static void fwohci_task_busreset(void *, int);
168 static void fwohci_task_sid(void *, int);
169 static void fwohci_task_dma(void *, int);
172 * memory allocated for DMA programs
174 #define DMA_PROG_ALLOC (8 * PAGE_SIZE)
176 #define NDB FWMAXQUEUE
178 #define OHCI_VERSION 0x00
179 #define OHCI_ATRETRY 0x08
180 #define OHCI_CROMHDR 0x18
181 #define OHCI_BUS_OPT 0x20
182 #define OHCI_BUSIRMC (1 << 31)
183 #define OHCI_BUSCMC (1 << 30)
184 #define OHCI_BUSISC (1 << 29)
185 #define OHCI_BUSBMC (1 << 28)
186 #define OHCI_BUSPMC (1 << 27)
187 #define OHCI_BUSFNC OHCI_BUSIRMC | OHCI_BUSCMC | OHCI_BUSISC |\
188 OHCI_BUSBMC | OHCI_BUSPMC
190 #define OHCI_EUID_HI 0x24
191 #define OHCI_EUID_LO 0x28
193 #define OHCI_CROMPTR 0x34
194 #define OHCI_HCCCTL 0x50
195 #define OHCI_HCCCTLCLR 0x54
196 #define OHCI_AREQHI 0x100
197 #define OHCI_AREQHICLR 0x104
198 #define OHCI_AREQLO 0x108
199 #define OHCI_AREQLOCLR 0x10c
200 #define OHCI_PREQHI 0x110
201 #define OHCI_PREQHICLR 0x114
202 #define OHCI_PREQLO 0x118
203 #define OHCI_PREQLOCLR 0x11c
204 #define OHCI_PREQUPPER 0x120
206 #define OHCI_SID_BUF 0x64
207 #define OHCI_SID_CNT 0x68
208 #define OHCI_SID_ERR (1 << 31)
209 #define OHCI_SID_CNT_MASK 0xffc
211 #define OHCI_IT_STAT 0x90
212 #define OHCI_IT_STATCLR 0x94
213 #define OHCI_IT_MASK 0x98
214 #define OHCI_IT_MASKCLR 0x9c
216 #define OHCI_IR_STAT 0xa0
217 #define OHCI_IR_STATCLR 0xa4
218 #define OHCI_IR_MASK 0xa8
219 #define OHCI_IR_MASKCLR 0xac
221 #define OHCI_LNKCTL 0xe0
222 #define OHCI_LNKCTLCLR 0xe4
224 #define OHCI_PHYACCESS 0xec
225 #define OHCI_CYCLETIMER 0xf0
227 #define OHCI_DMACTL(off) (off)
228 #define OHCI_DMACTLCLR(off) (off + 4)
229 #define OHCI_DMACMD(off) (off + 0xc)
230 #define OHCI_DMAMATCH(off) (off + 0x10)
232 #define OHCI_ATQOFF 0x180
233 #define OHCI_ATQCTL OHCI_ATQOFF
234 #define OHCI_ATQCTLCLR (OHCI_ATQOFF + 4)
235 #define OHCI_ATQCMD (OHCI_ATQOFF + 0xc)
236 #define OHCI_ATQMATCH (OHCI_ATQOFF + 0x10)
238 #define OHCI_ATSOFF 0x1a0
239 #define OHCI_ATSCTL OHCI_ATSOFF
240 #define OHCI_ATSCTLCLR (OHCI_ATSOFF + 4)
241 #define OHCI_ATSCMD (OHCI_ATSOFF + 0xc)
242 #define OHCI_ATSMATCH (OHCI_ATSOFF + 0x10)
244 #define OHCI_ARQOFF 0x1c0
245 #define OHCI_ARQCTL OHCI_ARQOFF
246 #define OHCI_ARQCTLCLR (OHCI_ARQOFF + 4)
247 #define OHCI_ARQCMD (OHCI_ARQOFF + 0xc)
248 #define OHCI_ARQMATCH (OHCI_ARQOFF + 0x10)
250 #define OHCI_ARSOFF 0x1e0
251 #define OHCI_ARSCTL OHCI_ARSOFF
252 #define OHCI_ARSCTLCLR (OHCI_ARSOFF + 4)
253 #define OHCI_ARSCMD (OHCI_ARSOFF + 0xc)
254 #define OHCI_ARSMATCH (OHCI_ARSOFF + 0x10)
256 #define OHCI_ITOFF(CH) (0x200 + 0x10 * (CH))
257 #define OHCI_ITCTL(CH) (OHCI_ITOFF(CH))
258 #define OHCI_ITCTLCLR(CH) (OHCI_ITOFF(CH) + 4)
259 #define OHCI_ITCMD(CH) (OHCI_ITOFF(CH) + 0xc)
261 #define OHCI_IROFF(CH) (0x400 + 0x20 * (CH))
262 #define OHCI_IRCTL(CH) (OHCI_IROFF(CH))
263 #define OHCI_IRCTLCLR(CH) (OHCI_IROFF(CH) + 4)
264 #define OHCI_IRCMD(CH) (OHCI_IROFF(CH) + 0xc)
265 #define OHCI_IRMATCH(CH) (OHCI_IROFF(CH) + 0x10)
267 d_ioctl_t fwohci_ioctl;
270 * Communication with PHY device
272 /* XXX need lock for phy access */
274 fwphy_wrdata( struct fwohci_softc *sc, uint32_t addr, uint32_t data)
281 fun = (PHYDEV_WRCMD | (addr << PHYDEV_REGADDR) | (data << PHYDEV_WRDATA));
282 OWRITE(sc, OHCI_PHYACCESS, fun);
285 return(fwphy_rddata( sc, addr));
289 fwohci_set_bus_manager(struct firewire_comm *fc, u_int node)
291 struct fwohci_softc *sc = (struct fwohci_softc *)fc;
295 #define OHCI_CSR_DATA 0x0c
296 #define OHCI_CSR_COMP 0x10
297 #define OHCI_CSR_CONT 0x14
298 #define OHCI_BUS_MANAGER_ID 0
300 OWRITE(sc, OHCI_CSR_DATA, node);
301 OWRITE(sc, OHCI_CSR_COMP, 0x3f);
302 OWRITE(sc, OHCI_CSR_CONT, OHCI_BUS_MANAGER_ID);
303 for (i = 0; !(OREAD(sc, OHCI_CSR_CONT) & (1<<31)) && (i < 1000); i++)
305 bm = OREAD(sc, OHCI_CSR_DATA);
306 if((bm & 0x3f) == 0x3f)
309 device_printf(sc->fc.dev, "%s: %d->%d (loop=%d)\n",
310 __func__, bm, node, i);
316 fwphy_rddata(struct fwohci_softc *sc, u_int addr)
322 #define MAX_RETRY 100
324 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_REG_FAIL);
325 fun = PHYDEV_RDCMD | (addr << PHYDEV_REGADDR);
326 OWRITE(sc, OHCI_PHYACCESS, fun);
327 for ( i = 0 ; i < MAX_RETRY ; i ++ ){
328 fun = OREAD(sc, OHCI_PHYACCESS);
329 if ((fun & PHYDEV_RDCMD) == 0 && (fun & PHYDEV_RDDONE) != 0)
335 device_printf(sc->fc.dev, "%s: failed(1).\n", __func__);
336 if (++retry < MAX_RETRY) {
341 /* Make sure that SCLK is started */
342 stat = OREAD(sc, FWOHCI_INTSTAT);
343 if ((stat & OHCI_INT_REG_FAIL) != 0 ||
344 ((fun >> PHYDEV_REGADDR) & 0xf) != addr) {
346 device_printf(sc->fc.dev, "%s: failed(2).\n", __func__);
347 if (++retry < MAX_RETRY) {
352 if (firewire_debug > 1 || retry >= MAX_RETRY)
353 device_printf(sc->fc.dev,
354 "%s:: 0x%x loop=%d, retry=%d\n",
355 __func__, addr, i, retry);
357 return((fun >> PHYDEV_RDDATA )& 0xff);
359 /* Device specific ioctl. */
361 fwohci_ioctl (struct cdev *dev, u_long cmd, caddr_t data, int flag, fw_proc *td)
363 struct firewire_softc *sc;
364 struct fwohci_softc *fc;
365 int unit = DEV2UNIT(dev);
367 struct fw_reg_req_t *reg = (struct fw_reg_req_t *) data;
368 uint32_t *dmach = (uint32_t *) data;
370 sc = devclass_get_softc(firewire_devclass, unit);
374 fc = (struct fwohci_softc *)sc->fc;
381 #define OHCI_MAX_REG 0x800
382 if(reg->addr <= OHCI_MAX_REG){
383 OWRITE(fc, reg->addr, reg->data);
384 reg->data = OREAD(fc, reg->addr);
390 if(reg->addr <= OHCI_MAX_REG){
391 reg->data = OREAD(fc, reg->addr);
396 /* Read DMA descriptors for debug */
398 if(*dmach <= OHCI_MAX_DMA_CH ){
399 dump_dma(fc, *dmach);
405 /* Read/Write Phy registers */
406 #define OHCI_MAX_PHY_REG 0xf
407 case FWOHCI_RDPHYREG:
408 if (reg->addr <= OHCI_MAX_PHY_REG)
409 reg->data = fwphy_rddata(fc, reg->addr);
413 case FWOHCI_WRPHYREG:
414 if (reg->addr <= OHCI_MAX_PHY_REG)
415 reg->data = fwphy_wrdata(fc, reg->addr, reg->data);
427 fwohci_probe_phy(struct fwohci_softc *sc, device_t dev)
432 * probe PHY parameters
433 * 0. to prove PHY version, whether compliance of 1394a.
434 * 1. to probe maximum speed supported by the PHY and
435 * number of port supported by core-logic.
436 * It is not actually available port on your PC .
438 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS);
441 reg = fwphy_rddata(sc, FW_PHY_SPD_REG);
443 if((reg >> 5) != 7 ){
444 sc->fc.mode &= ~FWPHYASYST;
445 sc->fc.nport = reg & FW_PHY_NP;
446 sc->fc.speed = reg & FW_PHY_SPD >> 6;
447 if (sc->fc.speed > MAX_SPEED) {
448 device_printf(dev, "invalid speed %d (fixed to %d).\n",
449 sc->fc.speed, MAX_SPEED);
450 sc->fc.speed = MAX_SPEED;
453 "Phy 1394 only %s, %d ports.\n",
454 linkspeed[sc->fc.speed], sc->fc.nport);
456 reg2 = fwphy_rddata(sc, FW_PHY_ESPD_REG);
457 sc->fc.mode |= FWPHYASYST;
458 sc->fc.nport = reg & FW_PHY_NP;
459 sc->fc.speed = (reg2 & FW_PHY_ESPD) >> 5;
460 if (sc->fc.speed > MAX_SPEED) {
461 device_printf(dev, "invalid speed %d (fixed to %d).\n",
462 sc->fc.speed, MAX_SPEED);
463 sc->fc.speed = MAX_SPEED;
466 "Phy 1394a available %s, %d ports.\n",
467 linkspeed[sc->fc.speed], sc->fc.nport);
469 /* check programPhyEnable */
470 reg2 = fwphy_rddata(sc, 5);
472 if (e1394a && (OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_PRPHY)) {
473 #else /* XXX force to enable 1394a */
478 "Enable 1394a Enhancements\n");
481 /* set aPhyEnhanceEnable */
482 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_PHYEN);
483 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_PRPHY);
488 reg2 = fwphy_wrdata(sc, 5, reg2);
491 reg = fwphy_rddata(sc, FW_PHY_SPD_REG);
492 if((reg >> 5) == 7 ){
493 reg = fwphy_rddata(sc, 4);
495 fwphy_wrdata(sc, 4, reg);
496 reg = fwphy_rddata(sc, 4);
503 fwohci_reset(struct fwohci_softc *sc, device_t dev)
505 int i, max_rec, speed;
507 struct fwohcidb_tr *db_tr;
509 /* Disable interrupts */
510 OWRITE(sc, FWOHCI_INTMASKCLR, ~0);
512 /* Now stopping all DMA channels */
513 OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN);
514 OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN);
515 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN);
516 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN);
518 OWRITE(sc, OHCI_IR_MASKCLR, ~0);
519 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){
520 OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN);
521 OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN);
524 /* FLUSH FIFO and reset Transmitter/Reciever */
525 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET);
527 device_printf(dev, "resetting OHCI...");
529 while(OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_RESET) {
530 if (i++ > 100) break;
534 printf("done (loop=%d)\n", i);
537 fwohci_probe_phy(sc, dev);
540 reg = OREAD(sc, OHCI_BUS_OPT);
541 reg2 = reg | OHCI_BUSFNC;
542 max_rec = (reg & 0x0000f000) >> 12;
543 speed = (reg & 0x00000007);
544 device_printf(dev, "Link %s, max_rec %d bytes.\n",
545 linkspeed[speed], MAXREC(max_rec));
546 /* XXX fix max_rec */
547 sc->fc.maxrec = sc->fc.speed + 8;
548 if (max_rec != sc->fc.maxrec) {
549 reg2 = (reg2 & 0xffff0fff) | (sc->fc.maxrec << 12);
550 device_printf(dev, "max_rec %d -> %d\n",
551 MAXREC(max_rec), MAXREC(sc->fc.maxrec));
554 device_printf(dev, "BUS_OPT 0x%x -> 0x%x\n", reg, reg2);
555 OWRITE(sc, OHCI_BUS_OPT, reg2);
557 /* Initialize registers */
558 OWRITE(sc, OHCI_CROMHDR, sc->fc.config_rom[0]);
559 OWRITE(sc, OHCI_CROMPTR, sc->crom_dma.bus_addr);
560 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_BIGEND);
561 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_POSTWR);
562 OWRITE(sc, OHCI_SID_BUF, sc->sid_dma.bus_addr);
563 OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_SID);
566 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LINKEN);
568 /* Force to start async RX DMA */
569 sc->arrq.xferq.flag &= ~FWXFERQ_RUNNING;
570 sc->arrs.xferq.flag &= ~FWXFERQ_RUNNING;
571 fwohci_rx_enable(sc, &sc->arrq);
572 fwohci_rx_enable(sc, &sc->arrs);
574 /* Initialize async TX */
575 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD);
576 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD);
579 OWRITE(sc, FWOHCI_RETRY,
580 /* CycleLimit PhyRespRetries ATRespRetries ATReqRetries */
581 (0xffff << 16 ) | (0x0f << 8) | (0x0f << 4) | 0x0f) ;
583 sc->atrq.top = STAILQ_FIRST(&sc->atrq.db_trq);
584 sc->atrs.top = STAILQ_FIRST(&sc->atrs.db_trq);
585 sc->atrq.bottom = sc->atrq.top;
586 sc->atrs.bottom = sc->atrs.top;
588 for( i = 0, db_tr = sc->atrq.top; i < sc->atrq.ndb ;
589 i ++, db_tr = STAILQ_NEXT(db_tr, link)){
592 for( i = 0, db_tr = sc->atrs.top; i < sc->atrs.ndb ;
593 i ++, db_tr = STAILQ_NEXT(db_tr, link)){
598 /* Enable interrupts */
599 sc->intmask = (OHCI_INT_ERR | OHCI_INT_PHY_SID
600 | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS
601 | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS
602 | OHCI_INT_PHY_BUS_R | OHCI_INT_PW_ERR);
603 sc->intmask |= OHCI_INT_DMA_IR | OHCI_INT_DMA_IT;
604 sc->intmask |= OHCI_INT_CYC_LOST | OHCI_INT_PHY_INT;
605 OWRITE(sc, FWOHCI_INTMASK, sc->intmask);
606 fwohci_set_intr(&sc->fc, 1);
611 fwohci_init(struct fwohci_softc *sc, device_t dev)
618 reg = OREAD(sc, OHCI_VERSION);
619 mver = (reg >> 16) & 0xff;
620 device_printf(dev, "OHCI version %x.%x (ROM=%d)\n",
621 mver, reg & 0xff, (reg>>24) & 1);
622 if (mver < 1 || mver > 9) {
623 device_printf(dev, "invalid OHCI version\n");
627 /* Available Isochronous DMA channel probe */
628 OWRITE(sc, OHCI_IT_MASK, 0xffffffff);
629 OWRITE(sc, OHCI_IR_MASK, 0xffffffff);
630 reg = OREAD(sc, OHCI_IT_MASK) & OREAD(sc, OHCI_IR_MASK);
631 OWRITE(sc, OHCI_IT_MASKCLR, 0xffffffff);
632 OWRITE(sc, OHCI_IR_MASKCLR, 0xffffffff);
633 for (i = 0; i < 0x20; i++)
634 if ((reg & (1 << i)) == 0)
637 device_printf(dev, "No. of Isochronous channels is %d.\n", i);
641 sc->fc.arq = &sc->arrq.xferq;
642 sc->fc.ars = &sc->arrs.xferq;
643 sc->fc.atq = &sc->atrq.xferq;
644 sc->fc.ats = &sc->atrs.xferq;
646 sc->arrq.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE);
647 sc->arrs.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE);
648 sc->atrq.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE);
649 sc->atrs.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE);
651 sc->arrq.xferq.start = NULL;
652 sc->arrs.xferq.start = NULL;
653 sc->atrq.xferq.start = fwohci_start_atq;
654 sc->atrs.xferq.start = fwohci_start_ats;
656 sc->arrq.xferq.buf = NULL;
657 sc->arrs.xferq.buf = NULL;
658 sc->atrq.xferq.buf = NULL;
659 sc->atrs.xferq.buf = NULL;
661 sc->arrq.xferq.dmach = -1;
662 sc->arrs.xferq.dmach = -1;
663 sc->atrq.xferq.dmach = -1;
664 sc->atrs.xferq.dmach = -1;
668 sc->atrq.ndesc = 8; /* equal to maximum of mbuf chains */
672 sc->arrs.ndb = NDB / 2;
674 sc->atrs.ndb = NDB / 2;
676 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){
677 sc->fc.it[i] = &sc->it[i].xferq;
678 sc->fc.ir[i] = &sc->ir[i].xferq;
679 sc->it[i].xferq.dmach = i;
680 sc->ir[i].xferq.dmach = i;
685 sc->fc.tcode = tinfo;
688 sc->fc.config_rom = fwdma_malloc(&sc->fc, CROMSIZE, CROMSIZE,
689 &sc->crom_dma, BUS_DMA_WAITOK | BUS_DMA_COHERENT);
690 if(sc->fc.config_rom == NULL){
691 device_printf(dev, "config_rom alloc failed.");
696 bzero(&sc->fc.config_rom[0], CROMSIZE);
697 sc->fc.config_rom[1] = 0x31333934;
698 sc->fc.config_rom[2] = 0xf000a002;
699 sc->fc.config_rom[3] = OREAD(sc, OHCI_EUID_HI);
700 sc->fc.config_rom[4] = OREAD(sc, OHCI_EUID_LO);
701 sc->fc.config_rom[5] = 0;
702 sc->fc.config_rom[0] = (4 << 24) | (5 << 16);
704 sc->fc.config_rom[0] |= fw_crc16(&sc->fc.config_rom[1], 5*4);
708 /* SID recieve buffer must align 2^11 */
709 #define OHCI_SIDSIZE (1 << 11)
710 sc->sid_buf = fwdma_malloc(&sc->fc, OHCI_SIDSIZE, OHCI_SIDSIZE,
711 &sc->sid_dma, BUS_DMA_WAITOK | BUS_DMA_COHERENT);
712 if (sc->sid_buf == NULL) {
713 device_printf(dev, "sid_buf alloc failed.");
717 fwdma_malloc(&sc->fc, sizeof(uint32_t), sizeof(uint32_t),
718 &sc->dummy_dma, BUS_DMA_WAITOK);
720 if (sc->dummy_dma.v_addr == NULL) {
721 device_printf(dev, "dummy_dma alloc failed.");
725 fwohci_db_init(sc, &sc->arrq);
726 if ((sc->arrq.flags & FWOHCI_DBCH_INIT) == 0)
729 fwohci_db_init(sc, &sc->arrs);
730 if ((sc->arrs.flags & FWOHCI_DBCH_INIT) == 0)
733 fwohci_db_init(sc, &sc->atrq);
734 if ((sc->atrq.flags & FWOHCI_DBCH_INIT) == 0)
737 fwohci_db_init(sc, &sc->atrs);
738 if ((sc->atrs.flags & FWOHCI_DBCH_INIT) == 0)
741 sc->fc.eui.hi = OREAD(sc, FWOHCIGUID_H);
742 sc->fc.eui.lo = OREAD(sc, FWOHCIGUID_L);
743 for( i = 0 ; i < 8 ; i ++)
744 ui[i] = FW_EUI64_BYTE(&sc->fc.eui,i);
745 device_printf(dev, "EUI64 %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n",
746 ui[0], ui[1], ui[2], ui[3], ui[4], ui[5], ui[6], ui[7]);
748 sc->fc.ioctl = fwohci_ioctl;
749 sc->fc.cyctimer = fwohci_cyctimer;
750 sc->fc.set_bmr = fwohci_set_bus_manager;
751 sc->fc.ibr = fwohci_ibr;
752 sc->fc.irx_enable = fwohci_irx_enable;
753 sc->fc.irx_disable = fwohci_irx_disable;
755 sc->fc.itx_enable = fwohci_itxbuf_enable;
756 sc->fc.itx_disable = fwohci_itx_disable;
757 #if BYTE_ORDER == BIG_ENDIAN
758 sc->fc.irx_post = fwohci_irx_post;
760 sc->fc.irx_post = NULL;
762 sc->fc.itx_post = NULL;
763 sc->fc.timeout = fwohci_timeout;
764 sc->fc.poll = fwohci_poll;
765 sc->fc.set_intr = fwohci_set_intr;
767 sc->intmask = sc->irstat = sc->itstat = 0;
769 /* Init task queue */
770 sc->fc.taskqueue = taskqueue_create_fast("fw_taskq", M_WAITOK,
771 taskqueue_thread_enqueue, &sc->fc.taskqueue);
772 taskqueue_start_threads(&sc->fc.taskqueue, 1, PI_NET, "fw%d_taskq",
773 device_get_unit(dev));
774 TASK_INIT(&sc->fwohci_task_busreset, 2, fwohci_task_busreset, sc);
775 TASK_INIT(&sc->fwohci_task_sid, 1, fwohci_task_sid, sc);
776 TASK_INIT(&sc->fwohci_task_dma, 0, fwohci_task_dma, sc);
779 fwohci_reset(sc, dev);
785 fwohci_timeout(void *arg)
787 struct fwohci_softc *sc;
789 sc = (struct fwohci_softc *)arg;
793 fwohci_cyctimer(struct firewire_comm *fc)
795 struct fwohci_softc *sc = (struct fwohci_softc *)fc;
796 return(OREAD(sc, OHCI_CYCLETIMER));
800 fwohci_detach(struct fwohci_softc *sc, device_t dev)
804 if (sc->sid_buf != NULL)
805 fwdma_free(&sc->fc, &sc->sid_dma);
806 if (sc->fc.config_rom != NULL)
807 fwdma_free(&sc->fc, &sc->crom_dma);
809 fwohci_db_free(&sc->arrq);
810 fwohci_db_free(&sc->arrs);
812 fwohci_db_free(&sc->atrq);
813 fwohci_db_free(&sc->atrs);
815 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){
816 fwohci_db_free(&sc->it[i]);
817 fwohci_db_free(&sc->ir[i]);
819 if (sc->fc.taskqueue != NULL) {
820 taskqueue_drain(sc->fc.taskqueue, &sc->fwohci_task_busreset);
821 taskqueue_drain(sc->fc.taskqueue, &sc->fwohci_task_sid);
822 taskqueue_drain(sc->fc.taskqueue, &sc->fwohci_task_dma);
823 taskqueue_drain(sc->fc.taskqueue, &sc->fc.task_timeout);
824 taskqueue_free(sc->fc.taskqueue);
825 sc->fc.taskqueue = NULL;
831 #define LAST_DB(dbtr, db) do { \
832 struct fwohcidb_tr *_dbtr = (dbtr); \
833 int _cnt = _dbtr->dbcnt; \
834 db = &_dbtr->db[ (_cnt > 2) ? (_cnt -1) : 0]; \
838 fwohci_execute_db(void *arg, bus_dma_segment_t *segs, int nseg, int error)
840 struct fwohcidb_tr *db_tr;
842 bus_dma_segment_t *s;
845 db_tr = (struct fwohcidb_tr *)arg;
846 db = &db_tr->db[db_tr->dbcnt];
848 if (firewire_debug || error != EFBIG)
849 printf("fwohci_execute_db: error=%d\n", error);
852 for (i = 0; i < nseg; i++) {
854 FWOHCI_DMA_WRITE(db->db.desc.addr, s->ds_addr);
855 FWOHCI_DMA_WRITE(db->db.desc.cmd, s->ds_len);
856 FWOHCI_DMA_WRITE(db->db.desc.res, 0);
863 fwohci_execute_db2(void *arg, bus_dma_segment_t *segs, int nseg,
864 bus_size_t size, int error)
866 fwohci_execute_db(arg, segs, nseg, error);
870 fwohci_start(struct fwohci_softc *sc, struct fwohci_dbch *dbch)
873 int tcode, hdr_len, pl_off;
876 struct fw_xfer *xfer;
878 struct fwohci_txpkthdr *ohcifp;
879 struct fwohcidb_tr *db_tr;
882 struct tcode_info *info;
883 static int maxdesc=0;
885 FW_GLOCK_ASSERT(&sc->fc);
887 if(&sc->atrq == dbch){
889 }else if(&sc->atrs == dbch){
895 if (dbch->flags & FWOHCI_DBCH_FULL)
901 xfer = STAILQ_FIRST(&dbch->xferq.q);
906 if(dbch->xferq.queued == 0 ){
907 device_printf(sc->fc.dev, "TX queue empty\n");
910 STAILQ_REMOVE_HEAD(&dbch->xferq.q, link);
912 xfer->flag = FWXF_START;
914 fp = &xfer->send.hdr;
915 tcode = fp->mode.common.tcode;
917 ohcifp = (struct fwohci_txpkthdr *) db_tr->db[1].db.immed;
918 info = &tinfo[tcode];
919 hdr_len = pl_off = info->hdr_len;
921 ld = &ohcifp->mode.ld[0];
922 ld[0] = ld[1] = ld[2] = ld[3] = 0;
923 for( i = 0 ; i < pl_off ; i+= 4)
924 ld[i/4] = fp->mode.ld[i/4];
926 ohcifp->mode.common.spd = xfer->send.spd & 0x7;
927 if (tcode == FWTCODE_STREAM ){
929 ohcifp->mode.stream.len = fp->mode.stream.len;
930 } else if (tcode == FWTCODE_PHY) {
932 ld[1] = fp->mode.ld[1];
933 ld[2] = fp->mode.ld[2];
934 ohcifp->mode.common.spd = 0;
935 ohcifp->mode.common.tcode = FWOHCITCODE_PHY;
937 ohcifp->mode.asycomm.dst = fp->mode.hdr.dst;
938 ohcifp->mode.asycomm.srcbus = OHCI_ASYSRCBUS;
939 ohcifp->mode.asycomm.tlrt |= FWRETRY_X;
942 FWOHCI_DMA_WRITE(db->db.desc.cmd,
943 OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | hdr_len);
944 FWOHCI_DMA_WRITE(db->db.desc.addr, 0);
945 FWOHCI_DMA_WRITE(db->db.desc.res, 0);
946 /* Specify bound timer of asy. responce */
947 if(&sc->atrs == dbch){
948 FWOHCI_DMA_WRITE(db->db.desc.res,
949 (OREAD(sc, OHCI_CYCLETIMER) >> 12) + (1 << 13));
951 #if BYTE_ORDER == BIG_ENDIAN
952 if (tcode == FWTCODE_WREQQ || tcode == FWTCODE_RRESQ)
954 for (i = 0; i < hdr_len/4; i ++)
955 FWOHCI_DMA_WRITE(ld[i], ld[i]);
960 db = &db_tr->db[db_tr->dbcnt];
961 if (xfer->send.pay_len > 0) {
964 if (xfer->mbuf == NULL) {
965 err = bus_dmamap_load(dbch->dmat, db_tr->dma_map,
966 &xfer->send.payload[0], xfer->send.pay_len,
967 fwohci_execute_db, db_tr,
970 /* XXX we can handle only 6 (=8-2) mbuf chains */
971 err = bus_dmamap_load_mbuf(dbch->dmat, db_tr->dma_map,
973 fwohci_execute_db2, db_tr,
979 device_printf(sc->fc.dev, "EFBIG.\n");
980 m0 = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
982 m_copydata(xfer->mbuf, 0,
983 xfer->mbuf->m_pkthdr.len,
985 m0->m_len = m0->m_pkthdr.len =
986 xfer->mbuf->m_pkthdr.len;
991 device_printf(sc->fc.dev, "m_getcl failed.\n");
995 printf("dmamap_load: err=%d\n", err);
996 bus_dmamap_sync(dbch->dmat, db_tr->dma_map,
997 BUS_DMASYNC_PREWRITE);
998 #if 0 /* OHCI_OUTPUT_MODE == 0 */
999 for (i = 2; i < db_tr->dbcnt; i++)
1000 FWOHCI_DMA_SET(db_tr->db[i].db.desc.cmd,
1004 if (maxdesc < db_tr->dbcnt) {
1005 maxdesc = db_tr->dbcnt;
1007 device_printf(sc->fc.dev, "%s: maxdesc %d\n", __func__, maxdesc);
1011 FWOHCI_DMA_SET(db->db.desc.cmd,
1012 OHCI_OUTPUT_LAST | OHCI_INTERRUPT_ALWAYS | OHCI_BRANCH_ALWAYS);
1013 FWOHCI_DMA_WRITE(db->db.desc.depend,
1014 STAILQ_NEXT(db_tr, link)->bus_addr);
1017 fsegment = db_tr->dbcnt;
1018 if (dbch->pdb_tr != NULL) {
1019 LAST_DB(dbch->pdb_tr, db);
1020 FWOHCI_DMA_SET(db->db.desc.depend, db_tr->dbcnt);
1022 dbch->xferq.queued ++;
1023 dbch->pdb_tr = db_tr;
1024 db_tr = STAILQ_NEXT(db_tr, link);
1025 if(db_tr != dbch->bottom){
1028 device_printf(sc->fc.dev, "fwohci_start: lack of db_trq\n");
1029 dbch->flags |= FWOHCI_DBCH_FULL;
1033 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD);
1034 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE);
1036 if(dbch->xferq.flag & FWXFERQ_RUNNING) {
1037 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_WAKE);
1040 device_printf(sc->fc.dev, "start AT DMA status=%x\n",
1041 OREAD(sc, OHCI_DMACTL(off)));
1042 OWRITE(sc, OHCI_DMACMD(off), dbch->top->bus_addr | fsegment);
1043 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN);
1044 dbch->xferq.flag |= FWXFERQ_RUNNING;
1053 fwohci_start_atq(struct firewire_comm *fc)
1055 struct fwohci_softc *sc = (struct fwohci_softc *)fc;
1057 fwohci_start( sc, &(sc->atrq));
1058 FW_GUNLOCK(&sc->fc);
1063 fwohci_start_ats(struct firewire_comm *fc)
1065 struct fwohci_softc *sc = (struct fwohci_softc *)fc;
1067 fwohci_start( sc, &(sc->atrs));
1068 FW_GUNLOCK(&sc->fc);
1073 fwohci_txd(struct fwohci_softc *sc, struct fwohci_dbch *dbch)
1076 struct fwohcidb_tr *tr;
1077 struct fwohcidb *db;
1078 struct fw_xfer *xfer;
1082 struct firewire_comm *fc = (struct firewire_comm *)sc;
1084 if(&sc->atrq == dbch){
1087 }else if(&sc->atrs == dbch){
1096 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTREAD);
1097 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTWRITE);
1098 while(dbch->xferq.queued > 0){
1100 status = FWOHCI_DMA_READ(db->db.desc.res) >> OHCI_STATUS_SHIFT;
1101 if(!(status & OHCI_CNTL_DMA_ACTIVE)){
1102 if (fc->status != FWBUSINIT)
1103 /* maybe out of order?? */
1106 bus_dmamap_sync(dbch->dmat, tr->dma_map,
1107 BUS_DMASYNC_POSTWRITE);
1108 bus_dmamap_unload(dbch->dmat, tr->dma_map);
1110 if (firewire_debug > 1)
1113 if(status & OHCI_CNTL_DMA_DEAD) {
1115 OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN);
1116 device_printf(sc->fc.dev, "force reset AT FIFO\n");
1117 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_LINKEN);
1118 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS | OHCI_HCC_LINKEN);
1119 OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN);
1121 stat = status & FWOHCIEV_MASK;
1123 case FWOHCIEV_ACKPEND:
1124 case FWOHCIEV_ACKCOMPL:
1127 case FWOHCIEV_ACKBSA:
1128 case FWOHCIEV_ACKBSB:
1129 case FWOHCIEV_ACKBSX:
1130 device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]);
1133 case FWOHCIEV_FLUSHED:
1134 case FWOHCIEV_ACKTARD:
1135 device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]);
1138 case FWOHCIEV_MISSACK:
1139 case FWOHCIEV_UNDRRUN:
1140 case FWOHCIEV_OVRRUN:
1141 case FWOHCIEV_DESCERR:
1142 case FWOHCIEV_DTRDERR:
1143 case FWOHCIEV_TIMEOUT:
1144 case FWOHCIEV_TCODERR:
1145 case FWOHCIEV_UNKNOWN:
1146 case FWOHCIEV_ACKDERR:
1147 case FWOHCIEV_ACKTERR:
1149 device_printf(sc->fc.dev, "txd err=%2x %s\n",
1150 stat, fwohcicode[stat]);
1154 if (tr->xfer != NULL) {
1156 if (xfer->flag & FWXF_RCVD) {
1159 printf("already rcvd\n");
1163 microtime(&xfer->tv);
1164 xfer->flag = FWXF_SENT;
1166 xfer->flag = FWXF_BUSY;
1168 xfer->recv.pay_len = 0;
1170 } else if (stat != FWOHCIEV_ACKPEND) {
1171 if (stat != FWOHCIEV_ACKCOMPL)
1172 xfer->flag = FWXF_SENTERR;
1174 xfer->recv.pay_len = 0;
1179 * The watchdog timer takes care of split
1180 * transcation timeout for ACKPEND case.
1183 printf("this shouldn't happen\n");
1186 dbch->xferq.queued --;
1191 tr = STAILQ_NEXT(tr, link);
1193 if (dbch->bottom == dbch->top) {
1194 /* we reaches the end of context program */
1195 if (firewire_debug && dbch->xferq.queued > 0)
1196 printf("queued > 0\n");
1201 if ((dbch->flags & FWOHCI_DBCH_FULL) && packets > 0) {
1202 printf("make free slot\n");
1203 dbch->flags &= ~FWOHCI_DBCH_FULL;
1205 fwohci_start(sc, dbch);
1212 fwohci_db_free(struct fwohci_dbch *dbch)
1214 struct fwohcidb_tr *db_tr;
1217 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0)
1220 for(db_tr = STAILQ_FIRST(&dbch->db_trq), idb = 0; idb < dbch->ndb;
1221 db_tr = STAILQ_NEXT(db_tr, link), idb++){
1222 if ((dbch->xferq.flag & FWXFERQ_EXTBUF) == 0 &&
1223 db_tr->buf != NULL) {
1224 fwdma_free_size(dbch->dmat, db_tr->dma_map,
1225 db_tr->buf, dbch->xferq.psize);
1227 } else if (db_tr->dma_map != NULL)
1228 bus_dmamap_destroy(dbch->dmat, db_tr->dma_map);
1231 db_tr = STAILQ_FIRST(&dbch->db_trq);
1232 fwdma_free_multiseg(dbch->am);
1234 STAILQ_INIT(&dbch->db_trq);
1235 dbch->flags &= ~FWOHCI_DBCH_INIT;
1239 fwohci_db_init(struct fwohci_softc *sc, struct fwohci_dbch *dbch)
1242 struct fwohcidb_tr *db_tr;
1244 if ((dbch->flags & FWOHCI_DBCH_INIT) != 0)
1247 /* create dma_tag for buffers */
1248 #define MAX_REQCOUNT 0xffff
1249 if (bus_dma_tag_create(/*parent*/ sc->fc.dmat,
1250 /*alignment*/ 1, /*boundary*/ 0,
1251 /*lowaddr*/ BUS_SPACE_MAXADDR_32BIT,
1252 /*highaddr*/ BUS_SPACE_MAXADDR,
1253 /*filter*/NULL, /*filterarg*/NULL,
1254 /*maxsize*/ dbch->xferq.psize,
1255 /*nsegments*/ dbch->ndesc > 3 ? dbch->ndesc - 2 : 1,
1256 /*maxsegsz*/ MAX_REQCOUNT,
1258 #if defined(__FreeBSD__) && __FreeBSD_version >= 501102
1259 /*lockfunc*/busdma_lock_mutex,
1260 /*lockarg*/FW_GMTX(&sc->fc),
1265 /* allocate DB entries and attach one to each DMA channels */
1266 /* DB entry must start at 16 bytes bounary. */
1267 STAILQ_INIT(&dbch->db_trq);
1268 db_tr = (struct fwohcidb_tr *)
1269 malloc(sizeof(struct fwohcidb_tr) * dbch->ndb,
1270 M_FW, M_WAITOK | M_ZERO);
1272 printf("fwohci_db_init: malloc(1) failed\n");
1276 #define DB_SIZE(x) (sizeof(struct fwohcidb) * (x)->ndesc)
1277 dbch->am = fwdma_malloc_multiseg(&sc->fc, DB_SIZE(dbch),
1278 DB_SIZE(dbch), dbch->ndb, BUS_DMA_WAITOK);
1279 if (dbch->am == NULL) {
1280 printf("fwohci_db_init: fwdma_malloc_multiseg failed\n");
1284 /* Attach DB to DMA ch. */
1285 for(idb = 0 ; idb < dbch->ndb ; idb++){
1287 db_tr->db = (struct fwohcidb *)fwdma_v_addr(dbch->am, idb);
1288 db_tr->bus_addr = fwdma_bus_addr(dbch->am, idb);
1289 /* create dmamap for buffers */
1290 /* XXX do we need 4bytes alignment tag? */
1291 /* XXX don't alloc dma_map for AR */
1292 if (bus_dmamap_create(dbch->dmat, 0, &db_tr->dma_map) != 0) {
1293 printf("bus_dmamap_create failed\n");
1294 dbch->flags = FWOHCI_DBCH_INIT; /* XXX fake */
1295 fwohci_db_free(dbch);
1298 STAILQ_INSERT_TAIL(&dbch->db_trq, db_tr, link);
1299 if (dbch->xferq.flag & FWXFERQ_EXTBUF) {
1300 if (idb % dbch->xferq.bnpacket == 0)
1301 dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket
1302 ].start = (caddr_t)db_tr;
1303 if ((idb + 1) % dbch->xferq.bnpacket == 0)
1304 dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket
1305 ].end = (caddr_t)db_tr;
1309 STAILQ_LAST(&dbch->db_trq, fwohcidb_tr,link)->link.stqe_next
1310 = STAILQ_FIRST(&dbch->db_trq);
1312 dbch->xferq.queued = 0;
1313 dbch->pdb_tr = NULL;
1314 dbch->top = STAILQ_FIRST(&dbch->db_trq);
1315 dbch->bottom = dbch->top;
1316 dbch->flags = FWOHCI_DBCH_INIT;
1320 fwohci_itx_disable(struct firewire_comm *fc, int dmach)
1322 struct fwohci_softc *sc = (struct fwohci_softc *)fc;
1324 OWRITE(sc, OHCI_ITCTLCLR(dmach),
1325 OHCI_CNTL_DMA_RUN | OHCI_CNTL_CYCMATCH_S);
1326 OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach);
1327 OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach);
1328 /* XXX we cannot free buffers until the DMA really stops */
1329 pause("fwitxd", hz);
1330 fwohci_db_free(&sc->it[dmach]);
1331 sc->it[dmach].xferq.flag &= ~FWXFERQ_RUNNING;
1336 fwohci_irx_disable(struct firewire_comm *fc, int dmach)
1338 struct fwohci_softc *sc = (struct fwohci_softc *)fc;
1340 OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN);
1341 OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach);
1342 OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach);
1343 /* XXX we cannot free buffers until the DMA really stops */
1344 pause("fwirxd", hz);
1345 fwohci_db_free(&sc->ir[dmach]);
1346 sc->ir[dmach].xferq.flag &= ~FWXFERQ_RUNNING;
1350 #if BYTE_ORDER == BIG_ENDIAN
1352 fwohci_irx_post (struct firewire_comm *fc , uint32_t *qld)
1354 qld[0] = FWOHCI_DMA_READ(qld[0]);
1360 fwohci_tx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch)
1363 int idb, z, i, dmach = 0, ldesc;
1365 struct fwohcidb_tr *db_tr;
1366 struct fwohcidb *db;
1368 if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){
1373 for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){
1374 if( &sc->it[dmach] == dbch){
1375 off = OHCI_ITOFF(dmach);
1383 if(dbch->xferq.flag & FWXFERQ_RUNNING)
1385 dbch->xferq.flag |= FWXFERQ_RUNNING;
1386 for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){
1387 dbch->bottom = STAILQ_NEXT(dbch->bottom, link);
1390 for (idb = 0; idb < dbch->ndb; idb ++) {
1391 fwohci_add_tx_buf(dbch, db_tr, idb);
1392 if(STAILQ_NEXT(db_tr, link) == NULL){
1396 ldesc = db_tr->dbcnt - 1;
1397 FWOHCI_DMA_WRITE(db[0].db.desc.depend,
1398 STAILQ_NEXT(db_tr, link)->bus_addr | z);
1399 db[ldesc].db.desc.depend = db[0].db.desc.depend;
1400 if(dbch->xferq.flag & FWXFERQ_EXTBUF){
1401 if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){
1403 db[ldesc].db.desc.cmd,
1404 OHCI_INTERRUPT_ALWAYS);
1405 /* OHCI 1.1 and above */
1408 OHCI_INTERRUPT_ALWAYS);
1411 db_tr = STAILQ_NEXT(db_tr, link);
1414 dbch->bottom->db[dbch->bottom->dbcnt - 1].db.desc.depend, 0xf);
1419 fwohci_rx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch)
1422 int idb, z, i, dmach = 0, ldesc;
1424 struct fwohcidb_tr *db_tr;
1425 struct fwohcidb *db;
1428 if(&sc->arrq == dbch){
1430 }else if(&sc->arrs == dbch){
1433 for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){
1434 if( &sc->ir[dmach] == dbch){
1435 off = OHCI_IROFF(dmach);
1444 if(dbch->xferq.flag & FWXFERQ_STREAM){
1445 if(dbch->xferq.flag & FWXFERQ_RUNNING)
1448 if(dbch->xferq.flag & FWXFERQ_RUNNING){
1453 dbch->xferq.flag |= FWXFERQ_RUNNING;
1454 dbch->top = STAILQ_FIRST(&dbch->db_trq);
1455 for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){
1456 dbch->bottom = STAILQ_NEXT(dbch->bottom, link);
1459 for (idb = 0; idb < dbch->ndb; idb ++) {
1460 fwohci_add_rx_buf(dbch, db_tr, idb, &sc->dummy_dma);
1461 if (STAILQ_NEXT(db_tr, link) == NULL)
1464 ldesc = db_tr->dbcnt - 1;
1465 FWOHCI_DMA_WRITE(db[ldesc].db.desc.depend,
1466 STAILQ_NEXT(db_tr, link)->bus_addr | z);
1467 if(dbch->xferq.flag & FWXFERQ_EXTBUF){
1468 if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){
1470 db[ldesc].db.desc.cmd,
1471 OHCI_INTERRUPT_ALWAYS);
1473 db[ldesc].db.desc.depend,
1477 db_tr = STAILQ_NEXT(db_tr, link);
1480 dbch->bottom->db[db_tr->dbcnt - 1].db.desc.depend, 0xf);
1481 dbch->buf_offset = 0;
1482 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD);
1483 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE);
1484 if(dbch->xferq.flag & FWXFERQ_STREAM){
1487 OWRITE(sc, OHCI_DMACMD(off), dbch->top->bus_addr | z);
1489 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN);
1494 fwohci_next_cycle(struct firewire_comm *fc, int cycle_now)
1496 int sec, cycle, cycle_match;
1498 cycle = cycle_now & 0x1fff;
1499 sec = cycle_now >> 13;
1500 #define CYCLE_MOD 0x10
1502 #define CYCLE_DELAY 8 /* min delay to start DMA */
1504 #define CYCLE_DELAY 7000 /* min delay to start DMA */
1506 cycle = cycle + CYCLE_DELAY;
1507 if (cycle >= 8000) {
1511 cycle = roundup2(cycle, CYCLE_MOD);
1512 if (cycle >= 8000) {
1519 cycle_match = ((sec << 13) | cycle) & 0x7ffff;
1521 return(cycle_match);
1525 fwohci_itxbuf_enable(struct firewire_comm *fc, int dmach)
1527 struct fwohci_softc *sc = (struct fwohci_softc *)fc;
1529 unsigned short tag, ich;
1530 struct fwohci_dbch *dbch;
1531 int cycle_match, cycle_now, s, ldesc;
1533 struct fw_bulkxfer *first, *chunk, *prev;
1534 struct fw_xferq *it;
1536 dbch = &sc->it[dmach];
1539 tag = (it->flag >> 6) & 3;
1540 ich = it->flag & 0x3f;
1541 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) {
1542 dbch->ndb = it->bnpacket * it->bnchunk;
1544 fwohci_db_init(sc, dbch);
1545 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0)
1548 err = fwohci_tx_enable(sc, dbch);
1553 ldesc = dbch->ndesc - 1;
1556 prev = STAILQ_LAST(&it->stdma, fw_bulkxfer, link);
1557 while ((chunk = STAILQ_FIRST(&it->stvalid)) != NULL) {
1558 struct fwohcidb *db;
1560 fwdma_sync_multiseg(it->buf, chunk->poffset, it->bnpacket,
1561 BUS_DMASYNC_PREWRITE);
1562 fwohci_txbufdb(sc, dmach, chunk);
1564 db = ((struct fwohcidb_tr *)(prev->end))->db;
1565 #if 0 /* XXX necessary? */
1566 FWOHCI_DMA_SET(db[ldesc].db.desc.cmd,
1567 OHCI_BRANCH_ALWAYS);
1569 #if 0 /* if bulkxfer->npacket changes */
1570 db[ldesc].db.desc.depend = db[0].db.desc.depend =
1571 ((struct fwohcidb_tr *)
1572 (chunk->start))->bus_addr | dbch->ndesc;
1574 FWOHCI_DMA_SET(db[0].db.desc.depend, dbch->ndesc);
1575 FWOHCI_DMA_SET(db[ldesc].db.desc.depend, dbch->ndesc);
1578 STAILQ_REMOVE_HEAD(&it->stvalid, link);
1579 STAILQ_INSERT_TAIL(&it->stdma, chunk, link);
1583 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE);
1584 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD);
1586 stat = OREAD(sc, OHCI_ITCTL(dmach));
1587 if (firewire_debug && (stat & OHCI_CNTL_CYCMATCH_S))
1588 printf("stat 0x%x\n", stat);
1590 if (stat & (OHCI_CNTL_DMA_ACTIVE | OHCI_CNTL_CYCMATCH_S))
1594 OWRITE(sc, OHCI_ITCTLCLR(dmach), OHCI_CNTL_DMA_RUN);
1596 OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach);
1597 OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach);
1598 OWRITE(sc, OHCI_IT_MASK, 1 << dmach);
1599 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IT);
1601 first = STAILQ_FIRST(&it->stdma);
1602 OWRITE(sc, OHCI_ITCMD(dmach),
1603 ((struct fwohcidb_tr *)(first->start))->bus_addr | dbch->ndesc);
1604 if (firewire_debug > 1) {
1605 printf("fwohci_itxbuf_enable: kick 0x%08x\n", stat);
1607 dump_dma(sc, ITX_CH + dmach);
1610 if ((stat & OHCI_CNTL_DMA_RUN) == 0) {
1612 /* Don't start until all chunks are buffered */
1613 if (STAILQ_FIRST(&it->stfree) != NULL)
1617 /* Clear cycle match counter bits */
1618 OWRITE(sc, OHCI_ITCTLCLR(dmach), 0xffff0000);
1620 /* 2bit second + 13bit cycle */
1621 cycle_now = (fc->cyctimer(fc) >> 12) & 0x7fff;
1622 cycle_match = fwohci_next_cycle(fc, cycle_now);
1624 OWRITE(sc, OHCI_ITCTL(dmach),
1625 OHCI_CNTL_CYCMATCH_S | (cycle_match << 16)
1626 | OHCI_CNTL_DMA_RUN);
1628 OWRITE(sc, OHCI_ITCTL(dmach), OHCI_CNTL_DMA_RUN);
1630 if (firewire_debug > 1) {
1631 printf("cycle_match: 0x%04x->0x%04x\n",
1632 cycle_now, cycle_match);
1633 dump_dma(sc, ITX_CH + dmach);
1634 dump_db(sc, ITX_CH + dmach);
1636 } else if ((stat & OHCI_CNTL_CYCMATCH_S) == 0) {
1637 device_printf(sc->fc.dev,
1638 "IT DMA underrun (0x%08x)\n", stat);
1639 OWRITE(sc, OHCI_ITCTL(dmach), OHCI_CNTL_DMA_WAKE);
1646 fwohci_irx_enable(struct firewire_comm *fc, int dmach)
1648 struct fwohci_softc *sc = (struct fwohci_softc *)fc;
1649 int err = 0, s, ldesc;
1650 unsigned short tag, ich;
1652 struct fwohci_dbch *dbch;
1653 struct fwohcidb_tr *db_tr;
1654 struct fw_bulkxfer *first, *prev, *chunk;
1655 struct fw_xferq *ir;
1657 dbch = &sc->ir[dmach];
1660 if ((ir->flag & FWXFERQ_RUNNING) == 0) {
1661 tag = (ir->flag >> 6) & 3;
1662 ich = ir->flag & 0x3f;
1663 OWRITE(sc, OHCI_IRMATCH(dmach), tagbit[tag] | ich);
1666 dbch->ndb = ir->bnpacket * ir->bnchunk;
1668 fwohci_db_init(sc, dbch);
1669 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0)
1671 err = fwohci_rx_enable(sc, dbch);
1676 first = STAILQ_FIRST(&ir->stfree);
1677 if (first == NULL) {
1678 device_printf(fc->dev, "IR DMA no free chunk\n");
1682 ldesc = dbch->ndesc - 1;
1684 if ((ir->flag & FWXFERQ_HANDLER) == 0)
1686 prev = STAILQ_LAST(&ir->stdma, fw_bulkxfer, link);
1687 while ((chunk = STAILQ_FIRST(&ir->stfree)) != NULL) {
1688 struct fwohcidb *db;
1690 #if 1 /* XXX for if_fwe */
1691 if (chunk->mbuf != NULL) {
1692 db_tr = (struct fwohcidb_tr *)(chunk->start);
1694 err = bus_dmamap_load_mbuf(dbch->dmat, db_tr->dma_map,
1695 chunk->mbuf, fwohci_execute_db2, db_tr,
1697 FWOHCI_DMA_SET(db_tr->db[1].db.desc.cmd,
1698 OHCI_UPDATE | OHCI_INPUT_LAST |
1699 OHCI_INTERRUPT_ALWAYS | OHCI_BRANCH_ALWAYS);
1702 db = ((struct fwohcidb_tr *)(chunk->end))->db;
1703 FWOHCI_DMA_WRITE(db[ldesc].db.desc.res, 0);
1704 FWOHCI_DMA_CLEAR(db[ldesc].db.desc.depend, 0xf);
1706 db = ((struct fwohcidb_tr *)(prev->end))->db;
1707 FWOHCI_DMA_SET(db[ldesc].db.desc.depend, dbch->ndesc);
1709 STAILQ_REMOVE_HEAD(&ir->stfree, link);
1710 STAILQ_INSERT_TAIL(&ir->stdma, chunk, link);
1713 if ((ir->flag & FWXFERQ_HANDLER) == 0)
1715 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE);
1716 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD);
1718 stat = OREAD(sc, OHCI_IRCTL(dmach));
1719 if (stat & OHCI_CNTL_DMA_ACTIVE)
1721 if (stat & OHCI_CNTL_DMA_RUN) {
1722 OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN);
1723 device_printf(sc->fc.dev, "IR DMA overrun (0x%08x)\n", stat);
1727 printf("start IR DMA 0x%x\n", stat);
1728 OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach);
1729 OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach);
1730 OWRITE(sc, OHCI_IR_MASK, 1 << dmach);
1731 OWRITE(sc, OHCI_IRCTLCLR(dmach), 0xf0000000);
1732 OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_ISOHDR);
1733 OWRITE(sc, OHCI_IRCMD(dmach),
1734 ((struct fwohcidb_tr *)(first->start))->bus_addr
1736 OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_DMA_RUN);
1737 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IR);
1739 dump_db(sc, IRX_CH + dmach);
1745 fwohci_stop(struct fwohci_softc *sc, device_t dev)
1749 fwohci_set_intr(&sc->fc, 0);
1751 /* Now stopping all DMA channel */
1752 OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN);
1753 OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN);
1754 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN);
1755 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN);
1757 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){
1758 OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN);
1759 OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN);
1762 #if 0 /* Let dcons(4) be accessed */
1763 /* Stop interrupt */
1764 OWRITE(sc, FWOHCI_INTMASKCLR,
1765 OHCI_INT_EN | OHCI_INT_ERR | OHCI_INT_PHY_SID
1767 | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS
1768 | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS
1769 | OHCI_INT_DMA_ARRQ | OHCI_INT_DMA_ARRS
1770 | OHCI_INT_PHY_BUS_R);
1772 /* FLUSH FIFO and reset Transmitter/Reciever */
1773 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET);
1776 /* XXX Link down? Bus reset? */
1781 fwohci_resume(struct fwohci_softc *sc, device_t dev)
1784 struct fw_xferq *ir;
1785 struct fw_bulkxfer *chunk;
1787 fwohci_reset(sc, dev);
1788 /* XXX resume isochronous receive automatically. (how about TX?) */
1789 for(i = 0; i < sc->fc.nisodma; i ++) {
1790 ir = &sc->ir[i].xferq;
1791 if((ir->flag & FWXFERQ_RUNNING) != 0) {
1792 device_printf(sc->fc.dev,
1793 "resume iso receive ch: %d\n", i);
1794 ir->flag &= ~FWXFERQ_RUNNING;
1795 /* requeue stdma to stfree */
1796 while((chunk = STAILQ_FIRST(&ir->stdma)) != NULL) {
1797 STAILQ_REMOVE_HEAD(&ir->stdma, link);
1798 STAILQ_INSERT_TAIL(&ir->stfree, chunk, link);
1800 sc->fc.irx_enable(&sc->fc, i);
1804 bus_generic_resume(dev);
1805 sc->fc.ibr(&sc->fc);
1811 fwohci_dump_intr(struct fwohci_softc *sc, uint32_t stat)
1813 if(stat & OREAD(sc, FWOHCI_INTMASK))
1814 device_printf(fc->dev, "INTERRUPT < %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s> 0x%08x, 0x%08x\n",
1815 stat & OHCI_INT_EN ? "DMA_EN ":"",
1816 stat & OHCI_INT_PHY_REG ? "PHY_REG ":"",
1817 stat & OHCI_INT_CYC_LONG ? "CYC_LONG ":"",
1818 stat & OHCI_INT_ERR ? "INT_ERR ":"",
1819 stat & OHCI_INT_CYC_ERR ? "CYC_ERR ":"",
1820 stat & OHCI_INT_CYC_LOST ? "CYC_LOST ":"",
1821 stat & OHCI_INT_CYC_64SECOND ? "CYC_64SECOND ":"",
1822 stat & OHCI_INT_CYC_START ? "CYC_START ":"",
1823 stat & OHCI_INT_PHY_INT ? "PHY_INT ":"",
1824 stat & OHCI_INT_PHY_BUS_R ? "BUS_RESET ":"",
1825 stat & OHCI_INT_PHY_SID ? "SID ":"",
1826 stat & OHCI_INT_LR_ERR ? "DMA_LR_ERR ":"",
1827 stat & OHCI_INT_PW_ERR ? "DMA_PW_ERR ":"",
1828 stat & OHCI_INT_DMA_IR ? "DMA_IR ":"",
1829 stat & OHCI_INT_DMA_IT ? "DMA_IT " :"",
1830 stat & OHCI_INT_DMA_PRRS ? "DMA_PRRS " :"",
1831 stat & OHCI_INT_DMA_PRRQ ? "DMA_PRRQ " :"",
1832 stat & OHCI_INT_DMA_ARRS ? "DMA_ARRS " :"",
1833 stat & OHCI_INT_DMA_ARRQ ? "DMA_ARRQ " :"",
1834 stat & OHCI_INT_DMA_ATRS ? "DMA_ATRS " :"",
1835 stat & OHCI_INT_DMA_ATRQ ? "DMA_ATRQ " :"",
1836 stat, OREAD(sc, FWOHCI_INTMASK)
1841 fwohci_intr_core(struct fwohci_softc *sc, uint32_t stat, int count)
1843 struct firewire_comm *fc = (struct firewire_comm *)sc;
1844 uint32_t node_id, plen;
1846 FW_GLOCK_ASSERT(fc);
1847 if ((stat & OHCI_INT_PHY_BUS_R) && (fc->status != FWBUSRESET)) {
1848 fc->status = FWBUSRESET;
1849 /* Disable bus reset interrupt until sid recv. */
1850 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_PHY_BUS_R);
1852 device_printf(fc->dev, "%s: BUS reset\n", __func__);
1853 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_CYC_LOST);
1854 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCSRC);
1856 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN);
1857 sc->atrq.xferq.flag &= ~FWXFERQ_RUNNING;
1858 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN);
1859 sc->atrs.xferq.flag &= ~FWXFERQ_RUNNING;
1862 taskqueue_enqueue(sc->fc.taskqueue, &sc->fwohci_task_busreset);
1864 if (stat & OHCI_INT_PHY_SID) {
1865 /* Enable bus reset interrupt */
1866 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_BUS_R);
1867 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_PHY_BUS_R);
1869 /* Allow async. request to us */
1870 OWRITE(sc, OHCI_AREQHI, 1 << 31);
1871 if (firewire_phydma_enable) {
1872 /* allow from all nodes */
1873 OWRITE(sc, OHCI_PREQHI, 0x7fffffff);
1874 OWRITE(sc, OHCI_PREQLO, 0xffffffff);
1875 /* 0 to 4GB region */
1876 OWRITE(sc, OHCI_PREQUPPER, 0x10000);
1878 /* Set ATRetries register */
1879 OWRITE(sc, OHCI_ATRETRY, 1<<(13+16) | 0xfff);
1882 * Checking whether the node is root or not. If root, turn on
1885 node_id = OREAD(sc, FWOHCI_NODEID);
1886 plen = OREAD(sc, OHCI_SID_CNT);
1888 fc->nodeid = node_id & 0x3f;
1889 device_printf(fc->dev, "%s: node_id=0x%08x, SelfID Count=%d, ",
1890 __func__, fc->nodeid, (plen >> 16) & 0xff);
1891 if (!(node_id & OHCI_NODE_VALID)) {
1892 device_printf(fc->dev, "%s: Bus reset failure\n",
1899 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_CYC_LOST);
1900 if ((node_id & OHCI_NODE_ROOT) && !nocyclemaster) {
1901 printf("CYCLEMASTER mode\n");
1902 OWRITE(sc, OHCI_LNKCTL,
1903 OHCI_CNTL_CYCMTR | OHCI_CNTL_CYCTIMER);
1905 printf("non CYCLEMASTER mode\n");
1906 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCMTR);
1907 OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_CYCTIMER);
1910 fc->status = FWBUSINIT;
1913 taskqueue_enqueue(sc->fc.taskqueue, &sc->fwohci_task_sid);
1916 if ((stat & ~(OHCI_INT_PHY_BUS_R | OHCI_INT_PHY_SID)) && (!kdb_active))
1917 taskqueue_enqueue(sc->fc.taskqueue, &sc->fwohci_task_dma);
1921 fwohci_intr_dma(struct fwohci_softc *sc, uint32_t stat, int count)
1923 uint32_t irstat, itstat;
1925 struct firewire_comm *fc = (struct firewire_comm *)sc;
1927 if (stat & OHCI_INT_DMA_IR) {
1928 irstat = atomic_readandclear_int(&sc->irstat);
1929 for(i = 0; i < fc->nisodma ; i++){
1930 struct fwohci_dbch *dbch;
1932 if((irstat & (1 << i)) != 0){
1934 if ((dbch->xferq.flag & FWXFERQ_OPEN) == 0) {
1935 device_printf(sc->fc.dev,
1936 "dma(%d) not active\n", i);
1939 fwohci_rbuf_update(sc, i);
1943 if (stat & OHCI_INT_DMA_IT) {
1944 itstat = atomic_readandclear_int(&sc->itstat);
1945 for(i = 0; i < fc->nisodma ; i++){
1946 if((itstat & (1 << i)) != 0){
1947 fwohci_tbuf_update(sc, i);
1951 if (stat & OHCI_INT_DMA_PRRS) {
1953 dump_dma(sc, ARRS_CH);
1954 dump_db(sc, ARRS_CH);
1956 fwohci_arcv(sc, &sc->arrs, count);
1958 if (stat & OHCI_INT_DMA_PRRQ) {
1960 dump_dma(sc, ARRQ_CH);
1961 dump_db(sc, ARRQ_CH);
1963 fwohci_arcv(sc, &sc->arrq, count);
1965 if (stat & OHCI_INT_CYC_LOST) {
1966 if (sc->cycle_lost >= 0)
1968 if (sc->cycle_lost > 10) {
1969 sc->cycle_lost = -1;
1971 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCTIMER);
1973 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_CYC_LOST);
1974 device_printf(fc->dev, "too many cycles lost, "
1975 "no cycle master present?\n");
1978 if (stat & OHCI_INT_DMA_ATRQ) {
1979 fwohci_txd(sc, &(sc->atrq));
1981 if (stat & OHCI_INT_DMA_ATRS) {
1982 fwohci_txd(sc, &(sc->atrs));
1984 if (stat & OHCI_INT_PW_ERR) {
1985 device_printf(fc->dev, "posted write error\n");
1987 if (stat & OHCI_INT_ERR) {
1988 device_printf(fc->dev, "unrecoverable error\n");
1990 if (stat & OHCI_INT_PHY_INT) {
1991 device_printf(fc->dev, "phy int\n");
1998 fwohci_task_busreset(void *arg, int pending)
2000 struct fwohci_softc *sc = (struct fwohci_softc *)arg;
2003 fw_busreset(&sc->fc, FWBUSRESET);
2004 OWRITE(sc, OHCI_CROMHDR, ntohl(sc->fc.config_rom[0]));
2005 OWRITE(sc, OHCI_BUS_OPT, ntohl(sc->fc.config_rom[2]));
2006 FW_GUNLOCK(&sc->fc);
2010 fwohci_task_sid(void *arg, int pending)
2012 struct fwohci_softc *sc = (struct fwohci_softc *)arg;
2013 struct firewire_comm *fc = &sc->fc;
2019 * We really should have locking
2020 * here. Not sure why it's not
2022 plen = OREAD(sc, OHCI_SID_CNT);
2024 if (plen & OHCI_SID_ERR) {
2025 device_printf(fc->dev, "SID Error\n");
2028 plen &= OHCI_SID_CNT_MASK;
2029 if (plen < 4 || plen > OHCI_SIDSIZE) {
2030 device_printf(fc->dev, "invalid SID len = %d\n", plen);
2033 plen -= 4; /* chop control info */
2034 buf = (uint32_t *)malloc(OHCI_SIDSIZE, M_FW, M_NOWAIT);
2036 device_printf(fc->dev, "malloc failed\n");
2039 for (i = 0; i < plen / 4; i ++)
2040 buf[i] = FWOHCI_DMA_READ(sc->sid_buf[i+1]);
2042 /* pending all pre-bus_reset packets */
2043 fwohci_txd(sc, &sc->atrq);
2044 fwohci_txd(sc, &sc->atrs);
2045 fwohci_arcv(sc, &sc->arrs, -1);
2046 fwohci_arcv(sc, &sc->arrq, -1);
2048 fw_sidrcv(fc, buf, plen);
2053 fwohci_task_dma(void *arg, int pending)
2055 struct fwohci_softc *sc = (struct fwohci_softc *)arg;
2059 stat = atomic_readandclear_int(&sc->intstat);
2061 fwohci_intr_dma(sc, stat, -1);
2068 fwohci_check_stat(struct fwohci_softc *sc)
2070 uint32_t stat, irstat, itstat;
2072 FW_GLOCK_ASSERT(&sc->fc);
2073 stat = OREAD(sc, FWOHCI_INTSTAT);
2074 if (stat == 0xffffffff) {
2075 if (!bus_child_present(sc->fc.dev))
2076 return (FILTER_HANDLED);
2077 device_printf(sc->fc.dev, "device physically ejected?\n");
2078 return (FILTER_STRAY);
2081 OWRITE(sc, FWOHCI_INTSTATCLR, stat & ~OHCI_INT_PHY_BUS_R);
2083 stat &= sc->intmask;
2085 return (FILTER_STRAY);
2087 atomic_set_int(&sc->intstat, stat);
2088 if (stat & OHCI_INT_DMA_IR) {
2089 irstat = OREAD(sc, OHCI_IR_STAT);
2090 OWRITE(sc, OHCI_IR_STATCLR, irstat);
2091 atomic_set_int(&sc->irstat, irstat);
2093 if (stat & OHCI_INT_DMA_IT) {
2094 itstat = OREAD(sc, OHCI_IT_STAT);
2095 OWRITE(sc, OHCI_IT_STATCLR, itstat);
2096 atomic_set_int(&sc->itstat, itstat);
2099 fwohci_intr_core(sc, stat, -1);
2100 return (FILTER_HANDLED);
2104 fwohci_intr(void *arg)
2106 struct fwohci_softc *sc = (struct fwohci_softc *)arg;
2109 fwohci_check_stat(sc);
2110 FW_GUNLOCK(&sc->fc);
2114 fwohci_poll(struct firewire_comm *fc, int quick, int count)
2116 struct fwohci_softc *sc = (struct fwohci_softc *)fc;
2119 fwohci_check_stat(sc);
2124 fwohci_set_intr(struct firewire_comm *fc, int enable)
2126 struct fwohci_softc *sc;
2128 sc = (struct fwohci_softc *)fc;
2130 device_printf(sc->fc.dev, "fwohci_set_intr: %d\n", enable);
2132 sc->intmask |= OHCI_INT_EN;
2133 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_EN);
2135 sc->intmask &= ~OHCI_INT_EN;
2136 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_EN);
2141 fwohci_tbuf_update(struct fwohci_softc *sc, int dmach)
2143 struct firewire_comm *fc = &sc->fc;
2144 struct fwohcidb *db;
2145 struct fw_bulkxfer *chunk;
2146 struct fw_xferq *it;
2147 uint32_t stat, count;
2151 ldesc = sc->it[dmach].ndesc - 1;
2152 s = splfw(); /* unnecessary ? */
2154 fwdma_sync_multiseg_all(sc->it[dmach].am, BUS_DMASYNC_POSTREAD);
2156 dump_db(sc, ITX_CH + dmach);
2157 while ((chunk = STAILQ_FIRST(&it->stdma)) != NULL) {
2158 db = ((struct fwohcidb_tr *)(chunk->end))->db;
2159 stat = FWOHCI_DMA_READ(db[ldesc].db.desc.res)
2160 >> OHCI_STATUS_SHIFT;
2161 db = ((struct fwohcidb_tr *)(chunk->start))->db;
2163 count = FWOHCI_DMA_READ(db[ldesc].db.desc.res)
2167 STAILQ_REMOVE_HEAD(&it->stdma, link);
2168 switch (stat & FWOHCIEV_MASK){
2169 case FWOHCIEV_ACKCOMPL:
2171 device_printf(fc->dev, "0x%08x\n", count);
2175 device_printf(fc->dev,
2176 "Isochronous transmit err %02x(%s)\n",
2177 stat, fwohcicode[stat & 0x1f]);
2179 STAILQ_INSERT_TAIL(&it->stfree, chunk, link);
2189 fwohci_rbuf_update(struct fwohci_softc *sc, int dmach)
2191 struct firewire_comm *fc = &sc->fc;
2192 struct fwohcidb_tr *db_tr;
2193 struct fw_bulkxfer *chunk;
2194 struct fw_xferq *ir;
2196 int s, w = 0, ldesc;
2199 ldesc = sc->ir[dmach].ndesc - 1;
2205 if ((ir->flag & FWXFERQ_HANDLER) == 0)
2207 fwdma_sync_multiseg_all(sc->ir[dmach].am, BUS_DMASYNC_POSTREAD);
2208 while ((chunk = STAILQ_FIRST(&ir->stdma)) != NULL) {
2209 db_tr = (struct fwohcidb_tr *)chunk->end;
2210 stat = FWOHCI_DMA_READ(db_tr->db[ldesc].db.desc.res)
2211 >> OHCI_STATUS_SHIFT;
2215 if (chunk->mbuf != NULL) {
2216 bus_dmamap_sync(sc->ir[dmach].dmat, db_tr->dma_map,
2217 BUS_DMASYNC_POSTREAD);
2218 bus_dmamap_unload(sc->ir[dmach].dmat, db_tr->dma_map);
2219 } else if (ir->buf != NULL) {
2220 fwdma_sync_multiseg(ir->buf, chunk->poffset,
2221 ir->bnpacket, BUS_DMASYNC_POSTREAD);
2224 printf("fwohci_rbuf_update: this shouldn't happend\n");
2227 STAILQ_REMOVE_HEAD(&ir->stdma, link);
2228 STAILQ_INSERT_TAIL(&ir->stvalid, chunk, link);
2229 switch (stat & FWOHCIEV_MASK) {
2230 case FWOHCIEV_ACKCOMPL:
2234 chunk->resp = EINVAL;
2235 device_printf(fc->dev,
2236 "Isochronous receive err %02x(%s)\n",
2237 stat, fwohcicode[stat & 0x1f]);
2241 if ((ir->flag & FWXFERQ_HANDLER) == 0)
2247 if (ir->flag & FWXFERQ_HANDLER)
2254 dump_dma(struct fwohci_softc *sc, uint32_t ch)
2256 uint32_t off, cntl, stat, cmd, match;
2266 }else if(ch < IRX_CH){
2267 off = OHCI_ITCTL(ch - ITX_CH);
2269 off = OHCI_IRCTL(ch - IRX_CH);
2271 cntl = stat = OREAD(sc, off);
2272 cmd = OREAD(sc, off + 0xc);
2273 match = OREAD(sc, off + 0x10);
2275 device_printf(sc->fc.dev, "ch %1x cntl:0x%08x cmd:0x%08x match:0x%08x\n",
2282 device_printf(sc->fc.dev, "dma %d ch:%s%s%s%s%s%s %s(%x)\n",
2284 stat & OHCI_CNTL_DMA_RUN ? "RUN," : "",
2285 stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "",
2286 stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "",
2287 stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "",
2288 stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "",
2289 stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "",
2290 fwohcicode[stat & 0x1f],
2294 device_printf(sc->fc.dev, "dma %d ch: Nostat\n", ch);
2299 dump_db(struct fwohci_softc *sc, uint32_t ch)
2301 struct fwohci_dbch *dbch;
2302 struct fwohcidb_tr *cp = NULL, *pp, *np = NULL;
2303 struct fwohcidb *curr = NULL, *prev, *next = NULL;
2318 }else if(ch < IRX_CH){
2319 off = OHCI_ITCTL(ch - ITX_CH);
2320 dbch = &sc->it[ch - ITX_CH];
2322 off = OHCI_IRCTL(ch - IRX_CH);
2323 dbch = &sc->ir[ch - IRX_CH];
2325 cmd = OREAD(sc, off + 0xc);
2327 if( dbch->ndb == 0 ){
2328 device_printf(sc->fc.dev, "No DB is attached ch=%d\n", ch);
2333 for(idb = 0 ; idb < dbch->ndb ; idb ++ ){
2334 cp = STAILQ_NEXT(pp, link);
2339 np = STAILQ_NEXT(cp, link);
2340 for(jdb = 0 ; jdb < dbch->ndesc ; jdb ++ ){
2341 if ((cmd & 0xfffffff0) == cp->bus_addr) {
2351 pp = STAILQ_NEXT(pp, link);
2361 printf("Prev DB %d\n", ch);
2362 print_db(pp, prev, ch, dbch->ndesc);
2364 printf("Current DB %d\n", ch);
2365 print_db(cp, curr, ch, dbch->ndesc);
2367 printf("Next DB %d\n", ch);
2368 print_db(np, next, ch, dbch->ndesc);
2371 printf("dbdump err ch = %d cmd = 0x%08x\n", ch, cmd);
2377 print_db(struct fwohcidb_tr *db_tr, struct fwohcidb *db,
2378 uint32_t ch, uint32_t max)
2385 printf("No Descriptor is found\n");
2389 printf("ch = %d\n%8s %s %s %s %s %4s %8s %8s %4s:%4s\n",
2401 for( i = 0 ; i <= max ; i ++){
2402 cmd = FWOHCI_DMA_READ(db[i].db.desc.cmd);
2403 res = FWOHCI_DMA_READ(db[i].db.desc.res);
2404 key = cmd & OHCI_KEY_MASK;
2405 stat = res >> OHCI_STATUS_SHIFT;
2406 #if defined(__DragonFly__) || __FreeBSD_version < 500000
2407 printf("%08x %s %s %s %s %5d %08x %08x %04x:%04x",
2410 printf("%08jx %s %s %s %s %5d %08x %08x %04x:%04x",
2411 (uintmax_t)db_tr->bus_addr,
2413 dbcode[(cmd >> 28) & 0xf],
2414 dbkey[(cmd >> 24) & 0x7],
2415 dbcond[(cmd >> 20) & 0x3],
2416 dbcond[(cmd >> 18) & 0x3],
2417 cmd & OHCI_COUNT_MASK,
2418 FWOHCI_DMA_READ(db[i].db.desc.addr),
2419 FWOHCI_DMA_READ(db[i].db.desc.depend),
2421 res & OHCI_COUNT_MASK);
2423 printf(" %s%s%s%s%s%s %s(%x)\n",
2424 stat & OHCI_CNTL_DMA_RUN ? "RUN," : "",
2425 stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "",
2426 stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "",
2427 stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "",
2428 stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "",
2429 stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "",
2430 fwohcicode[stat & 0x1f],
2434 printf(" Nostat\n");
2436 if(key == OHCI_KEY_ST2 ){
2437 printf("0x%08x 0x%08x 0x%08x 0x%08x\n",
2438 FWOHCI_DMA_READ(db[i+1].db.immed[0]),
2439 FWOHCI_DMA_READ(db[i+1].db.immed[1]),
2440 FWOHCI_DMA_READ(db[i+1].db.immed[2]),
2441 FWOHCI_DMA_READ(db[i+1].db.immed[3]));
2443 if(key == OHCI_KEY_DEVICE){
2446 if((cmd & OHCI_BRANCH_MASK)
2447 == OHCI_BRANCH_ALWAYS){
2450 if((cmd & OHCI_CMD_MASK)
2451 == OHCI_OUTPUT_LAST){
2454 if((cmd & OHCI_CMD_MASK)
2455 == OHCI_INPUT_LAST){
2458 if(key == OHCI_KEY_ST2 ){
2466 fwohci_ibr(struct firewire_comm *fc)
2468 struct fwohci_softc *sc;
2471 device_printf(fc->dev, "Initiate bus reset\n");
2472 sc = (struct fwohci_softc *)fc;
2476 * Make sure our cached values from the config rom are
2479 OWRITE(sc, OHCI_CROMHDR, ntohl(sc->fc.config_rom[0]));
2480 OWRITE(sc, OHCI_BUS_OPT, ntohl(sc->fc.config_rom[2]));
2483 * Set root hold-off bit so that non cyclemaster capable node
2484 * shouldn't became the root node.
2487 fun = fwphy_rddata(sc, FW_PHY_IBR_REG);
2488 fun |= FW_PHY_IBR | FW_PHY_RHB;
2489 fun = fwphy_wrdata(sc, FW_PHY_IBR_REG, fun);
2490 #else /* Short bus reset */
2491 fun = fwphy_rddata(sc, FW_PHY_ISBR_REG);
2492 fun |= FW_PHY_ISBR | FW_PHY_RHB;
2493 fun = fwphy_wrdata(sc, FW_PHY_ISBR_REG, fun);
2499 fwohci_txbufdb(struct fwohci_softc *sc, int dmach, struct fw_bulkxfer *bulkxfer)
2501 struct fwohcidb_tr *db_tr, *fdb_tr;
2502 struct fwohci_dbch *dbch;
2503 struct fwohcidb *db;
2505 struct fwohci_txpkthdr *ohcifp;
2506 unsigned short chtag;
2509 FW_GLOCK_ASSERT(&sc->fc);
2511 dbch = &sc->it[dmach];
2512 chtag = sc->it[dmach].xferq.flag & 0xff;
2514 db_tr = (struct fwohcidb_tr *)(bulkxfer->start);
2515 fdb_tr = (struct fwohcidb_tr *)(bulkxfer->end);
2517 device_printf(sc->fc.dev, "DB %08x %08x %08x\n", bulkxfer, db_tr->bus_addr, fdb_tr->bus_addr);
2519 for (idb = 0; idb < dbch->xferq.bnpacket; idb ++) {
2521 fp = (struct fw_pkt *)db_tr->buf;
2522 ohcifp = (struct fwohci_txpkthdr *) db[1].db.immed;
2523 ohcifp->mode.ld[0] = fp->mode.ld[0];
2524 ohcifp->mode.common.spd = 0 & 0x7;
2525 ohcifp->mode.stream.len = fp->mode.stream.len;
2526 ohcifp->mode.stream.chtag = chtag;
2527 ohcifp->mode.stream.tcode = 0xa;
2528 #if BYTE_ORDER == BIG_ENDIAN
2529 FWOHCI_DMA_WRITE(db[1].db.immed[0], db[1].db.immed[0]);
2530 FWOHCI_DMA_WRITE(db[1].db.immed[1], db[1].db.immed[1]);
2533 FWOHCI_DMA_CLEAR(db[2].db.desc.cmd, OHCI_COUNT_MASK);
2534 FWOHCI_DMA_SET(db[2].db.desc.cmd, fp->mode.stream.len);
2535 FWOHCI_DMA_WRITE(db[2].db.desc.res, 0);
2536 #if 0 /* if bulkxfer->npackets changes */
2537 db[2].db.desc.cmd = OHCI_OUTPUT_LAST
2539 | OHCI_BRANCH_ALWAYS;
2540 db[0].db.desc.depend =
2541 = db[dbch->ndesc - 1].db.desc.depend
2542 = STAILQ_NEXT(db_tr, link)->bus_addr | dbch->ndesc;
2544 FWOHCI_DMA_SET(db[0].db.desc.depend, dbch->ndesc);
2545 FWOHCI_DMA_SET(db[dbch->ndesc - 1].db.desc.depend, dbch->ndesc);
2547 bulkxfer->end = (caddr_t)db_tr;
2548 db_tr = STAILQ_NEXT(db_tr, link);
2550 db = ((struct fwohcidb_tr *)bulkxfer->end)->db;
2551 FWOHCI_DMA_CLEAR(db[0].db.desc.depend, 0xf);
2552 FWOHCI_DMA_CLEAR(db[dbch->ndesc - 1].db.desc.depend, 0xf);
2553 #if 0 /* if bulkxfer->npackets changes */
2554 db[dbch->ndesc - 1].db.desc.control |= OHCI_INTERRUPT_ALWAYS;
2555 /* OHCI 1.1 and above */
2556 db[0].db.desc.control |= OHCI_INTERRUPT_ALWAYS;
2559 db_tr = (struct fwohcidb_tr *)bulkxfer->start;
2560 fdb_tr = (struct fwohcidb_tr *)bulkxfer->end;
2561 device_printf(sc->fc.dev, "DB %08x %3d %08x %08x\n", bulkxfer, bulkxfer->npacket, db_tr->bus_addr, fdb_tr->bus_addr);
2567 fwohci_add_tx_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr,
2570 struct fwohcidb *db = db_tr->db;
2571 struct fw_xferq *it;
2579 db_tr->buf = fwdma_v_addr(it->buf, poffset);
2582 FWOHCI_DMA_WRITE(db[0].db.desc.cmd,
2583 OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | 8);
2584 FWOHCI_DMA_WRITE(db[0].db.desc.addr, 0);
2585 bzero((void *)&db[1].db.immed[0], sizeof(db[1].db.immed));
2586 FWOHCI_DMA_WRITE(db[2].db.desc.addr,
2587 fwdma_bus_addr(it->buf, poffset) + sizeof(uint32_t));
2589 FWOHCI_DMA_WRITE(db[2].db.desc.cmd,
2590 OHCI_OUTPUT_LAST | OHCI_UPDATE | OHCI_BRANCH_ALWAYS);
2592 FWOHCI_DMA_WRITE(db[0].db.desc.res, 0);
2593 FWOHCI_DMA_WRITE(db[2].db.desc.res, 0);
2599 fwohci_add_rx_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr,
2600 int poffset, struct fwdma_alloc *dummy_dma)
2602 struct fwohcidb *db = db_tr->db;
2603 struct fw_xferq *ir;
2609 if (ir->buf == NULL && (dbch->xferq.flag & FWXFERQ_EXTBUF) == 0) {
2610 if (db_tr->buf == NULL) {
2611 db_tr->buf = fwdma_malloc_size(dbch->dmat,
2612 &db_tr->dma_map, ir->psize, &dbuf[0],
2614 if (db_tr->buf == NULL)
2618 dsiz[0] = ir->psize;
2619 bus_dmamap_sync(dbch->dmat, db_tr->dma_map,
2620 BUS_DMASYNC_PREREAD);
2623 if (dummy_dma != NULL) {
2624 dsiz[db_tr->dbcnt] = sizeof(uint32_t);
2625 dbuf[db_tr->dbcnt++] = dummy_dma->bus_addr;
2627 dsiz[db_tr->dbcnt] = ir->psize;
2628 if (ir->buf != NULL) {
2629 db_tr->buf = fwdma_v_addr(ir->buf, poffset);
2630 dbuf[db_tr->dbcnt] = fwdma_bus_addr( ir->buf, poffset);
2634 for(i = 0 ; i < db_tr->dbcnt ; i++){
2635 FWOHCI_DMA_WRITE(db[i].db.desc.addr, dbuf[i]);
2636 FWOHCI_DMA_WRITE(db[i].db.desc.cmd, OHCI_INPUT_MORE | dsiz[i]);
2637 if (ir->flag & FWXFERQ_STREAM) {
2638 FWOHCI_DMA_SET(db[i].db.desc.cmd, OHCI_UPDATE);
2640 FWOHCI_DMA_WRITE(db[i].db.desc.res, dsiz[i]);
2642 ldesc = db_tr->dbcnt - 1;
2643 if (ir->flag & FWXFERQ_STREAM) {
2644 FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, OHCI_INPUT_LAST);
2646 FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, OHCI_BRANCH_ALWAYS);
2652 fwohci_arcv_swap(struct fw_pkt *fp, int len)
2657 #if BYTE_ORDER == BIG_ENDIAN
2661 ld0 = FWOHCI_DMA_READ(fp->mode.ld[0]);
2663 printf("ld0: x%08x\n", ld0);
2665 fp0 = (struct fw_pkt *)&ld0;
2666 /* determine length to swap */
2667 switch (fp0->mode.common.tcode) {
2672 case FWOHCITCODE_PHY:
2683 printf("Unknown tcode %d\n", fp0->mode.common.tcode);
2686 hlen = tinfo[fp0->mode.common.tcode].hdr_len;
2689 printf("splitted header\n");
2692 #if BYTE_ORDER == BIG_ENDIAN
2693 for(i = 0; i < slen/4; i ++)
2694 fp->mode.ld[i] = FWOHCI_DMA_READ(fp->mode.ld[i]);
2700 fwohci_get_plen(struct fwohci_softc *sc, struct fwohci_dbch *dbch, struct fw_pkt *fp)
2702 struct tcode_info *info;
2705 info = &tinfo[fp->mode.common.tcode];
2706 r = info->hdr_len + sizeof(uint32_t);
2707 if ((info->flag & FWTI_BLOCK_ASY) != 0)
2708 r += roundup2(fp->mode.wreqb.len, sizeof(uint32_t));
2710 if (r == sizeof(uint32_t)) {
2712 device_printf(sc->fc.dev, "Unknown tcode %d\n",
2713 fp->mode.common.tcode);
2717 if (r > dbch->xferq.psize) {
2718 device_printf(sc->fc.dev, "Invalid packet length %d\n", r);
2727 fwohci_arcv_free_buf(struct fwohci_softc *sc, struct fwohci_dbch *dbch,
2728 struct fwohcidb_tr *db_tr, uint32_t off, int wake)
2730 struct fwohcidb *db = &db_tr->db[0];
2732 FWOHCI_DMA_CLEAR(db->db.desc.depend, 0xf);
2733 FWOHCI_DMA_WRITE(db->db.desc.res, dbch->xferq.psize);
2734 FWOHCI_DMA_SET(dbch->bottom->db[0].db.desc.depend, 1);
2735 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE);
2736 dbch->bottom = db_tr;
2739 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_WAKE);
2743 fwohci_arcv(struct fwohci_softc *sc, struct fwohci_dbch *dbch, int count)
2745 struct fwohcidb_tr *db_tr;
2746 struct iovec vec[2];
2747 struct fw_pkt pktbuf;
2751 uint32_t stat, off, status, event;
2753 int len, plen, hlen, pcnt, offset;
2758 if(&sc->arrq == dbch){
2760 }else if(&sc->arrs == dbch){
2769 /* XXX we cannot handle a packet which lies in more than two buf */
2770 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTREAD);
2771 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTWRITE);
2772 status = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) >> OHCI_STATUS_SHIFT;
2773 resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) & OHCI_COUNT_MASK;
2774 while (status & OHCI_CNTL_DMA_ACTIVE) {
2777 if (off == OHCI_ARQOFF)
2778 printf("buf 0x%08x, status 0x%04x, resCount 0x%04x\n",
2779 db_tr->bus_addr, status, resCount);
2781 len = dbch->xferq.psize - resCount;
2782 ld = (uint8_t *)db_tr->buf;
2783 if (dbch->pdb_tr == NULL) {
2784 len -= dbch->buf_offset;
2785 ld += dbch->buf_offset;
2788 bus_dmamap_sync(dbch->dmat, db_tr->dma_map,
2789 BUS_DMASYNC_POSTREAD);
2791 if (count >= 0 && count-- == 0)
2793 if(dbch->pdb_tr != NULL){
2794 /* we have a fragment in previous buffer */
2797 offset = dbch->buf_offset;
2800 buf = dbch->pdb_tr->buf + offset;
2801 rlen = dbch->xferq.psize - offset;
2803 printf("rlen=%d, offset=%d\n",
2804 rlen, dbch->buf_offset);
2805 if (dbch->buf_offset < 0) {
2806 /* splitted in header, pull up */
2809 p = (char *)&pktbuf;
2810 bcopy(buf, p, rlen);
2812 /* this must be too long but harmless */
2813 rlen = sizeof(pktbuf) - rlen;
2815 printf("why rlen < 0\n");
2816 bcopy(db_tr->buf, p, rlen);
2819 hlen = fwohci_arcv_swap(&pktbuf, sizeof(pktbuf));
2821 printf("hlen should be positive.");
2824 offset = sizeof(pktbuf);
2825 vec[0].iov_base = (char *)&pktbuf;
2826 vec[0].iov_len = offset;
2828 /* splitted in payload */
2830 vec[0].iov_base = buf;
2831 vec[0].iov_len = rlen;
2833 fp=(struct fw_pkt *)vec[0].iov_base;
2836 /* no fragment in previous buffer */
2837 fp=(struct fw_pkt *)ld;
2838 hlen = fwohci_arcv_swap(fp, len);
2842 dbch->pdb_tr = db_tr;
2843 dbch->buf_offset = - dbch->buf_offset;
2845 if (resCount != 0) {
2846 printf("resCount=%d hlen=%d\n",
2855 plen = fwohci_get_plen(sc, dbch, fp) - offset;
2857 /* minimum header size + trailer
2858 = sizeof(fw_pkt) so this shouldn't happens */
2859 printf("plen(%d) is negative! offset=%d\n",
2866 dbch->pdb_tr = db_tr;
2868 printf("splitted payload\n");
2870 if (resCount != 0) {
2871 printf("resCount=%d plen=%d"
2873 resCount, plen, len);
2878 vec[nvec].iov_base = ld;
2879 vec[nvec].iov_len = plen;
2883 dbch->buf_offset = ld - (uint8_t *)db_tr->buf;
2885 printf("nvec == 0\n");
2887 /* DMA result-code will be written at the tail of packet */
2888 stat = FWOHCI_DMA_READ(*(uint32_t *)(ld - sizeof(struct fwohci_trailer)));
2890 printf("plen: %d, stat %x\n",
2893 spd = (stat >> 21) & 0x3;
2894 event = (stat >> 16) & 0x1f;
2896 case FWOHCIEV_ACKPEND:
2898 printf("fwohci_arcv: ack pending tcode=0x%x..\n", fp->mode.common.tcode);
2901 case FWOHCIEV_ACKCOMPL:
2903 struct fw_rcv_buf rb;
2905 if ((vec[nvec-1].iov_len -=
2906 sizeof(struct fwohci_trailer)) == 0)
2915 case FWOHCIEV_BUSRST:
2916 if ((sc->fc.status != FWBUSRESET) &&
2917 (sc->fc.status != FWBUSINIT))
2918 printf("got BUSRST packet!?\n");
2921 device_printf(sc->fc.dev,
2922 "Async DMA Receive error err=%02x %s"
2923 " plen=%d offset=%d len=%d status=0x%08x"
2924 " tcode=0x%x, stat=0x%08x\n",
2925 event, fwohcicode[event], plen,
2926 dbch->buf_offset, len,
2927 OREAD(sc, OHCI_DMACTL(off)),
2928 fp->mode.common.tcode, stat);
2935 if (dbch->pdb_tr != NULL) {
2936 fwohci_arcv_free_buf(sc, dbch, dbch->pdb_tr,
2938 dbch->pdb_tr = NULL;
2943 if (resCount == 0) {
2944 /* done on this buffer */
2945 if (dbch->pdb_tr == NULL) {
2946 fwohci_arcv_free_buf(sc, dbch, db_tr, off, 1);
2947 dbch->buf_offset = 0;
2949 if (dbch->pdb_tr != db_tr)
2950 printf("pdb_tr != db_tr\n");
2951 db_tr = STAILQ_NEXT(db_tr, link);
2952 status = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res)
2953 >> OHCI_STATUS_SHIFT;
2954 resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res)
2956 /* XXX check buffer overrun */
2959 dbch->buf_offset = dbch->xferq.psize - resCount;
2962 /* XXX make sure DMA is not dead */
2966 printf("fwohci_arcv: no packets\n");
2972 device_printf(sc->fc.dev, "AR DMA status=%x, ",
2973 OREAD(sc, OHCI_DMACTL(off)));
2974 dbch->pdb_tr = NULL;
2975 /* skip until resCount != 0 */
2976 printf(" skip buffer");
2977 while (resCount == 0) {
2979 fwohci_arcv_free_buf(sc, dbch, db_tr, off, 0);
2980 db_tr = STAILQ_NEXT(db_tr, link);
2981 resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res)
2986 dbch->buf_offset = dbch->xferq.psize - resCount;
2987 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_WAKE);