2 * Copyright (c) 1995, David Greenman
3 * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice unmodified, this list of conditions, and the following
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 * Intel EtherExpress Pro/100B PCI Fast Ethernet driver
35 #include <sys/param.h>
36 #include <sys/systm.h>
38 #include <sys/malloc.h>
39 /* #include <sys/mutex.h> */
40 #include <sys/kernel.h>
41 #include <sys/socket.h>
42 #include <sys/sysctl.h>
45 #include <net/if_dl.h>
46 #include <net/if_media.h>
50 #include <netns/ns_if.h>
54 #include <sys/sockio.h>
56 #include <machine/bus.h>
58 #include <machine/resource.h>
60 #include <net/ethernet.h>
61 #include <net/if_arp.h>
63 #include <vm/vm.h> /* for vtophys */
64 #include <vm/pmap.h> /* for vtophys */
65 #include <machine/clock.h> /* for DELAY */
67 #include <net/if_types.h>
68 #include <net/if_vlan_var.h>
70 #include <pci/pcivar.h>
71 #include <pci/pcireg.h> /* for PCIM_CMD_xxx */
73 #include <dev/mii/mii.h>
74 #include <dev/mii/miivar.h>
76 #include <dev/fxp/if_fxpreg.h>
77 #include <dev/fxp/if_fxpvar.h>
78 #include <dev/fxp/rcvbundl.h>
80 MODULE_DEPEND(fxp, miibus, 1, 1, 1);
81 #include "miibus_if.h"
84 * NOTE! On the Alpha, we have an alignment constraint. The
85 * card DMAs the packet immediately following the RFA. However,
86 * the first thing in the packet is a 14-byte Ethernet header.
87 * This means that the packet is misaligned. To compensate,
88 * we actually offset the RFA 2 bytes into the cluster. This
89 * alignes the packet after the Ethernet header at a 32-bit
90 * boundary. HOWEVER! This means that the RFA is misaligned!
92 #define RFA_ALIGNMENT_FUDGE 2
95 * Set initial transmit threshold at 64 (512 bytes). This is
96 * increased by 64 (512 bytes) at a time, to maximum of 192
97 * (1536 bytes), if an underrun occurs.
99 static int tx_threshold = 64;
102 * The configuration byte map has several undefined fields which
103 * must be one or must be zero. Set up a template for these bits
104 * only, (assuming a 82557 chip) leaving the actual configuration
107 * See struct fxp_cb_config for the bit definitions.
109 static u_char fxp_cb_config_template[] = {
110 0x0, 0x0, /* cb_status */
111 0x0, 0x0, /* cb_command */
112 0x0, 0x0, 0x0, 0x0, /* link_addr */
143 * Claim various Intel PCI device identifiers for this driver. The
144 * sub-vendor and sub-device field are extensively used to identify
145 * particular variants, but we don't currently differentiate between
148 static struct fxp_ident fxp_ident_table[] = {
149 { 0x1229, "Intel Pro 10/100B/100+ Ethernet" },
150 { 0x2449, "Intel Pro/100 Ethernet" },
151 { 0x1209, "Intel Embedded 10/100 Ethernet" },
152 { 0x1029, "Intel Pro/100 Ethernet" },
153 { 0x1030, "Intel Pro/100 Ethernet" },
154 { 0x1031, "Intel Pro/100 Ethernet" },
155 { 0x1032, "Intel Pro/100 Ethernet" },
156 { 0x1033, "Intel Pro/100 Ethernet" },
157 { 0x1034, "Intel Pro/100 Ethernet" },
158 { 0x1035, "Intel Pro/100 Ethernet" },
159 { 0x1036, "Intel Pro/100 Ethernet" },
160 { 0x1037, "Intel Pro/100 Ethernet" },
161 { 0x1038, "Intel Pro/100 Ethernet" },
165 static int fxp_probe(device_t dev);
166 static int fxp_attach(device_t dev);
167 static int fxp_detach(device_t dev);
168 static int fxp_shutdown(device_t dev);
169 static int fxp_suspend(device_t dev);
170 static int fxp_resume(device_t dev);
172 static void fxp_intr(void *xsc);
173 static void fxp_init(void *xsc);
174 static void fxp_tick(void *xsc);
175 static void fxp_powerstate_d0(device_t dev);
176 static void fxp_start(struct ifnet *ifp);
177 static void fxp_stop(struct fxp_softc *sc);
178 static void fxp_release(struct fxp_softc *sc);
179 static int fxp_ioctl(struct ifnet *ifp, u_long command,
181 static void fxp_watchdog(struct ifnet *ifp);
182 static int fxp_add_rfabuf(struct fxp_softc *sc, struct mbuf *oldm);
183 static int fxp_mc_addrs(struct fxp_softc *sc);
184 static void fxp_mc_setup(struct fxp_softc *sc);
185 static u_int16_t fxp_eeprom_getword(struct fxp_softc *sc, int offset,
187 static void fxp_eeprom_putword(struct fxp_softc *sc, int offset,
189 static void fxp_autosize_eeprom(struct fxp_softc *sc);
190 static void fxp_read_eeprom(struct fxp_softc *sc, u_short *data,
191 int offset, int words);
192 static void fxp_write_eeprom(struct fxp_softc *sc, u_short *data,
193 int offset, int words);
194 static int fxp_ifmedia_upd(struct ifnet *ifp);
195 static void fxp_ifmedia_sts(struct ifnet *ifp,
196 struct ifmediareq *ifmr);
197 static int fxp_serial_ifmedia_upd(struct ifnet *ifp);
198 static void fxp_serial_ifmedia_sts(struct ifnet *ifp,
199 struct ifmediareq *ifmr);
200 static volatile int fxp_miibus_readreg(device_t dev, int phy, int reg);
201 static void fxp_miibus_writereg(device_t dev, int phy, int reg,
203 static void fxp_load_ucode(struct fxp_softc *sc);
204 static int sysctl_int_range(SYSCTL_HANDLER_ARGS,
206 static int sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS);
207 static int sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS);
208 static __inline void fxp_lwcopy(volatile u_int32_t *src,
209 volatile u_int32_t *dst);
210 static __inline void fxp_scb_wait(struct fxp_softc *sc);
211 static __inline void fxp_scb_cmd(struct fxp_softc *sc, int cmd);
212 static __inline void fxp_dma_wait(volatile u_int16_t *status,
213 struct fxp_softc *sc);
215 static device_method_t fxp_methods[] = {
216 /* Device interface */
217 DEVMETHOD(device_probe, fxp_probe),
218 DEVMETHOD(device_attach, fxp_attach),
219 DEVMETHOD(device_detach, fxp_detach),
220 DEVMETHOD(device_shutdown, fxp_shutdown),
221 DEVMETHOD(device_suspend, fxp_suspend),
222 DEVMETHOD(device_resume, fxp_resume),
225 DEVMETHOD(miibus_readreg, fxp_miibus_readreg),
226 DEVMETHOD(miibus_writereg, fxp_miibus_writereg),
231 static driver_t fxp_driver = {
234 sizeof(struct fxp_softc),
237 static devclass_t fxp_devclass;
239 DRIVER_MODULE(if_fxp, pci, fxp_driver, fxp_devclass, 0, 0);
240 DRIVER_MODULE(if_fxp, cardbus, fxp_driver, fxp_devclass, 0, 0);
241 DRIVER_MODULE(miibus, fxp, miibus_driver, miibus_devclass, 0, 0);
244 * Inline function to copy a 16-bit aligned 32-bit quantity.
247 fxp_lwcopy(volatile u_int32_t *src, volatile u_int32_t *dst)
252 volatile u_int16_t *a = (volatile u_int16_t *)src;
253 volatile u_int16_t *b = (volatile u_int16_t *)dst;
261 * Wait for the previous command to be accepted (but not necessarily
265 fxp_scb_wait(struct fxp_softc *sc)
269 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i)
272 device_printf(sc->dev, "SCB timeout: 0x%x 0x%x 0x%x 0x%x\n",
273 CSR_READ_1(sc, FXP_CSR_SCB_COMMAND),
274 CSR_READ_1(sc, FXP_CSR_SCB_STATACK),
275 CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS),
276 CSR_READ_2(sc, FXP_CSR_FLOWCONTROL));
280 fxp_scb_cmd(struct fxp_softc *sc, int cmd)
283 if (cmd == FXP_SCB_COMMAND_CU_RESUME && sc->cu_resume_bug) {
284 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_CB_COMMAND_NOP);
287 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd);
291 fxp_dma_wait(volatile u_int16_t *status, struct fxp_softc *sc)
295 while (!(*status & FXP_CB_STATUS_C) && --i)
298 device_printf(sc->dev, "DMA timeout\n");
302 * Return identification string if this is device is ours.
305 fxp_probe(device_t dev)
308 struct fxp_ident *ident;
310 if (pci_get_vendor(dev) == FXP_VENDORID_INTEL) {
311 devid = pci_get_device(dev);
312 for (ident = fxp_ident_table; ident->name != NULL; ident++) {
313 if (ident->devid == devid) {
314 device_set_desc(dev, ident->name);
323 fxp_powerstate_d0(device_t dev)
325 #if __FreeBSD_version >= 430002
326 u_int32_t iobase, membase, irq;
328 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
329 /* Save important PCI config data. */
330 iobase = pci_read_config(dev, FXP_PCI_IOBA, 4);
331 membase = pci_read_config(dev, FXP_PCI_MMBA, 4);
332 irq = pci_read_config(dev, PCIR_INTLINE, 4);
334 /* Reset the power state. */
335 device_printf(dev, "chip is in D%d power mode "
336 "-- setting to D0\n", pci_get_powerstate(dev));
338 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
340 /* Restore PCI config data. */
341 pci_write_config(dev, FXP_PCI_IOBA, iobase, 4);
342 pci_write_config(dev, FXP_PCI_MMBA, membase, 4);
343 pci_write_config(dev, PCIR_INTLINE, irq, 4);
349 fxp_attach(device_t dev)
352 struct fxp_softc *sc = device_get_softc(dev);
356 int i, rid, m1, m2, prefer_iomap;
359 bzero(sc, sizeof(*sc));
361 callout_handle_init(&sc->stat_ch);
362 sysctl_ctx_init(&sc->sysctl_ctx);
363 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_DEF | MTX_RECURSE);
368 * Enable bus mastering. Enable memory space too, in case
369 * BIOS/Prom forgot about it.
371 val = pci_read_config(dev, PCIR_COMMAND, 2);
372 val |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
373 pci_write_config(dev, PCIR_COMMAND, val, 2);
374 val = pci_read_config(dev, PCIR_COMMAND, 2);
376 fxp_powerstate_d0(dev);
379 * Figure out which we should try first - memory mapping or i/o mapping?
380 * We default to memory mapping. Then we accept an override from the
381 * command line. Then we check to see which one is enabled.
384 m2 = PCIM_CMD_PORTEN;
386 if (resource_int_value(device_get_name(dev), device_get_unit(dev),
387 "prefer_iomap", &prefer_iomap) == 0 && prefer_iomap != 0) {
388 m1 = PCIM_CMD_PORTEN;
394 (m1 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT;
395 sc->rgd = (m1 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA;
396 sc->mem = bus_alloc_resource(dev, sc->rtp, &sc->rgd,
397 0, ~0, 1, RF_ACTIVE);
399 if (sc->mem == NULL && (val & m2)) {
401 (m2 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT;
402 sc->rgd = (m2 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA;
403 sc->mem = bus_alloc_resource(dev, sc->rtp, &sc->rgd,
404 0, ~0, 1, RF_ACTIVE);
408 device_printf(dev, "could not map device registers\n");
413 device_printf(dev, "using %s space register mapping\n",
414 sc->rtp == SYS_RES_MEMORY? "memory" : "I/O");
417 sc->sc_st = rman_get_bustag(sc->mem);
418 sc->sc_sh = rman_get_bushandle(sc->mem);
421 * Allocate our interrupt.
424 sc->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
425 RF_SHAREABLE | RF_ACTIVE);
426 if (sc->irq == NULL) {
427 device_printf(dev, "could not map interrupt\n");
432 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET,
433 fxp_intr, sc, &sc->ih);
435 device_printf(dev, "could not setup irq\n");
440 * Reset to a stable state.
442 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET);
445 sc->cbl_base = malloc(sizeof(struct fxp_cb_tx) * FXP_NTXCB,
446 M_DEVBUF, M_NOWAIT | M_ZERO);
447 if (sc->cbl_base == NULL)
450 sc->fxp_stats = malloc(sizeof(struct fxp_stats), M_DEVBUF,
452 if (sc->fxp_stats == NULL)
455 sc->mcsp = malloc(sizeof(struct fxp_cb_mcs), M_DEVBUF, M_NOWAIT);
456 if (sc->mcsp == NULL)
460 * Pre-allocate our receive buffers.
462 for (i = 0; i < FXP_NRFABUFS; i++) {
463 if (fxp_add_rfabuf(sc, NULL) != 0) {
469 * Find out how large of an SEEPROM we have.
471 fxp_autosize_eeprom(sc);
474 * Determine whether we must use the 503 serial interface.
476 fxp_read_eeprom(sc, &data, 6, 1);
477 if ((data & FXP_PHY_DEVICE_MASK) != 0 &&
478 (data & FXP_PHY_SERIAL_ONLY))
479 sc->flags |= FXP_FLAG_SERIAL_MEDIA;
482 * Create the sysctl tree
484 sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx,
485 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO,
486 device_get_nameunit(dev), CTLFLAG_RD, 0, "");
487 if (sc->sysctl_tree == NULL)
489 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
490 OID_AUTO, "int_delay", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_PRISON,
491 &sc->tunable_int_delay, 0, &sysctl_hw_fxp_int_delay, "I",
492 "FXP driver receive interrupt microcode bundling delay");
493 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
494 OID_AUTO, "bundle_max", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_PRISON,
495 &sc->tunable_bundle_max, 0, &sysctl_hw_fxp_bundle_max, "I",
496 "FXP driver receive interrupt microcode bundle size limit");
499 * Pull in device tunables.
501 sc->tunable_int_delay = TUNABLE_INT_DELAY;
502 sc->tunable_bundle_max = TUNABLE_BUNDLE_MAX;
503 (void) resource_int_value(device_get_name(dev), device_get_unit(dev),
504 "int_delay", &sc->tunable_int_delay);
505 (void) resource_int_value(device_get_name(dev), device_get_unit(dev),
506 "bundle_max", &sc->tunable_bundle_max);
509 * Find out the chip revision; lump all 82557 revs together.
511 fxp_read_eeprom(sc, &data, 5, 1);
512 if ((data >> 8) == 1)
513 sc->revision = FXP_REV_82557;
515 sc->revision = pci_get_revid(dev);
518 * Enable workarounds for certain chip revision deficiencies.
520 * Systems based on the ICH2/ICH2-M chip from Intel, and possibly
521 * some systems based a normal 82559 design, have a defect where
522 * the chip can cause a PCI protocol violation if it receives
523 * a CU_RESUME command when it is entering the IDLE state. The
524 * workaround is to disable Dynamic Standby Mode, so the chip never
525 * deasserts CLKRUN#, and always remains in an active state.
527 * See Intel 82801BA/82801BAM Specification Update, Errata #30.
529 i = pci_get_device(dev);
530 if (i == 0x2449 || (i > 0x1030 && i < 0x1039) ||
531 sc->revision >= FXP_REV_82559_A0) {
532 fxp_read_eeprom(sc, &data, 10, 1);
533 if (data & 0x02) { /* STB enable */
538 "Disabling dynamic standby mode in EEPROM\n");
540 fxp_write_eeprom(sc, &data, 10, 1);
541 device_printf(dev, "New EEPROM ID: 0x%x\n", data);
543 for (i = 0; i < (1 << sc->eeprom_size) - 1; i++) {
544 fxp_read_eeprom(sc, &data, i, 1);
547 i = (1 << sc->eeprom_size) - 1;
548 cksum = 0xBABA - cksum;
549 fxp_read_eeprom(sc, &data, i, 1);
550 fxp_write_eeprom(sc, &cksum, i, 1);
552 "EEPROM checksum @ 0x%x: 0x%x -> 0x%x\n",
556 * If the user elects to continue, try the software
557 * workaround, as it is better than nothing.
559 sc->flags |= FXP_FLAG_CU_RESUME_BUG;
565 * If we are not a 82557 chip, we can enable extended features.
567 if (sc->revision != FXP_REV_82557) {
569 * If MWI is enabled in the PCI configuration, and there
570 * is a valid cacheline size (8 or 16 dwords), then tell
571 * the board to turn on MWI.
573 if (val & PCIM_CMD_MWRICEN &&
574 pci_read_config(dev, PCIR_CACHELNSZ, 1) != 0)
575 sc->flags |= FXP_FLAG_MWI_ENABLE;
577 /* turn on the extended TxCB feature */
578 sc->flags |= FXP_FLAG_EXT_TXCB;
580 /* enable reception of long frames for VLAN */
581 sc->flags |= FXP_FLAG_LONG_PKT_EN;
587 fxp_read_eeprom(sc, (u_int16_t *)sc->arpcom.ac_enaddr, 0, 3);
588 device_printf(dev, "Ethernet address %6D%s\n",
589 sc->arpcom.ac_enaddr, ":",
590 sc->flags & FXP_FLAG_SERIAL_MEDIA ? ", 10Mbps" : "");
592 device_printf(dev, "PCI IDs: %04x %04x %04x %04x %04x\n",
593 pci_get_vendor(dev), pci_get_device(dev),
594 pci_get_subvendor(dev), pci_get_subdevice(dev),
596 fxp_read_eeprom(sc, &data, 10, 1);
597 device_printf(dev, "Dynamic Standby mode is %s\n",
598 data & 0x02 ? "enabled" : "disabled");
602 * If this is only a 10Mbps device, then there is no MII, and
603 * the PHY will use a serial interface instead.
605 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter
606 * doesn't have a programming interface of any sort. The
607 * media is sensed automatically based on how the link partner
608 * is configured. This is, in essence, manual configuration.
610 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) {
611 ifmedia_init(&sc->sc_media, 0, fxp_serial_ifmedia_upd,
612 fxp_serial_ifmedia_sts);
613 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL);
614 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL);
616 if (mii_phy_probe(dev, &sc->miibus, fxp_ifmedia_upd,
618 device_printf(dev, "MII without any PHY!\n");
624 ifp = &sc->arpcom.ac_if;
625 ifp->if_unit = device_get_unit(dev);
626 ifp->if_name = "fxp";
627 ifp->if_output = ether_output;
628 ifp->if_baudrate = 100000000;
629 ifp->if_init = fxp_init;
631 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
632 ifp->if_ioctl = fxp_ioctl;
633 ifp->if_start = fxp_start;
634 ifp->if_watchdog = fxp_watchdog;
637 * Attach the interface.
639 ether_ifattach(ifp, ETHER_BPF_SUPPORTED);
642 * Tell the upper layer(s) we support long frames.
644 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
647 * Let the system queue as many packets as we have available
650 ifp->if_snd.ifq_maxlen = FXP_NTXCB - 1;
656 device_printf(dev, "Failed to malloc memory\n");
665 * release all resources
668 fxp_release(struct fxp_softc *sc)
671 bus_generic_detach(sc->dev);
673 device_delete_child(sc->dev, sc->miibus);
676 free(sc->cbl_base, M_DEVBUF);
678 free(sc->fxp_stats, M_DEVBUF);
680 free(sc->mcsp, M_DEVBUF);
682 m_freem(sc->rfa_headm);
685 bus_teardown_intr(sc->dev, sc->irq, sc->ih);
687 bus_release_resource(sc->dev, SYS_RES_IRQ, 0, sc->irq);
689 bus_release_resource(sc->dev, sc->rtp, sc->rgd, sc->mem);
691 sysctl_ctx_free(&sc->sysctl_ctx);
693 mtx_destroy(&sc->sc_mtx);
700 fxp_detach(device_t dev)
702 struct fxp_softc *sc = device_get_softc(dev);
705 /* disable interrupts */
706 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE);
711 * Stop DMA and drop transmit queue.
716 * Close down routes etc.
718 ether_ifdetach(&sc->arpcom.ac_if, ETHER_BPF_SUPPORTED);
721 * Free all media structures.
723 ifmedia_removeall(&sc->sc_media);
727 /* Release our allocated resources. */
734 * Device shutdown routine. Called at system shutdown after sync. The
735 * main purpose of this routine is to shut off receiver DMA so that
736 * kernel memory doesn't get clobbered during warmboot.
739 fxp_shutdown(device_t dev)
742 * Make sure that DMA is disabled prior to reboot. Not doing
743 * do could allow DMA to corrupt kernel memory during the
744 * reboot before the driver initializes.
746 fxp_stop((struct fxp_softc *) device_get_softc(dev));
751 * Device suspend routine. Stop the interface and save some PCI
752 * settings in case the BIOS doesn't restore them properly on
756 fxp_suspend(device_t dev)
758 struct fxp_softc *sc = device_get_softc(dev);
765 for (i = 0; i < 5; i++)
766 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4);
767 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4);
768 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1);
769 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
770 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
779 * Device resume routine. Restore some PCI settings in case the BIOS
780 * doesn't, re-enable busmastering, and restart the interface if
784 fxp_resume(device_t dev)
786 struct fxp_softc *sc = device_get_softc(dev);
787 struct ifnet *ifp = &sc->sc_if;
788 u_int16_t pci_command;
793 fxp_powerstate_d0(dev);
795 /* better way to do this? */
796 for (i = 0; i < 5; i++)
797 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4);
798 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4);
799 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1);
800 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1);
801 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1);
803 /* reenable busmastering */
804 pci_command = pci_read_config(dev, PCIR_COMMAND, 2);
805 pci_command |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
806 pci_write_config(dev, PCIR_COMMAND, pci_command, 2);
808 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET);
811 /* reinitialize interface if necessary */
812 if (ifp->if_flags & IFF_UP)
822 fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int length)
830 for (x = 1 << (length - 1); x; x >>= 1) {
832 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI;
834 reg = FXP_EEPROM_EECS;
835 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
837 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK);
839 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
845 * Read from the serial EEPROM. Basically, you manually shift in
846 * the read opcode (one bit at a time) and then shift in the address,
847 * and then you shift out the data (all of this one bit at a time).
848 * The word size is 16 bits, so you have to provide the address for
849 * every 16 bits of data.
852 fxp_eeprom_getword(struct fxp_softc *sc, int offset, int autosize)
857 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
859 * Shift in read opcode.
861 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3);
866 for (x = 1 << (sc->eeprom_size - 1); x; x >>= 1) {
868 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI;
870 reg = FXP_EEPROM_EECS;
871 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
873 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK);
875 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
877 reg = CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO;
879 if (autosize && reg == 0) {
880 sc->eeprom_size = data;
888 reg = FXP_EEPROM_EECS;
889 for (x = 1 << 15; x; x >>= 1) {
890 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK);
892 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO)
894 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
897 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
904 fxp_eeprom_putword(struct fxp_softc *sc, int offset, u_int16_t data)
909 * Erase/write enable.
911 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
912 fxp_eeprom_shiftin(sc, 0x4, 3);
913 fxp_eeprom_shiftin(sc, 0x03 << (sc->eeprom_size - 2), sc->eeprom_size);
914 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
917 * Shift in write opcode, address, data.
919 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
920 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3);
921 fxp_eeprom_shiftin(sc, offset, sc->eeprom_size);
922 fxp_eeprom_shiftin(sc, data, 16);
923 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
926 * Wait for EEPROM to finish up.
928 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
930 for (i = 0; i < 1000; i++) {
931 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO)
935 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
938 * Erase/write disable.
940 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
941 fxp_eeprom_shiftin(sc, 0x4, 3);
942 fxp_eeprom_shiftin(sc, 0, sc->eeprom_size);
943 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
950 * Figure out EEPROM size.
952 * 559's can have either 64-word or 256-word EEPROMs, the 558
953 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet
954 * talks about the existance of 16 to 256 word EEPROMs.
956 * The only known sizes are 64 and 256, where the 256 version is used
957 * by CardBus cards to store CIS information.
959 * The address is shifted in msb-to-lsb, and after the last
960 * address-bit the EEPROM is supposed to output a `dummy zero' bit,
961 * after which follows the actual data. We try to detect this zero, by
962 * probing the data-out bit in the EEPROM control register just after
963 * having shifted in a bit. If the bit is zero, we assume we've
964 * shifted enough address bits. The data-out should be tri-state,
965 * before this, which should translate to a logical one.
968 fxp_autosize_eeprom(struct fxp_softc *sc)
971 /* guess maximum size of 256 words */
975 (void) fxp_eeprom_getword(sc, 0, 1);
979 fxp_read_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words)
983 for (i = 0; i < words; i++)
984 data[i] = fxp_eeprom_getword(sc, offset + i, 0);
988 fxp_write_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words)
992 for (i = 0; i < words; i++)
993 fxp_eeprom_putword(sc, offset + i, data[i]);
997 * Start packet transmission on the interface.
1000 fxp_start(struct ifnet *ifp)
1002 struct fxp_softc *sc = ifp->if_softc;
1003 struct fxp_cb_tx *txp;
1006 * See if we need to suspend xmit until the multicast filter
1007 * has been reprogrammed (which can only be done at the head
1008 * of the command chain).
1010 if (sc->need_mcsetup) {
1017 * We're finished if there is nothing more to add to the list or if
1018 * we're all filled up with buffers to transmit.
1019 * NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add
1020 * a NOP command when needed.
1022 while (ifp->if_snd.ifq_head != NULL && sc->tx_queued < FXP_NTXCB - 1) {
1023 struct mbuf *m, *mb_head;
1027 * Grab a packet to transmit.
1029 IF_DEQUEUE(&ifp->if_snd, mb_head);
1032 * Get pointer to next available tx desc.
1034 txp = sc->cbl_last->next;
1037 * Go through each of the mbufs in the chain and initialize
1038 * the transmit buffer descriptors with the physical address
1039 * and size of the mbuf.
1042 for (m = mb_head, segment = 0; m != NULL; m = m->m_next) {
1043 if (m->m_len != 0) {
1044 if (segment == FXP_NTXSEG)
1046 txp->tbd[segment].tb_addr =
1047 vtophys(mtod(m, vm_offset_t));
1048 txp->tbd[segment].tb_size = m->m_len;
1056 * We ran out of segments. We have to recopy this
1057 * mbuf chain first. Bail out if we can't get the
1060 MGETHDR(mn, M_DONTWAIT, MT_DATA);
1065 if (mb_head->m_pkthdr.len > MHLEN) {
1066 MCLGET(mn, M_DONTWAIT);
1067 if ((mn->m_flags & M_EXT) == 0) {
1073 m_copydata(mb_head, 0, mb_head->m_pkthdr.len,
1075 mn->m_pkthdr.len = mn->m_len = mb_head->m_pkthdr.len;
1081 txp->tbd_number = segment;
1082 txp->mb_head = mb_head;
1084 if (sc->tx_queued != FXP_CXINT_THRESH - 1) {
1086 FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF |
1090 FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF |
1091 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I;
1093 * Set a 5 second timer just in case we don't hear
1094 * from the card again.
1098 txp->tx_threshold = tx_threshold;
1101 * Advance the end of list forward.
1106 * On platforms which can't access memory in 16-bit
1107 * granularities, we must prevent the card from DMA'ing
1108 * up the status while we update the command field.
1109 * This could cause us to overwrite the completion status.
1111 atomic_clear_short(&sc->cbl_last->cb_command,
1114 sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S;
1115 #endif /*__alpha__*/
1119 * Advance the beginning of the list forward if there are
1120 * no other packets queued (when nothing is queued, cbl_first
1121 * sits on the last TxCB that was sent out).
1123 if (sc->tx_queued == 0)
1124 sc->cbl_first = txp;
1129 * Pass packet to bpf if there is a listener.
1132 bpf_mtap(ifp, mb_head);
1136 * We're finished. If we added to the list, issue a RESUME to get DMA
1137 * going again if suspended.
1141 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME);
1145 static void fxp_intr_body(struct fxp_softc *sc, u_int8_t statack, int count);
1147 #ifdef DEVICE_POLLING
1148 static poll_handler_t fxp_poll;
1151 fxp_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1153 struct fxp_softc *sc = ifp->if_softc;
1156 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */
1157 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0);
1160 statack = FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA |
1162 if (cmd == POLL_AND_CHECK_STATUS) {
1165 tmp = CSR_READ_1(sc, FXP_CSR_SCB_STATACK);
1166 if (tmp == 0xff || tmp == 0)
1167 return; /* nothing to do */
1169 /* ack what we can */
1171 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, tmp);
1174 fxp_intr_body(sc, statack, count);
1176 #endif /* DEVICE_POLLING */
1179 * Process interface interrupts.
1184 struct fxp_softc *sc = xsc;
1187 #ifdef DEVICE_POLLING
1188 struct ifnet *ifp = &sc->sc_if;
1190 if (ifp->if_ipending & IFF_POLLING)
1192 if (ether_poll_register(fxp_poll, ifp)) {
1193 /* disable interrupts */
1194 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE);
1195 fxp_poll(ifp, 0, 1);
1200 if (sc->suspended) {
1204 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) {
1206 * It should not be possible to have all bits set; the
1207 * FXP_SCB_INTR_SWI bit always returns 0 on a read. If
1208 * all bits are set, this may indicate that the card has
1209 * been physically ejected, so ignore it.
1211 if (statack == 0xff)
1215 * First ACK all the interrupts in this pass.
1217 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack);
1218 fxp_intr_body(sc, statack, -1);
1223 fxp_intr_body(struct fxp_softc *sc, u_int8_t statack, int count)
1225 struct ifnet *ifp = &sc->sc_if;
1228 * Free any finished transmit mbuf chains.
1230 * Handle the CNA event likt a CXTNO event. It used to
1231 * be that this event (control unit not ready) was not
1232 * encountered, but it is now with the SMPng modifications.
1233 * The exact sequence of events that occur when the interface
1234 * is brought up are different now, and if this event
1235 * goes unhandled, the configuration/rxfilter setup sequence
1236 * can stall for several seconds. The result is that no
1237 * packets go out onto the wire for about 5 to 10 seconds
1238 * after the interface is ifconfig'ed for the first time.
1240 if (statack & (FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA)) {
1241 struct fxp_cb_tx *txp;
1243 for (txp = sc->cbl_first; sc->tx_queued &&
1244 (txp->cb_status & FXP_CB_STATUS_C) != 0;
1246 if (txp->mb_head != NULL) {
1247 m_freem(txp->mb_head);
1248 txp->mb_head = NULL;
1252 sc->cbl_first = txp;
1254 if (sc->tx_queued == 0) {
1255 if (sc->need_mcsetup)
1259 * Try to start more packets transmitting.
1261 if (ifp->if_snd.ifq_head != NULL)
1265 * Process receiver interrupts. If a no-resource (RNR)
1266 * condition exists, get whatever packets we can and
1267 * re-start the receiver.
1269 if (statack & (FXP_SCB_STATACK_FR | FXP_SCB_STATACK_RNR)) {
1271 struct fxp_rfa *rfa;
1274 rfa = (struct fxp_rfa *)(m->m_ext.ext_buf +
1275 RFA_ALIGNMENT_FUDGE);
1277 #ifdef DEVICE_POLLING /* loop at most count times if count >=0 */
1278 if (count < 0 || count-- > 0)
1280 if (rfa->rfa_status & FXP_RFA_STATUS_C) {
1282 * Remove first packet from the chain.
1284 sc->rfa_headm = m->m_next;
1288 * Add a new buffer to the receive chain.
1289 * If this fails, the old buffer is recycled
1292 if (fxp_add_rfabuf(sc, m) == 0) {
1293 struct ether_header *eh;
1296 total_len = rfa->actual_size &
1299 sizeof(struct ether_header)) {
1305 * Drop the packet if it has CRC
1306 * errors. This test is only needed
1307 * when doing 802.1q VLAN on the 82557
1310 if (rfa->rfa_status &
1311 FXP_RFA_STATUS_CRC) {
1316 m->m_pkthdr.rcvif = ifp;
1317 m->m_pkthdr.len = m->m_len = total_len;
1318 eh = mtod(m, struct ether_header *);
1320 sizeof(struct ether_header);
1322 sizeof(struct ether_header);
1323 m->m_pkthdr.len = m->m_len;
1324 ether_input(ifp, eh, m);
1328 if (statack & FXP_SCB_STATACK_RNR) {
1330 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL,
1331 vtophys(sc->rfa_headm->m_ext.ext_buf) +
1332 RFA_ALIGNMENT_FUDGE);
1333 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START);
1339 * Update packet in/out/collision statistics. The i82557 doesn't
1340 * allow you to access these counters without doing a fairly
1341 * expensive DMA to get _all_ of the statistics it maintains, so
1342 * we do this operation here only once per second. The statistics
1343 * counters in the kernel are updated from the previous dump-stats
1344 * DMA and then a new dump-stats DMA is started. The on-chip
1345 * counters are zeroed when the DMA completes. If we can't start
1346 * the DMA immediately, we don't wait - we just prepare to read
1347 * them again next time.
1352 struct fxp_softc *sc = xsc;
1353 struct ifnet *ifp = &sc->sc_if;
1354 struct fxp_stats *sp = sc->fxp_stats;
1355 struct fxp_cb_tx *txp;
1358 ifp->if_opackets += sp->tx_good;
1359 ifp->if_collisions += sp->tx_total_collisions;
1361 ifp->if_ipackets += sp->rx_good;
1362 sc->rx_idle_secs = 0;
1365 * Receiver's been idle for another second.
1371 sp->rx_alignment_errors +
1373 sp->rx_overrun_errors;
1375 * If any transmit underruns occured, bump up the transmit
1376 * threshold by another 512 bytes (64 * 8).
1378 if (sp->tx_underruns) {
1379 ifp->if_oerrors += sp->tx_underruns;
1380 if (tx_threshold < 192)
1385 * Release any xmit buffers that have completed DMA. This isn't
1386 * strictly necessary to do here, but it's advantagous for mbufs
1387 * with external storage to be released in a timely manner rather
1388 * than being defered for a potentially long time. This limits
1389 * the delay to a maximum of one second.
1391 for (txp = sc->cbl_first; sc->tx_queued &&
1392 (txp->cb_status & FXP_CB_STATUS_C) != 0;
1394 if (txp->mb_head != NULL) {
1395 m_freem(txp->mb_head);
1396 txp->mb_head = NULL;
1400 sc->cbl_first = txp;
1402 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds,
1403 * then assume the receiver has locked up and attempt to clear
1404 * the condition by reprogramming the multicast filter. This is
1405 * a work-around for a bug in the 82557 where the receiver locks
1406 * up if it gets certain types of garbage in the syncronization
1407 * bits prior to the packet header. This bug is supposed to only
1408 * occur in 10Mbps mode, but has been seen to occur in 100Mbps
1409 * mode as well (perhaps due to a 10/100 speed transition).
1411 if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) {
1412 sc->rx_idle_secs = 0;
1416 * If there is no pending command, start another stats
1417 * dump. Otherwise punt for now.
1419 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) {
1421 * Start another stats dump.
1423 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET);
1426 * A previous command is still waiting to be accepted.
1427 * Just zero our copy of the stats and wait for the
1428 * next timer event to update them.
1431 sp->tx_underruns = 0;
1432 sp->tx_total_collisions = 0;
1435 sp->rx_crc_errors = 0;
1436 sp->rx_alignment_errors = 0;
1437 sp->rx_rnr_errors = 0;
1438 sp->rx_overrun_errors = 0;
1440 if (sc->miibus != NULL)
1441 mii_tick(device_get_softc(sc->miibus));
1444 * Schedule another timeout one second from now.
1446 sc->stat_ch = timeout(fxp_tick, sc, hz);
1450 * Stop the interface. Cancels the statistics updater and resets
1454 fxp_stop(struct fxp_softc *sc)
1456 struct ifnet *ifp = &sc->sc_if;
1457 struct fxp_cb_tx *txp;
1460 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1463 #ifdef DEVICE_POLLING
1464 ether_poll_deregister(ifp);
1467 * Cancel stats updater.
1469 untimeout(fxp_tick, sc, sc->stat_ch);
1472 * Issue software reset, which also unloads the microcode.
1474 sc->flags &= ~FXP_FLAG_UCODE;
1475 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET);
1479 * Release any xmit buffers.
1483 for (i = 0; i < FXP_NTXCB; i++) {
1484 if (txp[i].mb_head != NULL) {
1485 m_freem(txp[i].mb_head);
1486 txp[i].mb_head = NULL;
1493 * Free all the receive buffers then reallocate/reinitialize
1495 if (sc->rfa_headm != NULL)
1496 m_freem(sc->rfa_headm);
1497 sc->rfa_headm = NULL;
1498 sc->rfa_tailm = NULL;
1499 for (i = 0; i < FXP_NRFABUFS; i++) {
1500 if (fxp_add_rfabuf(sc, NULL) != 0) {
1502 * This "can't happen" - we're at splimp()
1503 * and we just freed all the buffers we need
1506 panic("fxp_stop: no buffers!");
1512 * Watchdog/transmission transmit timeout handler. Called when a
1513 * transmission is started on the interface, but no interrupt is
1514 * received before the timeout. This usually indicates that the
1515 * card has wedged for some reason.
1518 fxp_watchdog(struct ifnet *ifp)
1520 struct fxp_softc *sc = ifp->if_softc;
1522 device_printf(sc->dev, "device timeout\n");
1531 struct fxp_softc *sc = xsc;
1532 struct ifnet *ifp = &sc->sc_if;
1533 struct fxp_cb_config *cbp;
1534 struct fxp_cb_ias *cb_ias;
1535 struct fxp_cb_tx *txp;
1536 struct fxp_cb_mcs *mcsp;
1541 * Cancel any pending I/O
1545 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0;
1548 * Initialize base of CBL and RFA memory. Loading with zero
1549 * sets it up for regular linear addressing.
1551 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0);
1552 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE);
1555 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE);
1558 * Initialize base of dump-stats buffer.
1561 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(sc->fxp_stats));
1562 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR);
1565 * Attempt to load microcode if requested.
1567 if (ifp->if_flags & IFF_LINK0 && (sc->flags & FXP_FLAG_UCODE) == 0)
1571 * Initialize the multicast address list.
1573 if (fxp_mc_addrs(sc)) {
1575 mcsp->cb_status = 0;
1576 mcsp->cb_command = FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL;
1577 mcsp->link_addr = -1;
1579 * Start the multicast setup command.
1582 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&mcsp->cb_status));
1583 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
1584 /* ...and wait for it to complete. */
1585 fxp_dma_wait(&mcsp->cb_status, sc);
1589 * We temporarily use memory that contains the TxCB list to
1590 * construct the config CB. The TxCB list memory is rebuilt
1593 cbp = (struct fxp_cb_config *) sc->cbl_base;
1596 * This bcopy is kind of disgusting, but there are a bunch of must be
1597 * zero and must be one bits in this structure and this is the easiest
1598 * way to initialize them all to proper values.
1600 bcopy(fxp_cb_config_template,
1601 (void *)(uintptr_t)(volatile void *)&cbp->cb_status,
1602 sizeof(fxp_cb_config_template));
1605 cbp->cb_command = FXP_CB_COMMAND_CONFIG | FXP_CB_COMMAND_EL;
1606 cbp->link_addr = -1; /* (no) next command */
1607 cbp->byte_count = 22; /* (22) bytes to config */
1608 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */
1609 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */
1610 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */
1611 cbp->mwi_enable = sc->flags & FXP_FLAG_MWI_ENABLE ? 1 : 0;
1612 cbp->type_enable = 0; /* actually reserved */
1613 cbp->read_align_en = sc->flags & FXP_FLAG_READ_ALIGN ? 1 : 0;
1614 cbp->end_wr_on_cl = sc->flags & FXP_FLAG_WRITE_ALIGN ? 1 : 0;
1615 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */
1616 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */
1617 cbp->dma_mbce = 0; /* (disable) dma max counters */
1618 cbp->late_scb = 0; /* (don't) defer SCB update */
1619 cbp->direct_dma_dis = 1; /* disable direct rcv dma mode */
1620 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */
1621 cbp->ci_int = 1; /* interrupt on CU idle */
1622 cbp->ext_txcb_dis = sc->flags & FXP_FLAG_EXT_TXCB ? 0 : 1;
1623 cbp->ext_stats_dis = 1; /* disable extended counters */
1624 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */
1625 cbp->save_bf = sc->revision == FXP_REV_82557 ? 1 : prm;
1626 cbp->disc_short_rx = !prm; /* discard short packets */
1627 cbp->underrun_retry = 1; /* retry mode (once) on DMA underrun */
1628 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */
1629 cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */
1630 cbp->mediatype = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 0 : 1;
1631 cbp->csma_dis = 0; /* (don't) disable link */
1632 cbp->tcp_udp_cksum = 0; /* (don't) enable checksum */
1633 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */
1634 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */
1635 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */
1636 cbp->mc_wake_en = 0; /* (don't) enable PME# on mcmatch */
1637 cbp->nsai = 1; /* (don't) disable source addr insert */
1638 cbp->preamble_length = 2; /* (7 byte) preamble */
1639 cbp->loopback = 0; /* (don't) loopback */
1640 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */
1641 cbp->linear_pri_mode = 0; /* (wait after xmit only) */
1642 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */
1643 cbp->promiscuous = prm; /* promiscuous mode */
1644 cbp->bcast_disable = 0; /* (don't) disable broadcasts */
1645 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/
1646 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */
1647 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */
1648 cbp->crscdt = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 1 : 0;
1650 cbp->stripping = !prm; /* truncate rx packet to byte count */
1651 cbp->padding = 1; /* (do) pad short tx packets */
1652 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */
1653 cbp->long_rx_en = sc->flags & FXP_FLAG_LONG_PKT_EN ? 1 : 0;
1654 cbp->ia_wake_en = 0; /* (don't) wake up on address match */
1655 cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */
1656 /* must set wake_en in PMCSR also */
1657 cbp->force_fdx = 0; /* (don't) force full duplex */
1658 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */
1659 cbp->multi_ia = 0; /* (don't) accept multiple IAs */
1660 cbp->mc_all = sc->flags & FXP_FLAG_ALL_MCAST ? 1 : 0;
1662 if (sc->revision == FXP_REV_82557) {
1664 * The 82557 has no hardware flow control, the values
1665 * below are the defaults for the chip.
1667 cbp->fc_delay_lsb = 0;
1668 cbp->fc_delay_msb = 0x40;
1669 cbp->pri_fc_thresh = 3;
1671 cbp->rx_fc_restop = 0;
1672 cbp->rx_fc_restart = 0;
1674 cbp->pri_fc_loc = 1;
1676 cbp->fc_delay_lsb = 0x1f;
1677 cbp->fc_delay_msb = 0x01;
1678 cbp->pri_fc_thresh = 3;
1679 cbp->tx_fc_dis = 0; /* enable transmit FC */
1680 cbp->rx_fc_restop = 1; /* enable FC restop frames */
1681 cbp->rx_fc_restart = 1; /* enable FC restart frames */
1682 cbp->fc_filter = !prm; /* drop FC frames to host */
1683 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */
1687 * Start the config command/DMA.
1690 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&cbp->cb_status));
1691 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
1692 /* ...and wait for it to complete. */
1693 fxp_dma_wait(&cbp->cb_status, sc);
1696 * Now initialize the station address. Temporarily use the TxCB
1697 * memory area like we did above for the config CB.
1699 cb_ias = (struct fxp_cb_ias *) sc->cbl_base;
1700 cb_ias->cb_status = 0;
1701 cb_ias->cb_command = FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL;
1702 cb_ias->link_addr = -1;
1703 bcopy(sc->arpcom.ac_enaddr,
1704 (void *)(uintptr_t)(volatile void *)cb_ias->macaddr,
1705 sizeof(sc->arpcom.ac_enaddr));
1708 * Start the IAS (Individual Address Setup) command/DMA.
1711 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
1712 /* ...and wait for it to complete. */
1713 fxp_dma_wait(&cb_ias->cb_status, sc);
1716 * Initialize transmit control block (TxCB) list.
1720 bzero(txp, sizeof(struct fxp_cb_tx) * FXP_NTXCB);
1721 for (i = 0; i < FXP_NTXCB; i++) {
1722 txp[i].cb_status = FXP_CB_STATUS_C | FXP_CB_STATUS_OK;
1723 txp[i].cb_command = FXP_CB_COMMAND_NOP;
1725 vtophys(&txp[(i + 1) & FXP_TXCB_MASK].cb_status);
1726 if (sc->flags & FXP_FLAG_EXT_TXCB)
1727 txp[i].tbd_array_addr = vtophys(&txp[i].tbd[2]);
1729 txp[i].tbd_array_addr = vtophys(&txp[i].tbd[0]);
1730 txp[i].next = &txp[(i + 1) & FXP_TXCB_MASK];
1733 * Set the suspend flag on the first TxCB and start the control
1734 * unit. It will execute the NOP and then suspend.
1736 txp->cb_command = FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S;
1737 sc->cbl_first = sc->cbl_last = txp;
1741 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
1744 * Initialize receiver buffer area - RFA.
1747 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL,
1748 vtophys(sc->rfa_headm->m_ext.ext_buf) + RFA_ALIGNMENT_FUDGE);
1749 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START);
1752 * Set current media.
1754 if (sc->miibus != NULL)
1755 mii_mediachg(device_get_softc(sc->miibus));
1757 ifp->if_flags |= IFF_RUNNING;
1758 ifp->if_flags &= ~IFF_OACTIVE;
1761 * Enable interrupts.
1763 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0);
1767 * Start stats updater.
1769 sc->stat_ch = timeout(fxp_tick, sc, hz);
1773 fxp_serial_ifmedia_upd(struct ifnet *ifp)
1780 fxp_serial_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1783 ifmr->ifm_active = IFM_ETHER|IFM_MANUAL;
1787 * Change media according to request.
1790 fxp_ifmedia_upd(struct ifnet *ifp)
1792 struct fxp_softc *sc = ifp->if_softc;
1793 struct mii_data *mii;
1795 mii = device_get_softc(sc->miibus);
1801 * Notify the world which media we're using.
1804 fxp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1806 struct fxp_softc *sc = ifp->if_softc;
1807 struct mii_data *mii;
1809 mii = device_get_softc(sc->miibus);
1811 ifmr->ifm_active = mii->mii_media_active;
1812 ifmr->ifm_status = mii->mii_media_status;
1814 if (ifmr->ifm_status & IFM_10_T && sc->flags & FXP_FLAG_CU_RESUME_BUG)
1815 sc->cu_resume_bug = 1;
1817 sc->cu_resume_bug = 0;
1821 * Add a buffer to the end of the RFA buffer list.
1822 * Return 0 if successful, 1 for failure. A failure results in
1823 * adding the 'oldm' (if non-NULL) on to the end of the list -
1824 * tossing out its old contents and recycling it.
1825 * The RFA struct is stuck at the beginning of mbuf cluster and the
1826 * data pointer is fixed up to point just past it.
1829 fxp_add_rfabuf(struct fxp_softc *sc, struct mbuf *oldm)
1833 struct fxp_rfa *rfa, *p_rfa;
1835 MGETHDR(m, M_DONTWAIT, MT_DATA);
1837 MCLGET(m, M_DONTWAIT);
1838 if ((m->m_flags & M_EXT) == 0) {
1843 m->m_data = m->m_ext.ext_buf;
1849 m->m_data = m->m_ext.ext_buf;
1853 * Move the data pointer up so that the incoming data packet
1854 * will be 32-bit aligned.
1856 m->m_data += RFA_ALIGNMENT_FUDGE;
1859 * Get a pointer to the base of the mbuf cluster and move
1860 * data start past it.
1862 rfa = mtod(m, struct fxp_rfa *);
1863 m->m_data += sizeof(struct fxp_rfa);
1864 rfa->size = (u_int16_t)(MCLBYTES - sizeof(struct fxp_rfa) - RFA_ALIGNMENT_FUDGE);
1867 * Initialize the rest of the RFA. Note that since the RFA
1868 * is misaligned, we cannot store values directly. Instead,
1869 * we use an optimized, inline copy.
1872 rfa->rfa_status = 0;
1873 rfa->rfa_control = FXP_RFA_CONTROL_EL;
1874 rfa->actual_size = 0;
1877 fxp_lwcopy(&v, (volatile u_int32_t *) rfa->link_addr);
1878 fxp_lwcopy(&v, (volatile u_int32_t *) rfa->rbd_addr);
1881 * If there are other buffers already on the list, attach this
1882 * one to the end by fixing up the tail to point to this one.
1884 if (sc->rfa_headm != NULL) {
1885 p_rfa = (struct fxp_rfa *) (sc->rfa_tailm->m_ext.ext_buf +
1886 RFA_ALIGNMENT_FUDGE);
1887 sc->rfa_tailm->m_next = m;
1889 fxp_lwcopy(&v, (volatile u_int32_t *) p_rfa->link_addr);
1890 p_rfa->rfa_control = 0;
1900 fxp_miibus_readreg(device_t dev, int phy, int reg)
1902 struct fxp_softc *sc = device_get_softc(dev);
1906 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL,
1907 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21));
1909 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0
1914 device_printf(dev, "fxp_miibus_readreg: timed out\n");
1916 return (value & 0xffff);
1920 fxp_miibus_writereg(device_t dev, int phy, int reg, int value)
1922 struct fxp_softc *sc = device_get_softc(dev);
1925 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL,
1926 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) |
1929 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 &&
1934 device_printf(dev, "fxp_miibus_writereg: timed out\n");
1938 fxp_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
1940 struct fxp_softc *sc = ifp->if_softc;
1941 struct ifreq *ifr = (struct ifreq *)data;
1942 struct mii_data *mii;
1951 error = ether_ioctl(ifp, command, data);
1955 if (ifp->if_flags & IFF_ALLMULTI)
1956 sc->flags |= FXP_FLAG_ALL_MCAST;
1958 sc->flags &= ~FXP_FLAG_ALL_MCAST;
1961 * If interface is marked up and not running, then start it.
1962 * If it is marked down and running, stop it.
1963 * XXX If it's up then re-initialize it. This is so flags
1964 * such as IFF_PROMISC are handled.
1966 if (ifp->if_flags & IFF_UP) {
1969 if (ifp->if_flags & IFF_RUNNING)
1976 if (ifp->if_flags & IFF_ALLMULTI)
1977 sc->flags |= FXP_FLAG_ALL_MCAST;
1979 sc->flags &= ~FXP_FLAG_ALL_MCAST;
1981 * Multicast list has changed; set the hardware filter
1984 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0)
1987 * fxp_mc_setup() can set FXP_FLAG_ALL_MCAST, so check it
1988 * again rather than else {}.
1990 if (sc->flags & FXP_FLAG_ALL_MCAST)
1997 if (sc->miibus != NULL) {
1998 mii = device_get_softc(sc->miibus);
1999 error = ifmedia_ioctl(ifp, ifr,
2000 &mii->mii_media, command);
2002 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command);
2014 * Fill in the multicast address list and return number of entries.
2017 fxp_mc_addrs(struct fxp_softc *sc)
2019 struct fxp_cb_mcs *mcsp = sc->mcsp;
2020 struct ifnet *ifp = &sc->sc_if;
2021 struct ifmultiaddr *ifma;
2025 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) {
2026 #if __FreeBSD_version < 500000
2027 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
2029 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
2031 if (ifma->ifma_addr->sa_family != AF_LINK)
2033 if (nmcasts >= MAXMCADDR) {
2034 sc->flags |= FXP_FLAG_ALL_MCAST;
2038 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
2039 (void *)(uintptr_t)(volatile void *)
2040 &sc->mcsp->mc_addr[nmcasts][0], 6);
2044 mcsp->mc_cnt = nmcasts * 6;
2049 * Program the multicast filter.
2051 * We have an artificial restriction that the multicast setup command
2052 * must be the first command in the chain, so we take steps to ensure
2053 * this. By requiring this, it allows us to keep up the performance of
2054 * the pre-initialized command ring (esp. link pointers) by not actually
2055 * inserting the mcsetup command in the ring - i.e. its link pointer
2056 * points to the TxCB ring, but the mcsetup descriptor itself is not part
2057 * of it. We then can do 'CU_START' on the mcsetup descriptor and have it
2058 * lead into the regular TxCB ring when it completes.
2060 * This function must be called at splimp.
2063 fxp_mc_setup(struct fxp_softc *sc)
2065 struct fxp_cb_mcs *mcsp = sc->mcsp;
2066 struct ifnet *ifp = &sc->sc_if;
2070 * If there are queued commands, we must wait until they are all
2071 * completed. If we are already waiting, then add a NOP command
2072 * with interrupt option so that we're notified when all commands
2073 * have been completed - fxp_start() ensures that no additional
2074 * TX commands will be added when need_mcsetup is true.
2076 if (sc->tx_queued) {
2077 struct fxp_cb_tx *txp;
2080 * need_mcsetup will be true if we are already waiting for the
2081 * NOP command to be completed (see below). In this case, bail.
2083 if (sc->need_mcsetup)
2085 sc->need_mcsetup = 1;
2088 * Add a NOP command with interrupt so that we are notified
2089 * when all TX commands have been processed.
2091 txp = sc->cbl_last->next;
2092 txp->mb_head = NULL;
2094 txp->cb_command = FXP_CB_COMMAND_NOP |
2095 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I;
2097 * Advance the end of list forward.
2099 sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S;
2103 * Issue a resume in case the CU has just suspended.
2106 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME);
2108 * Set a 5 second timer just in case we don't hear from the
2115 sc->need_mcsetup = 0;
2118 * Initialize multicast setup descriptor.
2120 mcsp->next = sc->cbl_base;
2121 mcsp->mb_head = NULL;
2122 mcsp->cb_status = 0;
2123 mcsp->cb_command = FXP_CB_COMMAND_MCAS |
2124 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I;
2125 mcsp->link_addr = vtophys(&sc->cbl_base->cb_status);
2126 (void) fxp_mc_addrs(sc);
2127 sc->cbl_first = sc->cbl_last = (struct fxp_cb_tx *) mcsp;
2131 * Wait until command unit is not active. This should never
2132 * be the case when nothing is queued, but make sure anyway.
2135 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) ==
2136 FXP_SCB_CUS_ACTIVE && --count)
2139 device_printf(sc->dev, "command queue timeout\n");
2144 * Start the multicast setup command.
2147 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&mcsp->cb_status));
2148 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
2154 static u_int32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE;
2155 static u_int32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE;
2156 static u_int32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE;
2157 static u_int32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE;
2158 static u_int32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE;
2159 static u_int32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE;
2161 #define UCODE(x) x, sizeof(x)
2167 u_short int_delay_offset;
2168 u_short bundle_max_offset;
2170 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), D101_CPUSAVER_DWORD, 0 },
2171 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), D101_CPUSAVER_DWORD, 0 },
2172 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma),
2173 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD },
2174 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s),
2175 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD },
2176 { FXP_REV_82550, UCODE(fxp_ucode_d102),
2177 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD },
2178 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c),
2179 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD },
2180 { 0, NULL, 0, 0, 0 }
2184 fxp_load_ucode(struct fxp_softc *sc)
2187 struct fxp_cb_ucode *cbp;
2189 for (uc = ucode_table; uc->ucode != NULL; uc++)
2190 if (sc->revision == uc->revision)
2192 if (uc->ucode == NULL)
2194 cbp = (struct fxp_cb_ucode *)sc->cbl_base;
2196 cbp->cb_command = FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL;
2197 cbp->link_addr = -1; /* (no) next command */
2198 memcpy(cbp->ucode, uc->ucode, uc->length);
2199 if (uc->int_delay_offset)
2200 *(u_short *)&cbp->ucode[uc->int_delay_offset] =
2201 sc->tunable_int_delay + sc->tunable_int_delay / 2;
2202 if (uc->bundle_max_offset)
2203 *(u_short *)&cbp->ucode[uc->bundle_max_offset] =
2204 sc->tunable_bundle_max;
2206 * Download the ucode to the chip.
2209 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&cbp->cb_status));
2210 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
2211 /* ...and wait for it to complete. */
2212 fxp_dma_wait(&cbp->cb_status, sc);
2213 device_printf(sc->dev,
2214 "Microcode loaded, int_delay: %d usec bundle_max: %d\n",
2215 sc->tunable_int_delay,
2216 uc->bundle_max_offset == 0 ? 0 : sc->tunable_bundle_max);
2217 sc->flags |= FXP_FLAG_UCODE;
2221 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high)
2225 value = *(int *)arg1;
2226 error = sysctl_handle_int(oidp, &value, 0, req);
2227 if (error || !req->newptr)
2229 if (value < low || value > high)
2231 *(int *)arg1 = value;
2236 * Interrupt delay is expressed in microseconds, a multiplier is used
2237 * to convert this to the appropriate clock ticks before using.
2240 sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS)
2242 return (sysctl_int_range(oidp, arg1, arg2, req, 300, 3000));
2246 sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS)
2248 return (sysctl_int_range(oidp, arg1, arg2, req, 1, 0xffff));