2 * Copyright (c) 1995, David Greenman
5 * Modifications to support media selection:
6 * Copyright (c) 1997 Jason R. Thorpe. All rights reserved.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice unmodified, this list of conditions, and the following
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 * Intel EtherExpress Pro/100B PCI Fast Ethernet driver
37 #include <sys/param.h>
38 #include <sys/systm.h>
40 #include <sys/malloc.h>
41 #include <sys/mutex.h>
42 #include <sys/kernel.h>
43 #include <sys/socket.h>
46 #include <net/if_dl.h>
47 #include <net/if_media.h>
51 #include <netns/ns_if.h>
55 #include <sys/sockio.h>
57 #include <machine/bus.h>
59 #include <machine/resource.h>
61 #include <net/ethernet.h>
62 #include <net/if_arp.h>
64 #include <vm/vm.h> /* for vtophys */
65 #include <vm/pmap.h> /* for vtophys */
67 #include <pci/pcivar.h>
68 #include <pci/pcireg.h> /* for PCIM_CMD_xxx */
69 #include <pci/if_fxpreg.h>
70 #include <pci/if_fxpvar.h>
72 #ifdef __alpha__ /* XXX */
73 /* XXX XXX NEED REAL DMA MAPPING SUPPORT XXX XXX */
75 #define vtophys(va) alpha_XXX_dmamap((vm_offset_t)(va))
76 #endif /* __alpha__ */
79 * NOTE! On the Alpha, we have an alignment constraint. The
80 * card DMAs the packet immediately following the RFA. However,
81 * the first thing in the packet is a 14-byte Ethernet header.
82 * This means that the packet is misaligned. To compensate,
83 * we actually offset the RFA 2 bytes into the cluster. This
84 * alignes the packet after the Ethernet header at a 32-bit
85 * boundary. HOWEVER! This means that the RFA is misaligned!
87 #define RFA_ALIGNMENT_FUDGE 2
90 * Inline function to copy a 16-bit aligned 32-bit quantity.
92 static __inline void fxp_lwcopy __P((volatile u_int32_t *,
93 volatile u_int32_t *));
96 volatile u_int32_t *src, *dst;
101 volatile u_int16_t *a = (volatile u_int16_t *)src;
102 volatile u_int16_t *b = (volatile u_int16_t *)dst;
110 * Template for default configuration parameters.
111 * See struct fxp_cb_config for the bit definitions.
113 static u_char fxp_cb_config_template[] = {
114 0x0, 0x0, /* cb_status */
115 0x80, 0x2, /* cb_command */
116 0xff, 0xff, 0xff, 0xff, /* link_addr */
141 /* Supported media types. */
142 struct fxp_supported_media {
143 const int fsm_phy; /* PHY type */
144 const int *fsm_media; /* the media array */
145 const int fsm_nmedia; /* the number of supported media */
146 const int fsm_defmedia; /* default media for this PHY */
149 static const int fxp_media_standard[] = {
151 IFM_ETHER|IFM_10_T|IFM_FDX,
152 IFM_ETHER|IFM_100_TX,
153 IFM_ETHER|IFM_100_TX|IFM_FDX,
156 #define FXP_MEDIA_STANDARD_DEFMEDIA (IFM_ETHER|IFM_AUTO)
158 static const int fxp_media_default[] = {
159 IFM_ETHER|IFM_MANUAL, /* XXX IFM_AUTO ? */
161 #define FXP_MEDIA_DEFAULT_DEFMEDIA (IFM_ETHER|IFM_MANUAL)
163 static const struct fxp_supported_media fxp_media[] = {
164 { FXP_PHY_DP83840, fxp_media_standard,
165 sizeof(fxp_media_standard) / sizeof(fxp_media_standard[0]),
166 FXP_MEDIA_STANDARD_DEFMEDIA },
167 { FXP_PHY_DP83840A, fxp_media_standard,
168 sizeof(fxp_media_standard) / sizeof(fxp_media_standard[0]),
169 FXP_MEDIA_STANDARD_DEFMEDIA },
170 { FXP_PHY_82553A, fxp_media_standard,
171 sizeof(fxp_media_standard) / sizeof(fxp_media_standard[0]),
172 FXP_MEDIA_STANDARD_DEFMEDIA },
173 { FXP_PHY_82553C, fxp_media_standard,
174 sizeof(fxp_media_standard) / sizeof(fxp_media_standard[0]),
175 FXP_MEDIA_STANDARD_DEFMEDIA },
176 { FXP_PHY_82555, fxp_media_standard,
177 sizeof(fxp_media_standard) / sizeof(fxp_media_standard[0]),
178 FXP_MEDIA_STANDARD_DEFMEDIA },
179 { FXP_PHY_82555B, fxp_media_standard,
180 sizeof(fxp_media_standard) / sizeof(fxp_media_standard[0]),
181 FXP_MEDIA_STANDARD_DEFMEDIA },
182 { FXP_PHY_80C24, fxp_media_default,
183 sizeof(fxp_media_default) / sizeof(fxp_media_default[0]),
184 FXP_MEDIA_DEFAULT_DEFMEDIA },
186 #define NFXPMEDIA (sizeof(fxp_media) / sizeof(fxp_media[0]))
188 static int fxp_mediachange __P((struct ifnet *));
189 static void fxp_mediastatus __P((struct ifnet *, struct ifmediareq *));
190 static void fxp_set_media __P((struct fxp_softc *, int));
191 static __inline void fxp_scb_wait __P((struct fxp_softc *));
192 static __inline void fxp_dma_wait __P((volatile u_int16_t *, struct fxp_softc *sc));
193 static void fxp_intr __P((void *));
194 static void fxp_start __P((struct ifnet *));
195 static int fxp_ioctl __P((struct ifnet *,
197 static void fxp_init __P((void *));
198 static void fxp_stop __P((struct fxp_softc *));
199 static void fxp_watchdog __P((struct ifnet *));
200 static int fxp_add_rfabuf __P((struct fxp_softc *, struct mbuf *));
201 static int fxp_mdi_read __P((struct fxp_softc *, int, int));
202 static void fxp_mdi_write __P((struct fxp_softc *, int, int, int));
203 static void fxp_autosize_eeprom __P((struct fxp_softc *));
204 static void fxp_read_eeprom __P((struct fxp_softc *, u_int16_t *,
206 static int fxp_attach_common __P((struct fxp_softc *, u_int8_t *));
207 static void fxp_stats_update __P((void *));
208 static void fxp_mc_setup __P((struct fxp_softc *));
211 * Set initial transmit threshold at 64 (512 bytes). This is
212 * increased by 64 (512 bytes) at a time, to maximum of 192
213 * (1536 bytes), if an underrun occurs.
215 static int tx_threshold = 64;
218 * Number of transmit control blocks. This determines the number
219 * of transmit buffers that can be chained in the CB list.
220 * This must be a power of two.
222 #define FXP_NTXCB 128
225 * Number of completed TX commands at which point an interrupt
226 * will be generated to garbage collect the attached buffers.
227 * Must be at least one less than FXP_NTXCB, and should be
228 * enough less so that the transmitter doesn't becomes idle
229 * during the buffer rundown (which would reduce performance).
231 #define FXP_CXINT_THRESH 120
234 * TxCB list index mask. This is used to do list wrap-around.
236 #define FXP_TXCB_MASK (FXP_NTXCB - 1)
239 * Number of receive frame area buffers. These are large so chose
242 #define FXP_NRFABUFS 64
245 * Maximum number of seconds that the receiver can be idle before we
246 * assume it's dead and attempt to reset it by reprogramming the
247 * multicast filter. This is part of a work-around for a bug in the
248 * NIC. See fxp_stats_update().
250 #define FXP_MAX_RX_IDLE 15
253 * Wait for the previous command to be accepted (but not necessarily
258 struct fxp_softc *sc;
262 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i)
265 printf("fxp%d: SCB timeout\n", FXP_UNIT(sc));
269 fxp_dma_wait(status, sc)
270 volatile u_int16_t *status;
271 struct fxp_softc *sc;
275 while (!(*status & FXP_CB_STATUS_C) && --i)
278 printf("fxp%d: DMA timeout\n", FXP_UNIT(sc));
282 * Return identification string if this is device is ours.
285 fxp_probe(device_t dev)
287 if (pci_get_vendor(dev) == FXP_VENDORID_INTEL) {
288 switch (pci_get_device(dev)) {
290 case FXP_DEVICEID_i82557:
291 device_set_desc(dev, "Intel Pro 10/100B/100+ Ethernet");
293 case FXP_DEVICEID_i82559:
294 device_set_desc(dev, "Intel InBusiness 10/100 Ethernet");
296 case FXP_DEVICEID_i82559ER:
297 device_set_desc(dev, "Intel Embedded 10/100 Ethernet");
299 case FXP_DEVICEID_i82562:
300 device_set_desc(dev, "Intel PLC 10/100 Ethernet");
311 fxp_attach(device_t dev)
314 struct fxp_softc *sc = device_get_softc(dev);
317 int rid, m1, m2, ebitmap;
319 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_DEF | MTX_RECURSE);
320 callout_handle_init(&sc->stat_ch);
325 * Enable bus mastering. Enable memory space too, in case
326 * BIOS/Prom forgot about it.
328 val = pci_read_config(dev, PCIR_COMMAND, 2);
329 val |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
330 pci_write_config(dev, PCIR_COMMAND, val, 2);
331 val = pci_read_config(dev, PCIR_COMMAND, 2);
333 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
334 u_int32_t iobase, membase, irq;
336 /* Save important PCI config data. */
337 iobase = pci_read_config(dev, FXP_PCI_IOBA, 4);
338 membase = pci_read_config(dev, FXP_PCI_MMBA, 4);
339 irq = pci_read_config(dev, PCIR_INTLINE, 4);
341 /* Reset the power state. */
342 device_printf(dev, "chip is in D%d power mode "
343 "-- setting to D0\n", pci_get_powerstate(dev));
345 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
347 /* Restore PCI config data. */
348 pci_write_config(dev, FXP_PCI_IOBA, iobase, 4);
349 pci_write_config(dev, FXP_PCI_MMBA, membase, 4);
350 pci_write_config(dev, PCIR_INTLINE, irq, 4);
354 * Figure out which we should try first - memory mapping or i/o mapping?
355 * We default to memory mapping. Then we accept an override from the
356 * command line. Then we check to see which one is enabled.
359 m2 = PCIM_CMD_PORTEN;
361 if (getenv_int("fxp_iomap", &ebitmap)) {
362 if (ebitmap & (1 << device_get_unit(dev))) {
363 m1 = PCIM_CMD_PORTEN;
370 (m1 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT;
371 sc->rgd = (m1 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA;
372 sc->mem = bus_alloc_resource(dev, sc->rtp, &sc->rgd,
373 0, ~0, 1, RF_ACTIVE);
375 if (sc->mem == NULL && (val & m2)) {
377 (m2 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT;
378 sc->rgd = (m2 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA;
379 sc->mem = bus_alloc_resource(dev, sc->rtp, &sc->rgd,
380 0, ~0, 1, RF_ACTIVE);
384 device_printf(dev, "could not map device registers\n");
389 device_printf(dev, "using %s space register mapping\n",
390 sc->rtp == SYS_RES_MEMORY? "memory" : "I/O");
393 sc->sc_st = rman_get_bustag(sc->mem);
394 sc->sc_sh = rman_get_bushandle(sc->mem);
397 * Allocate our interrupt.
400 sc->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
401 RF_SHAREABLE | RF_ACTIVE);
402 if (sc->irq == NULL) {
403 device_printf(dev, "could not map interrupt\n");
408 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET,
409 fxp_intr, sc, &sc->ih);
411 device_printf(dev, "could not setup irq\n");
415 /* Do generic parts of attach. */
416 if (fxp_attach_common(sc, sc->arpcom.ac_enaddr)) {
418 bus_teardown_intr(dev, sc->irq, sc->ih);
419 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq);
420 bus_release_resource(dev, sc->rtp, sc->rgd, sc->mem);
425 device_printf(dev, "Ethernet address %6D%s\n",
426 sc->arpcom.ac_enaddr, ":", sc->phy_10Mbps_only ? ", 10Mbps" : "");
428 ifp = &sc->arpcom.ac_if;
429 ifp->if_unit = device_get_unit(dev);
430 ifp->if_name = "fxp";
431 ifp->if_output = ether_output;
432 ifp->if_baudrate = 100000000;
433 ifp->if_init = fxp_init;
435 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
436 ifp->if_ioctl = fxp_ioctl;
437 ifp->if_start = fxp_start;
438 ifp->if_watchdog = fxp_watchdog;
441 * Attach the interface.
443 ether_ifattach(ifp, ETHER_BPF_SUPPORTED);
445 * Let the system queue as many packets as we have available
448 ifp->if_snd.ifq_maxlen = FXP_NTXCB - 1;
455 mtx_destroy(&sc->sc_mtx);
463 fxp_detach(device_t dev)
465 struct fxp_softc *sc = device_get_softc(dev);
470 * Close down routes etc.
472 ether_ifdetach(&sc->arpcom.ac_if, ETHER_BPF_SUPPORTED);
475 * Stop DMA and drop transmit queue.
480 * Deallocate resources.
482 bus_teardown_intr(dev, sc->irq, sc->ih);
483 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq);
484 bus_release_resource(dev, sc->rtp, sc->rgd, sc->mem);
487 * Free all the receive buffers.
489 if (sc->rfa_headm != NULL)
490 m_freem(sc->rfa_headm);
493 * Free all media structures.
495 ifmedia_removeall(&sc->sc_media);
498 * Free anciliary structures.
500 free(sc->cbl_base, M_DEVBUF);
501 free(sc->fxp_stats, M_DEVBUF);
502 free(sc->mcsp, M_DEVBUF);
505 mtx_destroy(&sc->sc_mtx);
511 * Device shutdown routine. Called at system shutdown after sync. The
512 * main purpose of this routine is to shut off receiver DMA so that
513 * kernel memory doesn't get clobbered during warmboot.
516 fxp_shutdown(device_t dev)
519 * Make sure that DMA is disabled prior to reboot. Not doing
520 * do could allow DMA to corrupt kernel memory during the
521 * reboot before the driver initializes.
523 fxp_stop((struct fxp_softc *) device_get_softc(dev));
528 * Device suspend routine. Stop the interface and save some PCI
529 * settings in case the BIOS doesn't restore them properly on
533 fxp_suspend(device_t dev)
535 struct fxp_softc *sc = device_get_softc(dev);
543 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i*4, 4);
544 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4);
545 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1);
546 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
547 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
557 * Device resume routine. Restore some PCI settings in case the BIOS
558 * doesn't, re-enable busmastering, and restart the interface if
562 fxp_resume(device_t dev)
564 struct fxp_softc *sc = device_get_softc(dev);
565 struct ifnet *ifp = &sc->sc_if;
566 u_int16_t pci_command;
571 /* better way to do this? */
573 pci_write_config(dev, PCIR_MAPS + i*4, sc->saved_maps[i], 4);
574 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4);
575 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1);
576 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1);
577 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1);
579 /* reenable busmastering */
580 pci_command = pci_read_config(dev, PCIR_COMMAND, 2);
581 pci_command |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
582 pci_write_config(dev, PCIR_COMMAND, pci_command, 2);
584 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET);
587 /* reinitialize interface if necessary */
588 if (ifp->if_flags & IFF_UP)
598 static device_method_t fxp_methods[] = {
599 /* Device interface */
600 DEVMETHOD(device_probe, fxp_probe),
601 DEVMETHOD(device_attach, fxp_attach),
602 DEVMETHOD(device_detach, fxp_detach),
603 DEVMETHOD(device_shutdown, fxp_shutdown),
604 DEVMETHOD(device_suspend, fxp_suspend),
605 DEVMETHOD(device_resume, fxp_resume),
610 static driver_t fxp_driver = {
613 sizeof(struct fxp_softc),
616 static devclass_t fxp_devclass;
618 DRIVER_MODULE(if_fxp, pci, fxp_driver, fxp_devclass, 0, 0);
619 DRIVER_MODULE(if_fxp, cardbus, fxp_driver, fxp_devclass, 0, 0);
622 * Do generic parts of attach.
625 fxp_attach_common(sc, enaddr)
626 struct fxp_softc *sc;
630 int i, nmedia, defmedia;
634 * Reset to a stable state.
636 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET);
639 sc->cbl_base = malloc(sizeof(struct fxp_cb_tx) * FXP_NTXCB,
640 M_DEVBUF, M_NOWAIT | M_ZERO);
641 if (sc->cbl_base == NULL)
644 sc->fxp_stats = malloc(sizeof(struct fxp_stats), M_DEVBUF,
646 if (sc->fxp_stats == NULL)
649 sc->mcsp = malloc(sizeof(struct fxp_cb_mcs), M_DEVBUF, M_NOWAIT);
650 if (sc->mcsp == NULL)
654 * Pre-allocate our receive buffers.
656 for (i = 0; i < FXP_NRFABUFS; i++) {
657 if (fxp_add_rfabuf(sc, NULL) != 0) {
663 * Find out how large of an SEEPROM we have.
665 fxp_autosize_eeprom(sc);
668 * Get info about the primary PHY
670 fxp_read_eeprom(sc, (u_int16_t *)&data, 6, 1);
671 sc->phy_primary_addr = data & 0xff;
672 sc->phy_primary_device = (data >> 8) & 0x3f;
673 sc->phy_10Mbps_only = data >> 15;
678 fxp_read_eeprom(sc, (u_int16_t *)enaddr, 0, 3);
681 * Initialize the media structures.
684 media = fxp_media_default;
685 nmedia = sizeof(fxp_media_default) / sizeof(fxp_media_default[0]);
686 defmedia = FXP_MEDIA_DEFAULT_DEFMEDIA;
688 for (i = 0; i < NFXPMEDIA; i++) {
689 if (sc->phy_primary_device == fxp_media[i].fsm_phy) {
690 media = fxp_media[i].fsm_media;
691 nmedia = fxp_media[i].fsm_nmedia;
692 defmedia = fxp_media[i].fsm_defmedia;
696 ifmedia_init(&sc->sc_media, 0, fxp_mediachange, fxp_mediastatus);
697 for (i = 0; i < nmedia; i++) {
698 if (IFM_SUBTYPE(media[i]) == IFM_100_TX && sc->phy_10Mbps_only)
700 ifmedia_add(&sc->sc_media, media[i], 0, NULL);
702 ifmedia_set(&sc->sc_media, defmedia);
707 printf("fxp%d: Failed to malloc memory\n", FXP_UNIT(sc));
709 free(sc->cbl_base, M_DEVBUF);
711 free(sc->fxp_stats, M_DEVBUF);
713 free(sc->mcsp, M_DEVBUF);
714 /* frees entire chain */
716 m_freem(sc->rfa_headm);
724 * Figure out EEPROM size.
726 * 559's can have either 64-word or 256-word EEPROMs, the 558
727 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet
728 * talks about the existance of 16 to 256 word EEPROMs.
730 * The only known sizes are 64 and 256, where the 256 version is used
731 * by CardBus cards to store CIS information.
733 * The address is shifted in msb-to-lsb, and after the last
734 * address-bit the EEPROM is supposed to output a `dummy zero' bit,
735 * after which follows the actual data. We try to detect this zero, by
736 * probing the data-out bit in the EEPROM control register just after
737 * having shifted in a bit. If the bit is zero, we assume we've
738 * shifted enough address bits. The data-out should be tri-state,
739 * before this, which should translate to a logical one.
741 * Other ways to do this would be to try to read a register with known
742 * contents with a varying number of address bits, but no such
743 * register seem to be available. The high bits of register 10 are 01
744 * on the 558 and 559, but apparently not on the 557.
746 * The Linux driver computes a checksum on the EEPROM data, but the
747 * value of this checksum is not very well documented.
750 fxp_autosize_eeprom(sc)
751 struct fxp_softc *sc;
756 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
758 * Shift in read opcode.
760 for (x = 3; x > 0; x--) {
761 if (FXP_EEPROM_OPC_READ & (1 << (x - 1))) {
762 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI;
764 reg = FXP_EEPROM_EECS;
766 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
767 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL,
768 reg | FXP_EEPROM_EESK);
770 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
775 * Wait for the dummy zero following a correct address shift.
777 for (x = 1; x <= 8; x++) {
778 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
779 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL,
780 FXP_EEPROM_EECS | FXP_EEPROM_EESK);
782 if ((CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) == 0)
784 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
787 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
792 * Read from the serial EEPROM. Basically, you manually shift in
793 * the read opcode (one bit at a time) and then shift in the address,
794 * and then you shift out the data (all of this one bit at a time).
795 * The word size is 16 bits, so you have to provide the address for
796 * every 16 bits of data.
799 fxp_read_eeprom(sc, data, offset, words)
800 struct fxp_softc *sc;
808 for (i = 0; i < words; i++) {
809 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
811 * Shift in read opcode.
813 for (x = 3; x > 0; x--) {
814 if (FXP_EEPROM_OPC_READ & (1 << (x - 1))) {
815 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI;
817 reg = FXP_EEPROM_EECS;
819 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
820 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL,
821 reg | FXP_EEPROM_EESK);
823 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
829 for (x = sc->eeprom_size; x > 0; x--) {
830 if ((i + offset) & (1 << (x - 1))) {
831 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI;
833 reg = FXP_EEPROM_EECS;
835 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
836 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL,
837 reg | FXP_EEPROM_EESK);
839 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
842 reg = FXP_EEPROM_EECS;
847 for (x = 16; x > 0; x--) {
848 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL,
849 reg | FXP_EEPROM_EESK);
851 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) &
853 data[i] |= (1 << (x - 1));
854 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
857 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
863 * Start packet transmission on the interface.
869 struct fxp_softc *sc = ifp->if_softc;
870 struct fxp_cb_tx *txp;
874 * See if we need to suspend xmit until the multicast filter
875 * has been reprogrammed (which can only be done at the head
876 * of the command chain).
878 if (sc->need_mcsetup) {
886 * We're finished if there is nothing more to add to the list or if
887 * we're all filled up with buffers to transmit.
888 * NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add
889 * a NOP command when needed.
891 while (ifp->if_snd.ifq_head != NULL && sc->tx_queued < FXP_NTXCB - 1) {
892 struct mbuf *m, *mb_head;
896 * Grab a packet to transmit.
898 IF_DEQUEUE(&ifp->if_snd, mb_head);
901 * Get pointer to next available tx desc.
903 txp = sc->cbl_last->next;
906 * Go through each of the mbufs in the chain and initialize
907 * the transmit buffer descriptors with the physical address
908 * and size of the mbuf.
911 for (m = mb_head, segment = 0; m != NULL; m = m->m_next) {
913 if (segment == FXP_NTXSEG)
915 txp->tbd[segment].tb_addr =
916 vtophys(mtod(m, vm_offset_t));
917 txp->tbd[segment].tb_size = m->m_len;
925 * We ran out of segments. We have to recopy this mbuf
926 * chain first. Bail out if we can't get the new buffers.
928 MGETHDR(mn, M_DONTWAIT, MT_DATA);
933 if (mb_head->m_pkthdr.len > MHLEN) {
934 MCLGET(mn, M_DONTWAIT);
935 if ((mn->m_flags & M_EXT) == 0) {
941 m_copydata(mb_head, 0, mb_head->m_pkthdr.len,
943 mn->m_pkthdr.len = mn->m_len = mb_head->m_pkthdr.len;
949 txp->tbd_number = segment;
950 txp->mb_head = mb_head;
952 if (sc->tx_queued != FXP_CXINT_THRESH - 1) {
954 FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF | FXP_CB_COMMAND_S;
957 FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF | FXP_CB_COMMAND_S | FXP_CB_COMMAND_I;
959 * Set a 5 second timer just in case we don't hear from the
964 txp->tx_threshold = tx_threshold;
967 * Advance the end of list forward.
972 * On platforms which can't access memory in 16-bit
973 * granularities, we must prevent the card from DMA'ing
974 * up the status while we update the command field.
975 * This could cause us to overwrite the completion status.
977 atomic_clear_short(&sc->cbl_last->cb_command,
980 sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S;
985 * Advance the beginning of the list forward if there are
986 * no other packets queued (when nothing is queued, cbl_first
987 * sits on the last TxCB that was sent out).
989 if (sc->tx_queued == 0)
995 * Pass packet to bpf if there is a listener.
998 bpf_mtap(ifp, mb_head);
1002 * We're finished. If we added to the list, issue a RESUME to get DMA
1003 * going again if suspended.
1007 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_RESUME);
1013 * Process interface interrupts.
1019 struct fxp_softc *sc = arg;
1020 struct ifnet *ifp = &sc->sc_if;
1025 if (sc->suspended) {
1030 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) {
1032 * First ACK all the interrupts in this pass.
1034 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack);
1037 * Free any finished transmit mbuf chains.
1039 * Handle the CNA event likt a CXTNO event. It used to
1040 * be that this event (control unit not ready) was not
1041 * encountered, but it is now with the SMPng modifications.
1042 * The exact sequence of events that occur when the interface
1043 * is brought up are different now, and if this event
1044 * goes unhandled, the configuration/rxfilter setup sequence
1045 * can stall for several seconds. The result is that no
1046 * packets go out onto the wire for about 5 to 10 seconds
1047 * after the interface is ifconfig'ed for the first time.
1049 if (statack & (FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA)) {
1050 struct fxp_cb_tx *txp;
1052 for (txp = sc->cbl_first; sc->tx_queued &&
1053 (txp->cb_status & FXP_CB_STATUS_C) != 0;
1055 if (txp->mb_head != NULL) {
1056 m_freem(txp->mb_head);
1057 txp->mb_head = NULL;
1061 sc->cbl_first = txp;
1063 if (sc->tx_queued == 0) {
1064 if (sc->need_mcsetup)
1068 * Try to start more packets transmitting.
1070 if (ifp->if_snd.ifq_head != NULL)
1074 * Process receiver interrupts. If a no-resource (RNR)
1075 * condition exists, get whatever packets we can and
1076 * re-start the receiver.
1078 if (statack & (FXP_SCB_STATACK_FR | FXP_SCB_STATACK_RNR)) {
1080 struct fxp_rfa *rfa;
1083 rfa = (struct fxp_rfa *)(m->m_ext.ext_buf +
1084 RFA_ALIGNMENT_FUDGE);
1086 if (rfa->rfa_status & FXP_RFA_STATUS_C) {
1088 * Remove first packet from the chain.
1090 sc->rfa_headm = m->m_next;
1094 * Add a new buffer to the receive chain.
1095 * If this fails, the old buffer is recycled
1098 if (fxp_add_rfabuf(sc, m) == 0) {
1099 struct ether_header *eh;
1102 total_len = rfa->actual_size &
1105 sizeof(struct ether_header)) {
1109 m->m_pkthdr.rcvif = ifp;
1110 m->m_pkthdr.len = m->m_len = total_len;
1111 eh = mtod(m, struct ether_header *);
1113 sizeof(struct ether_header);
1115 sizeof(struct ether_header);
1116 m->m_pkthdr.len = m->m_len;
1117 ether_input(ifp, eh, m);
1121 if (statack & FXP_SCB_STATACK_RNR) {
1123 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL,
1124 vtophys(sc->rfa_headm->m_ext.ext_buf) +
1125 RFA_ALIGNMENT_FUDGE);
1126 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND,
1127 FXP_SCB_COMMAND_RU_START);
1135 * Update packet in/out/collision statistics. The i82557 doesn't
1136 * allow you to access these counters without doing a fairly
1137 * expensive DMA to get _all_ of the statistics it maintains, so
1138 * we do this operation here only once per second. The statistics
1139 * counters in the kernel are updated from the previous dump-stats
1140 * DMA and then a new dump-stats DMA is started. The on-chip
1141 * counters are zeroed when the DMA completes. If we can't start
1142 * the DMA immediately, we don't wait - we just prepare to read
1143 * them again next time.
1146 fxp_stats_update(arg)
1149 struct fxp_softc *sc = arg;
1150 struct ifnet *ifp = &sc->sc_if;
1151 struct fxp_stats *sp = sc->fxp_stats;
1152 struct fxp_cb_tx *txp;
1154 ifp->if_opackets += sp->tx_good;
1155 ifp->if_collisions += sp->tx_total_collisions;
1157 ifp->if_ipackets += sp->rx_good;
1158 sc->rx_idle_secs = 0;
1161 * Receiver's been idle for another second.
1167 sp->rx_alignment_errors +
1169 sp->rx_overrun_errors;
1171 * If any transmit underruns occured, bump up the transmit
1172 * threshold by another 512 bytes (64 * 8).
1174 if (sp->tx_underruns) {
1175 ifp->if_oerrors += sp->tx_underruns;
1176 if (tx_threshold < 192)
1181 * Release any xmit buffers that have completed DMA. This isn't
1182 * strictly necessary to do here, but it's advantagous for mbufs
1183 * with external storage to be released in a timely manner rather
1184 * than being defered for a potentially long time. This limits
1185 * the delay to a maximum of one second.
1187 for (txp = sc->cbl_first; sc->tx_queued &&
1188 (txp->cb_status & FXP_CB_STATUS_C) != 0;
1190 if (txp->mb_head != NULL) {
1191 m_freem(txp->mb_head);
1192 txp->mb_head = NULL;
1196 sc->cbl_first = txp;
1198 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds,
1199 * then assume the receiver has locked up and attempt to clear
1200 * the condition by reprogramming the multicast filter. This is
1201 * a work-around for a bug in the 82557 where the receiver locks
1202 * up if it gets certain types of garbage in the syncronization
1203 * bits prior to the packet header. This bug is supposed to only
1204 * occur in 10Mbps mode, but has been seen to occur in 100Mbps
1205 * mode as well (perhaps due to a 10/100 speed transition).
1207 if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) {
1208 sc->rx_idle_secs = 0;
1212 * If there is no pending command, start another stats
1213 * dump. Otherwise punt for now.
1215 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) {
1217 * Start another stats dump.
1219 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND,
1220 FXP_SCB_COMMAND_CU_DUMPRESET);
1223 * A previous command is still waiting to be accepted.
1224 * Just zero our copy of the stats and wait for the
1225 * next timer event to update them.
1228 sp->tx_underruns = 0;
1229 sp->tx_total_collisions = 0;
1232 sp->rx_crc_errors = 0;
1233 sp->rx_alignment_errors = 0;
1234 sp->rx_rnr_errors = 0;
1235 sp->rx_overrun_errors = 0;
1239 * Schedule another timeout one second from now.
1241 sc->stat_ch = timeout(fxp_stats_update, sc, hz);
1245 * Stop the interface. Cancels the statistics updater and resets
1250 struct fxp_softc *sc;
1252 struct ifnet *ifp = &sc->sc_if;
1253 struct fxp_cb_tx *txp;
1258 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1262 * Cancel stats updater.
1264 untimeout(fxp_stats_update, sc, sc->stat_ch);
1267 * Issue software reset
1269 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET);
1273 * Release any xmit buffers.
1277 for (i = 0; i < FXP_NTXCB; i++) {
1278 if (txp[i].mb_head != NULL) {
1279 m_freem(txp[i].mb_head);
1280 txp[i].mb_head = NULL;
1287 * Free all the receive buffers then reallocate/reinitialize
1289 if (sc->rfa_headm != NULL)
1290 m_freem(sc->rfa_headm);
1291 sc->rfa_headm = NULL;
1292 sc->rfa_tailm = NULL;
1293 for (i = 0; i < FXP_NRFABUFS; i++) {
1294 if (fxp_add_rfabuf(sc, NULL) != 0) {
1296 * This "can't happen" - we're at splimp()
1297 * and we just freed all the buffers we need
1300 panic("fxp_stop: no buffers!");
1308 * Watchdog/transmission transmit timeout handler. Called when a
1309 * transmission is started on the interface, but no interrupt is
1310 * received before the timeout. This usually indicates that the
1311 * card has wedged for some reason.
1317 struct fxp_softc *sc = ifp->if_softc;
1319 printf("fxp%d: device timeout\n", FXP_UNIT(sc));
1329 struct fxp_softc *sc = xsc;
1330 struct ifnet *ifp = &sc->sc_if;
1331 struct fxp_cb_config *cbp;
1332 struct fxp_cb_ias *cb_ias;
1333 struct fxp_cb_tx *txp;
1338 * Cancel any pending I/O
1342 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0;
1345 * Initialize base of CBL and RFA memory. Loading with zero
1346 * sets it up for regular linear addressing.
1348 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0);
1349 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_BASE);
1352 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_RU_BASE);
1355 * Initialize base of dump-stats buffer.
1358 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(sc->fxp_stats));
1359 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_DUMP_ADR);
1362 * We temporarily use memory that contains the TxCB list to
1363 * construct the config CB. The TxCB list memory is rebuilt
1366 cbp = (struct fxp_cb_config *) sc->cbl_base;
1369 * This bcopy is kind of disgusting, but there are a bunch of must be
1370 * zero and must be one bits in this structure and this is the easiest
1371 * way to initialize them all to proper values.
1373 bcopy(fxp_cb_config_template,
1374 (void *)(uintptr_t)(volatile void *)&cbp->cb_status,
1375 sizeof(fxp_cb_config_template));
1378 cbp->cb_command = FXP_CB_COMMAND_CONFIG | FXP_CB_COMMAND_EL;
1379 cbp->link_addr = -1; /* (no) next command */
1380 cbp->byte_count = 22; /* (22) bytes to config */
1381 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */
1382 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */
1383 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */
1384 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */
1385 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */
1386 cbp->dma_bce = 0; /* (disable) dma max counters */
1387 cbp->late_scb = 0; /* (don't) defer SCB update */
1388 cbp->tno_int = 0; /* (disable) tx not okay interrupt */
1389 cbp->ci_int = 1; /* interrupt on CU idle */
1390 cbp->save_bf = prm; /* save bad frames */
1391 cbp->disc_short_rx = !prm; /* discard short packets */
1392 cbp->underrun_retry = 1; /* retry mode (1) on DMA underrun */
1393 cbp->mediatype = !sc->phy_10Mbps_only; /* interface mode */
1394 cbp->nsai = 1; /* (don't) disable source addr insert */
1395 cbp->preamble_length = 2; /* (7 byte) preamble */
1396 cbp->loopback = 0; /* (don't) loopback */
1397 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */
1398 cbp->linear_pri_mode = 0; /* (wait after xmit only) */
1399 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */
1400 cbp->promiscuous = prm; /* promiscuous mode */
1401 cbp->bcast_disable = 0; /* (don't) disable broadcasts */
1402 cbp->crscdt = 0; /* (CRS only) */
1403 cbp->stripping = !prm; /* truncate rx packet to byte count */
1404 cbp->padding = 1; /* (do) pad short tx packets */
1405 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */
1406 cbp->force_fdx = 0; /* (don't) force full duplex */
1407 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */
1408 cbp->multi_ia = 0; /* (don't) accept multiple IAs */
1409 cbp->mc_all = sc->all_mcasts;/* accept all multicasts */
1412 * Start the config command/DMA.
1415 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&cbp->cb_status));
1416 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_START);
1417 /* ...and wait for it to complete. */
1418 fxp_dma_wait(&cbp->cb_status, sc);
1421 * Now initialize the station address. Temporarily use the TxCB
1422 * memory area like we did above for the config CB.
1424 cb_ias = (struct fxp_cb_ias *) sc->cbl_base;
1425 cb_ias->cb_status = 0;
1426 cb_ias->cb_command = FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL;
1427 cb_ias->link_addr = -1;
1428 bcopy(sc->arpcom.ac_enaddr,
1429 (void *)(uintptr_t)(volatile void *)cb_ias->macaddr,
1430 sizeof(sc->arpcom.ac_enaddr));
1433 * Start the IAS (Individual Address Setup) command/DMA.
1436 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_START);
1437 /* ...and wait for it to complete. */
1438 fxp_dma_wait(&cb_ias->cb_status, sc);
1441 * Initialize transmit control block (TxCB) list.
1445 bzero(txp, sizeof(struct fxp_cb_tx) * FXP_NTXCB);
1446 for (i = 0; i < FXP_NTXCB; i++) {
1447 txp[i].cb_status = FXP_CB_STATUS_C | FXP_CB_STATUS_OK;
1448 txp[i].cb_command = FXP_CB_COMMAND_NOP;
1449 txp[i].link_addr = vtophys(&txp[(i + 1) & FXP_TXCB_MASK].cb_status);
1450 txp[i].tbd_array_addr = vtophys(&txp[i].tbd[0]);
1451 txp[i].next = &txp[(i + 1) & FXP_TXCB_MASK];
1454 * Set the suspend flag on the first TxCB and start the control
1455 * unit. It will execute the NOP and then suspend.
1457 txp->cb_command = FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S;
1458 sc->cbl_first = sc->cbl_last = txp;
1462 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_START);
1465 * Initialize receiver buffer area - RFA.
1468 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL,
1469 vtophys(sc->rfa_headm->m_ext.ext_buf) + RFA_ALIGNMENT_FUDGE);
1470 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_RU_START);
1473 * Set current media.
1475 fxp_set_media(sc, sc->sc_media.ifm_cur->ifm_media);
1477 ifp->if_flags |= IFF_RUNNING;
1478 ifp->if_flags &= ~IFF_OACTIVE;
1482 * Start stats updater.
1484 sc->stat_ch = timeout(fxp_stats_update, sc, hz);
1488 fxp_set_media(sc, media)
1489 struct fxp_softc *sc;
1493 switch (sc->phy_primary_device) {
1494 case FXP_PHY_DP83840:
1495 case FXP_PHY_DP83840A:
1496 fxp_mdi_write(sc, sc->phy_primary_addr, FXP_DP83840_PCR,
1497 fxp_mdi_read(sc, sc->phy_primary_addr, FXP_DP83840_PCR) |
1498 FXP_DP83840_PCR_LED4_MODE | /* LED4 always indicates duplex */
1499 FXP_DP83840_PCR_F_CONNECT | /* force link disconnect bypass */
1500 FXP_DP83840_PCR_BIT10); /* XXX I have no idea */
1502 case FXP_PHY_82553A:
1503 case FXP_PHY_82553C: /* untested */
1505 case FXP_PHY_82555B:
1506 if (IFM_SUBTYPE(media) != IFM_AUTO) {
1509 flags = (IFM_SUBTYPE(media) == IFM_100_TX) ?
1510 FXP_PHY_BMCR_SPEED_100M : 0;
1511 flags |= (media & IFM_FDX) ?
1512 FXP_PHY_BMCR_FULLDUPLEX : 0;
1513 fxp_mdi_write(sc, sc->phy_primary_addr,
1515 (fxp_mdi_read(sc, sc->phy_primary_addr,
1517 ~(FXP_PHY_BMCR_AUTOEN | FXP_PHY_BMCR_SPEED_100M |
1518 FXP_PHY_BMCR_FULLDUPLEX)) | flags);
1520 fxp_mdi_write(sc, sc->phy_primary_addr,
1522 (fxp_mdi_read(sc, sc->phy_primary_addr,
1523 FXP_PHY_BMCR) | FXP_PHY_BMCR_AUTOEN));
1527 * The Seeq 80c24 doesn't have a PHY programming interface, so do
1533 printf("fxp%d: warning: unsupported PHY, type = %d, addr = %d\n",
1534 FXP_UNIT(sc), sc->phy_primary_device,
1535 sc->phy_primary_addr);
1540 * Change media according to request.
1543 fxp_mediachange(ifp)
1546 struct fxp_softc *sc = ifp->if_softc;
1547 struct ifmedia *ifm = &sc->sc_media;
1549 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1552 fxp_set_media(sc, ifm->ifm_media);
1557 * Notify the world which media we're using.
1560 fxp_mediastatus(ifp, ifmr)
1562 struct ifmediareq *ifmr;
1564 struct fxp_softc *sc = ifp->if_softc;
1565 int flags, stsflags;
1567 switch (sc->phy_primary_device) {
1569 case FXP_PHY_82555B:
1570 case FXP_PHY_DP83840:
1571 case FXP_PHY_DP83840A:
1572 ifmr->ifm_status = IFM_AVALID; /* IFM_ACTIVE will be valid */
1573 ifmr->ifm_active = IFM_ETHER;
1575 * the following is not an error.
1576 * You need to read this register twice to get current
1577 * status. This is correct documented behaviour, the
1578 * first read gets latched values.
1580 stsflags = fxp_mdi_read(sc, sc->phy_primary_addr, FXP_PHY_STS);
1581 stsflags = fxp_mdi_read(sc, sc->phy_primary_addr, FXP_PHY_STS);
1582 if (stsflags & FXP_PHY_STS_LINK_STS)
1583 ifmr->ifm_status |= IFM_ACTIVE;
1586 * If we are in auto mode, then try report the result.
1588 flags = fxp_mdi_read(sc, sc->phy_primary_addr, FXP_PHY_BMCR);
1589 if (flags & FXP_PHY_BMCR_AUTOEN) {
1590 ifmr->ifm_active |= IFM_AUTO; /* XXX presently 0 */
1591 if (stsflags & FXP_PHY_STS_AUTO_DONE) {
1593 * Intel and National parts report
1594 * differently on what they found.
1596 if ((sc->phy_primary_device == FXP_PHY_82555)
1597 || (sc->phy_primary_device == FXP_PHY_82555B)) {
1598 flags = fxp_mdi_read(sc,
1599 sc->phy_primary_addr,
1602 if (flags & FXP_PHY_USC_SPEED)
1603 ifmr->ifm_active |= IFM_100_TX;
1605 ifmr->ifm_active |= IFM_10_T;
1607 if (flags & FXP_PHY_USC_DUPLEX)
1608 ifmr->ifm_active |= IFM_FDX;
1609 } else { /* it's National. only know speed */
1610 flags = fxp_mdi_read(sc,
1611 sc->phy_primary_addr,
1614 if (flags & FXP_DP83840_PAR_SPEED_10)
1615 ifmr->ifm_active |= IFM_10_T;
1617 ifmr->ifm_active |= IFM_100_TX;
1620 } else { /* in manual mode.. just report what we were set to */
1621 if (flags & FXP_PHY_BMCR_SPEED_100M)
1622 ifmr->ifm_active |= IFM_100_TX;
1624 ifmr->ifm_active |= IFM_10_T;
1626 if (flags & FXP_PHY_BMCR_FULLDUPLEX)
1627 ifmr->ifm_active |= IFM_FDX;
1633 ifmr->ifm_active = IFM_ETHER|IFM_MANUAL; /* XXX IFM_AUTO ? */
1638 * Add a buffer to the end of the RFA buffer list.
1639 * Return 0 if successful, 1 for failure. A failure results in
1640 * adding the 'oldm' (if non-NULL) on to the end of the list -
1641 * tossing out its old contents and recycling it.
1642 * The RFA struct is stuck at the beginning of mbuf cluster and the
1643 * data pointer is fixed up to point just past it.
1646 fxp_add_rfabuf(sc, oldm)
1647 struct fxp_softc *sc;
1652 struct fxp_rfa *rfa, *p_rfa;
1654 MGETHDR(m, M_DONTWAIT, MT_DATA);
1656 MCLGET(m, M_DONTWAIT);
1657 if ((m->m_flags & M_EXT) == 0) {
1662 m->m_data = m->m_ext.ext_buf;
1668 m->m_data = m->m_ext.ext_buf;
1672 * Move the data pointer up so that the incoming data packet
1673 * will be 32-bit aligned.
1675 m->m_data += RFA_ALIGNMENT_FUDGE;
1678 * Get a pointer to the base of the mbuf cluster and move
1679 * data start past it.
1681 rfa = mtod(m, struct fxp_rfa *);
1682 m->m_data += sizeof(struct fxp_rfa);
1683 rfa->size = (u_int16_t)(MCLBYTES - sizeof(struct fxp_rfa) - RFA_ALIGNMENT_FUDGE);
1686 * Initialize the rest of the RFA. Note that since the RFA
1687 * is misaligned, we cannot store values directly. Instead,
1688 * we use an optimized, inline copy.
1691 rfa->rfa_status = 0;
1692 rfa->rfa_control = FXP_RFA_CONTROL_EL;
1693 rfa->actual_size = 0;
1696 fxp_lwcopy(&v, (volatile u_int32_t *) rfa->link_addr);
1697 fxp_lwcopy(&v, (volatile u_int32_t *) rfa->rbd_addr);
1700 * If there are other buffers already on the list, attach this
1701 * one to the end by fixing up the tail to point to this one.
1703 if (sc->rfa_headm != NULL) {
1704 p_rfa = (struct fxp_rfa *) (sc->rfa_tailm->m_ext.ext_buf +
1705 RFA_ALIGNMENT_FUDGE);
1706 sc->rfa_tailm->m_next = m;
1708 fxp_lwcopy(&v, (volatile u_int32_t *) p_rfa->link_addr);
1709 p_rfa->rfa_control = 0;
1719 fxp_mdi_read(sc, phy, reg)
1720 struct fxp_softc *sc;
1727 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL,
1728 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21));
1730 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0
1735 printf("fxp%d: fxp_mdi_read: timed out\n", FXP_UNIT(sc));
1737 return (value & 0xffff);
1741 fxp_mdi_write(sc, phy, reg, value)
1742 struct fxp_softc *sc;
1749 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL,
1750 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) |
1753 while((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 &&
1758 printf("fxp%d: fxp_mdi_write: timed out\n", FXP_UNIT(sc));
1762 fxp_ioctl(ifp, command, data)
1767 struct fxp_softc *sc = ifp->if_softc;
1768 struct ifreq *ifr = (struct ifreq *)data;
1778 error = ether_ioctl(ifp, command, data);
1782 sc->all_mcasts = (ifp->if_flags & IFF_ALLMULTI) ? 1 : 0;
1785 * If interface is marked up and not running, then start it.
1786 * If it is marked down and running, stop it.
1787 * XXX If it's up then re-initialize it. This is so flags
1788 * such as IFF_PROMISC are handled.
1790 if (ifp->if_flags & IFF_UP) {
1793 if (ifp->if_flags & IFF_RUNNING)
1800 sc->all_mcasts = (ifp->if_flags & IFF_ALLMULTI) ? 1 : 0;
1802 * Multicast list has changed; set the hardware filter
1805 if (!sc->all_mcasts)
1808 * fxp_mc_setup() can turn on sc->all_mcasts, so check it
1809 * again rather than else {}.
1818 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command);
1829 * Program the multicast filter.
1831 * We have an artificial restriction that the multicast setup command
1832 * must be the first command in the chain, so we take steps to ensure
1833 * this. By requiring this, it allows us to keep up the performance of
1834 * the pre-initialized command ring (esp. link pointers) by not actually
1835 * inserting the mcsetup command in the ring - i.e. its link pointer
1836 * points to the TxCB ring, but the mcsetup descriptor itself is not part
1837 * of it. We then can do 'CU_START' on the mcsetup descriptor and have it
1838 * lead into the regular TxCB ring when it completes.
1840 * This function must be called at splimp.
1844 struct fxp_softc *sc;
1846 struct fxp_cb_mcs *mcsp = sc->mcsp;
1847 struct ifnet *ifp = &sc->sc_if;
1848 struct ifmultiaddr *ifma;
1853 * If there are queued commands, we must wait until they are all
1854 * completed. If we are already waiting, then add a NOP command
1855 * with interrupt option so that we're notified when all commands
1856 * have been completed - fxp_start() ensures that no additional
1857 * TX commands will be added when need_mcsetup is true.
1859 if (sc->tx_queued) {
1860 struct fxp_cb_tx *txp;
1863 * need_mcsetup will be true if we are already waiting for the
1864 * NOP command to be completed (see below). In this case, bail.
1866 if (sc->need_mcsetup)
1868 sc->need_mcsetup = 1;
1871 * Add a NOP command with interrupt so that we are notified when all
1872 * TX commands have been processed.
1874 txp = sc->cbl_last->next;
1875 txp->mb_head = NULL;
1877 txp->cb_command = FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S | FXP_CB_COMMAND_I;
1879 * Advance the end of list forward.
1881 sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S;
1885 * Issue a resume in case the CU has just suspended.
1888 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_RESUME);
1890 * Set a 5 second timer just in case we don't hear from the
1897 sc->need_mcsetup = 0;
1900 * Initialize multicast setup descriptor.
1902 mcsp->next = sc->cbl_base;
1903 mcsp->mb_head = NULL;
1904 mcsp->cb_status = 0;
1905 mcsp->cb_command = FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_S | FXP_CB_COMMAND_I;
1906 mcsp->link_addr = vtophys(&sc->cbl_base->cb_status);
1909 if (!sc->all_mcasts) {
1910 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1911 if (ifma->ifma_addr->sa_family != AF_LINK)
1913 if (nmcasts >= MAXMCADDR) {
1918 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1919 (void *)(uintptr_t)(volatile void *)
1920 &sc->mcsp->mc_addr[nmcasts][0], 6);
1924 mcsp->mc_cnt = nmcasts * 6;
1925 sc->cbl_first = sc->cbl_last = (struct fxp_cb_tx *) mcsp;
1929 * Wait until command unit is not active. This should never
1930 * be the case when nothing is queued, but make sure anyway.
1933 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) ==
1934 FXP_SCB_CUS_ACTIVE && --count)
1937 printf("fxp%d: command queue timeout\n", FXP_UNIT(sc));
1942 * Start the multicast setup command.
1945 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&mcsp->cb_status));
1946 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_START);