2 * SPDX-License-Identifier: BSD-2-Clause-NetBSD
4 * Copyright (c) 1995, David Greenman
5 * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org>
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice unmodified, this list of conditions, and the following
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 #include <sys/cdefs.h>
33 __FBSDID("$FreeBSD$");
36 * Intel EtherExpress Pro/100B PCI Fast Ethernet driver
39 #ifdef HAVE_KERNEL_OPTION_HEADERS
40 #include "opt_device_polling.h"
43 #include <sys/param.h>
44 #include <sys/systm.h>
46 #include <sys/endian.h>
47 #include <sys/kernel.h>
50 #include <sys/malloc.h>
51 #include <sys/module.h>
52 #include <sys/mutex.h>
54 #include <sys/socket.h>
55 #include <sys/sockio.h>
56 #include <sys/sysctl.h>
59 #include <net/ethernet.h>
61 #include <net/if_var.h>
62 #include <net/if_arp.h>
63 #include <net/if_dl.h>
64 #include <net/if_media.h>
65 #include <net/if_types.h>
66 #include <net/if_vlan_var.h>
68 #include <netinet/in.h>
69 #include <netinet/in_systm.h>
70 #include <netinet/ip.h>
71 #include <netinet/tcp.h>
72 #include <netinet/udp.h>
74 #include <machine/bus.h>
75 #include <machine/in_cksum.h>
76 #include <machine/resource.h>
78 #include <dev/pci/pcivar.h>
79 #include <dev/pci/pcireg.h> /* for PCIM_CMD_xxx */
81 #include <dev/mii/mii.h>
82 #include <dev/mii/miivar.h>
84 #include <dev/fxp/if_fxpreg.h>
85 #include <dev/fxp/if_fxpvar.h>
86 #include <dev/fxp/rcvbundl.h>
88 MODULE_DEPEND(fxp, pci, 1, 1, 1);
89 MODULE_DEPEND(fxp, ether, 1, 1, 1);
90 MODULE_DEPEND(fxp, miibus, 1, 1, 1);
91 #include "miibus_if.h"
94 * NOTE! On !x86 we typically have an alignment constraint. The
95 * card DMAs the packet immediately following the RFA. However,
96 * the first thing in the packet is a 14-byte Ethernet header.
97 * This means that the packet is misaligned. To compensate,
98 * we actually offset the RFA 2 bytes into the cluster. This
99 * alignes the packet after the Ethernet header at a 32-bit
100 * boundary. HOWEVER! This means that the RFA is misaligned!
102 #define RFA_ALIGNMENT_FUDGE 2
105 * Set initial transmit threshold at 64 (512 bytes). This is
106 * increased by 64 (512 bytes) at a time, to maximum of 192
107 * (1536 bytes), if an underrun occurs.
109 static int tx_threshold = 64;
112 * The configuration byte map has several undefined fields which
113 * must be one or must be zero. Set up a template for these bits.
114 * The actual configuration is performed in fxp_init_body.
116 * See struct fxp_cb_config for the bit definitions.
118 static const u_char fxp_cb_config_template[] = {
119 0x0, 0x0, /* cb_status */
120 0x0, 0x0, /* cb_command */
121 0x0, 0x0, 0x0, 0x0, /* link_addr */
157 * Claim various Intel PCI device identifiers for this driver. The
158 * sub-vendor and sub-device field are extensively used to identify
159 * particular variants, but we don't currently differentiate between
162 static const struct fxp_ident fxp_ident_table[] = {
163 { 0x8086, 0x1029, -1, 0, "Intel 82559 PCI/CardBus Pro/100" },
164 { 0x8086, 0x1030, -1, 0, "Intel 82559 Pro/100 Ethernet" },
165 { 0x8086, 0x1031, -1, 3, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" },
166 { 0x8086, 0x1032, -1, 3, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" },
167 { 0x8086, 0x1033, -1, 3, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" },
168 { 0x8086, 0x1034, -1, 3, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" },
169 { 0x8086, 0x1035, -1, 3, "Intel 82801CAM (ICH3) Pro/100 Ethernet" },
170 { 0x8086, 0x1036, -1, 3, "Intel 82801CAM (ICH3) Pro/100 Ethernet" },
171 { 0x8086, 0x1037, -1, 3, "Intel 82801CAM (ICH3) Pro/100 Ethernet" },
172 { 0x8086, 0x1038, -1, 3, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" },
173 { 0x8086, 0x1039, -1, 4, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" },
174 { 0x8086, 0x103A, -1, 4, "Intel 82801DB (ICH4) Pro/100 Ethernet" },
175 { 0x8086, 0x103B, -1, 4, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" },
176 { 0x8086, 0x103C, -1, 4, "Intel 82801DB (ICH4) Pro/100 Ethernet" },
177 { 0x8086, 0x103D, -1, 4, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" },
178 { 0x8086, 0x103E, -1, 4, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" },
179 { 0x8086, 0x1050, -1, 5, "Intel 82801BA (D865) Pro/100 VE Ethernet" },
180 { 0x8086, 0x1051, -1, 5, "Intel 82562ET (ICH5/ICH5R) Pro/100 VE Ethernet" },
181 { 0x8086, 0x1059, -1, 0, "Intel 82551QM Pro/100 M Mobile Connection" },
182 { 0x8086, 0x1064, -1, 6, "Intel 82562EZ (ICH6)" },
183 { 0x8086, 0x1065, -1, 6, "Intel 82562ET/EZ/GT/GZ PRO/100 VE Ethernet" },
184 { 0x8086, 0x1068, -1, 6, "Intel 82801FBM (ICH6-M) Pro/100 VE Ethernet" },
185 { 0x8086, 0x1069, -1, 6, "Intel 82562EM/EX/GX Pro/100 Ethernet" },
186 { 0x8086, 0x1091, -1, 7, "Intel 82562GX Pro/100 Ethernet" },
187 { 0x8086, 0x1092, -1, 7, "Intel Pro/100 VE Network Connection" },
188 { 0x8086, 0x1093, -1, 7, "Intel Pro/100 VM Network Connection" },
189 { 0x8086, 0x1094, -1, 7, "Intel Pro/100 946GZ (ICH7) Network Connection" },
190 { 0x8086, 0x1209, -1, 0, "Intel 82559ER Embedded 10/100 Ethernet" },
191 { 0x8086, 0x1229, 0x01, 0, "Intel 82557 Pro/100 Ethernet" },
192 { 0x8086, 0x1229, 0x02, 0, "Intel 82557 Pro/100 Ethernet" },
193 { 0x8086, 0x1229, 0x03, 0, "Intel 82557 Pro/100 Ethernet" },
194 { 0x8086, 0x1229, 0x04, 0, "Intel 82558 Pro/100 Ethernet" },
195 { 0x8086, 0x1229, 0x05, 0, "Intel 82558 Pro/100 Ethernet" },
196 { 0x8086, 0x1229, 0x06, 0, "Intel 82559 Pro/100 Ethernet" },
197 { 0x8086, 0x1229, 0x07, 0, "Intel 82559 Pro/100 Ethernet" },
198 { 0x8086, 0x1229, 0x08, 0, "Intel 82559 Pro/100 Ethernet" },
199 { 0x8086, 0x1229, 0x09, 0, "Intel 82559ER Pro/100 Ethernet" },
200 { 0x8086, 0x1229, 0x0c, 0, "Intel 82550 Pro/100 Ethernet" },
201 { 0x8086, 0x1229, 0x0d, 0, "Intel 82550C Pro/100 Ethernet" },
202 { 0x8086, 0x1229, 0x0e, 0, "Intel 82550 Pro/100 Ethernet" },
203 { 0x8086, 0x1229, 0x0f, 0, "Intel 82551 Pro/100 Ethernet" },
204 { 0x8086, 0x1229, 0x10, 0, "Intel 82551 Pro/100 Ethernet" },
205 { 0x8086, 0x1229, -1, 0, "Intel 82557/8/9 Pro/100 Ethernet" },
206 { 0x8086, 0x2449, -1, 2, "Intel 82801BA/CAM (ICH2/3) Pro/100 Ethernet" },
207 { 0x8086, 0x27dc, -1, 7, "Intel 82801GB (ICH7) 10/100 Ethernet" },
208 { 0, 0, -1, 0, NULL },
211 #ifdef FXP_IP_CSUM_WAR
212 #define FXP_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
214 #define FXP_CSUM_FEATURES (CSUM_TCP | CSUM_UDP)
217 static int fxp_probe(device_t dev);
218 static int fxp_attach(device_t dev);
219 static int fxp_detach(device_t dev);
220 static int fxp_shutdown(device_t dev);
221 static int fxp_suspend(device_t dev);
222 static int fxp_resume(device_t dev);
224 static const struct fxp_ident *fxp_find_ident(device_t dev);
225 static void fxp_intr(void *xsc);
226 static void fxp_rxcsum(struct fxp_softc *sc, if_t ifp,
227 struct mbuf *m, uint16_t status, int pos);
228 static int fxp_intr_body(struct fxp_softc *sc, if_t ifp,
229 uint8_t statack, int count);
230 static void fxp_init(void *xsc);
231 static void fxp_init_body(struct fxp_softc *sc, int);
232 static void fxp_tick(void *xsc);
233 static void fxp_start(if_t ifp);
234 static void fxp_start_body(if_t ifp);
235 static int fxp_encap(struct fxp_softc *sc, struct mbuf **m_head);
236 static void fxp_txeof(struct fxp_softc *sc);
237 static void fxp_stop(struct fxp_softc *sc);
238 static void fxp_release(struct fxp_softc *sc);
239 static int fxp_ioctl(if_t ifp, u_long command,
241 static void fxp_watchdog(struct fxp_softc *sc);
242 static void fxp_add_rfabuf(struct fxp_softc *sc,
244 static void fxp_discard_rfabuf(struct fxp_softc *sc,
246 static int fxp_new_rfabuf(struct fxp_softc *sc,
248 static void fxp_mc_addrs(struct fxp_softc *sc);
249 static void fxp_mc_setup(struct fxp_softc *sc);
250 static uint16_t fxp_eeprom_getword(struct fxp_softc *sc, int offset,
252 static void fxp_eeprom_putword(struct fxp_softc *sc, int offset,
254 static void fxp_autosize_eeprom(struct fxp_softc *sc);
255 static void fxp_load_eeprom(struct fxp_softc *sc);
256 static void fxp_read_eeprom(struct fxp_softc *sc, u_short *data,
257 int offset, int words);
258 static void fxp_write_eeprom(struct fxp_softc *sc, u_short *data,
259 int offset, int words);
260 static int fxp_ifmedia_upd(if_t ifp);
261 static void fxp_ifmedia_sts(if_t ifp,
262 struct ifmediareq *ifmr);
263 static int fxp_serial_ifmedia_upd(if_t ifp);
264 static void fxp_serial_ifmedia_sts(if_t ifp,
265 struct ifmediareq *ifmr);
266 static int fxp_miibus_readreg(device_t dev, int phy, int reg);
267 static int fxp_miibus_writereg(device_t dev, int phy, int reg,
269 static void fxp_miibus_statchg(device_t dev);
270 static void fxp_load_ucode(struct fxp_softc *sc);
271 static void fxp_update_stats(struct fxp_softc *sc);
272 static void fxp_sysctl_node(struct fxp_softc *sc);
273 static int sysctl_int_range(SYSCTL_HANDLER_ARGS,
275 static int sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS);
276 static int sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS);
277 static void fxp_scb_wait(struct fxp_softc *sc);
278 static void fxp_scb_cmd(struct fxp_softc *sc, int cmd);
279 static void fxp_dma_wait(struct fxp_softc *sc,
280 volatile uint16_t *status, bus_dma_tag_t dmat,
283 static device_method_t fxp_methods[] = {
284 /* Device interface */
285 DEVMETHOD(device_probe, fxp_probe),
286 DEVMETHOD(device_attach, fxp_attach),
287 DEVMETHOD(device_detach, fxp_detach),
288 DEVMETHOD(device_shutdown, fxp_shutdown),
289 DEVMETHOD(device_suspend, fxp_suspend),
290 DEVMETHOD(device_resume, fxp_resume),
293 DEVMETHOD(miibus_readreg, fxp_miibus_readreg),
294 DEVMETHOD(miibus_writereg, fxp_miibus_writereg),
295 DEVMETHOD(miibus_statchg, fxp_miibus_statchg),
300 static driver_t fxp_driver = {
303 sizeof(struct fxp_softc),
306 static devclass_t fxp_devclass;
308 DRIVER_MODULE_ORDERED(fxp, pci, fxp_driver, fxp_devclass, NULL, NULL,
310 MODULE_PNP_INFO("U16:vendor;U16:device", pci, fxp, fxp_ident_table,
311 nitems(fxp_ident_table) - 1);
312 DRIVER_MODULE(miibus, fxp, miibus_driver, miibus_devclass, NULL, NULL);
314 static struct resource_spec fxp_res_spec_mem[] = {
315 { SYS_RES_MEMORY, FXP_PCI_MMBA, RF_ACTIVE },
316 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
320 static struct resource_spec fxp_res_spec_io[] = {
321 { SYS_RES_IOPORT, FXP_PCI_IOBA, RF_ACTIVE },
322 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
327 * Wait for the previous command to be accepted (but not necessarily
331 fxp_scb_wait(struct fxp_softc *sc)
339 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i)
342 flowctl.b[0] = CSR_READ_1(sc, FXP_CSR_FC_THRESH);
343 flowctl.b[1] = CSR_READ_1(sc, FXP_CSR_FC_STATUS);
344 device_printf(sc->dev, "SCB timeout: 0x%x 0x%x 0x%x 0x%x\n",
345 CSR_READ_1(sc, FXP_CSR_SCB_COMMAND),
346 CSR_READ_1(sc, FXP_CSR_SCB_STATACK),
347 CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS), flowctl.w);
352 fxp_scb_cmd(struct fxp_softc *sc, int cmd)
355 if (cmd == FXP_SCB_COMMAND_CU_RESUME && sc->cu_resume_bug) {
356 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_CB_COMMAND_NOP);
359 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd);
363 fxp_dma_wait(struct fxp_softc *sc, volatile uint16_t *status,
364 bus_dma_tag_t dmat, bus_dmamap_t map)
368 for (i = 10000; i > 0; i--) {
370 bus_dmamap_sync(dmat, map,
371 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
372 if ((le16toh(*status) & FXP_CB_STATUS_C) != 0)
376 device_printf(sc->dev, "DMA timeout\n");
379 static const struct fxp_ident *
380 fxp_find_ident(device_t dev)
385 const struct fxp_ident *ident;
387 vendor = pci_get_vendor(dev);
388 device = pci_get_device(dev);
389 revid = pci_get_revid(dev);
390 for (ident = fxp_ident_table; ident->name != NULL; ident++) {
391 if (ident->vendor == vendor && ident->device == device &&
392 (ident->revid == revid || ident->revid == -1)) {
400 * Return identification string if this device is ours.
403 fxp_probe(device_t dev)
405 const struct fxp_ident *ident;
407 ident = fxp_find_ident(dev);
409 device_set_desc(dev, ident->name);
410 return (BUS_PROBE_DEFAULT);
416 fxp_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
423 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg));
425 *addr = segs->ds_addr;
429 fxp_attach(device_t dev)
431 struct fxp_softc *sc;
432 struct fxp_cb_tx *tcbp;
438 u_char eaddr[ETHER_ADDR_LEN];
439 int error, flags, i, pmc, prefer_iomap;
442 sc = device_get_softc(dev);
444 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
446 callout_init_mtx(&sc->stat_ch, &sc->sc_mtx, 0);
447 ifmedia_init(&sc->sc_media, 0, fxp_serial_ifmedia_upd,
448 fxp_serial_ifmedia_sts);
450 ifp = sc->ifp = if_gethandle(IFT_ETHER);
451 if (ifp == (void *)NULL) {
452 device_printf(dev, "can not if_alloc()\n");
458 * Enable bus mastering.
460 pci_enable_busmaster(dev);
463 * Figure out which we should try first - memory mapping or i/o mapping?
464 * We default to memory mapping. Then we accept an override from the
465 * command line. Then we check to see which one is enabled.
468 resource_int_value(device_get_name(dev), device_get_unit(dev),
469 "prefer_iomap", &prefer_iomap);
471 sc->fxp_spec = fxp_res_spec_io;
473 sc->fxp_spec = fxp_res_spec_mem;
475 error = bus_alloc_resources(dev, sc->fxp_spec, sc->fxp_res);
477 if (sc->fxp_spec == fxp_res_spec_mem)
478 sc->fxp_spec = fxp_res_spec_io;
480 sc->fxp_spec = fxp_res_spec_mem;
481 error = bus_alloc_resources(dev, sc->fxp_spec, sc->fxp_res);
484 device_printf(dev, "could not allocate resources\n");
490 device_printf(dev, "using %s space register mapping\n",
491 sc->fxp_spec == fxp_res_spec_mem ? "memory" : "I/O");
495 * Put CU/RU idle state and prepare full reset.
497 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET);
499 /* Full reset and disable interrupts. */
500 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET);
502 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE);
505 * Find out how large of an SEEPROM we have.
507 fxp_autosize_eeprom(sc);
511 * Find out the chip revision; lump all 82557 revs together.
513 sc->ident = fxp_find_ident(dev);
514 if (sc->ident->ich > 0) {
515 /* Assume ICH controllers are 82559. */
516 sc->revision = FXP_REV_82559_A0;
518 data = sc->eeprom[FXP_EEPROM_MAP_CNTR];
519 if ((data >> 8) == 1)
520 sc->revision = FXP_REV_82557;
522 sc->revision = pci_get_revid(dev);
526 * Check availability of WOL. 82559ER does not support WOL.
528 if (sc->revision >= FXP_REV_82558_A4 &&
529 sc->revision != FXP_REV_82559S_A) {
530 data = sc->eeprom[FXP_EEPROM_MAP_ID];
531 if ((data & 0x20) != 0 &&
532 pci_find_cap(sc->dev, PCIY_PMG, &pmc) == 0)
533 sc->flags |= FXP_FLAG_WOLCAP;
536 if (sc->revision == FXP_REV_82550_C) {
538 * 82550C with server extension requires microcode to
539 * receive fragmented UDP datagrams. However if the
540 * microcode is used for client-only featured 82550C
541 * it locks up controller.
543 data = sc->eeprom[FXP_EEPROM_MAP_COMPAT];
544 if ((data & 0x0400) == 0)
545 sc->flags |= FXP_FLAG_NO_UCODE;
548 /* Receiver lock-up workaround detection. */
549 if (sc->revision < FXP_REV_82558_A4) {
550 data = sc->eeprom[FXP_EEPROM_MAP_COMPAT];
551 if ((data & 0x03) != 0x03) {
552 sc->flags |= FXP_FLAG_RXBUG;
553 device_printf(dev, "Enabling Rx lock-up workaround\n");
558 * Determine whether we must use the 503 serial interface.
560 data = sc->eeprom[FXP_EEPROM_MAP_PRI_PHY];
561 if (sc->revision == FXP_REV_82557 && (data & FXP_PHY_DEVICE_MASK) != 0
562 && (data & FXP_PHY_SERIAL_ONLY))
563 sc->flags |= FXP_FLAG_SERIAL_MEDIA;
567 * Enable workarounds for certain chip revision deficiencies.
569 * Systems based on the ICH2/ICH2-M chip from Intel, and possibly
570 * some systems based a normal 82559 design, have a defect where
571 * the chip can cause a PCI protocol violation if it receives
572 * a CU_RESUME command when it is entering the IDLE state. The
573 * workaround is to disable Dynamic Standby Mode, so the chip never
574 * deasserts CLKRUN#, and always remains in an active state.
576 * See Intel 82801BA/82801BAM Specification Update, Errata #30.
578 if ((sc->ident->ich >= 2 && sc->ident->ich <= 3) ||
579 (sc->ident->ich == 0 && sc->revision >= FXP_REV_82559_A0)) {
580 data = sc->eeprom[FXP_EEPROM_MAP_ID];
581 if (data & 0x02) { /* STB enable */
586 "Disabling dynamic standby mode in EEPROM\n");
588 sc->eeprom[FXP_EEPROM_MAP_ID] = data;
589 fxp_write_eeprom(sc, &data, FXP_EEPROM_MAP_ID, 1);
590 device_printf(dev, "New EEPROM ID: 0x%x\n", data);
592 for (i = 0; i < (1 << sc->eeprom_size) - 1; i++)
593 cksum += sc->eeprom[i];
594 i = (1 << sc->eeprom_size) - 1;
595 cksum = 0xBABA - cksum;
596 fxp_write_eeprom(sc, &cksum, i, 1);
598 "EEPROM checksum @ 0x%x: 0x%x -> 0x%x\n",
599 i, sc->eeprom[i], cksum);
600 sc->eeprom[i] = cksum;
602 * If the user elects to continue, try the software
603 * workaround, as it is better than nothing.
605 sc->flags |= FXP_FLAG_CU_RESUME_BUG;
610 * If we are not a 82557 chip, we can enable extended features.
612 if (sc->revision != FXP_REV_82557) {
614 * If MWI is enabled in the PCI configuration, and there
615 * is a valid cacheline size (8 or 16 dwords), then tell
616 * the board to turn on MWI.
618 val = pci_read_config(dev, PCIR_COMMAND, 2);
619 if (val & PCIM_CMD_MWRICEN &&
620 pci_read_config(dev, PCIR_CACHELNSZ, 1) != 0)
621 sc->flags |= FXP_FLAG_MWI_ENABLE;
623 /* turn on the extended TxCB feature */
624 sc->flags |= FXP_FLAG_EXT_TXCB;
626 /* enable reception of long frames for VLAN */
627 sc->flags |= FXP_FLAG_LONG_PKT_EN;
629 /* a hack to get long VLAN frames on a 82557 */
630 sc->flags |= FXP_FLAG_SAVE_BAD;
633 /* For 82559 or later chips, Rx checksum offload is supported. */
634 if (sc->revision >= FXP_REV_82559_A0) {
635 /* 82559ER does not support Rx checksum offloading. */
636 if (sc->ident->device != 0x1209)
637 sc->flags |= FXP_FLAG_82559_RXCSUM;
640 * Enable use of extended RFDs and TCBs for 82550
641 * and later chips. Note: we need extended TXCB support
642 * too, but that's already enabled by the code above.
643 * Be careful to do this only on the right devices.
645 if (sc->revision == FXP_REV_82550 || sc->revision == FXP_REV_82550_C ||
646 sc->revision == FXP_REV_82551_E || sc->revision == FXP_REV_82551_F
647 || sc->revision == FXP_REV_82551_10) {
648 sc->rfa_size = sizeof (struct fxp_rfa);
649 sc->tx_cmd = FXP_CB_COMMAND_IPCBXMIT;
650 sc->flags |= FXP_FLAG_EXT_RFA;
651 /* Use extended RFA instead of 82559 checksum mode. */
652 sc->flags &= ~FXP_FLAG_82559_RXCSUM;
654 sc->rfa_size = sizeof (struct fxp_rfa) - FXP_RFAX_LEN;
655 sc->tx_cmd = FXP_CB_COMMAND_XMIT;
659 * Allocate DMA tags and DMA safe memory.
661 sc->maxtxseg = FXP_NTXSEG;
662 sc->maxsegsize = MCLBYTES;
663 if (sc->flags & FXP_FLAG_EXT_RFA) {
665 sc->maxsegsize = FXP_TSO_SEGSIZE;
667 error = bus_dma_tag_create(bus_get_dma_tag(dev), 2, 0,
668 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
669 sc->maxsegsize * sc->maxtxseg + sizeof(struct ether_vlan_header),
670 sc->maxtxseg, sc->maxsegsize, 0, NULL, NULL, &sc->fxp_txmtag);
672 device_printf(dev, "could not create TX DMA tag\n");
676 error = bus_dma_tag_create(bus_get_dma_tag(dev), 2, 0,
677 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
678 MCLBYTES, 1, MCLBYTES, 0, NULL, NULL, &sc->fxp_rxmtag);
680 device_printf(dev, "could not create RX DMA tag\n");
684 error = bus_dma_tag_create(bus_get_dma_tag(dev), 4, 0,
685 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
686 sizeof(struct fxp_stats), 1, sizeof(struct fxp_stats), 0,
687 NULL, NULL, &sc->fxp_stag);
689 device_printf(dev, "could not create stats DMA tag\n");
693 error = bus_dmamem_alloc(sc->fxp_stag, (void **)&sc->fxp_stats,
694 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->fxp_smap);
696 device_printf(dev, "could not allocate stats DMA memory\n");
699 error = bus_dmamap_load(sc->fxp_stag, sc->fxp_smap, sc->fxp_stats,
700 sizeof(struct fxp_stats), fxp_dma_map_addr, &sc->stats_addr,
703 device_printf(dev, "could not load the stats DMA buffer\n");
707 error = bus_dma_tag_create(bus_get_dma_tag(dev), 4, 0,
708 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
709 FXP_TXCB_SZ, 1, FXP_TXCB_SZ, 0, NULL, NULL, &sc->cbl_tag);
711 device_printf(dev, "could not create TxCB DMA tag\n");
715 error = bus_dmamem_alloc(sc->cbl_tag, (void **)&sc->fxp_desc.cbl_list,
716 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->cbl_map);
718 device_printf(dev, "could not allocate TxCB DMA memory\n");
722 error = bus_dmamap_load(sc->cbl_tag, sc->cbl_map,
723 sc->fxp_desc.cbl_list, FXP_TXCB_SZ, fxp_dma_map_addr,
724 &sc->fxp_desc.cbl_addr, BUS_DMA_NOWAIT);
726 device_printf(dev, "could not load TxCB DMA buffer\n");
730 error = bus_dma_tag_create(bus_get_dma_tag(dev), 4, 0,
731 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
732 sizeof(struct fxp_cb_mcs), 1, sizeof(struct fxp_cb_mcs), 0,
733 NULL, NULL, &sc->mcs_tag);
736 "could not create multicast setup DMA tag\n");
740 error = bus_dmamem_alloc(sc->mcs_tag, (void **)&sc->mcsp,
741 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->mcs_map);
744 "could not allocate multicast setup DMA memory\n");
747 error = bus_dmamap_load(sc->mcs_tag, sc->mcs_map, sc->mcsp,
748 sizeof(struct fxp_cb_mcs), fxp_dma_map_addr, &sc->mcs_addr,
752 "can't load the multicast setup DMA buffer\n");
757 * Pre-allocate the TX DMA maps and setup the pointers to
758 * the TX command blocks.
760 txp = sc->fxp_desc.tx_list;
761 tcbp = sc->fxp_desc.cbl_list;
762 for (i = 0; i < FXP_NTXCB; i++) {
763 txp[i].tx_cb = tcbp + i;
764 error = bus_dmamap_create(sc->fxp_txmtag, 0, &txp[i].tx_map);
766 device_printf(dev, "can't create DMA map for TX\n");
770 error = bus_dmamap_create(sc->fxp_rxmtag, 0, &sc->spare_map);
772 device_printf(dev, "can't create spare DMA map\n");
777 * Pre-allocate our receive buffers.
779 sc->fxp_desc.rx_head = sc->fxp_desc.rx_tail = NULL;
780 for (i = 0; i < FXP_NRFABUFS; i++) {
781 rxp = &sc->fxp_desc.rx_list[i];
782 error = bus_dmamap_create(sc->fxp_rxmtag, 0, &rxp->rx_map);
784 device_printf(dev, "can't create DMA map for RX\n");
787 if (fxp_new_rfabuf(sc, rxp) != 0) {
791 fxp_add_rfabuf(sc, rxp);
797 eaddr[0] = sc->eeprom[FXP_EEPROM_MAP_IA0] & 0xff;
798 eaddr[1] = sc->eeprom[FXP_EEPROM_MAP_IA0] >> 8;
799 eaddr[2] = sc->eeprom[FXP_EEPROM_MAP_IA1] & 0xff;
800 eaddr[3] = sc->eeprom[FXP_EEPROM_MAP_IA1] >> 8;
801 eaddr[4] = sc->eeprom[FXP_EEPROM_MAP_IA2] & 0xff;
802 eaddr[5] = sc->eeprom[FXP_EEPROM_MAP_IA2] >> 8;
804 device_printf(dev, "PCI IDs: %04x %04x %04x %04x %04x\n",
805 pci_get_vendor(dev), pci_get_device(dev),
806 pci_get_subvendor(dev), pci_get_subdevice(dev),
808 device_printf(dev, "Dynamic Standby mode is %s\n",
809 sc->eeprom[FXP_EEPROM_MAP_ID] & 0x02 ? "enabled" :
814 * If this is only a 10Mbps device, then there is no MII, and
815 * the PHY will use a serial interface instead.
817 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter
818 * doesn't have a programming interface of any sort. The
819 * media is sensed automatically based on how the link partner
820 * is configured. This is, in essence, manual configuration.
822 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) {
823 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL);
824 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL);
827 * i82557 wedge when isolating all of their PHYs.
829 flags = MIIF_NOISOLATE;
830 if (sc->revision >= FXP_REV_82558_A4)
831 flags |= MIIF_DOPAUSE;
832 error = mii_attach(dev, &sc->miibus, ifp,
833 (ifm_change_cb_t)fxp_ifmedia_upd,
834 (ifm_stat_cb_t)fxp_ifmedia_sts, BMSR_DEFCAPMASK,
835 MII_PHY_ANY, MII_OFFSET_ANY, flags);
837 device_printf(dev, "attaching PHYs failed\n");
842 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
844 if_setinitfn(ifp, fxp_init);
845 if_setsoftc(ifp, sc);
846 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST);
847 if_setioctlfn(ifp, fxp_ioctl);
848 if_setstartfn(ifp, fxp_start);
850 if_setcapabilities(ifp, 0);
851 if_setcapenable(ifp, 0);
853 /* Enable checksum offload/TSO for 82550 or better chips */
854 if (sc->flags & FXP_FLAG_EXT_RFA) {
855 if_sethwassist(ifp, FXP_CSUM_FEATURES | CSUM_TSO);
856 if_setcapabilitiesbit(ifp, IFCAP_HWCSUM | IFCAP_TSO4, 0);
857 if_setcapenablebit(ifp, IFCAP_HWCSUM | IFCAP_TSO4, 0);
860 if (sc->flags & FXP_FLAG_82559_RXCSUM) {
861 if_setcapabilitiesbit(ifp, IFCAP_RXCSUM, 0);
862 if_setcapenablebit(ifp, IFCAP_RXCSUM, 0);
865 if (sc->flags & FXP_FLAG_WOLCAP) {
866 if_setcapabilitiesbit(ifp, IFCAP_WOL_MAGIC, 0);
867 if_setcapenablebit(ifp, IFCAP_WOL_MAGIC, 0);
870 #ifdef DEVICE_POLLING
871 /* Inform the world we support polling. */
872 if_setcapabilitiesbit(ifp, IFCAP_POLLING, 0);
876 * Attach the interface.
878 ether_ifattach(ifp, eaddr);
881 * Tell the upper layer(s) we support long frames.
882 * Must appear after the call to ether_ifattach() because
883 * ether_ifattach() sets ifi_hdrlen to the default value.
885 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header));
886 if_setcapabilitiesbit(ifp, IFCAP_VLAN_MTU, 0);
887 if_setcapenablebit(ifp, IFCAP_VLAN_MTU, 0);
888 if ((sc->flags & FXP_FLAG_EXT_RFA) != 0) {
889 if_setcapabilitiesbit(ifp, IFCAP_VLAN_HWTAGGING |
890 IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO, 0);
891 if_setcapenablebit(ifp, IFCAP_VLAN_HWTAGGING |
892 IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO, 0);
896 * Let the system queue as many packets as we have available
899 if_setsendqlen(ifp, FXP_NTXCB - 1);
900 if_setsendqready(ifp);
903 * Hook our interrupt after all initialization is complete.
905 error = bus_setup_intr(dev, sc->fxp_res[1], INTR_TYPE_NET | INTR_MPSAFE,
906 NULL, fxp_intr, sc, &sc->ih);
908 device_printf(dev, "could not setup irq\n");
909 ether_ifdetach(sc->ifp);
914 * Configure hardware to reject magic frames otherwise
915 * system will hang on recipt of magic frames.
917 if ((sc->flags & FXP_FLAG_WOLCAP) != 0) {
919 /* Clear wakeup events. */
920 CSR_WRITE_1(sc, FXP_CSR_PMDR, CSR_READ_1(sc, FXP_CSR_PMDR));
921 fxp_init_body(sc, 0);
933 * Release all resources. The softc lock should not be held and the
934 * interrupt should already be torn down.
937 fxp_release(struct fxp_softc *sc)
943 FXP_LOCK_ASSERT(sc, MA_NOTOWNED);
944 KASSERT(sc->ih == NULL,
945 ("fxp_release() called with intr handle still active"));
947 device_delete_child(sc->dev, sc->miibus);
948 bus_generic_detach(sc->dev);
949 ifmedia_removeall(&sc->sc_media);
950 if (sc->fxp_desc.cbl_list) {
951 bus_dmamap_unload(sc->cbl_tag, sc->cbl_map);
952 bus_dmamem_free(sc->cbl_tag, sc->fxp_desc.cbl_list,
956 bus_dmamap_unload(sc->fxp_stag, sc->fxp_smap);
957 bus_dmamem_free(sc->fxp_stag, sc->fxp_stats, sc->fxp_smap);
960 bus_dmamap_unload(sc->mcs_tag, sc->mcs_map);
961 bus_dmamem_free(sc->mcs_tag, sc->mcsp, sc->mcs_map);
963 bus_release_resources(sc->dev, sc->fxp_spec, sc->fxp_res);
964 if (sc->fxp_rxmtag) {
965 for (i = 0; i < FXP_NRFABUFS; i++) {
966 rxp = &sc->fxp_desc.rx_list[i];
967 if (rxp->rx_mbuf != NULL) {
968 bus_dmamap_sync(sc->fxp_rxmtag, rxp->rx_map,
969 BUS_DMASYNC_POSTREAD);
970 bus_dmamap_unload(sc->fxp_rxmtag, rxp->rx_map);
971 m_freem(rxp->rx_mbuf);
973 bus_dmamap_destroy(sc->fxp_rxmtag, rxp->rx_map);
975 bus_dmamap_destroy(sc->fxp_rxmtag, sc->spare_map);
976 bus_dma_tag_destroy(sc->fxp_rxmtag);
978 if (sc->fxp_txmtag) {
979 for (i = 0; i < FXP_NTXCB; i++) {
980 txp = &sc->fxp_desc.tx_list[i];
981 if (txp->tx_mbuf != NULL) {
982 bus_dmamap_sync(sc->fxp_txmtag, txp->tx_map,
983 BUS_DMASYNC_POSTWRITE);
984 bus_dmamap_unload(sc->fxp_txmtag, txp->tx_map);
985 m_freem(txp->tx_mbuf);
987 bus_dmamap_destroy(sc->fxp_txmtag, txp->tx_map);
989 bus_dma_tag_destroy(sc->fxp_txmtag);
992 bus_dma_tag_destroy(sc->fxp_stag);
994 bus_dma_tag_destroy(sc->cbl_tag);
996 bus_dma_tag_destroy(sc->mcs_tag);
1000 mtx_destroy(&sc->sc_mtx);
1007 fxp_detach(device_t dev)
1009 struct fxp_softc *sc = device_get_softc(dev);
1011 #ifdef DEVICE_POLLING
1012 if (if_getcapenable(sc->ifp) & IFCAP_POLLING)
1013 ether_poll_deregister(sc->ifp);
1018 * Stop DMA and drop transmit queue, but disable interrupts first.
1020 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE);
1023 callout_drain(&sc->stat_ch);
1026 * Close down routes etc.
1028 ether_ifdetach(sc->ifp);
1031 * Unhook interrupt before dropping lock. This is to prevent
1032 * races with fxp_intr().
1034 bus_teardown_intr(sc->dev, sc->fxp_res[1], sc->ih);
1037 /* Release our allocated resources. */
1043 * Device shutdown routine. Called at system shutdown after sync. The
1044 * main purpose of this routine is to shut off receiver DMA so that
1045 * kernel memory doesn't get clobbered during warmboot.
1048 fxp_shutdown(device_t dev)
1052 * Make sure that DMA is disabled prior to reboot. Not doing
1053 * do could allow DMA to corrupt kernel memory during the
1054 * reboot before the driver initializes.
1056 return (fxp_suspend(dev));
1060 * Device suspend routine. Stop the interface and save some PCI
1061 * settings in case the BIOS doesn't restore them properly on
1065 fxp_suspend(device_t dev)
1067 struct fxp_softc *sc = device_get_softc(dev);
1075 if (pci_find_cap(sc->dev, PCIY_PMG, &pmc) == 0) {
1076 pmstat = pci_read_config(sc->dev, pmc + PCIR_POWER_STATUS, 2);
1077 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
1078 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) != 0) {
1080 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
1081 sc->flags |= FXP_FLAG_WOL;
1082 /* Reconfigure hardware to accept magic frames. */
1083 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
1084 fxp_init_body(sc, 0);
1086 pci_write_config(sc->dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
1097 * Device resume routine. re-enable busmastering, and restart the interface if
1101 fxp_resume(device_t dev)
1103 struct fxp_softc *sc = device_get_softc(dev);
1110 if (pci_find_cap(sc->dev, PCIY_PMG, &pmc) == 0) {
1111 sc->flags &= ~FXP_FLAG_WOL;
1112 pmstat = pci_read_config(sc->dev, pmc + PCIR_POWER_STATUS, 2);
1113 /* Disable PME and clear PME status. */
1114 pmstat &= ~PCIM_PSTAT_PMEENABLE;
1115 pci_write_config(sc->dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
1116 if ((sc->flags & FXP_FLAG_WOLCAP) != 0)
1117 CSR_WRITE_1(sc, FXP_CSR_PMDR,
1118 CSR_READ_1(sc, FXP_CSR_PMDR));
1121 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET);
1124 /* reinitialize interface if necessary */
1125 if (if_getflags(ifp) & IFF_UP)
1126 fxp_init_body(sc, 1);
1135 fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int length)
1143 for (x = 1 << (length - 1); x; x >>= 1) {
1145 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI;
1147 reg = FXP_EEPROM_EECS;
1148 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1150 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK);
1152 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1158 * Read from the serial EEPROM. Basically, you manually shift in
1159 * the read opcode (one bit at a time) and then shift in the address,
1160 * and then you shift out the data (all of this one bit at a time).
1161 * The word size is 16 bits, so you have to provide the address for
1162 * every 16 bits of data.
1165 fxp_eeprom_getword(struct fxp_softc *sc, int offset, int autosize)
1170 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
1172 * Shift in read opcode.
1174 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3);
1179 for (x = 1 << (sc->eeprom_size - 1); x; x >>= 1) {
1181 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI;
1183 reg = FXP_EEPROM_EECS;
1184 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1186 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK);
1188 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1190 reg = CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO;
1192 if (autosize && reg == 0) {
1193 sc->eeprom_size = data;
1201 reg = FXP_EEPROM_EECS;
1202 for (x = 1 << 15; x; x >>= 1) {
1203 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK);
1205 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO)
1207 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1210 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1217 fxp_eeprom_putword(struct fxp_softc *sc, int offset, uint16_t data)
1222 * Erase/write enable.
1224 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
1225 fxp_eeprom_shiftin(sc, 0x4, 3);
1226 fxp_eeprom_shiftin(sc, 0x03 << (sc->eeprom_size - 2), sc->eeprom_size);
1227 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1230 * Shift in write opcode, address, data.
1232 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
1233 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3);
1234 fxp_eeprom_shiftin(sc, offset, sc->eeprom_size);
1235 fxp_eeprom_shiftin(sc, data, 16);
1236 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1239 * Wait for EEPROM to finish up.
1241 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
1243 for (i = 0; i < 1000; i++) {
1244 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO)
1248 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1251 * Erase/write disable.
1253 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
1254 fxp_eeprom_shiftin(sc, 0x4, 3);
1255 fxp_eeprom_shiftin(sc, 0, sc->eeprom_size);
1256 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1263 * Figure out EEPROM size.
1265 * 559's can have either 64-word or 256-word EEPROMs, the 558
1266 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet
1267 * talks about the existence of 16 to 256 word EEPROMs.
1269 * The only known sizes are 64 and 256, where the 256 version is used
1270 * by CardBus cards to store CIS information.
1272 * The address is shifted in msb-to-lsb, and after the last
1273 * address-bit the EEPROM is supposed to output a `dummy zero' bit,
1274 * after which follows the actual data. We try to detect this zero, by
1275 * probing the data-out bit in the EEPROM control register just after
1276 * having shifted in a bit. If the bit is zero, we assume we've
1277 * shifted enough address bits. The data-out should be tri-state,
1278 * before this, which should translate to a logical one.
1281 fxp_autosize_eeprom(struct fxp_softc *sc)
1284 /* guess maximum size of 256 words */
1285 sc->eeprom_size = 8;
1288 (void) fxp_eeprom_getword(sc, 0, 1);
1292 fxp_read_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words)
1296 for (i = 0; i < words; i++)
1297 data[i] = fxp_eeprom_getword(sc, offset + i, 0);
1301 fxp_write_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words)
1305 for (i = 0; i < words; i++)
1306 fxp_eeprom_putword(sc, offset + i, data[i]);
1310 fxp_load_eeprom(struct fxp_softc *sc)
1315 fxp_read_eeprom(sc, sc->eeprom, 0, 1 << sc->eeprom_size);
1317 for (i = 0; i < (1 << sc->eeprom_size) - 1; i++)
1318 cksum += sc->eeprom[i];
1319 cksum = 0xBABA - cksum;
1320 if (cksum != sc->eeprom[(1 << sc->eeprom_size) - 1])
1321 device_printf(sc->dev,
1322 "EEPROM checksum mismatch! (0x%04x -> 0x%04x)\n",
1323 cksum, sc->eeprom[(1 << sc->eeprom_size) - 1]);
1327 * Grab the softc lock and call the real fxp_start_body() routine
1332 struct fxp_softc *sc = if_getsoftc(ifp);
1335 fxp_start_body(ifp);
1340 * Start packet transmission on the interface.
1341 * This routine must be called with the softc lock held, and is an
1342 * internal entry point only.
1345 fxp_start_body(if_t ifp)
1347 struct fxp_softc *sc = if_getsoftc(ifp);
1348 struct mbuf *mb_head;
1351 FXP_LOCK_ASSERT(sc, MA_OWNED);
1353 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
1357 if (sc->tx_queued > FXP_NTXCB_HIWAT)
1360 * We're finished if there is nothing more to add to the list or if
1361 * we're all filled up with buffers to transmit.
1362 * NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add
1363 * a NOP command when needed.
1366 while (!if_sendq_empty(ifp) && sc->tx_queued < FXP_NTXCB - 1) {
1369 * Grab a packet to transmit.
1371 mb_head = if_dequeue(ifp);
1372 if (mb_head == NULL)
1375 if (fxp_encap(sc, &mb_head)) {
1376 if (mb_head == NULL)
1378 if_sendq_prepend(ifp, mb_head);
1379 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0);
1383 * Pass packet to bpf if there is a listener.
1385 if_bpfmtap(ifp, mb_head);
1389 * We're finished. If we added to the list, issue a RESUME to get DMA
1390 * going again if suspended.
1393 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map,
1394 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1396 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME);
1398 * Set a 5 second timer just in case we don't hear
1399 * from the card again.
1401 sc->watchdog_timer = 5;
1406 fxp_encap(struct fxp_softc *sc, struct mbuf **m_head)
1410 struct fxp_cb_tx *cbp;
1412 bus_dma_segment_t segs[FXP_NTXSEG];
1413 int error, i, nseg, tcp_payload;
1415 FXP_LOCK_ASSERT(sc, MA_OWNED);
1420 * Get pointer to next available tx desc.
1422 txp = sc->fxp_desc.tx_last->tx_next;
1425 * A note in Appendix B of the Intel 8255x 10/100 Mbps
1426 * Ethernet Controller Family Open Source Software
1427 * Developer Manual says:
1428 * Using software parsing is only allowed with legal
1429 * TCP/IP or UDP/IP packets.
1431 * For all other datagrams, hardware parsing must
1433 * Software parsing appears to truncate ICMP and
1434 * fragmented UDP packets that contain one to three
1435 * bytes in the second (and final) mbuf of the packet.
1437 if (sc->flags & FXP_FLAG_EXT_RFA)
1438 txp->tx_cb->ipcb_ip_activation_high =
1439 FXP_IPCB_HARDWAREPARSING_ENABLE;
1442 if (m->m_pkthdr.csum_flags & CSUM_TSO) {
1444 * 82550/82551 requires ethernet/IP/TCP headers must be
1445 * contained in the first active transmit buffer.
1447 struct ether_header *eh;
1449 uint32_t ip_off, poff;
1451 if (M_WRITABLE(*m_head) == 0) {
1452 /* Get a writable copy. */
1453 m = m_dup(*m_head, M_NOWAIT);
1461 ip_off = sizeof(struct ether_header);
1462 m = m_pullup(*m_head, ip_off);
1467 eh = mtod(m, struct ether_header *);
1468 /* Check the existence of VLAN tag. */
1469 if (eh->ether_type == htons(ETHERTYPE_VLAN)) {
1470 ip_off = sizeof(struct ether_vlan_header);
1471 m = m_pullup(m, ip_off);
1477 m = m_pullup(m, ip_off + sizeof(struct ip));
1482 ip = (struct ip *)(mtod(m, char *) + ip_off);
1483 poff = ip_off + (ip->ip_hl << 2);
1484 m = m_pullup(m, poff + sizeof(struct tcphdr));
1489 tcp = (struct tcphdr *)(mtod(m, char *) + poff);
1490 m = m_pullup(m, poff + (tcp->th_off << 2));
1497 * Since 82550/82551 doesn't modify IP length and pseudo
1498 * checksum in the first frame driver should compute it.
1500 ip = (struct ip *)(mtod(m, char *) + ip_off);
1501 tcp = (struct tcphdr *)(mtod(m, char *) + poff);
1503 ip->ip_len = htons(m->m_pkthdr.tso_segsz + (ip->ip_hl << 2) +
1504 (tcp->th_off << 2));
1505 tcp->th_sum = in_pseudo(ip->ip_src.s_addr, ip->ip_dst.s_addr,
1506 htons(IPPROTO_TCP + (tcp->th_off << 2) +
1507 m->m_pkthdr.tso_segsz));
1508 /* Compute total TCP payload. */
1509 tcp_payload = m->m_pkthdr.len - ip_off - (ip->ip_hl << 2);
1510 tcp_payload -= tcp->th_off << 2;
1512 } else if (m->m_pkthdr.csum_flags & FXP_CSUM_FEATURES) {
1514 * Deal with TCP/IP checksum offload. Note that
1515 * in order for TCP checksum offload to work,
1516 * the pseudo header checksum must have already
1517 * been computed and stored in the checksum field
1518 * in the TCP header. The stack should have
1519 * already done this for us.
1521 txp->tx_cb->ipcb_ip_schedule = FXP_IPCB_TCPUDP_CHECKSUM_ENABLE;
1522 if (m->m_pkthdr.csum_flags & CSUM_TCP)
1523 txp->tx_cb->ipcb_ip_schedule |= FXP_IPCB_TCP_PACKET;
1525 #ifdef FXP_IP_CSUM_WAR
1527 * XXX The 82550 chip appears to have trouble
1528 * dealing with IP header checksums in very small
1529 * datagrams, namely fragments from 1 to 3 bytes
1530 * in size. For example, say you want to transmit
1531 * a UDP packet of 1473 bytes. The packet will be
1532 * fragmented over two IP datagrams, the latter
1533 * containing only one byte of data. The 82550 will
1534 * botch the header checksum on the 1-byte fragment.
1535 * As long as the datagram contains 4 or more bytes
1536 * of data, you're ok.
1538 * The following code attempts to work around this
1539 * problem: if the datagram is less than 38 bytes
1540 * in size (14 bytes ether header, 20 bytes IP header,
1541 * plus 4 bytes of data), we punt and compute the IP
1542 * header checksum by hand. This workaround doesn't
1543 * work very well, however, since it can be fooled
1544 * by things like VLAN tags and IP options that make
1545 * the header sizes/offsets vary.
1548 if (m->m_pkthdr.csum_flags & CSUM_IP) {
1549 if (m->m_pkthdr.len < 38) {
1551 m->m_data += ETHER_HDR_LEN;
1552 ip = mtod(m, struct ip *);
1553 ip->ip_sum = in_cksum(m, ip->ip_hl << 2);
1554 m->m_data -= ETHER_HDR_LEN;
1555 m->m_pkthdr.csum_flags &= ~CSUM_IP;
1557 txp->tx_cb->ipcb_ip_activation_high =
1558 FXP_IPCB_HARDWAREPARSING_ENABLE;
1559 txp->tx_cb->ipcb_ip_schedule |=
1560 FXP_IPCB_IP_CHECKSUM_ENABLE;
1566 error = bus_dmamap_load_mbuf_sg(sc->fxp_txmtag, txp->tx_map, *m_head,
1568 if (error == EFBIG) {
1569 m = m_collapse(*m_head, M_NOWAIT, sc->maxtxseg);
1576 error = bus_dmamap_load_mbuf_sg(sc->fxp_txmtag, txp->tx_map,
1577 *m_head, segs, &nseg, 0);
1583 } else if (error != 0)
1591 KASSERT(nseg <= sc->maxtxseg, ("too many DMA segments"));
1592 bus_dmamap_sync(sc->fxp_txmtag, txp->tx_map, BUS_DMASYNC_PREWRITE);
1595 for (i = 0; i < nseg; i++) {
1597 * If this is an 82550/82551, then we're using extended
1598 * TxCBs _and_ we're using checksum offload. This means
1599 * that the TxCB is really an IPCB. One major difference
1600 * between the two is that with plain extended TxCBs,
1601 * the bottom half of the TxCB contains two entries from
1602 * the TBD array, whereas IPCBs contain just one entry:
1603 * one entry (8 bytes) has been sacrificed for the TCP/IP
1604 * checksum offload control bits. So to make things work
1605 * right, we have to start filling in the TBD array
1606 * starting from a different place depending on whether
1607 * the chip is an 82550/82551 or not.
1609 if (sc->flags & FXP_FLAG_EXT_RFA) {
1610 cbp->tbd[i + 1].tb_addr = htole32(segs[i].ds_addr);
1611 cbp->tbd[i + 1].tb_size = htole32(segs[i].ds_len);
1613 cbp->tbd[i].tb_addr = htole32(segs[i].ds_addr);
1614 cbp->tbd[i].tb_size = htole32(segs[i].ds_len);
1617 if (sc->flags & FXP_FLAG_EXT_RFA) {
1618 /* Configure dynamic TBD for 82550/82551. */
1619 cbp->tbd_number = 0xFF;
1620 cbp->tbd[nseg].tb_size |= htole32(0x8000);
1622 cbp->tbd_number = nseg;
1623 /* Configure TSO. */
1624 if (m->m_pkthdr.csum_flags & CSUM_TSO) {
1625 cbp->tbdtso.tb_size = htole32(m->m_pkthdr.tso_segsz << 16);
1626 cbp->tbd[1].tb_size |= htole32(tcp_payload << 16);
1627 cbp->ipcb_ip_schedule |= FXP_IPCB_LARGESEND_ENABLE |
1628 FXP_IPCB_IP_CHECKSUM_ENABLE |
1629 FXP_IPCB_TCP_PACKET |
1630 FXP_IPCB_TCPUDP_CHECKSUM_ENABLE;
1632 /* Configure VLAN hardware tag insertion. */
1633 if ((m->m_flags & M_VLANTAG) != 0) {
1634 cbp->ipcb_vlan_id = htons(m->m_pkthdr.ether_vtag);
1635 txp->tx_cb->ipcb_ip_activation_high |=
1636 FXP_IPCB_INSERTVLAN_ENABLE;
1640 txp->tx_cb->cb_status = 0;
1641 txp->tx_cb->byte_count = 0;
1642 if (sc->tx_queued != FXP_CXINT_THRESH - 1)
1643 txp->tx_cb->cb_command =
1644 htole16(sc->tx_cmd | FXP_CB_COMMAND_SF |
1647 txp->tx_cb->cb_command =
1648 htole16(sc->tx_cmd | FXP_CB_COMMAND_SF |
1649 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I);
1650 if ((m->m_pkthdr.csum_flags & CSUM_TSO) == 0)
1651 txp->tx_cb->tx_threshold = tx_threshold;
1654 * Advance the end of list forward.
1656 sc->fxp_desc.tx_last->tx_cb->cb_command &= htole16(~FXP_CB_COMMAND_S);
1657 sc->fxp_desc.tx_last = txp;
1660 * Advance the beginning of the list forward if there are
1661 * no other packets queued (when nothing is queued, tx_first
1662 * sits on the last TxCB that was sent out).
1664 if (sc->tx_queued == 0)
1665 sc->fxp_desc.tx_first = txp;
1672 #ifdef DEVICE_POLLING
1673 static poll_handler_t fxp_poll;
1676 fxp_poll(if_t ifp, enum poll_cmd cmd, int count)
1678 struct fxp_softc *sc = if_getsoftc(ifp);
1683 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) {
1688 statack = FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA |
1690 if (cmd == POLL_AND_CHECK_STATUS) {
1693 tmp = CSR_READ_1(sc, FXP_CSR_SCB_STATACK);
1694 if (tmp == 0xff || tmp == 0) {
1696 return (rx_npkts); /* nothing to do */
1699 /* ack what we can */
1701 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, tmp);
1704 rx_npkts = fxp_intr_body(sc, ifp, statack, count);
1708 #endif /* DEVICE_POLLING */
1711 * Process interface interrupts.
1716 struct fxp_softc *sc = xsc;
1721 if (sc->suspended) {
1726 #ifdef DEVICE_POLLING
1727 if (if_getcapenable(ifp) & IFCAP_POLLING) {
1732 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) {
1734 * It should not be possible to have all bits set; the
1735 * FXP_SCB_INTR_SWI bit always returns 0 on a read. If
1736 * all bits are set, this may indicate that the card has
1737 * been physically ejected, so ignore it.
1739 if (statack == 0xff) {
1745 * First ACK all the interrupts in this pass.
1747 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack);
1748 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0)
1749 fxp_intr_body(sc, ifp, statack, -1);
1755 fxp_txeof(struct fxp_softc *sc)
1761 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map,
1762 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1763 for (txp = sc->fxp_desc.tx_first; sc->tx_queued &&
1764 (le16toh(txp->tx_cb->cb_status) & FXP_CB_STATUS_C) != 0;
1765 txp = txp->tx_next) {
1766 if (txp->tx_mbuf != NULL) {
1767 bus_dmamap_sync(sc->fxp_txmtag, txp->tx_map,
1768 BUS_DMASYNC_POSTWRITE);
1769 bus_dmamap_unload(sc->fxp_txmtag, txp->tx_map);
1770 m_freem(txp->tx_mbuf);
1771 txp->tx_mbuf = NULL;
1772 /* clear this to reset csum offload bits */
1773 txp->tx_cb->tbd[0].tb_addr = 0;
1776 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
1778 sc->fxp_desc.tx_first = txp;
1779 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map,
1780 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1781 if (sc->tx_queued == 0)
1782 sc->watchdog_timer = 0;
1786 fxp_rxcsum(struct fxp_softc *sc, if_t ifp, struct mbuf *m,
1787 uint16_t status, int pos)
1789 struct ether_header *eh;
1792 int32_t hlen, len, pktlen, temp32;
1793 uint16_t csum, *opts;
1795 if ((sc->flags & FXP_FLAG_82559_RXCSUM) == 0) {
1796 if ((status & FXP_RFA_STATUS_PARSE) != 0) {
1797 if (status & FXP_RFDX_CS_IP_CSUM_BIT_VALID)
1798 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
1799 if (status & FXP_RFDX_CS_IP_CSUM_VALID)
1800 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1801 if ((status & FXP_RFDX_CS_TCPUDP_CSUM_BIT_VALID) &&
1802 (status & FXP_RFDX_CS_TCPUDP_CSUM_VALID)) {
1803 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
1805 m->m_pkthdr.csum_data = 0xffff;
1811 pktlen = m->m_pkthdr.len;
1812 if (pktlen < sizeof(struct ether_header) + sizeof(struct ip))
1814 eh = mtod(m, struct ether_header *);
1815 if (eh->ether_type != htons(ETHERTYPE_IP))
1817 ip = (struct ip *)(eh + 1);
1818 if (ip->ip_v != IPVERSION)
1821 hlen = ip->ip_hl << 2;
1822 pktlen -= sizeof(struct ether_header);
1823 if (hlen < sizeof(struct ip))
1825 if (ntohs(ip->ip_len) < hlen)
1827 if (ntohs(ip->ip_len) != pktlen)
1829 if (ip->ip_off & htons(IP_MF | IP_OFFMASK))
1830 return; /* can't handle fragmented packet */
1834 if (pktlen < (hlen + sizeof(struct tcphdr)))
1838 if (pktlen < (hlen + sizeof(struct udphdr)))
1840 uh = (struct udphdr *)((caddr_t)ip + hlen);
1841 if (uh->uh_sum == 0)
1842 return; /* no checksum */
1847 /* Extract computed checksum. */
1848 csum = be16dec(mtod(m, char *) + pos);
1849 /* checksum fixup for IP options */
1850 len = hlen - sizeof(struct ip);
1852 opts = (uint16_t *)(ip + 1);
1853 for (; len > 0; len -= sizeof(uint16_t), opts++) {
1854 temp32 = csum - *opts;
1855 temp32 = (temp32 >> 16) + (temp32 & 65535);
1856 csum = temp32 & 65535;
1859 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID;
1860 m->m_pkthdr.csum_data = csum;
1864 fxp_intr_body(struct fxp_softc *sc, if_t ifp, uint8_t statack,
1869 struct fxp_rfa *rfa;
1870 int rnr = (statack & FXP_SCB_STATACK_RNR) ? 1 : 0;
1875 FXP_LOCK_ASSERT(sc, MA_OWNED);
1879 #ifdef DEVICE_POLLING
1880 /* Pick up a deferred RNR condition if `count' ran out last time. */
1881 if (sc->flags & FXP_FLAG_DEFERRED_RNR) {
1882 sc->flags &= ~FXP_FLAG_DEFERRED_RNR;
1888 * Free any finished transmit mbuf chains.
1890 * Handle the CNA event likt a CXTNO event. It used to
1891 * be that this event (control unit not ready) was not
1892 * encountered, but it is now with the SMPng modifications.
1893 * The exact sequence of events that occur when the interface
1894 * is brought up are different now, and if this event
1895 * goes unhandled, the configuration/rxfilter setup sequence
1896 * can stall for several seconds. The result is that no
1897 * packets go out onto the wire for about 5 to 10 seconds
1898 * after the interface is ifconfig'ed for the first time.
1900 if (statack & (FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA))
1904 * Try to start more packets transmitting.
1906 if (!if_sendq_empty(ifp))
1907 fxp_start_body(ifp);
1910 * Just return if nothing happened on the receive side.
1912 if (!rnr && (statack & FXP_SCB_STATACK_FR) == 0)
1916 * Process receiver interrupts. If a no-resource (RNR)
1917 * condition exists, get whatever packets we can and
1918 * re-start the receiver.
1920 * When using polling, we do not process the list to completion,
1921 * so when we get an RNR interrupt we must defer the restart
1922 * until we hit the last buffer with the C bit set.
1923 * If we run out of cycles and rfa_headm has the C bit set,
1924 * record the pending RNR in the FXP_FLAG_DEFERRED_RNR flag so
1925 * that the info will be used in the subsequent polling cycle.
1928 rxp = sc->fxp_desc.rx_head;
1930 rfa = (struct fxp_rfa *)(m->m_ext.ext_buf +
1931 RFA_ALIGNMENT_FUDGE);
1932 bus_dmamap_sync(sc->fxp_rxmtag, rxp->rx_map,
1933 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1935 #ifdef DEVICE_POLLING /* loop at most count times if count >=0 */
1936 if (count >= 0 && count-- == 0) {
1938 /* Defer RNR processing until the next time. */
1939 sc->flags |= FXP_FLAG_DEFERRED_RNR;
1944 #endif /* DEVICE_POLLING */
1946 status = le16toh(rfa->rfa_status);
1947 if ((status & FXP_RFA_STATUS_C) == 0)
1950 if ((status & FXP_RFA_STATUS_RNR) != 0)
1953 * Advance head forward.
1955 sc->fxp_desc.rx_head = rxp->rx_next;
1958 * Add a new buffer to the receive chain.
1959 * If this fails, the old buffer is recycled
1962 if (fxp_new_rfabuf(sc, rxp) == 0) {
1966 * Fetch packet length (the top 2 bits of
1967 * actual_size are flags set by the controller
1968 * upon completion), and drop the packet in case
1969 * of bogus length or CRC errors.
1971 total_len = le16toh(rfa->actual_size) & 0x3fff;
1972 if ((sc->flags & FXP_FLAG_82559_RXCSUM) != 0 &&
1973 (if_getcapenable(ifp) & IFCAP_RXCSUM) != 0) {
1974 /* Adjust for appended checksum bytes. */
1977 if (total_len < (int)sizeof(struct ether_header) ||
1978 total_len > (MCLBYTES - RFA_ALIGNMENT_FUDGE -
1980 status & (FXP_RFA_STATUS_CRC |
1981 FXP_RFA_STATUS_ALIGN | FXP_RFA_STATUS_OVERRUN)) {
1983 fxp_add_rfabuf(sc, rxp);
1987 m->m_pkthdr.len = m->m_len = total_len;
1988 if_setrcvif(m, ifp);
1990 /* Do IP checksum checking. */
1991 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0)
1992 fxp_rxcsum(sc, ifp, m, status, total_len);
1993 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0 &&
1994 (status & FXP_RFA_STATUS_VLAN) != 0) {
1995 m->m_pkthdr.ether_vtag =
1996 ntohs(rfa->rfax_vlan_id);
1997 m->m_flags |= M_VLANTAG;
2000 * Drop locks before calling if_input() since it
2001 * may re-enter fxp_start() in the netisr case.
2002 * This would result in a lock reversal. Better
2003 * performance might be obtained by chaining all
2004 * packets received, dropping the lock, and then
2005 * calling if_input() on each one.
2011 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0)
2014 /* Reuse RFA and loaded DMA map. */
2015 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
2016 fxp_discard_rfabuf(sc, rxp);
2018 fxp_add_rfabuf(sc, rxp);
2022 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL,
2023 sc->fxp_desc.rx_head->rx_addr);
2024 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START);
2030 fxp_update_stats(struct fxp_softc *sc)
2033 struct fxp_stats *sp = sc->fxp_stats;
2034 struct fxp_hwstats *hsp;
2037 FXP_LOCK_ASSERT(sc, MA_OWNED);
2039 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap,
2040 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2041 /* Update statistical counters. */
2042 if (sc->revision >= FXP_REV_82559_A0)
2043 status = &sp->completion_status;
2044 else if (sc->revision >= FXP_REV_82558_A4)
2045 status = (uint32_t *)&sp->tx_tco;
2047 status = &sp->tx_pause;
2048 if (*status == htole32(FXP_STATS_DR_COMPLETE)) {
2049 hsp = &sc->fxp_hwstats;
2050 hsp->tx_good += le32toh(sp->tx_good);
2051 hsp->tx_maxcols += le32toh(sp->tx_maxcols);
2052 hsp->tx_latecols += le32toh(sp->tx_latecols);
2053 hsp->tx_underruns += le32toh(sp->tx_underruns);
2054 hsp->tx_lostcrs += le32toh(sp->tx_lostcrs);
2055 hsp->tx_deffered += le32toh(sp->tx_deffered);
2056 hsp->tx_single_collisions += le32toh(sp->tx_single_collisions);
2057 hsp->tx_multiple_collisions +=
2058 le32toh(sp->tx_multiple_collisions);
2059 hsp->tx_total_collisions += le32toh(sp->tx_total_collisions);
2060 hsp->rx_good += le32toh(sp->rx_good);
2061 hsp->rx_crc_errors += le32toh(sp->rx_crc_errors);
2062 hsp->rx_alignment_errors += le32toh(sp->rx_alignment_errors);
2063 hsp->rx_rnr_errors += le32toh(sp->rx_rnr_errors);
2064 hsp->rx_overrun_errors += le32toh(sp->rx_overrun_errors);
2065 hsp->rx_cdt_errors += le32toh(sp->rx_cdt_errors);
2066 hsp->rx_shortframes += le32toh(sp->rx_shortframes);
2067 hsp->tx_pause += le32toh(sp->tx_pause);
2068 hsp->rx_pause += le32toh(sp->rx_pause);
2069 hsp->rx_controls += le32toh(sp->rx_controls);
2070 hsp->tx_tco += le16toh(sp->tx_tco);
2071 hsp->rx_tco += le16toh(sp->rx_tco);
2073 if_inc_counter(ifp, IFCOUNTER_OPACKETS, le32toh(sp->tx_good));
2074 if_inc_counter(ifp, IFCOUNTER_COLLISIONS,
2075 le32toh(sp->tx_total_collisions));
2077 if_inc_counter(ifp, IFCOUNTER_IPACKETS,
2078 le32toh(sp->rx_good));
2079 sc->rx_idle_secs = 0;
2080 } else if (sc->flags & FXP_FLAG_RXBUG) {
2082 * Receiver's been idle for another second.
2086 if_inc_counter(ifp, IFCOUNTER_IERRORS,
2087 le32toh(sp->rx_crc_errors) +
2088 le32toh(sp->rx_alignment_errors) +
2089 le32toh(sp->rx_rnr_errors) +
2090 le32toh(sp->rx_overrun_errors));
2092 * If any transmit underruns occurred, bump up the transmit
2093 * threshold by another 512 bytes (64 * 8).
2095 if (sp->tx_underruns) {
2096 if_inc_counter(ifp, IFCOUNTER_OERRORS,
2097 le32toh(sp->tx_underruns));
2098 if (tx_threshold < 192)
2102 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap,
2103 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2108 * Update packet in/out/collision statistics. The i82557 doesn't
2109 * allow you to access these counters without doing a fairly
2110 * expensive DMA to get _all_ of the statistics it maintains, so
2111 * we do this operation here only once per second. The statistics
2112 * counters in the kernel are updated from the previous dump-stats
2113 * DMA and then a new dump-stats DMA is started. The on-chip
2114 * counters are zeroed when the DMA completes. If we can't start
2115 * the DMA immediately, we don't wait - we just prepare to read
2116 * them again next time.
2121 struct fxp_softc *sc = xsc;
2124 FXP_LOCK_ASSERT(sc, MA_OWNED);
2126 /* Update statistical counters. */
2127 fxp_update_stats(sc);
2130 * Release any xmit buffers that have completed DMA. This isn't
2131 * strictly necessary to do here, but it's advantagous for mbufs
2132 * with external storage to be released in a timely manner rather
2133 * than being defered for a potentially long time. This limits
2134 * the delay to a maximum of one second.
2139 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds,
2140 * then assume the receiver has locked up and attempt to clear
2141 * the condition by reprogramming the multicast filter. This is
2142 * a work-around for a bug in the 82557 where the receiver locks
2143 * up if it gets certain types of garbage in the synchronization
2144 * bits prior to the packet header. This bug is supposed to only
2145 * occur in 10Mbps mode, but has been seen to occur in 100Mbps
2146 * mode as well (perhaps due to a 10/100 speed transition).
2148 if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) {
2149 sc->rx_idle_secs = 0;
2150 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) {
2151 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
2152 fxp_init_body(sc, 1);
2157 * If there is no pending command, start another stats
2158 * dump. Otherwise punt for now.
2160 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) {
2162 * Start another stats dump.
2164 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET);
2166 if (sc->miibus != NULL)
2167 mii_tick(device_get_softc(sc->miibus));
2170 * Check that chip hasn't hung.
2175 * Schedule another timeout one second from now.
2177 callout_reset(&sc->stat_ch, hz, fxp_tick, sc);
2181 * Stop the interface. Cancels the statistics updater and resets
2185 fxp_stop(struct fxp_softc *sc)
2191 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE));
2192 sc->watchdog_timer = 0;
2195 * Cancel stats updater.
2197 callout_stop(&sc->stat_ch);
2200 * Preserve PCI configuration, configure, IA/multicast
2201 * setup and put RU and CU into idle state.
2203 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET);
2205 /* Disable interrupts. */
2206 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE);
2208 fxp_update_stats(sc);
2211 * Release any xmit buffers.
2213 txp = sc->fxp_desc.tx_list;
2214 for (i = 0; i < FXP_NTXCB; i++) {
2215 if (txp[i].tx_mbuf != NULL) {
2216 bus_dmamap_sync(sc->fxp_txmtag, txp[i].tx_map,
2217 BUS_DMASYNC_POSTWRITE);
2218 bus_dmamap_unload(sc->fxp_txmtag, txp[i].tx_map);
2219 m_freem(txp[i].tx_mbuf);
2220 txp[i].tx_mbuf = NULL;
2221 /* clear this to reset csum offload bits */
2222 txp[i].tx_cb->tbd[0].tb_addr = 0;
2225 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map,
2226 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2231 * Watchdog/transmission transmit timeout handler. Called when a
2232 * transmission is started on the interface, but no interrupt is
2233 * received before the timeout. This usually indicates that the
2234 * card has wedged for some reason.
2237 fxp_watchdog(struct fxp_softc *sc)
2241 FXP_LOCK_ASSERT(sc, MA_OWNED);
2243 if (sc->watchdog_timer == 0 || --sc->watchdog_timer)
2246 device_printf(sc->dev, "device timeout\n");
2247 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
2249 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
2250 fxp_init_body(sc, 1);
2254 * Acquire locks and then call the real initialization function. This
2255 * is necessary because ether_ioctl() calls if_init() and this would
2256 * result in mutex recursion if the mutex was held.
2261 struct fxp_softc *sc = xsc;
2264 fxp_init_body(sc, 1);
2269 * Perform device initialization. This routine must be called with the
2273 fxp_init_body(struct fxp_softc *sc, int setmedia)
2276 struct mii_data *mii;
2277 struct fxp_cb_config *cbp;
2278 struct fxp_cb_ias *cb_ias;
2279 struct fxp_cb_tx *tcbp;
2283 FXP_LOCK_ASSERT(sc, MA_OWNED);
2285 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING)
2289 * Cancel any pending I/O
2294 * Issue software reset, which also unloads the microcode.
2296 sc->flags &= ~FXP_FLAG_UCODE;
2297 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET);
2300 prm = (if_getflags(ifp) & IFF_PROMISC) ? 1 : 0;
2303 * Initialize base of CBL and RFA memory. Loading with zero
2304 * sets it up for regular linear addressing.
2306 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0);
2307 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE);
2310 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE);
2313 * Initialize base of dump-stats buffer.
2316 bzero(sc->fxp_stats, sizeof(struct fxp_stats));
2317 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap,
2318 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2319 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->stats_addr);
2320 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR);
2323 * Attempt to load microcode if requested.
2324 * For ICH based controllers do not load microcode.
2326 if (sc->ident->ich == 0) {
2327 if (if_getflags(ifp) & IFF_LINK0 &&
2328 (sc->flags & FXP_FLAG_UCODE) == 0)
2333 * Set IFF_ALLMULTI status. It's needed in configure action
2339 * We temporarily use memory that contains the TxCB list to
2340 * construct the config CB. The TxCB list memory is rebuilt
2343 cbp = (struct fxp_cb_config *)sc->fxp_desc.cbl_list;
2346 * This bcopy is kind of disgusting, but there are a bunch of must be
2347 * zero and must be one bits in this structure and this is the easiest
2348 * way to initialize them all to proper values.
2350 bcopy(fxp_cb_config_template, cbp, sizeof(fxp_cb_config_template));
2353 cbp->cb_command = htole16(FXP_CB_COMMAND_CONFIG |
2355 cbp->link_addr = 0xffffffff; /* (no) next command */
2356 cbp->byte_count = sc->flags & FXP_FLAG_EXT_RFA ? 32 : 22;
2357 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */
2358 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */
2359 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */
2360 cbp->mwi_enable = sc->flags & FXP_FLAG_MWI_ENABLE ? 1 : 0;
2361 cbp->type_enable = 0; /* actually reserved */
2362 cbp->read_align_en = sc->flags & FXP_FLAG_READ_ALIGN ? 1 : 0;
2363 cbp->end_wr_on_cl = sc->flags & FXP_FLAG_WRITE_ALIGN ? 1 : 0;
2364 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */
2365 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */
2366 cbp->dma_mbce = 0; /* (disable) dma max counters */
2367 cbp->late_scb = 0; /* (don't) defer SCB update */
2368 cbp->direct_dma_dis = 1; /* disable direct rcv dma mode */
2369 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */
2370 cbp->ci_int = 1; /* interrupt on CU idle */
2371 cbp->ext_txcb_dis = sc->flags & FXP_FLAG_EXT_TXCB ? 0 : 1;
2372 cbp->ext_stats_dis = 1; /* disable extended counters */
2373 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */
2374 cbp->save_bf = sc->flags & FXP_FLAG_SAVE_BAD ? 1 : prm;
2375 cbp->disc_short_rx = !prm; /* discard short packets */
2376 cbp->underrun_retry = 1; /* retry mode (once) on DMA underrun */
2377 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */
2378 cbp->dyn_tbd = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0;
2379 cbp->ext_rfa = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0;
2380 cbp->mediatype = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 0 : 1;
2381 cbp->csma_dis = 0; /* (don't) disable link */
2382 cbp->tcp_udp_cksum = ((sc->flags & FXP_FLAG_82559_RXCSUM) != 0 &&
2383 (if_getcapenable(ifp) & IFCAP_RXCSUM) != 0) ? 1 : 0;
2384 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */
2385 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */
2386 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */
2387 cbp->mc_wake_en = 0; /* (don't) enable PME# on mcmatch */
2388 cbp->nsai = 1; /* (don't) disable source addr insert */
2389 cbp->preamble_length = 2; /* (7 byte) preamble */
2390 cbp->loopback = 0; /* (don't) loopback */
2391 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */
2392 cbp->linear_pri_mode = 0; /* (wait after xmit only) */
2393 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */
2394 cbp->promiscuous = prm; /* promiscuous mode */
2395 cbp->bcast_disable = 0; /* (don't) disable broadcasts */
2396 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/
2397 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */
2398 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */
2399 cbp->crscdt = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 1 : 0;
2401 cbp->stripping = !prm; /* truncate rx packet to byte count */
2402 cbp->padding = 1; /* (do) pad short tx packets */
2403 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */
2404 cbp->long_rx_en = sc->flags & FXP_FLAG_LONG_PKT_EN ? 1 : 0;
2405 cbp->ia_wake_en = 0; /* (don't) wake up on address match */
2406 cbp->magic_pkt_dis = sc->flags & FXP_FLAG_WOL ? 0 : 1;
2407 cbp->force_fdx = 0; /* (don't) force full duplex */
2408 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */
2409 cbp->multi_ia = 0; /* (don't) accept multiple IAs */
2410 cbp->mc_all = if_getflags(ifp) & IFF_ALLMULTI ? 1 : prm;
2411 cbp->gamla_rx = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0;
2412 cbp->vlan_strip_en = ((sc->flags & FXP_FLAG_EXT_RFA) != 0 &&
2413 (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0) ? 1 : 0;
2415 if (sc->revision == FXP_REV_82557) {
2417 * The 82557 has no hardware flow control, the values
2418 * below are the defaults for the chip.
2420 cbp->fc_delay_lsb = 0;
2421 cbp->fc_delay_msb = 0x40;
2422 cbp->pri_fc_thresh = 3;
2424 cbp->rx_fc_restop = 0;
2425 cbp->rx_fc_restart = 0;
2427 cbp->pri_fc_loc = 1;
2429 /* Set pause RX FIFO threshold to 1KB. */
2430 CSR_WRITE_1(sc, FXP_CSR_FC_THRESH, 1);
2431 /* Set pause time. */
2432 cbp->fc_delay_lsb = 0xff;
2433 cbp->fc_delay_msb = 0xff;
2434 cbp->pri_fc_thresh = 3;
2435 mii = device_get_softc(sc->miibus);
2436 if ((IFM_OPTIONS(mii->mii_media_active) &
2437 IFM_ETH_TXPAUSE) != 0)
2438 /* enable transmit FC */
2441 /* disable transmit FC */
2443 if ((IFM_OPTIONS(mii->mii_media_active) &
2444 IFM_ETH_RXPAUSE) != 0) {
2445 /* enable FC restart/restop frames */
2446 cbp->rx_fc_restart = 1;
2447 cbp->rx_fc_restop = 1;
2449 /* disable FC restart/restop frames */
2450 cbp->rx_fc_restart = 0;
2451 cbp->rx_fc_restop = 0;
2453 cbp->fc_filter = !prm; /* drop FC frames to host */
2454 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */
2457 /* Enable 82558 and 82559 extended statistics functionality. */
2458 if (sc->revision >= FXP_REV_82558_A4) {
2459 if (sc->revision >= FXP_REV_82559_A0) {
2461 * Extend configuration table size to 32
2462 * to include TCO configuration.
2464 cbp->byte_count = 32;
2465 cbp->ext_stats_dis = 1;
2466 /* Enable TCO stats. */
2467 cbp->tno_int_or_tco_en = 1;
2470 cbp->ext_stats_dis = 0;
2474 * Start the config command/DMA.
2477 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map,
2478 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2479 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr);
2480 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
2481 /* ...and wait for it to complete. */
2482 fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map);
2485 * Now initialize the station address. Temporarily use the TxCB
2486 * memory area like we did above for the config CB.
2488 cb_ias = (struct fxp_cb_ias *)sc->fxp_desc.cbl_list;
2489 cb_ias->cb_status = 0;
2490 cb_ias->cb_command = htole16(FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL);
2491 cb_ias->link_addr = 0xffffffff;
2492 bcopy(if_getlladdr(sc->ifp), cb_ias->macaddr, ETHER_ADDR_LEN);
2495 * Start the IAS (Individual Address Setup) command/DMA.
2498 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map,
2499 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2500 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr);
2501 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
2502 /* ...and wait for it to complete. */
2503 fxp_dma_wait(sc, &cb_ias->cb_status, sc->cbl_tag, sc->cbl_map);
2506 * Initialize the multicast address list.
2511 * Initialize transmit control block (TxCB) list.
2513 txp = sc->fxp_desc.tx_list;
2514 tcbp = sc->fxp_desc.cbl_list;
2515 bzero(tcbp, FXP_TXCB_SZ);
2516 for (i = 0; i < FXP_NTXCB; i++) {
2517 txp[i].tx_mbuf = NULL;
2518 tcbp[i].cb_status = htole16(FXP_CB_STATUS_C | FXP_CB_STATUS_OK);
2519 tcbp[i].cb_command = htole16(FXP_CB_COMMAND_NOP);
2520 tcbp[i].link_addr = htole32(sc->fxp_desc.cbl_addr +
2521 (((i + 1) & FXP_TXCB_MASK) * sizeof(struct fxp_cb_tx)));
2522 if (sc->flags & FXP_FLAG_EXT_TXCB)
2523 tcbp[i].tbd_array_addr =
2524 htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[2]));
2526 tcbp[i].tbd_array_addr =
2527 htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[0]));
2528 txp[i].tx_next = &txp[(i + 1) & FXP_TXCB_MASK];
2531 * Set the suspend flag on the first TxCB and start the control
2532 * unit. It will execute the NOP and then suspend.
2534 tcbp->cb_command = htole16(FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S);
2535 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map,
2536 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2537 sc->fxp_desc.tx_first = sc->fxp_desc.tx_last = txp;
2541 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr);
2542 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
2545 * Initialize receiver buffer area - RFA.
2548 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.rx_head->rx_addr);
2549 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START);
2551 if (sc->miibus != NULL && setmedia != 0)
2552 mii_mediachg(device_get_softc(sc->miibus));
2554 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE);
2557 * Enable interrupts.
2559 #ifdef DEVICE_POLLING
2561 * ... but only do that if we are not polling. And because (presumably)
2562 * the default is interrupts on, we need to disable them explicitly!
2564 if (if_getcapenable(ifp) & IFCAP_POLLING )
2565 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE);
2567 #endif /* DEVICE_POLLING */
2568 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0);
2571 * Start stats updater.
2573 callout_reset(&sc->stat_ch, hz, fxp_tick, sc);
2577 fxp_serial_ifmedia_upd(if_t ifp)
2584 fxp_serial_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr)
2587 ifmr->ifm_active = IFM_ETHER|IFM_MANUAL;
2591 * Change media according to request.
2594 fxp_ifmedia_upd(if_t ifp)
2596 struct fxp_softc *sc = if_getsoftc(ifp);
2597 struct mii_data *mii;
2598 struct mii_softc *miisc;
2600 mii = device_get_softc(sc->miibus);
2602 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
2610 * Notify the world which media we're using.
2613 fxp_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr)
2615 struct fxp_softc *sc = if_getsoftc(ifp);
2616 struct mii_data *mii;
2618 mii = device_get_softc(sc->miibus);
2621 ifmr->ifm_active = mii->mii_media_active;
2622 ifmr->ifm_status = mii->mii_media_status;
2627 * Add a buffer to the end of the RFA buffer list.
2628 * Return 0 if successful, 1 for failure. A failure results in
2629 * reusing the RFA buffer.
2630 * The RFA struct is stuck at the beginning of mbuf cluster and the
2631 * data pointer is fixed up to point just past it.
2634 fxp_new_rfabuf(struct fxp_softc *sc, struct fxp_rx *rxp)
2637 struct fxp_rfa *rfa;
2638 bus_dmamap_t tmp_map;
2641 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
2646 * Move the data pointer up so that the incoming data packet
2647 * will be 32-bit aligned.
2649 m->m_data += RFA_ALIGNMENT_FUDGE;
2652 * Get a pointer to the base of the mbuf cluster and move
2653 * data start past it.
2655 rfa = mtod(m, struct fxp_rfa *);
2656 m->m_data += sc->rfa_size;
2657 rfa->size = htole16(MCLBYTES - sc->rfa_size - RFA_ALIGNMENT_FUDGE);
2659 rfa->rfa_status = 0;
2660 rfa->rfa_control = htole16(FXP_RFA_CONTROL_EL);
2661 rfa->actual_size = 0;
2662 m->m_len = m->m_pkthdr.len = MCLBYTES - RFA_ALIGNMENT_FUDGE -
2666 * Initialize the rest of the RFA. Note that since the RFA
2667 * is misaligned, we cannot store values directly. We're thus
2668 * using the le32enc() function which handles endianness and
2669 * is also alignment-safe.
2671 le32enc(&rfa->link_addr, 0xffffffff);
2672 le32enc(&rfa->rbd_addr, 0xffffffff);
2674 /* Map the RFA into DMA memory. */
2675 error = bus_dmamap_load(sc->fxp_rxmtag, sc->spare_map, rfa,
2676 MCLBYTES - RFA_ALIGNMENT_FUDGE, fxp_dma_map_addr,
2677 &rxp->rx_addr, BUS_DMA_NOWAIT);
2683 if (rxp->rx_mbuf != NULL)
2684 bus_dmamap_unload(sc->fxp_rxmtag, rxp->rx_map);
2685 tmp_map = sc->spare_map;
2686 sc->spare_map = rxp->rx_map;
2687 rxp->rx_map = tmp_map;
2690 bus_dmamap_sync(sc->fxp_rxmtag, rxp->rx_map,
2691 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2696 fxp_add_rfabuf(struct fxp_softc *sc, struct fxp_rx *rxp)
2698 struct fxp_rfa *p_rfa;
2699 struct fxp_rx *p_rx;
2702 * If there are other buffers already on the list, attach this
2703 * one to the end by fixing up the tail to point to this one.
2705 if (sc->fxp_desc.rx_head != NULL) {
2706 p_rx = sc->fxp_desc.rx_tail;
2707 p_rfa = (struct fxp_rfa *)
2708 (p_rx->rx_mbuf->m_ext.ext_buf + RFA_ALIGNMENT_FUDGE);
2709 p_rx->rx_next = rxp;
2710 le32enc(&p_rfa->link_addr, rxp->rx_addr);
2711 p_rfa->rfa_control = 0;
2712 bus_dmamap_sync(sc->fxp_rxmtag, p_rx->rx_map,
2713 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2715 rxp->rx_next = NULL;
2716 sc->fxp_desc.rx_head = rxp;
2718 sc->fxp_desc.rx_tail = rxp;
2722 fxp_discard_rfabuf(struct fxp_softc *sc, struct fxp_rx *rxp)
2725 struct fxp_rfa *rfa;
2728 m->m_data = m->m_ext.ext_buf;
2730 * Move the data pointer up so that the incoming data packet
2731 * will be 32-bit aligned.
2733 m->m_data += RFA_ALIGNMENT_FUDGE;
2736 * Get a pointer to the base of the mbuf cluster and move
2737 * data start past it.
2739 rfa = mtod(m, struct fxp_rfa *);
2740 m->m_data += sc->rfa_size;
2741 rfa->size = htole16(MCLBYTES - sc->rfa_size - RFA_ALIGNMENT_FUDGE);
2743 rfa->rfa_status = 0;
2744 rfa->rfa_control = htole16(FXP_RFA_CONTROL_EL);
2745 rfa->actual_size = 0;
2748 * Initialize the rest of the RFA. Note that since the RFA
2749 * is misaligned, we cannot store values directly. We're thus
2750 * using the le32enc() function which handles endianness and
2751 * is also alignment-safe.
2753 le32enc(&rfa->link_addr, 0xffffffff);
2754 le32enc(&rfa->rbd_addr, 0xffffffff);
2756 bus_dmamap_sync(sc->fxp_rxmtag, rxp->rx_map,
2757 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2761 fxp_miibus_readreg(device_t dev, int phy, int reg)
2763 struct fxp_softc *sc = device_get_softc(dev);
2767 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL,
2768 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21));
2770 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0
2775 device_printf(dev, "fxp_miibus_readreg: timed out\n");
2777 return (value & 0xffff);
2781 fxp_miibus_writereg(device_t dev, int phy, int reg, int value)
2783 struct fxp_softc *sc = device_get_softc(dev);
2786 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL,
2787 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) |
2790 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 &&
2795 device_printf(dev, "fxp_miibus_writereg: timed out\n");
2800 fxp_miibus_statchg(device_t dev)
2802 struct fxp_softc *sc;
2803 struct mii_data *mii;
2806 sc = device_get_softc(dev);
2807 mii = device_get_softc(sc->miibus);
2809 if (mii == NULL || ifp == (void *)NULL ||
2810 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0 ||
2811 (mii->mii_media_status & (IFM_AVALID | IFM_ACTIVE)) !=
2812 (IFM_AVALID | IFM_ACTIVE))
2815 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T &&
2816 sc->flags & FXP_FLAG_CU_RESUME_BUG)
2817 sc->cu_resume_bug = 1;
2819 sc->cu_resume_bug = 0;
2821 * Call fxp_init_body in order to adjust the flow control settings.
2822 * Note that the 82557 doesn't support hardware flow control.
2824 if (sc->revision == FXP_REV_82557)
2826 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
2827 fxp_init_body(sc, 0);
2831 fxp_ioctl(if_t ifp, u_long command, caddr_t data)
2833 struct fxp_softc *sc = if_getsoftc(ifp);
2834 struct ifreq *ifr = (struct ifreq *)data;
2835 struct mii_data *mii;
2836 int flag, mask, error = 0, reinit;
2842 * If interface is marked up and not running, then start it.
2843 * If it is marked down and running, stop it.
2844 * XXX If it's up then re-initialize it. This is so flags
2845 * such as IFF_PROMISC are handled.
2847 if (if_getflags(ifp) & IFF_UP) {
2848 if (((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) &&
2849 ((if_getflags(ifp) ^ sc->if_flags) &
2850 (IFF_PROMISC | IFF_ALLMULTI | IFF_LINK0)) != 0) {
2851 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
2852 fxp_init_body(sc, 0);
2853 } else if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0)
2854 fxp_init_body(sc, 1);
2856 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0)
2859 sc->if_flags = if_getflags(ifp);
2866 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) {
2867 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
2868 fxp_init_body(sc, 0);
2875 if (sc->miibus != NULL) {
2876 mii = device_get_softc(sc->miibus);
2877 error = ifmedia_ioctl(ifp, ifr,
2878 &mii->mii_media, command);
2880 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command);
2886 mask = if_getcapenable(ifp) ^ ifr->ifr_reqcap;
2887 #ifdef DEVICE_POLLING
2888 if (mask & IFCAP_POLLING) {
2889 if (ifr->ifr_reqcap & IFCAP_POLLING) {
2890 error = ether_poll_register(fxp_poll, ifp);
2894 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL,
2895 FXP_SCB_INTR_DISABLE);
2896 if_setcapenablebit(ifp, IFCAP_POLLING, 0);
2899 error = ether_poll_deregister(ifp);
2900 /* Enable interrupts in any case */
2902 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0);
2903 if_setcapenablebit(ifp, 0, IFCAP_POLLING);
2909 if ((mask & IFCAP_TXCSUM) != 0 &&
2910 (if_getcapabilities(ifp) & IFCAP_TXCSUM) != 0) {
2911 if_togglecapenable(ifp, IFCAP_TXCSUM);
2912 if ((if_getcapenable(ifp) & IFCAP_TXCSUM) != 0)
2913 if_sethwassistbits(ifp, FXP_CSUM_FEATURES, 0);
2915 if_sethwassistbits(ifp, 0, FXP_CSUM_FEATURES);
2917 if ((mask & IFCAP_RXCSUM) != 0 &&
2918 (if_getcapabilities(ifp) & IFCAP_RXCSUM) != 0) {
2919 if_togglecapenable(ifp, IFCAP_RXCSUM);
2920 if ((sc->flags & FXP_FLAG_82559_RXCSUM) != 0)
2923 if ((mask & IFCAP_TSO4) != 0 &&
2924 (if_getcapabilities(ifp) & IFCAP_TSO4) != 0) {
2925 if_togglecapenable(ifp, IFCAP_TSO4);
2926 if ((if_getcapenable(ifp) & IFCAP_TSO4) != 0)
2927 if_sethwassistbits(ifp, CSUM_TSO, 0);
2929 if_sethwassistbits(ifp, 0, CSUM_TSO);
2931 if ((mask & IFCAP_WOL_MAGIC) != 0 &&
2932 (if_getcapabilities(ifp) & IFCAP_WOL_MAGIC) != 0)
2933 if_togglecapenable(ifp, IFCAP_WOL_MAGIC);
2934 if ((mask & IFCAP_VLAN_MTU) != 0 &&
2935 (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) != 0) {
2936 if_togglecapenable(ifp, IFCAP_VLAN_MTU);
2937 if (sc->revision != FXP_REV_82557)
2938 flag = FXP_FLAG_LONG_PKT_EN;
2939 else /* a hack to get long frames on the old chip */
2940 flag = FXP_FLAG_SAVE_BAD;
2942 if (if_getflags(ifp) & IFF_UP)
2945 if ((mask & IFCAP_VLAN_HWCSUM) != 0 &&
2946 (if_getcapabilities(ifp) & IFCAP_VLAN_HWCSUM) != 0)
2947 if_togglecapenable(ifp, IFCAP_VLAN_HWCSUM);
2948 if ((mask & IFCAP_VLAN_HWTSO) != 0 &&
2949 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTSO) != 0)
2950 if_togglecapenable(ifp, IFCAP_VLAN_HWTSO);
2951 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
2952 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTAGGING) != 0) {
2953 if_togglecapenable(ifp, IFCAP_VLAN_HWTAGGING);
2954 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) == 0)
2955 if_setcapenablebit(ifp, 0, IFCAP_VLAN_HWTSO |
2960 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) {
2961 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
2962 fxp_init_body(sc, 0);
2969 error = ether_ioctl(ifp, command, data);
2975 fxp_setup_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt)
2977 struct fxp_softc *sc = arg;
2978 struct fxp_cb_mcs *mcsp = sc->mcsp;
2980 if (mcsp->mc_cnt < MAXMCADDR)
2981 bcopy(LLADDR(sdl), mcsp->mc_addr[mcsp->mc_cnt * ETHER_ADDR_LEN],
2988 * Fill in the multicast address list and return number of entries.
2991 fxp_mc_addrs(struct fxp_softc *sc)
2993 struct fxp_cb_mcs *mcsp = sc->mcsp;
2996 if ((if_getflags(ifp) & IFF_ALLMULTI) == 0) {
2998 if_foreach_llmaddr(sc->ifp, fxp_setup_maddr, sc);
2999 if (mcsp->mc_cnt >= MAXMCADDR) {
3000 if_setflagbits(ifp, IFF_ALLMULTI, 0);
3004 mcsp->mc_cnt = htole16(mcsp->mc_cnt * ETHER_ADDR_LEN);
3008 * Program the multicast filter.
3010 * We have an artificial restriction that the multicast setup command
3011 * must be the first command in the chain, so we take steps to ensure
3012 * this. By requiring this, it allows us to keep up the performance of
3013 * the pre-initialized command ring (esp. link pointers) by not actually
3014 * inserting the mcsetup command in the ring - i.e. its link pointer
3015 * points to the TxCB ring, but the mcsetup descriptor itself is not part
3016 * of it. We then can do 'CU_START' on the mcsetup descriptor and have it
3017 * lead into the regular TxCB ring when it completes.
3020 fxp_mc_setup(struct fxp_softc *sc)
3022 struct fxp_cb_mcs *mcsp;
3025 FXP_LOCK_ASSERT(sc, MA_OWNED);
3028 mcsp->cb_status = 0;
3029 mcsp->cb_command = htole16(FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL);
3030 mcsp->link_addr = 0xffffffff;
3034 * Wait until command unit is idle. This should never be the
3035 * case when nothing is queued, but make sure anyway.
3038 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) !=
3039 FXP_SCB_CUS_IDLE && --count)
3042 device_printf(sc->dev, "command queue timeout\n");
3047 * Start the multicast setup command.
3050 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map,
3051 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3052 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->mcs_addr);
3053 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
3054 /* ...and wait for it to complete. */
3055 fxp_dma_wait(sc, &mcsp->cb_status, sc->mcs_tag, sc->mcs_map);
3058 static uint32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE;
3059 static uint32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE;
3060 static uint32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE;
3061 static uint32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE;
3062 static uint32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE;
3063 static uint32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE;
3064 static uint32_t fxp_ucode_d102e[] = D102_E_RCVBUNDLE_UCODE;
3066 #define UCODE(x) x, sizeof(x)/sizeof(uint32_t)
3068 static const struct ucode {
3072 u_short int_delay_offset;
3073 u_short bundle_max_offset;
3075 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), D101_CPUSAVER_DWORD, 0 },
3076 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), D101_CPUSAVER_DWORD, 0 },
3077 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma),
3078 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD },
3079 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s),
3080 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD },
3081 { FXP_REV_82550, UCODE(fxp_ucode_d102),
3082 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD },
3083 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c),
3084 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD },
3085 { FXP_REV_82551_F, UCODE(fxp_ucode_d102e),
3086 D102_E_CPUSAVER_DWORD, D102_E_CPUSAVER_BUNDLE_MAX_DWORD },
3087 { FXP_REV_82551_10, UCODE(fxp_ucode_d102e),
3088 D102_E_CPUSAVER_DWORD, D102_E_CPUSAVER_BUNDLE_MAX_DWORD },
3089 { 0, NULL, 0, 0, 0 }
3093 fxp_load_ucode(struct fxp_softc *sc)
3095 const struct ucode *uc;
3096 struct fxp_cb_ucode *cbp;
3099 if (sc->flags & FXP_FLAG_NO_UCODE)
3102 for (uc = ucode_table; uc->ucode != NULL; uc++)
3103 if (sc->revision == uc->revision)
3105 if (uc->ucode == NULL)
3107 cbp = (struct fxp_cb_ucode *)sc->fxp_desc.cbl_list;
3109 cbp->cb_command = htole16(FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL);
3110 cbp->link_addr = 0xffffffff; /* (no) next command */
3111 for (i = 0; i < uc->length; i++)
3112 cbp->ucode[i] = htole32(uc->ucode[i]);
3113 if (uc->int_delay_offset)
3114 *(uint16_t *)&cbp->ucode[uc->int_delay_offset] =
3115 htole16(sc->tunable_int_delay + sc->tunable_int_delay / 2);
3116 if (uc->bundle_max_offset)
3117 *(uint16_t *)&cbp->ucode[uc->bundle_max_offset] =
3118 htole16(sc->tunable_bundle_max);
3120 * Download the ucode to the chip.
3123 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map,
3124 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3125 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr);
3126 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
3127 /* ...and wait for it to complete. */
3128 fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map);
3129 device_printf(sc->dev,
3130 "Microcode loaded, int_delay: %d usec bundle_max: %d\n",
3131 sc->tunable_int_delay,
3132 uc->bundle_max_offset == 0 ? 0 : sc->tunable_bundle_max);
3133 sc->flags |= FXP_FLAG_UCODE;
3134 bzero(cbp, FXP_TXCB_SZ);
3137 #define FXP_SYSCTL_STAT_ADD(c, h, n, p, d) \
3138 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d)
3141 fxp_sysctl_node(struct fxp_softc *sc)
3143 struct sysctl_ctx_list *ctx;
3144 struct sysctl_oid_list *child, *parent;
3145 struct sysctl_oid *tree;
3146 struct fxp_hwstats *hsp;
3148 ctx = device_get_sysctl_ctx(sc->dev);
3149 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev));
3151 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_delay",
3152 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE,
3153 &sc->tunable_int_delay, 0, sysctl_hw_fxp_int_delay, "I",
3154 "FXP driver receive interrupt microcode bundling delay");
3155 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "bundle_max",
3156 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE,
3157 &sc->tunable_bundle_max, 0, sysctl_hw_fxp_bundle_max, "I",
3158 "FXP driver receive interrupt microcode bundle size limit");
3159 SYSCTL_ADD_INT(ctx, child,OID_AUTO, "rnr", CTLFLAG_RD, &sc->rnr, 0,
3163 * Pull in device tunables.
3165 sc->tunable_int_delay = TUNABLE_INT_DELAY;
3166 sc->tunable_bundle_max = TUNABLE_BUNDLE_MAX;
3167 (void) resource_int_value(device_get_name(sc->dev),
3168 device_get_unit(sc->dev), "int_delay", &sc->tunable_int_delay);
3169 (void) resource_int_value(device_get_name(sc->dev),
3170 device_get_unit(sc->dev), "bundle_max", &sc->tunable_bundle_max);
3173 hsp = &sc->fxp_hwstats;
3174 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats",
3175 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "FXP statistics");
3176 parent = SYSCTL_CHILDREN(tree);
3178 /* Rx MAC statistics. */
3179 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx",
3180 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Rx MAC statistics");
3181 child = SYSCTL_CHILDREN(tree);
3182 FXP_SYSCTL_STAT_ADD(ctx, child, "good_frames",
3183 &hsp->rx_good, "Good frames");
3184 FXP_SYSCTL_STAT_ADD(ctx, child, "crc_errors",
3185 &hsp->rx_crc_errors, "CRC errors");
3186 FXP_SYSCTL_STAT_ADD(ctx, child, "alignment_errors",
3187 &hsp->rx_alignment_errors, "Alignment errors");
3188 FXP_SYSCTL_STAT_ADD(ctx, child, "rnr_errors",
3189 &hsp->rx_rnr_errors, "RNR errors");
3190 FXP_SYSCTL_STAT_ADD(ctx, child, "overrun_errors",
3191 &hsp->rx_overrun_errors, "Overrun errors");
3192 FXP_SYSCTL_STAT_ADD(ctx, child, "cdt_errors",
3193 &hsp->rx_cdt_errors, "Collision detect errors");
3194 FXP_SYSCTL_STAT_ADD(ctx, child, "shortframes",
3195 &hsp->rx_shortframes, "Short frame errors");
3196 if (sc->revision >= FXP_REV_82558_A4) {
3197 FXP_SYSCTL_STAT_ADD(ctx, child, "pause",
3198 &hsp->rx_pause, "Pause frames");
3199 FXP_SYSCTL_STAT_ADD(ctx, child, "controls",
3200 &hsp->rx_controls, "Unsupported control frames");
3202 if (sc->revision >= FXP_REV_82559_A0)
3203 FXP_SYSCTL_STAT_ADD(ctx, child, "tco",
3204 &hsp->rx_tco, "TCO frames");
3206 /* Tx MAC statistics. */
3207 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx",
3208 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Tx MAC statistics");
3209 child = SYSCTL_CHILDREN(tree);
3210 FXP_SYSCTL_STAT_ADD(ctx, child, "good_frames",
3211 &hsp->tx_good, "Good frames");
3212 FXP_SYSCTL_STAT_ADD(ctx, child, "maxcols",
3213 &hsp->tx_maxcols, "Maximum collisions errors");
3214 FXP_SYSCTL_STAT_ADD(ctx, child, "latecols",
3215 &hsp->tx_latecols, "Late collisions errors");
3216 FXP_SYSCTL_STAT_ADD(ctx, child, "underruns",
3217 &hsp->tx_underruns, "Underrun errors");
3218 FXP_SYSCTL_STAT_ADD(ctx, child, "lostcrs",
3219 &hsp->tx_lostcrs, "Lost carrier sense");
3220 FXP_SYSCTL_STAT_ADD(ctx, child, "deffered",
3221 &hsp->tx_deffered, "Deferred");
3222 FXP_SYSCTL_STAT_ADD(ctx, child, "single_collisions",
3223 &hsp->tx_single_collisions, "Single collisions");
3224 FXP_SYSCTL_STAT_ADD(ctx, child, "multiple_collisions",
3225 &hsp->tx_multiple_collisions, "Multiple collisions");
3226 FXP_SYSCTL_STAT_ADD(ctx, child, "total_collisions",
3227 &hsp->tx_total_collisions, "Total collisions");
3228 if (sc->revision >= FXP_REV_82558_A4)
3229 FXP_SYSCTL_STAT_ADD(ctx, child, "pause",
3230 &hsp->tx_pause, "Pause frames");
3231 if (sc->revision >= FXP_REV_82559_A0)
3232 FXP_SYSCTL_STAT_ADD(ctx, child, "tco",
3233 &hsp->tx_tco, "TCO frames");
3236 #undef FXP_SYSCTL_STAT_ADD
3239 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high)
3243 value = *(int *)arg1;
3244 error = sysctl_handle_int(oidp, &value, 0, req);
3245 if (error || !req->newptr)
3247 if (value < low || value > high)
3249 *(int *)arg1 = value;
3254 * Interrupt delay is expressed in microseconds, a multiplier is used
3255 * to convert this to the appropriate clock ticks before using.
3258 sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS)
3261 return (sysctl_int_range(oidp, arg1, arg2, req, 300, 3000));
3265 sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS)
3268 return (sysctl_int_range(oidp, arg1, arg2, req, 1, 0xffff));