2 * Copyright (c) 1995, David Greenman
3 * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice unmodified, this list of conditions, and the following
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
34 * Intel EtherExpress Pro/100B PCI Fast Ethernet driver
37 #ifdef HAVE_KERNEL_OPTION_HEADERS
38 #include "opt_device_polling.h"
41 #include <sys/param.h>
42 #include <sys/systm.h>
44 #include <sys/endian.h>
45 #include <sys/kernel.h>
48 #include <sys/module.h>
49 #include <sys/mutex.h>
51 #include <sys/socket.h>
52 #include <sys/sockio.h>
53 #include <sys/sysctl.h>
56 #include <net/ethernet.h>
58 #include <net/if_var.h>
59 #include <net/if_arp.h>
60 #include <net/if_dl.h>
61 #include <net/if_media.h>
62 #include <net/if_types.h>
63 #include <net/if_vlan_var.h>
65 #include <netinet/in.h>
66 #include <netinet/in_systm.h>
67 #include <netinet/ip.h>
68 #include <netinet/tcp.h>
69 #include <netinet/udp.h>
71 #include <machine/bus.h>
72 #include <machine/in_cksum.h>
73 #include <machine/resource.h>
75 #include <dev/pci/pcivar.h>
76 #include <dev/pci/pcireg.h> /* for PCIM_CMD_xxx */
78 #include <dev/mii/mii.h>
79 #include <dev/mii/miivar.h>
81 #include <dev/fxp/if_fxpreg.h>
82 #include <dev/fxp/if_fxpvar.h>
83 #include <dev/fxp/rcvbundl.h>
85 MODULE_DEPEND(fxp, pci, 1, 1, 1);
86 MODULE_DEPEND(fxp, ether, 1, 1, 1);
87 MODULE_DEPEND(fxp, miibus, 1, 1, 1);
88 #include "miibus_if.h"
91 * NOTE! On !x86 we typically have an alignment constraint. The
92 * card DMAs the packet immediately following the RFA. However,
93 * the first thing in the packet is a 14-byte Ethernet header.
94 * This means that the packet is misaligned. To compensate,
95 * we actually offset the RFA 2 bytes into the cluster. This
96 * alignes the packet after the Ethernet header at a 32-bit
97 * boundary. HOWEVER! This means that the RFA is misaligned!
99 #define RFA_ALIGNMENT_FUDGE 2
102 * Set initial transmit threshold at 64 (512 bytes). This is
103 * increased by 64 (512 bytes) at a time, to maximum of 192
104 * (1536 bytes), if an underrun occurs.
106 static int tx_threshold = 64;
109 * The configuration byte map has several undefined fields which
110 * must be one or must be zero. Set up a template for these bits.
111 * The actual configuration is performed in fxp_init_body.
113 * See struct fxp_cb_config for the bit definitions.
115 static const u_char fxp_cb_config_template[] = {
116 0x0, 0x0, /* cb_status */
117 0x0, 0x0, /* cb_command */
118 0x0, 0x0, 0x0, 0x0, /* link_addr */
154 * Claim various Intel PCI device identifiers for this driver. The
155 * sub-vendor and sub-device field are extensively used to identify
156 * particular variants, but we don't currently differentiate between
159 static const struct fxp_ident fxp_ident_table[] = {
160 { 0x8086, 0x1029, -1, 0, "Intel 82559 PCI/CardBus Pro/100" },
161 { 0x8086, 0x1030, -1, 0, "Intel 82559 Pro/100 Ethernet" },
162 { 0x8086, 0x1031, -1, 3, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" },
163 { 0x8086, 0x1032, -1, 3, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" },
164 { 0x8086, 0x1033, -1, 3, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" },
165 { 0x8086, 0x1034, -1, 3, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" },
166 { 0x8086, 0x1035, -1, 3, "Intel 82801CAM (ICH3) Pro/100 Ethernet" },
167 { 0x8086, 0x1036, -1, 3, "Intel 82801CAM (ICH3) Pro/100 Ethernet" },
168 { 0x8086, 0x1037, -1, 3, "Intel 82801CAM (ICH3) Pro/100 Ethernet" },
169 { 0x8086, 0x1038, -1, 3, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" },
170 { 0x8086, 0x1039, -1, 4, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" },
171 { 0x8086, 0x103A, -1, 4, "Intel 82801DB (ICH4) Pro/100 Ethernet" },
172 { 0x8086, 0x103B, -1, 4, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" },
173 { 0x8086, 0x103C, -1, 4, "Intel 82801DB (ICH4) Pro/100 Ethernet" },
174 { 0x8086, 0x103D, -1, 4, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" },
175 { 0x8086, 0x103E, -1, 4, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" },
176 { 0x8086, 0x1050, -1, 5, "Intel 82801BA (D865) Pro/100 VE Ethernet" },
177 { 0x8086, 0x1051, -1, 5, "Intel 82562ET (ICH5/ICH5R) Pro/100 VE Ethernet" },
178 { 0x8086, 0x1059, -1, 0, "Intel 82551QM Pro/100 M Mobile Connection" },
179 { 0x8086, 0x1064, -1, 6, "Intel 82562EZ (ICH6)" },
180 { 0x8086, 0x1065, -1, 6, "Intel 82562ET/EZ/GT/GZ PRO/100 VE Ethernet" },
181 { 0x8086, 0x1068, -1, 6, "Intel 82801FBM (ICH6-M) Pro/100 VE Ethernet" },
182 { 0x8086, 0x1069, -1, 6, "Intel 82562EM/EX/GX Pro/100 Ethernet" },
183 { 0x8086, 0x1091, -1, 7, "Intel 82562GX Pro/100 Ethernet" },
184 { 0x8086, 0x1092, -1, 7, "Intel Pro/100 VE Network Connection" },
185 { 0x8086, 0x1093, -1, 7, "Intel Pro/100 VM Network Connection" },
186 { 0x8086, 0x1094, -1, 7, "Intel Pro/100 946GZ (ICH7) Network Connection" },
187 { 0x8086, 0x1209, -1, 0, "Intel 82559ER Embedded 10/100 Ethernet" },
188 { 0x8086, 0x1229, 0x01, 0, "Intel 82557 Pro/100 Ethernet" },
189 { 0x8086, 0x1229, 0x02, 0, "Intel 82557 Pro/100 Ethernet" },
190 { 0x8086, 0x1229, 0x03, 0, "Intel 82557 Pro/100 Ethernet" },
191 { 0x8086, 0x1229, 0x04, 0, "Intel 82558 Pro/100 Ethernet" },
192 { 0x8086, 0x1229, 0x05, 0, "Intel 82558 Pro/100 Ethernet" },
193 { 0x8086, 0x1229, 0x06, 0, "Intel 82559 Pro/100 Ethernet" },
194 { 0x8086, 0x1229, 0x07, 0, "Intel 82559 Pro/100 Ethernet" },
195 { 0x8086, 0x1229, 0x08, 0, "Intel 82559 Pro/100 Ethernet" },
196 { 0x8086, 0x1229, 0x09, 0, "Intel 82559ER Pro/100 Ethernet" },
197 { 0x8086, 0x1229, 0x0c, 0, "Intel 82550 Pro/100 Ethernet" },
198 { 0x8086, 0x1229, 0x0d, 0, "Intel 82550C Pro/100 Ethernet" },
199 { 0x8086, 0x1229, 0x0e, 0, "Intel 82550 Pro/100 Ethernet" },
200 { 0x8086, 0x1229, 0x0f, 0, "Intel 82551 Pro/100 Ethernet" },
201 { 0x8086, 0x1229, 0x10, 0, "Intel 82551 Pro/100 Ethernet" },
202 { 0x8086, 0x1229, -1, 0, "Intel 82557/8/9 Pro/100 Ethernet" },
203 { 0x8086, 0x2449, -1, 2, "Intel 82801BA/CAM (ICH2/3) Pro/100 Ethernet" },
204 { 0x8086, 0x27dc, -1, 7, "Intel 82801GB (ICH7) 10/100 Ethernet" },
205 { 0, 0, -1, 0, NULL },
208 #ifdef FXP_IP_CSUM_WAR
209 #define FXP_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
211 #define FXP_CSUM_FEATURES (CSUM_TCP | CSUM_UDP)
214 static int fxp_probe(device_t dev);
215 static int fxp_attach(device_t dev);
216 static int fxp_detach(device_t dev);
217 static int fxp_shutdown(device_t dev);
218 static int fxp_suspend(device_t dev);
219 static int fxp_resume(device_t dev);
221 static const struct fxp_ident *fxp_find_ident(device_t dev);
222 static void fxp_intr(void *xsc);
223 static void fxp_rxcsum(struct fxp_softc *sc, if_t ifp,
224 struct mbuf *m, uint16_t status, int pos);
225 static int fxp_intr_body(struct fxp_softc *sc, if_t ifp,
226 uint8_t statack, int count);
227 static void fxp_init(void *xsc);
228 static void fxp_init_body(struct fxp_softc *sc, int);
229 static void fxp_tick(void *xsc);
230 static void fxp_start(if_t ifp);
231 static void fxp_start_body(if_t ifp);
232 static int fxp_encap(struct fxp_softc *sc, struct mbuf **m_head);
233 static void fxp_txeof(struct fxp_softc *sc);
234 static void fxp_stop(struct fxp_softc *sc);
235 static void fxp_release(struct fxp_softc *sc);
236 static int fxp_ioctl(if_t ifp, u_long command,
238 static void fxp_watchdog(struct fxp_softc *sc);
239 static void fxp_add_rfabuf(struct fxp_softc *sc,
241 static void fxp_discard_rfabuf(struct fxp_softc *sc,
243 static int fxp_new_rfabuf(struct fxp_softc *sc,
245 static int fxp_mc_addrs(struct fxp_softc *sc);
246 static void fxp_mc_setup(struct fxp_softc *sc);
247 static uint16_t fxp_eeprom_getword(struct fxp_softc *sc, int offset,
249 static void fxp_eeprom_putword(struct fxp_softc *sc, int offset,
251 static void fxp_autosize_eeprom(struct fxp_softc *sc);
252 static void fxp_load_eeprom(struct fxp_softc *sc);
253 static void fxp_read_eeprom(struct fxp_softc *sc, u_short *data,
254 int offset, int words);
255 static void fxp_write_eeprom(struct fxp_softc *sc, u_short *data,
256 int offset, int words);
257 static int fxp_ifmedia_upd(if_t ifp);
258 static void fxp_ifmedia_sts(if_t ifp,
259 struct ifmediareq *ifmr);
260 static int fxp_serial_ifmedia_upd(if_t ifp);
261 static void fxp_serial_ifmedia_sts(if_t ifp,
262 struct ifmediareq *ifmr);
263 static int fxp_miibus_readreg(device_t dev, int phy, int reg);
264 static int fxp_miibus_writereg(device_t dev, int phy, int reg,
266 static void fxp_miibus_statchg(device_t dev);
267 static void fxp_load_ucode(struct fxp_softc *sc);
268 static void fxp_update_stats(struct fxp_softc *sc);
269 static void fxp_sysctl_node(struct fxp_softc *sc);
270 static int sysctl_int_range(SYSCTL_HANDLER_ARGS,
272 static int sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS);
273 static int sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS);
274 static void fxp_scb_wait(struct fxp_softc *sc);
275 static void fxp_scb_cmd(struct fxp_softc *sc, int cmd);
276 static void fxp_dma_wait(struct fxp_softc *sc,
277 volatile uint16_t *status, bus_dma_tag_t dmat,
280 static device_method_t fxp_methods[] = {
281 /* Device interface */
282 DEVMETHOD(device_probe, fxp_probe),
283 DEVMETHOD(device_attach, fxp_attach),
284 DEVMETHOD(device_detach, fxp_detach),
285 DEVMETHOD(device_shutdown, fxp_shutdown),
286 DEVMETHOD(device_suspend, fxp_suspend),
287 DEVMETHOD(device_resume, fxp_resume),
290 DEVMETHOD(miibus_readreg, fxp_miibus_readreg),
291 DEVMETHOD(miibus_writereg, fxp_miibus_writereg),
292 DEVMETHOD(miibus_statchg, fxp_miibus_statchg),
297 static driver_t fxp_driver = {
300 sizeof(struct fxp_softc),
303 static devclass_t fxp_devclass;
305 DRIVER_MODULE_ORDERED(fxp, pci, fxp_driver, fxp_devclass, NULL, NULL,
307 DRIVER_MODULE(miibus, fxp, miibus_driver, miibus_devclass, NULL, NULL);
309 static struct resource_spec fxp_res_spec_mem[] = {
310 { SYS_RES_MEMORY, FXP_PCI_MMBA, RF_ACTIVE },
311 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
315 static struct resource_spec fxp_res_spec_io[] = {
316 { SYS_RES_IOPORT, FXP_PCI_IOBA, RF_ACTIVE },
317 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
322 * Wait for the previous command to be accepted (but not necessarily
326 fxp_scb_wait(struct fxp_softc *sc)
334 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i)
337 flowctl.b[0] = CSR_READ_1(sc, FXP_CSR_FC_THRESH);
338 flowctl.b[1] = CSR_READ_1(sc, FXP_CSR_FC_STATUS);
339 device_printf(sc->dev, "SCB timeout: 0x%x 0x%x 0x%x 0x%x\n",
340 CSR_READ_1(sc, FXP_CSR_SCB_COMMAND),
341 CSR_READ_1(sc, FXP_CSR_SCB_STATACK),
342 CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS), flowctl.w);
347 fxp_scb_cmd(struct fxp_softc *sc, int cmd)
350 if (cmd == FXP_SCB_COMMAND_CU_RESUME && sc->cu_resume_bug) {
351 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_CB_COMMAND_NOP);
354 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd);
358 fxp_dma_wait(struct fxp_softc *sc, volatile uint16_t *status,
359 bus_dma_tag_t dmat, bus_dmamap_t map)
363 for (i = 10000; i > 0; i--) {
365 bus_dmamap_sync(dmat, map,
366 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
367 if ((le16toh(*status) & FXP_CB_STATUS_C) != 0)
371 device_printf(sc->dev, "DMA timeout\n");
374 static const struct fxp_ident *
375 fxp_find_ident(device_t dev)
380 const struct fxp_ident *ident;
382 vendor = pci_get_vendor(dev);
383 device = pci_get_device(dev);
384 revid = pci_get_revid(dev);
385 for (ident = fxp_ident_table; ident->name != NULL; ident++) {
386 if (ident->vendor == vendor && ident->device == device &&
387 (ident->revid == revid || ident->revid == -1)) {
395 * Return identification string if this device is ours.
398 fxp_probe(device_t dev)
400 const struct fxp_ident *ident;
402 ident = fxp_find_ident(dev);
404 device_set_desc(dev, ident->name);
405 return (BUS_PROBE_DEFAULT);
411 fxp_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
418 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg));
420 *addr = segs->ds_addr;
424 fxp_attach(device_t dev)
426 struct fxp_softc *sc;
427 struct fxp_cb_tx *tcbp;
433 u_char eaddr[ETHER_ADDR_LEN];
434 int error, flags, i, pmc, prefer_iomap;
437 sc = device_get_softc(dev);
439 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
441 callout_init_mtx(&sc->stat_ch, &sc->sc_mtx, 0);
442 ifmedia_init(&sc->sc_media, 0, fxp_serial_ifmedia_upd,
443 fxp_serial_ifmedia_sts);
445 ifp = sc->ifp = if_gethandle(IFT_ETHER);
446 if (ifp == (void *)NULL) {
447 device_printf(dev, "can not if_alloc()\n");
453 * Enable bus mastering.
455 pci_enable_busmaster(dev);
458 * Figure out which we should try first - memory mapping or i/o mapping?
459 * We default to memory mapping. Then we accept an override from the
460 * command line. Then we check to see which one is enabled.
463 resource_int_value(device_get_name(dev), device_get_unit(dev),
464 "prefer_iomap", &prefer_iomap);
466 sc->fxp_spec = fxp_res_spec_io;
468 sc->fxp_spec = fxp_res_spec_mem;
470 error = bus_alloc_resources(dev, sc->fxp_spec, sc->fxp_res);
472 if (sc->fxp_spec == fxp_res_spec_mem)
473 sc->fxp_spec = fxp_res_spec_io;
475 sc->fxp_spec = fxp_res_spec_mem;
476 error = bus_alloc_resources(dev, sc->fxp_spec, sc->fxp_res);
479 device_printf(dev, "could not allocate resources\n");
485 device_printf(dev, "using %s space register mapping\n",
486 sc->fxp_spec == fxp_res_spec_mem ? "memory" : "I/O");
490 * Put CU/RU idle state and prepare full reset.
492 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET);
494 /* Full reset and disable interrupts. */
495 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET);
497 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE);
500 * Find out how large of an SEEPROM we have.
502 fxp_autosize_eeprom(sc);
506 * Find out the chip revision; lump all 82557 revs together.
508 sc->ident = fxp_find_ident(dev);
509 if (sc->ident->ich > 0) {
510 /* Assume ICH controllers are 82559. */
511 sc->revision = FXP_REV_82559_A0;
513 data = sc->eeprom[FXP_EEPROM_MAP_CNTR];
514 if ((data >> 8) == 1)
515 sc->revision = FXP_REV_82557;
517 sc->revision = pci_get_revid(dev);
521 * Check availability of WOL. 82559ER does not support WOL.
523 if (sc->revision >= FXP_REV_82558_A4 &&
524 sc->revision != FXP_REV_82559S_A) {
525 data = sc->eeprom[FXP_EEPROM_MAP_ID];
526 if ((data & 0x20) != 0 &&
527 pci_find_cap(sc->dev, PCIY_PMG, &pmc) == 0)
528 sc->flags |= FXP_FLAG_WOLCAP;
531 if (sc->revision == FXP_REV_82550_C) {
533 * 82550C with server extension requires microcode to
534 * receive fragmented UDP datagrams. However if the
535 * microcode is used for client-only featured 82550C
536 * it locks up controller.
538 data = sc->eeprom[FXP_EEPROM_MAP_COMPAT];
539 if ((data & 0x0400) == 0)
540 sc->flags |= FXP_FLAG_NO_UCODE;
543 /* Receiver lock-up workaround detection. */
544 if (sc->revision < FXP_REV_82558_A4) {
545 data = sc->eeprom[FXP_EEPROM_MAP_COMPAT];
546 if ((data & 0x03) != 0x03) {
547 sc->flags |= FXP_FLAG_RXBUG;
548 device_printf(dev, "Enabling Rx lock-up workaround\n");
553 * Determine whether we must use the 503 serial interface.
555 data = sc->eeprom[FXP_EEPROM_MAP_PRI_PHY];
556 if (sc->revision == FXP_REV_82557 && (data & FXP_PHY_DEVICE_MASK) != 0
557 && (data & FXP_PHY_SERIAL_ONLY))
558 sc->flags |= FXP_FLAG_SERIAL_MEDIA;
562 * Enable workarounds for certain chip revision deficiencies.
564 * Systems based on the ICH2/ICH2-M chip from Intel, and possibly
565 * some systems based a normal 82559 design, have a defect where
566 * the chip can cause a PCI protocol violation if it receives
567 * a CU_RESUME command when it is entering the IDLE state. The
568 * workaround is to disable Dynamic Standby Mode, so the chip never
569 * deasserts CLKRUN#, and always remains in an active state.
571 * See Intel 82801BA/82801BAM Specification Update, Errata #30.
573 if ((sc->ident->ich >= 2 && sc->ident->ich <= 3) ||
574 (sc->ident->ich == 0 && sc->revision >= FXP_REV_82559_A0)) {
575 data = sc->eeprom[FXP_EEPROM_MAP_ID];
576 if (data & 0x02) { /* STB enable */
581 "Disabling dynamic standby mode in EEPROM\n");
583 sc->eeprom[FXP_EEPROM_MAP_ID] = data;
584 fxp_write_eeprom(sc, &data, FXP_EEPROM_MAP_ID, 1);
585 device_printf(dev, "New EEPROM ID: 0x%x\n", data);
587 for (i = 0; i < (1 << sc->eeprom_size) - 1; i++)
588 cksum += sc->eeprom[i];
589 i = (1 << sc->eeprom_size) - 1;
590 cksum = 0xBABA - cksum;
591 fxp_write_eeprom(sc, &cksum, i, 1);
593 "EEPROM checksum @ 0x%x: 0x%x -> 0x%x\n",
594 i, sc->eeprom[i], cksum);
595 sc->eeprom[i] = cksum;
597 * If the user elects to continue, try the software
598 * workaround, as it is better than nothing.
600 sc->flags |= FXP_FLAG_CU_RESUME_BUG;
605 * If we are not a 82557 chip, we can enable extended features.
607 if (sc->revision != FXP_REV_82557) {
609 * If MWI is enabled in the PCI configuration, and there
610 * is a valid cacheline size (8 or 16 dwords), then tell
611 * the board to turn on MWI.
613 val = pci_read_config(dev, PCIR_COMMAND, 2);
614 if (val & PCIM_CMD_MWRICEN &&
615 pci_read_config(dev, PCIR_CACHELNSZ, 1) != 0)
616 sc->flags |= FXP_FLAG_MWI_ENABLE;
618 /* turn on the extended TxCB feature */
619 sc->flags |= FXP_FLAG_EXT_TXCB;
621 /* enable reception of long frames for VLAN */
622 sc->flags |= FXP_FLAG_LONG_PKT_EN;
624 /* a hack to get long VLAN frames on a 82557 */
625 sc->flags |= FXP_FLAG_SAVE_BAD;
628 /* For 82559 or later chips, Rx checksum offload is supported. */
629 if (sc->revision >= FXP_REV_82559_A0) {
630 /* 82559ER does not support Rx checksum offloading. */
631 if (sc->ident->device != 0x1209)
632 sc->flags |= FXP_FLAG_82559_RXCSUM;
635 * Enable use of extended RFDs and TCBs for 82550
636 * and later chips. Note: we need extended TXCB support
637 * too, but that's already enabled by the code above.
638 * Be careful to do this only on the right devices.
640 if (sc->revision == FXP_REV_82550 || sc->revision == FXP_REV_82550_C ||
641 sc->revision == FXP_REV_82551_E || sc->revision == FXP_REV_82551_F
642 || sc->revision == FXP_REV_82551_10) {
643 sc->rfa_size = sizeof (struct fxp_rfa);
644 sc->tx_cmd = FXP_CB_COMMAND_IPCBXMIT;
645 sc->flags |= FXP_FLAG_EXT_RFA;
646 /* Use extended RFA instead of 82559 checksum mode. */
647 sc->flags &= ~FXP_FLAG_82559_RXCSUM;
649 sc->rfa_size = sizeof (struct fxp_rfa) - FXP_RFAX_LEN;
650 sc->tx_cmd = FXP_CB_COMMAND_XMIT;
654 * Allocate DMA tags and DMA safe memory.
656 sc->maxtxseg = FXP_NTXSEG;
657 sc->maxsegsize = MCLBYTES;
658 if (sc->flags & FXP_FLAG_EXT_RFA) {
660 sc->maxsegsize = FXP_TSO_SEGSIZE;
662 error = bus_dma_tag_create(bus_get_dma_tag(dev), 2, 0,
663 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
664 sc->maxsegsize * sc->maxtxseg + sizeof(struct ether_vlan_header),
665 sc->maxtxseg, sc->maxsegsize, 0,
666 busdma_lock_mutex, &Giant, &sc->fxp_txmtag);
668 device_printf(dev, "could not create TX DMA tag\n");
672 error = bus_dma_tag_create(bus_get_dma_tag(dev), 2, 0,
673 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
674 MCLBYTES, 1, MCLBYTES, 0,
675 busdma_lock_mutex, &Giant, &sc->fxp_rxmtag);
677 device_printf(dev, "could not create RX DMA tag\n");
681 error = bus_dma_tag_create(bus_get_dma_tag(dev), 4, 0,
682 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
683 sizeof(struct fxp_stats), 1, sizeof(struct fxp_stats), 0,
684 busdma_lock_mutex, &Giant, &sc->fxp_stag);
686 device_printf(dev, "could not create stats DMA tag\n");
690 error = bus_dmamem_alloc(sc->fxp_stag, (void **)&sc->fxp_stats,
691 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->fxp_smap);
693 device_printf(dev, "could not allocate stats DMA memory\n");
696 error = bus_dmamap_load(sc->fxp_stag, sc->fxp_smap, sc->fxp_stats,
697 sizeof(struct fxp_stats), fxp_dma_map_addr, &sc->stats_addr,
700 device_printf(dev, "could not load the stats DMA buffer\n");
704 error = bus_dma_tag_create(bus_get_dma_tag(dev), 4, 0,
705 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
706 FXP_TXCB_SZ, 1, FXP_TXCB_SZ, 0,
707 busdma_lock_mutex, &Giant, &sc->cbl_tag);
709 device_printf(dev, "could not create TxCB DMA tag\n");
713 error = bus_dmamem_alloc(sc->cbl_tag, (void **)&sc->fxp_desc.cbl_list,
714 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->cbl_map);
716 device_printf(dev, "could not allocate TxCB DMA memory\n");
720 error = bus_dmamap_load(sc->cbl_tag, sc->cbl_map,
721 sc->fxp_desc.cbl_list, FXP_TXCB_SZ, fxp_dma_map_addr,
722 &sc->fxp_desc.cbl_addr, BUS_DMA_NOWAIT);
724 device_printf(dev, "could not load TxCB DMA buffer\n");
728 error = bus_dma_tag_create(bus_get_dma_tag(dev), 4, 0,
729 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
730 sizeof(struct fxp_cb_mcs), 1, sizeof(struct fxp_cb_mcs), 0,
731 busdma_lock_mutex, &Giant, &sc->mcs_tag);
734 "could not create multicast setup DMA tag\n");
738 error = bus_dmamem_alloc(sc->mcs_tag, (void **)&sc->mcsp,
739 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->mcs_map);
742 "could not allocate multicast setup DMA memory\n");
745 error = bus_dmamap_load(sc->mcs_tag, sc->mcs_map, sc->mcsp,
746 sizeof(struct fxp_cb_mcs), fxp_dma_map_addr, &sc->mcs_addr,
750 "can't load the multicast setup DMA buffer\n");
755 * Pre-allocate the TX DMA maps and setup the pointers to
756 * the TX command blocks.
758 txp = sc->fxp_desc.tx_list;
759 tcbp = sc->fxp_desc.cbl_list;
760 for (i = 0; i < FXP_NTXCB; i++) {
761 txp[i].tx_cb = tcbp + i;
762 error = bus_dmamap_create(sc->fxp_txmtag, 0, &txp[i].tx_map);
764 device_printf(dev, "can't create DMA map for TX\n");
768 error = bus_dmamap_create(sc->fxp_rxmtag, 0, &sc->spare_map);
770 device_printf(dev, "can't create spare DMA map\n");
775 * Pre-allocate our receive buffers.
777 sc->fxp_desc.rx_head = sc->fxp_desc.rx_tail = NULL;
778 for (i = 0; i < FXP_NRFABUFS; i++) {
779 rxp = &sc->fxp_desc.rx_list[i];
780 error = bus_dmamap_create(sc->fxp_rxmtag, 0, &rxp->rx_map);
782 device_printf(dev, "can't create DMA map for RX\n");
785 if (fxp_new_rfabuf(sc, rxp) != 0) {
789 fxp_add_rfabuf(sc, rxp);
795 eaddr[0] = sc->eeprom[FXP_EEPROM_MAP_IA0] & 0xff;
796 eaddr[1] = sc->eeprom[FXP_EEPROM_MAP_IA0] >> 8;
797 eaddr[2] = sc->eeprom[FXP_EEPROM_MAP_IA1] & 0xff;
798 eaddr[3] = sc->eeprom[FXP_EEPROM_MAP_IA1] >> 8;
799 eaddr[4] = sc->eeprom[FXP_EEPROM_MAP_IA2] & 0xff;
800 eaddr[5] = sc->eeprom[FXP_EEPROM_MAP_IA2] >> 8;
802 device_printf(dev, "PCI IDs: %04x %04x %04x %04x %04x\n",
803 pci_get_vendor(dev), pci_get_device(dev),
804 pci_get_subvendor(dev), pci_get_subdevice(dev),
806 device_printf(dev, "Dynamic Standby mode is %s\n",
807 sc->eeprom[FXP_EEPROM_MAP_ID] & 0x02 ? "enabled" :
812 * If this is only a 10Mbps device, then there is no MII, and
813 * the PHY will use a serial interface instead.
815 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter
816 * doesn't have a programming interface of any sort. The
817 * media is sensed automatically based on how the link partner
818 * is configured. This is, in essence, manual configuration.
820 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) {
821 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL);
822 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL);
825 * i82557 wedge when isolating all of their PHYs.
827 flags = MIIF_NOISOLATE;
828 if (sc->revision >= FXP_REV_82558_A4)
829 flags |= MIIF_DOPAUSE;
830 error = mii_attach(dev, &sc->miibus, ifp,
831 (ifm_change_cb_t)fxp_ifmedia_upd,
832 (ifm_stat_cb_t)fxp_ifmedia_sts, BMSR_DEFCAPMASK,
833 MII_PHY_ANY, MII_OFFSET_ANY, flags);
835 device_printf(dev, "attaching PHYs failed\n");
840 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
842 if_setinitfn(ifp, fxp_init);
843 if_setsoftc(ifp, sc);
844 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST);
845 if_setioctlfn(ifp, fxp_ioctl);
846 if_setstartfn(ifp, fxp_start);
848 if_setcapabilities(ifp, 0);
849 if_setcapenable(ifp, 0);
851 /* Enable checksum offload/TSO for 82550 or better chips */
852 if (sc->flags & FXP_FLAG_EXT_RFA) {
853 if_sethwassist(ifp, FXP_CSUM_FEATURES | CSUM_TSO);
854 if_setcapabilitiesbit(ifp, IFCAP_HWCSUM | IFCAP_TSO4, 0);
855 if_setcapenablebit(ifp, IFCAP_HWCSUM | IFCAP_TSO4, 0);
858 if (sc->flags & FXP_FLAG_82559_RXCSUM) {
859 if_setcapabilitiesbit(ifp, IFCAP_RXCSUM, 0);
860 if_setcapenablebit(ifp, IFCAP_RXCSUM, 0);
863 if (sc->flags & FXP_FLAG_WOLCAP) {
864 if_setcapabilitiesbit(ifp, IFCAP_WOL_MAGIC, 0);
865 if_setcapenablebit(ifp, IFCAP_WOL_MAGIC, 0);
868 #ifdef DEVICE_POLLING
869 /* Inform the world we support polling. */
870 if_setcapabilitiesbit(ifp, IFCAP_POLLING, 0);
874 * Attach the interface.
876 ether_ifattach(ifp, eaddr);
879 * Tell the upper layer(s) we support long frames.
880 * Must appear after the call to ether_ifattach() because
881 * ether_ifattach() sets ifi_hdrlen to the default value.
883 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header));
884 if_setcapabilitiesbit(ifp, IFCAP_VLAN_MTU, 0);
885 if_setcapenablebit(ifp, IFCAP_VLAN_MTU, 0);
886 if ((sc->flags & FXP_FLAG_EXT_RFA) != 0) {
887 if_setcapabilitiesbit(ifp, IFCAP_VLAN_HWTAGGING |
888 IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO, 0);
889 if_setcapenablebit(ifp, IFCAP_VLAN_HWTAGGING |
890 IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO, 0);
894 * Let the system queue as many packets as we have available
897 if_setsendqlen(ifp, FXP_NTXCB - 1);
898 if_setsendqready(ifp);
901 * Hook our interrupt after all initialization is complete.
903 error = bus_setup_intr(dev, sc->fxp_res[1], INTR_TYPE_NET | INTR_MPSAFE,
904 NULL, fxp_intr, sc, &sc->ih);
906 device_printf(dev, "could not setup irq\n");
907 ether_ifdetach(sc->ifp);
912 * Configure hardware to reject magic frames otherwise
913 * system will hang on recipt of magic frames.
915 if ((sc->flags & FXP_FLAG_WOLCAP) != 0) {
917 /* Clear wakeup events. */
918 CSR_WRITE_1(sc, FXP_CSR_PMDR, CSR_READ_1(sc, FXP_CSR_PMDR));
919 fxp_init_body(sc, 0);
931 * Release all resources. The softc lock should not be held and the
932 * interrupt should already be torn down.
935 fxp_release(struct fxp_softc *sc)
941 FXP_LOCK_ASSERT(sc, MA_NOTOWNED);
942 KASSERT(sc->ih == NULL,
943 ("fxp_release() called with intr handle still active"));
945 device_delete_child(sc->dev, sc->miibus);
946 bus_generic_detach(sc->dev);
947 ifmedia_removeall(&sc->sc_media);
948 if (sc->fxp_desc.cbl_list) {
949 bus_dmamap_unload(sc->cbl_tag, sc->cbl_map);
950 bus_dmamem_free(sc->cbl_tag, sc->fxp_desc.cbl_list,
954 bus_dmamap_unload(sc->fxp_stag, sc->fxp_smap);
955 bus_dmamem_free(sc->fxp_stag, sc->fxp_stats, sc->fxp_smap);
958 bus_dmamap_unload(sc->mcs_tag, sc->mcs_map);
959 bus_dmamem_free(sc->mcs_tag, sc->mcsp, sc->mcs_map);
961 bus_release_resources(sc->dev, sc->fxp_spec, sc->fxp_res);
962 if (sc->fxp_rxmtag) {
963 for (i = 0; i < FXP_NRFABUFS; i++) {
964 rxp = &sc->fxp_desc.rx_list[i];
965 if (rxp->rx_mbuf != NULL) {
966 bus_dmamap_sync(sc->fxp_rxmtag, rxp->rx_map,
967 BUS_DMASYNC_POSTREAD);
968 bus_dmamap_unload(sc->fxp_rxmtag, rxp->rx_map);
969 m_freem(rxp->rx_mbuf);
971 bus_dmamap_destroy(sc->fxp_rxmtag, rxp->rx_map);
973 bus_dmamap_destroy(sc->fxp_rxmtag, sc->spare_map);
974 bus_dma_tag_destroy(sc->fxp_rxmtag);
976 if (sc->fxp_txmtag) {
977 for (i = 0; i < FXP_NTXCB; i++) {
978 txp = &sc->fxp_desc.tx_list[i];
979 if (txp->tx_mbuf != NULL) {
980 bus_dmamap_sync(sc->fxp_txmtag, txp->tx_map,
981 BUS_DMASYNC_POSTWRITE);
982 bus_dmamap_unload(sc->fxp_txmtag, txp->tx_map);
983 m_freem(txp->tx_mbuf);
985 bus_dmamap_destroy(sc->fxp_txmtag, txp->tx_map);
987 bus_dma_tag_destroy(sc->fxp_txmtag);
990 bus_dma_tag_destroy(sc->fxp_stag);
992 bus_dma_tag_destroy(sc->cbl_tag);
994 bus_dma_tag_destroy(sc->mcs_tag);
998 mtx_destroy(&sc->sc_mtx);
1005 fxp_detach(device_t dev)
1007 struct fxp_softc *sc = device_get_softc(dev);
1009 #ifdef DEVICE_POLLING
1010 if (if_getcapenable(sc->ifp) & IFCAP_POLLING)
1011 ether_poll_deregister(sc->ifp);
1016 * Stop DMA and drop transmit queue, but disable interrupts first.
1018 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE);
1021 callout_drain(&sc->stat_ch);
1024 * Close down routes etc.
1026 ether_ifdetach(sc->ifp);
1029 * Unhook interrupt before dropping lock. This is to prevent
1030 * races with fxp_intr().
1032 bus_teardown_intr(sc->dev, sc->fxp_res[1], sc->ih);
1035 /* Release our allocated resources. */
1041 * Device shutdown routine. Called at system shutdown after sync. The
1042 * main purpose of this routine is to shut off receiver DMA so that
1043 * kernel memory doesn't get clobbered during warmboot.
1046 fxp_shutdown(device_t dev)
1050 * Make sure that DMA is disabled prior to reboot. Not doing
1051 * do could allow DMA to corrupt kernel memory during the
1052 * reboot before the driver initializes.
1054 return (fxp_suspend(dev));
1058 * Device suspend routine. Stop the interface and save some PCI
1059 * settings in case the BIOS doesn't restore them properly on
1063 fxp_suspend(device_t dev)
1065 struct fxp_softc *sc = device_get_softc(dev);
1073 if (pci_find_cap(sc->dev, PCIY_PMG, &pmc) == 0) {
1074 pmstat = pci_read_config(sc->dev, pmc + PCIR_POWER_STATUS, 2);
1075 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
1076 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) != 0) {
1078 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
1079 sc->flags |= FXP_FLAG_WOL;
1080 /* Reconfigure hardware to accept magic frames. */
1081 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
1082 fxp_init_body(sc, 0);
1084 pci_write_config(sc->dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
1095 * Device resume routine. re-enable busmastering, and restart the interface if
1099 fxp_resume(device_t dev)
1101 struct fxp_softc *sc = device_get_softc(dev);
1108 if (pci_find_cap(sc->dev, PCIY_PMG, &pmc) == 0) {
1109 sc->flags &= ~FXP_FLAG_WOL;
1110 pmstat = pci_read_config(sc->dev, pmc + PCIR_POWER_STATUS, 2);
1111 /* Disable PME and clear PME status. */
1112 pmstat &= ~PCIM_PSTAT_PMEENABLE;
1113 pci_write_config(sc->dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
1114 if ((sc->flags & FXP_FLAG_WOLCAP) != 0)
1115 CSR_WRITE_1(sc, FXP_CSR_PMDR,
1116 CSR_READ_1(sc, FXP_CSR_PMDR));
1119 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET);
1122 /* reinitialize interface if necessary */
1123 if (if_getflags(ifp) & IFF_UP)
1124 fxp_init_body(sc, 1);
1133 fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int length)
1141 for (x = 1 << (length - 1); x; x >>= 1) {
1143 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI;
1145 reg = FXP_EEPROM_EECS;
1146 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1148 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK);
1150 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1156 * Read from the serial EEPROM. Basically, you manually shift in
1157 * the read opcode (one bit at a time) and then shift in the address,
1158 * and then you shift out the data (all of this one bit at a time).
1159 * The word size is 16 bits, so you have to provide the address for
1160 * every 16 bits of data.
1163 fxp_eeprom_getword(struct fxp_softc *sc, int offset, int autosize)
1168 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
1170 * Shift in read opcode.
1172 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3);
1177 for (x = 1 << (sc->eeprom_size - 1); x; x >>= 1) {
1179 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI;
1181 reg = FXP_EEPROM_EECS;
1182 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1184 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK);
1186 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1188 reg = CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO;
1190 if (autosize && reg == 0) {
1191 sc->eeprom_size = data;
1199 reg = FXP_EEPROM_EECS;
1200 for (x = 1 << 15; x; x >>= 1) {
1201 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK);
1203 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO)
1205 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1208 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1215 fxp_eeprom_putword(struct fxp_softc *sc, int offset, uint16_t data)
1220 * Erase/write enable.
1222 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
1223 fxp_eeprom_shiftin(sc, 0x4, 3);
1224 fxp_eeprom_shiftin(sc, 0x03 << (sc->eeprom_size - 2), sc->eeprom_size);
1225 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1228 * Shift in write opcode, address, data.
1230 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
1231 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3);
1232 fxp_eeprom_shiftin(sc, offset, sc->eeprom_size);
1233 fxp_eeprom_shiftin(sc, data, 16);
1234 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1237 * Wait for EEPROM to finish up.
1239 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
1241 for (i = 0; i < 1000; i++) {
1242 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO)
1246 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1249 * Erase/write disable.
1251 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
1252 fxp_eeprom_shiftin(sc, 0x4, 3);
1253 fxp_eeprom_shiftin(sc, 0, sc->eeprom_size);
1254 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1261 * Figure out EEPROM size.
1263 * 559's can have either 64-word or 256-word EEPROMs, the 558
1264 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet
1265 * talks about the existance of 16 to 256 word EEPROMs.
1267 * The only known sizes are 64 and 256, where the 256 version is used
1268 * by CardBus cards to store CIS information.
1270 * The address is shifted in msb-to-lsb, and after the last
1271 * address-bit the EEPROM is supposed to output a `dummy zero' bit,
1272 * after which follows the actual data. We try to detect this zero, by
1273 * probing the data-out bit in the EEPROM control register just after
1274 * having shifted in a bit. If the bit is zero, we assume we've
1275 * shifted enough address bits. The data-out should be tri-state,
1276 * before this, which should translate to a logical one.
1279 fxp_autosize_eeprom(struct fxp_softc *sc)
1282 /* guess maximum size of 256 words */
1283 sc->eeprom_size = 8;
1286 (void) fxp_eeprom_getword(sc, 0, 1);
1290 fxp_read_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words)
1294 for (i = 0; i < words; i++)
1295 data[i] = fxp_eeprom_getword(sc, offset + i, 0);
1299 fxp_write_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words)
1303 for (i = 0; i < words; i++)
1304 fxp_eeprom_putword(sc, offset + i, data[i]);
1308 fxp_load_eeprom(struct fxp_softc *sc)
1313 fxp_read_eeprom(sc, sc->eeprom, 0, 1 << sc->eeprom_size);
1315 for (i = 0; i < (1 << sc->eeprom_size) - 1; i++)
1316 cksum += sc->eeprom[i];
1317 cksum = 0xBABA - cksum;
1318 if (cksum != sc->eeprom[(1 << sc->eeprom_size) - 1])
1319 device_printf(sc->dev,
1320 "EEPROM checksum mismatch! (0x%04x -> 0x%04x)\n",
1321 cksum, sc->eeprom[(1 << sc->eeprom_size) - 1]);
1325 * Grab the softc lock and call the real fxp_start_body() routine
1330 struct fxp_softc *sc = if_getsoftc(ifp);
1333 fxp_start_body(ifp);
1338 * Start packet transmission on the interface.
1339 * This routine must be called with the softc lock held, and is an
1340 * internal entry point only.
1343 fxp_start_body(if_t ifp)
1345 struct fxp_softc *sc = if_getsoftc(ifp);
1346 struct mbuf *mb_head;
1349 FXP_LOCK_ASSERT(sc, MA_OWNED);
1351 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
1355 if (sc->tx_queued > FXP_NTXCB_HIWAT)
1358 * We're finished if there is nothing more to add to the list or if
1359 * we're all filled up with buffers to transmit.
1360 * NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add
1361 * a NOP command when needed.
1364 while (!if_sendq_empty(ifp) && sc->tx_queued < FXP_NTXCB - 1) {
1367 * Grab a packet to transmit.
1369 mb_head = if_dequeue(ifp);
1370 if (mb_head == NULL)
1373 if (fxp_encap(sc, &mb_head)) {
1374 if (mb_head == NULL)
1376 if_sendq_prepend(ifp, mb_head);
1377 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0);
1381 * Pass packet to bpf if there is a listener.
1383 if_bpfmtap(ifp, mb_head);
1387 * We're finished. If we added to the list, issue a RESUME to get DMA
1388 * going again if suspended.
1391 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map,
1392 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1394 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME);
1396 * Set a 5 second timer just in case we don't hear
1397 * from the card again.
1399 sc->watchdog_timer = 5;
1404 fxp_encap(struct fxp_softc *sc, struct mbuf **m_head)
1409 struct fxp_cb_tx *cbp;
1411 bus_dma_segment_t segs[FXP_NTXSEG];
1412 int error, i, nseg, tcp_payload;
1414 FXP_LOCK_ASSERT(sc, MA_OWNED);
1420 * Get pointer to next available tx desc.
1422 txp = sc->fxp_desc.tx_last->tx_next;
1425 * A note in Appendix B of the Intel 8255x 10/100 Mbps
1426 * Ethernet Controller Family Open Source Software
1427 * Developer Manual says:
1428 * Using software parsing is only allowed with legal
1429 * TCP/IP or UDP/IP packets.
1431 * For all other datagrams, hardware parsing must
1433 * Software parsing appears to truncate ICMP and
1434 * fragmented UDP packets that contain one to three
1435 * bytes in the second (and final) mbuf of the packet.
1437 if (sc->flags & FXP_FLAG_EXT_RFA)
1438 txp->tx_cb->ipcb_ip_activation_high =
1439 FXP_IPCB_HARDWAREPARSING_ENABLE;
1442 if (m->m_pkthdr.csum_flags & CSUM_TSO) {
1444 * 82550/82551 requires ethernet/IP/TCP headers must be
1445 * contained in the first active transmit buffer.
1447 struct ether_header *eh;
1449 uint32_t ip_off, poff;
1451 if (M_WRITABLE(*m_head) == 0) {
1452 /* Get a writable copy. */
1453 m = m_dup(*m_head, M_NOWAIT);
1461 ip_off = sizeof(struct ether_header);
1462 m = m_pullup(*m_head, ip_off);
1467 eh = mtod(m, struct ether_header *);
1468 /* Check the existence of VLAN tag. */
1469 if (eh->ether_type == htons(ETHERTYPE_VLAN)) {
1470 ip_off = sizeof(struct ether_vlan_header);
1471 m = m_pullup(m, ip_off);
1477 m = m_pullup(m, ip_off + sizeof(struct ip));
1482 ip = (struct ip *)(mtod(m, char *) + ip_off);
1483 poff = ip_off + (ip->ip_hl << 2);
1484 m = m_pullup(m, poff + sizeof(struct tcphdr));
1489 tcp = (struct tcphdr *)(mtod(m, char *) + poff);
1490 m = m_pullup(m, poff + (tcp->th_off << 2));
1497 * Since 82550/82551 doesn't modify IP length and pseudo
1498 * checksum in the first frame driver should compute it.
1500 ip = (struct ip *)(mtod(m, char *) + ip_off);
1501 tcp = (struct tcphdr *)(mtod(m, char *) + poff);
1503 ip->ip_len = htons(m->m_pkthdr.tso_segsz + (ip->ip_hl << 2) +
1504 (tcp->th_off << 2));
1505 tcp->th_sum = in_pseudo(ip->ip_src.s_addr, ip->ip_dst.s_addr,
1506 htons(IPPROTO_TCP + (tcp->th_off << 2) +
1507 m->m_pkthdr.tso_segsz));
1508 /* Compute total TCP payload. */
1509 tcp_payload = m->m_pkthdr.len - ip_off - (ip->ip_hl << 2);
1510 tcp_payload -= tcp->th_off << 2;
1512 } else if (m->m_pkthdr.csum_flags & FXP_CSUM_FEATURES) {
1514 * Deal with TCP/IP checksum offload. Note that
1515 * in order for TCP checksum offload to work,
1516 * the pseudo header checksum must have already
1517 * been computed and stored in the checksum field
1518 * in the TCP header. The stack should have
1519 * already done this for us.
1521 txp->tx_cb->ipcb_ip_schedule = FXP_IPCB_TCPUDP_CHECKSUM_ENABLE;
1522 if (m->m_pkthdr.csum_flags & CSUM_TCP)
1523 txp->tx_cb->ipcb_ip_schedule |= FXP_IPCB_TCP_PACKET;
1525 #ifdef FXP_IP_CSUM_WAR
1527 * XXX The 82550 chip appears to have trouble
1528 * dealing with IP header checksums in very small
1529 * datagrams, namely fragments from 1 to 3 bytes
1530 * in size. For example, say you want to transmit
1531 * a UDP packet of 1473 bytes. The packet will be
1532 * fragmented over two IP datagrams, the latter
1533 * containing only one byte of data. The 82550 will
1534 * botch the header checksum on the 1-byte fragment.
1535 * As long as the datagram contains 4 or more bytes
1536 * of data, you're ok.
1538 * The following code attempts to work around this
1539 * problem: if the datagram is less than 38 bytes
1540 * in size (14 bytes ether header, 20 bytes IP header,
1541 * plus 4 bytes of data), we punt and compute the IP
1542 * header checksum by hand. This workaround doesn't
1543 * work very well, however, since it can be fooled
1544 * by things like VLAN tags and IP options that make
1545 * the header sizes/offsets vary.
1548 if (m->m_pkthdr.csum_flags & CSUM_IP) {
1549 if (m->m_pkthdr.len < 38) {
1551 m->m_data += ETHER_HDR_LEN;
1552 ip = mtod(m, struct ip *);
1553 ip->ip_sum = in_cksum(m, ip->ip_hl << 2);
1554 m->m_data -= ETHER_HDR_LEN;
1555 m->m_pkthdr.csum_flags &= ~CSUM_IP;
1557 txp->tx_cb->ipcb_ip_activation_high =
1558 FXP_IPCB_HARDWAREPARSING_ENABLE;
1559 txp->tx_cb->ipcb_ip_schedule |=
1560 FXP_IPCB_IP_CHECKSUM_ENABLE;
1566 error = bus_dmamap_load_mbuf_sg(sc->fxp_txmtag, txp->tx_map, *m_head,
1568 if (error == EFBIG) {
1569 m = m_collapse(*m_head, M_NOWAIT, sc->maxtxseg);
1576 error = bus_dmamap_load_mbuf_sg(sc->fxp_txmtag, txp->tx_map,
1577 *m_head, segs, &nseg, 0);
1583 } else if (error != 0)
1591 KASSERT(nseg <= sc->maxtxseg, ("too many DMA segments"));
1592 bus_dmamap_sync(sc->fxp_txmtag, txp->tx_map, BUS_DMASYNC_PREWRITE);
1595 for (i = 0; i < nseg; i++) {
1597 * If this is an 82550/82551, then we're using extended
1598 * TxCBs _and_ we're using checksum offload. This means
1599 * that the TxCB is really an IPCB. One major difference
1600 * between the two is that with plain extended TxCBs,
1601 * the bottom half of the TxCB contains two entries from
1602 * the TBD array, whereas IPCBs contain just one entry:
1603 * one entry (8 bytes) has been sacrificed for the TCP/IP
1604 * checksum offload control bits. So to make things work
1605 * right, we have to start filling in the TBD array
1606 * starting from a different place depending on whether
1607 * the chip is an 82550/82551 or not.
1609 if (sc->flags & FXP_FLAG_EXT_RFA) {
1610 cbp->tbd[i + 1].tb_addr = htole32(segs[i].ds_addr);
1611 cbp->tbd[i + 1].tb_size = htole32(segs[i].ds_len);
1613 cbp->tbd[i].tb_addr = htole32(segs[i].ds_addr);
1614 cbp->tbd[i].tb_size = htole32(segs[i].ds_len);
1617 if (sc->flags & FXP_FLAG_EXT_RFA) {
1618 /* Configure dynamic TBD for 82550/82551. */
1619 cbp->tbd_number = 0xFF;
1620 cbp->tbd[nseg].tb_size |= htole32(0x8000);
1622 cbp->tbd_number = nseg;
1623 /* Configure TSO. */
1624 if (m->m_pkthdr.csum_flags & CSUM_TSO) {
1625 cbp->tbd[-1].tb_size = htole32(m->m_pkthdr.tso_segsz << 16);
1626 cbp->tbd[1].tb_size |= htole32(tcp_payload << 16);
1627 cbp->ipcb_ip_schedule |= FXP_IPCB_LARGESEND_ENABLE |
1628 FXP_IPCB_IP_CHECKSUM_ENABLE |
1629 FXP_IPCB_TCP_PACKET |
1630 FXP_IPCB_TCPUDP_CHECKSUM_ENABLE;
1632 /* Configure VLAN hardware tag insertion. */
1633 if ((m->m_flags & M_VLANTAG) != 0) {
1634 cbp->ipcb_vlan_id = htons(m->m_pkthdr.ether_vtag);
1635 txp->tx_cb->ipcb_ip_activation_high |=
1636 FXP_IPCB_INSERTVLAN_ENABLE;
1640 txp->tx_cb->cb_status = 0;
1641 txp->tx_cb->byte_count = 0;
1642 if (sc->tx_queued != FXP_CXINT_THRESH - 1)
1643 txp->tx_cb->cb_command =
1644 htole16(sc->tx_cmd | FXP_CB_COMMAND_SF |
1647 txp->tx_cb->cb_command =
1648 htole16(sc->tx_cmd | FXP_CB_COMMAND_SF |
1649 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I);
1650 if ((m->m_pkthdr.csum_flags & CSUM_TSO) == 0)
1651 txp->tx_cb->tx_threshold = tx_threshold;
1654 * Advance the end of list forward.
1656 sc->fxp_desc.tx_last->tx_cb->cb_command &= htole16(~FXP_CB_COMMAND_S);
1657 sc->fxp_desc.tx_last = txp;
1660 * Advance the beginning of the list forward if there are
1661 * no other packets queued (when nothing is queued, tx_first
1662 * sits on the last TxCB that was sent out).
1664 if (sc->tx_queued == 0)
1665 sc->fxp_desc.tx_first = txp;
1672 #ifdef DEVICE_POLLING
1673 static poll_handler_t fxp_poll;
1676 fxp_poll(if_t ifp, enum poll_cmd cmd, int count)
1678 struct fxp_softc *sc = if_getsoftc(ifp);
1683 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) {
1688 statack = FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA |
1690 if (cmd == POLL_AND_CHECK_STATUS) {
1693 tmp = CSR_READ_1(sc, FXP_CSR_SCB_STATACK);
1694 if (tmp == 0xff || tmp == 0) {
1696 return (rx_npkts); /* nothing to do */
1699 /* ack what we can */
1701 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, tmp);
1704 rx_npkts = fxp_intr_body(sc, ifp, statack, count);
1708 #endif /* DEVICE_POLLING */
1711 * Process interface interrupts.
1716 struct fxp_softc *sc = xsc;
1721 if (sc->suspended) {
1726 #ifdef DEVICE_POLLING
1727 if (if_getcapenable(ifp) & IFCAP_POLLING) {
1732 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) {
1734 * It should not be possible to have all bits set; the
1735 * FXP_SCB_INTR_SWI bit always returns 0 on a read. If
1736 * all bits are set, this may indicate that the card has
1737 * been physically ejected, so ignore it.
1739 if (statack == 0xff) {
1745 * First ACK all the interrupts in this pass.
1747 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack);
1748 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0)
1749 fxp_intr_body(sc, ifp, statack, -1);
1755 fxp_txeof(struct fxp_softc *sc)
1761 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map,
1762 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1763 for (txp = sc->fxp_desc.tx_first; sc->tx_queued &&
1764 (le16toh(txp->tx_cb->cb_status) & FXP_CB_STATUS_C) != 0;
1765 txp = txp->tx_next) {
1766 if (txp->tx_mbuf != NULL) {
1767 bus_dmamap_sync(sc->fxp_txmtag, txp->tx_map,
1768 BUS_DMASYNC_POSTWRITE);
1769 bus_dmamap_unload(sc->fxp_txmtag, txp->tx_map);
1770 m_freem(txp->tx_mbuf);
1771 txp->tx_mbuf = NULL;
1772 /* clear this to reset csum offload bits */
1773 txp->tx_cb->tbd[0].tb_addr = 0;
1776 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
1778 sc->fxp_desc.tx_first = txp;
1779 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map,
1780 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1781 if (sc->tx_queued == 0)
1782 sc->watchdog_timer = 0;
1786 fxp_rxcsum(struct fxp_softc *sc, if_t ifp, struct mbuf *m,
1787 uint16_t status, int pos)
1789 struct ether_header *eh;
1792 int32_t hlen, len, pktlen, temp32;
1793 uint16_t csum, *opts;
1795 if ((sc->flags & FXP_FLAG_82559_RXCSUM) == 0) {
1796 if ((status & FXP_RFA_STATUS_PARSE) != 0) {
1797 if (status & FXP_RFDX_CS_IP_CSUM_BIT_VALID)
1798 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
1799 if (status & FXP_RFDX_CS_IP_CSUM_VALID)
1800 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1801 if ((status & FXP_RFDX_CS_TCPUDP_CSUM_BIT_VALID) &&
1802 (status & FXP_RFDX_CS_TCPUDP_CSUM_VALID)) {
1803 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
1805 m->m_pkthdr.csum_data = 0xffff;
1811 pktlen = m->m_pkthdr.len;
1812 if (pktlen < sizeof(struct ether_header) + sizeof(struct ip))
1814 eh = mtod(m, struct ether_header *);
1815 if (eh->ether_type != htons(ETHERTYPE_IP))
1817 ip = (struct ip *)(eh + 1);
1818 if (ip->ip_v != IPVERSION)
1821 hlen = ip->ip_hl << 2;
1822 pktlen -= sizeof(struct ether_header);
1823 if (hlen < sizeof(struct ip))
1825 if (ntohs(ip->ip_len) < hlen)
1827 if (ntohs(ip->ip_len) != pktlen)
1829 if (ip->ip_off & htons(IP_MF | IP_OFFMASK))
1830 return; /* can't handle fragmented packet */
1834 if (pktlen < (hlen + sizeof(struct tcphdr)))
1838 if (pktlen < (hlen + sizeof(struct udphdr)))
1840 uh = (struct udphdr *)((caddr_t)ip + hlen);
1841 if (uh->uh_sum == 0)
1842 return; /* no checksum */
1847 /* Extract computed checksum. */
1848 csum = be16dec(mtod(m, char *) + pos);
1849 /* checksum fixup for IP options */
1850 len = hlen - sizeof(struct ip);
1852 opts = (uint16_t *)(ip + 1);
1853 for (; len > 0; len -= sizeof(uint16_t), opts++) {
1854 temp32 = csum - *opts;
1855 temp32 = (temp32 >> 16) + (temp32 & 65535);
1856 csum = temp32 & 65535;
1859 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID;
1860 m->m_pkthdr.csum_data = csum;
1864 fxp_intr_body(struct fxp_softc *sc, if_t ifp, uint8_t statack,
1869 struct fxp_rfa *rfa;
1870 int rnr = (statack & FXP_SCB_STATACK_RNR) ? 1 : 0;
1875 FXP_LOCK_ASSERT(sc, MA_OWNED);
1879 #ifdef DEVICE_POLLING
1880 /* Pick up a deferred RNR condition if `count' ran out last time. */
1881 if (sc->flags & FXP_FLAG_DEFERRED_RNR) {
1882 sc->flags &= ~FXP_FLAG_DEFERRED_RNR;
1888 * Free any finished transmit mbuf chains.
1890 * Handle the CNA event likt a CXTNO event. It used to
1891 * be that this event (control unit not ready) was not
1892 * encountered, but it is now with the SMPng modifications.
1893 * The exact sequence of events that occur when the interface
1894 * is brought up are different now, and if this event
1895 * goes unhandled, the configuration/rxfilter setup sequence
1896 * can stall for several seconds. The result is that no
1897 * packets go out onto the wire for about 5 to 10 seconds
1898 * after the interface is ifconfig'ed for the first time.
1900 if (statack & (FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA))
1904 * Try to start more packets transmitting.
1906 if (!if_sendq_empty(ifp))
1907 fxp_start_body(ifp);
1910 * Just return if nothing happened on the receive side.
1912 if (!rnr && (statack & FXP_SCB_STATACK_FR) == 0)
1916 * Process receiver interrupts. If a no-resource (RNR)
1917 * condition exists, get whatever packets we can and
1918 * re-start the receiver.
1920 * When using polling, we do not process the list to completion,
1921 * so when we get an RNR interrupt we must defer the restart
1922 * until we hit the last buffer with the C bit set.
1923 * If we run out of cycles and rfa_headm has the C bit set,
1924 * record the pending RNR in the FXP_FLAG_DEFERRED_RNR flag so
1925 * that the info will be used in the subsequent polling cycle.
1928 rxp = sc->fxp_desc.rx_head;
1930 rfa = (struct fxp_rfa *)(m->m_ext.ext_buf +
1931 RFA_ALIGNMENT_FUDGE);
1932 bus_dmamap_sync(sc->fxp_rxmtag, rxp->rx_map,
1933 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1935 #ifdef DEVICE_POLLING /* loop at most count times if count >=0 */
1936 if (count >= 0 && count-- == 0) {
1938 /* Defer RNR processing until the next time. */
1939 sc->flags |= FXP_FLAG_DEFERRED_RNR;
1944 #endif /* DEVICE_POLLING */
1946 status = le16toh(rfa->rfa_status);
1947 if ((status & FXP_RFA_STATUS_C) == 0)
1950 if ((status & FXP_RFA_STATUS_RNR) != 0)
1953 * Advance head forward.
1955 sc->fxp_desc.rx_head = rxp->rx_next;
1958 * Add a new buffer to the receive chain.
1959 * If this fails, the old buffer is recycled
1962 if (fxp_new_rfabuf(sc, rxp) == 0) {
1966 * Fetch packet length (the top 2 bits of
1967 * actual_size are flags set by the controller
1968 * upon completion), and drop the packet in case
1969 * of bogus length or CRC errors.
1971 total_len = le16toh(rfa->actual_size) & 0x3fff;
1972 if ((sc->flags & FXP_FLAG_82559_RXCSUM) != 0 &&
1973 (if_getcapenable(ifp) & IFCAP_RXCSUM) != 0) {
1974 /* Adjust for appended checksum bytes. */
1977 if (total_len < (int)sizeof(struct ether_header) ||
1978 total_len > (MCLBYTES - RFA_ALIGNMENT_FUDGE -
1980 status & (FXP_RFA_STATUS_CRC |
1981 FXP_RFA_STATUS_ALIGN | FXP_RFA_STATUS_OVERRUN)) {
1983 fxp_add_rfabuf(sc, rxp);
1987 m->m_pkthdr.len = m->m_len = total_len;
1988 if_setrcvif(m, ifp);
1990 /* Do IP checksum checking. */
1991 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0)
1992 fxp_rxcsum(sc, ifp, m, status, total_len);
1993 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0 &&
1994 (status & FXP_RFA_STATUS_VLAN) != 0) {
1995 m->m_pkthdr.ether_vtag =
1996 ntohs(rfa->rfax_vlan_id);
1997 m->m_flags |= M_VLANTAG;
2000 * Drop locks before calling if_input() since it
2001 * may re-enter fxp_start() in the netisr case.
2002 * This would result in a lock reversal. Better
2003 * performance might be obtained by chaining all
2004 * packets received, dropping the lock, and then
2005 * calling if_input() on each one.
2011 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0)
2014 /* Reuse RFA and loaded DMA map. */
2015 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
2016 fxp_discard_rfabuf(sc, rxp);
2018 fxp_add_rfabuf(sc, rxp);
2022 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL,
2023 sc->fxp_desc.rx_head->rx_addr);
2024 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START);
2030 fxp_update_stats(struct fxp_softc *sc)
2033 struct fxp_stats *sp = sc->fxp_stats;
2034 struct fxp_hwstats *hsp;
2037 FXP_LOCK_ASSERT(sc, MA_OWNED);
2039 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap,
2040 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2041 /* Update statistical counters. */
2042 if (sc->revision >= FXP_REV_82559_A0)
2043 status = &sp->completion_status;
2044 else if (sc->revision >= FXP_REV_82558_A4)
2045 status = (uint32_t *)&sp->tx_tco;
2047 status = &sp->tx_pause;
2048 if (*status == htole32(FXP_STATS_DR_COMPLETE)) {
2049 hsp = &sc->fxp_hwstats;
2050 hsp->tx_good += le32toh(sp->tx_good);
2051 hsp->tx_maxcols += le32toh(sp->tx_maxcols);
2052 hsp->tx_latecols += le32toh(sp->tx_latecols);
2053 hsp->tx_underruns += le32toh(sp->tx_underruns);
2054 hsp->tx_lostcrs += le32toh(sp->tx_lostcrs);
2055 hsp->tx_deffered += le32toh(sp->tx_deffered);
2056 hsp->tx_single_collisions += le32toh(sp->tx_single_collisions);
2057 hsp->tx_multiple_collisions +=
2058 le32toh(sp->tx_multiple_collisions);
2059 hsp->tx_total_collisions += le32toh(sp->tx_total_collisions);
2060 hsp->rx_good += le32toh(sp->rx_good);
2061 hsp->rx_crc_errors += le32toh(sp->rx_crc_errors);
2062 hsp->rx_alignment_errors += le32toh(sp->rx_alignment_errors);
2063 hsp->rx_rnr_errors += le32toh(sp->rx_rnr_errors);
2064 hsp->rx_overrun_errors += le32toh(sp->rx_overrun_errors);
2065 hsp->rx_cdt_errors += le32toh(sp->rx_cdt_errors);
2066 hsp->rx_shortframes += le32toh(sp->rx_shortframes);
2067 hsp->tx_pause += le32toh(sp->tx_pause);
2068 hsp->rx_pause += le32toh(sp->rx_pause);
2069 hsp->rx_controls += le32toh(sp->rx_controls);
2070 hsp->tx_tco += le16toh(sp->tx_tco);
2071 hsp->rx_tco += le16toh(sp->rx_tco);
2073 if_inc_counter(ifp, IFCOUNTER_OPACKETS, le32toh(sp->tx_good));
2074 if_inc_counter(ifp, IFCOUNTER_COLLISIONS,
2075 le32toh(sp->tx_total_collisions));
2077 if_inc_counter(ifp, IFCOUNTER_IPACKETS,
2078 le32toh(sp->rx_good));
2079 sc->rx_idle_secs = 0;
2080 } else if (sc->flags & FXP_FLAG_RXBUG) {
2082 * Receiver's been idle for another second.
2086 if_inc_counter(ifp, IFCOUNTER_IERRORS,
2087 le32toh(sp->rx_crc_errors) +
2088 le32toh(sp->rx_alignment_errors) +
2089 le32toh(sp->rx_rnr_errors) +
2090 le32toh(sp->rx_overrun_errors));
2092 * If any transmit underruns occured, bump up the transmit
2093 * threshold by another 512 bytes (64 * 8).
2095 if (sp->tx_underruns) {
2096 if_inc_counter(ifp, IFCOUNTER_OERRORS,
2097 le32toh(sp->tx_underruns));
2098 if (tx_threshold < 192)
2102 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap,
2103 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2108 * Update packet in/out/collision statistics. The i82557 doesn't
2109 * allow you to access these counters without doing a fairly
2110 * expensive DMA to get _all_ of the statistics it maintains, so
2111 * we do this operation here only once per second. The statistics
2112 * counters in the kernel are updated from the previous dump-stats
2113 * DMA and then a new dump-stats DMA is started. The on-chip
2114 * counters are zeroed when the DMA completes. If we can't start
2115 * the DMA immediately, we don't wait - we just prepare to read
2116 * them again next time.
2121 struct fxp_softc *sc = xsc;
2124 FXP_LOCK_ASSERT(sc, MA_OWNED);
2126 /* Update statistical counters. */
2127 fxp_update_stats(sc);
2130 * Release any xmit buffers that have completed DMA. This isn't
2131 * strictly necessary to do here, but it's advantagous for mbufs
2132 * with external storage to be released in a timely manner rather
2133 * than being defered for a potentially long time. This limits
2134 * the delay to a maximum of one second.
2139 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds,
2140 * then assume the receiver has locked up and attempt to clear
2141 * the condition by reprogramming the multicast filter. This is
2142 * a work-around for a bug in the 82557 where the receiver locks
2143 * up if it gets certain types of garbage in the syncronization
2144 * bits prior to the packet header. This bug is supposed to only
2145 * occur in 10Mbps mode, but has been seen to occur in 100Mbps
2146 * mode as well (perhaps due to a 10/100 speed transition).
2148 if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) {
2149 sc->rx_idle_secs = 0;
2150 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) {
2151 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
2152 fxp_init_body(sc, 1);
2157 * If there is no pending command, start another stats
2158 * dump. Otherwise punt for now.
2160 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) {
2162 * Start another stats dump.
2164 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET);
2166 if (sc->miibus != NULL)
2167 mii_tick(device_get_softc(sc->miibus));
2170 * Check that chip hasn't hung.
2175 * Schedule another timeout one second from now.
2177 callout_reset(&sc->stat_ch, hz, fxp_tick, sc);
2181 * Stop the interface. Cancels the statistics updater and resets
2185 fxp_stop(struct fxp_softc *sc)
2191 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE));
2192 sc->watchdog_timer = 0;
2195 * Cancel stats updater.
2197 callout_stop(&sc->stat_ch);
2200 * Preserve PCI configuration, configure, IA/multicast
2201 * setup and put RU and CU into idle state.
2203 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET);
2205 /* Disable interrupts. */
2206 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE);
2208 fxp_update_stats(sc);
2211 * Release any xmit buffers.
2213 txp = sc->fxp_desc.tx_list;
2215 for (i = 0; i < FXP_NTXCB; i++) {
2216 if (txp[i].tx_mbuf != NULL) {
2217 bus_dmamap_sync(sc->fxp_txmtag, txp[i].tx_map,
2218 BUS_DMASYNC_POSTWRITE);
2219 bus_dmamap_unload(sc->fxp_txmtag,
2221 m_freem(txp[i].tx_mbuf);
2222 txp[i].tx_mbuf = NULL;
2223 /* clear this to reset csum offload bits */
2224 txp[i].tx_cb->tbd[0].tb_addr = 0;
2228 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map,
2229 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2234 * Watchdog/transmission transmit timeout handler. Called when a
2235 * transmission is started on the interface, but no interrupt is
2236 * received before the timeout. This usually indicates that the
2237 * card has wedged for some reason.
2240 fxp_watchdog(struct fxp_softc *sc)
2244 FXP_LOCK_ASSERT(sc, MA_OWNED);
2246 if (sc->watchdog_timer == 0 || --sc->watchdog_timer)
2249 device_printf(sc->dev, "device timeout\n");
2250 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
2252 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
2253 fxp_init_body(sc, 1);
2257 * Acquire locks and then call the real initialization function. This
2258 * is necessary because ether_ioctl() calls if_init() and this would
2259 * result in mutex recursion if the mutex was held.
2264 struct fxp_softc *sc = xsc;
2267 fxp_init_body(sc, 1);
2272 * Perform device initialization. This routine must be called with the
2276 fxp_init_body(struct fxp_softc *sc, int setmedia)
2279 struct mii_data *mii;
2280 struct fxp_cb_config *cbp;
2281 struct fxp_cb_ias *cb_ias;
2282 struct fxp_cb_tx *tcbp;
2286 FXP_LOCK_ASSERT(sc, MA_OWNED);
2288 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING)
2292 * Cancel any pending I/O
2297 * Issue software reset, which also unloads the microcode.
2299 sc->flags &= ~FXP_FLAG_UCODE;
2300 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET);
2303 prm = (if_getflags(ifp) & IFF_PROMISC) ? 1 : 0;
2306 * Initialize base of CBL and RFA memory. Loading with zero
2307 * sets it up for regular linear addressing.
2309 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0);
2310 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE);
2313 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE);
2316 * Initialize base of dump-stats buffer.
2319 bzero(sc->fxp_stats, sizeof(struct fxp_stats));
2320 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap,
2321 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2322 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->stats_addr);
2323 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR);
2326 * Attempt to load microcode if requested.
2327 * For ICH based controllers do not load microcode.
2329 if (sc->ident->ich == 0) {
2330 if (if_getflags(ifp) & IFF_LINK0 &&
2331 (sc->flags & FXP_FLAG_UCODE) == 0)
2336 * Set IFF_ALLMULTI status. It's needed in configure action
2342 * We temporarily use memory that contains the TxCB list to
2343 * construct the config CB. The TxCB list memory is rebuilt
2346 cbp = (struct fxp_cb_config *)sc->fxp_desc.cbl_list;
2349 * This bcopy is kind of disgusting, but there are a bunch of must be
2350 * zero and must be one bits in this structure and this is the easiest
2351 * way to initialize them all to proper values.
2353 bcopy(fxp_cb_config_template, cbp, sizeof(fxp_cb_config_template));
2356 cbp->cb_command = htole16(FXP_CB_COMMAND_CONFIG |
2358 cbp->link_addr = 0xffffffff; /* (no) next command */
2359 cbp->byte_count = sc->flags & FXP_FLAG_EXT_RFA ? 32 : 22;
2360 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */
2361 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */
2362 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */
2363 cbp->mwi_enable = sc->flags & FXP_FLAG_MWI_ENABLE ? 1 : 0;
2364 cbp->type_enable = 0; /* actually reserved */
2365 cbp->read_align_en = sc->flags & FXP_FLAG_READ_ALIGN ? 1 : 0;
2366 cbp->end_wr_on_cl = sc->flags & FXP_FLAG_WRITE_ALIGN ? 1 : 0;
2367 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */
2368 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */
2369 cbp->dma_mbce = 0; /* (disable) dma max counters */
2370 cbp->late_scb = 0; /* (don't) defer SCB update */
2371 cbp->direct_dma_dis = 1; /* disable direct rcv dma mode */
2372 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */
2373 cbp->ci_int = 1; /* interrupt on CU idle */
2374 cbp->ext_txcb_dis = sc->flags & FXP_FLAG_EXT_TXCB ? 0 : 1;
2375 cbp->ext_stats_dis = 1; /* disable extended counters */
2376 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */
2377 cbp->save_bf = sc->flags & FXP_FLAG_SAVE_BAD ? 1 : prm;
2378 cbp->disc_short_rx = !prm; /* discard short packets */
2379 cbp->underrun_retry = 1; /* retry mode (once) on DMA underrun */
2380 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */
2381 cbp->dyn_tbd = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0;
2382 cbp->ext_rfa = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0;
2383 cbp->mediatype = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 0 : 1;
2384 cbp->csma_dis = 0; /* (don't) disable link */
2385 cbp->tcp_udp_cksum = ((sc->flags & FXP_FLAG_82559_RXCSUM) != 0 &&
2386 (if_getcapenable(ifp) & IFCAP_RXCSUM) != 0) ? 1 : 0;
2387 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */
2388 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */
2389 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */
2390 cbp->mc_wake_en = 0; /* (don't) enable PME# on mcmatch */
2391 cbp->nsai = 1; /* (don't) disable source addr insert */
2392 cbp->preamble_length = 2; /* (7 byte) preamble */
2393 cbp->loopback = 0; /* (don't) loopback */
2394 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */
2395 cbp->linear_pri_mode = 0; /* (wait after xmit only) */
2396 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */
2397 cbp->promiscuous = prm; /* promiscuous mode */
2398 cbp->bcast_disable = 0; /* (don't) disable broadcasts */
2399 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/
2400 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */
2401 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */
2402 cbp->crscdt = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 1 : 0;
2404 cbp->stripping = !prm; /* truncate rx packet to byte count */
2405 cbp->padding = 1; /* (do) pad short tx packets */
2406 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */
2407 cbp->long_rx_en = sc->flags & FXP_FLAG_LONG_PKT_EN ? 1 : 0;
2408 cbp->ia_wake_en = 0; /* (don't) wake up on address match */
2409 cbp->magic_pkt_dis = sc->flags & FXP_FLAG_WOL ? 0 : 1;
2410 cbp->force_fdx = 0; /* (don't) force full duplex */
2411 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */
2412 cbp->multi_ia = 0; /* (don't) accept multiple IAs */
2413 cbp->mc_all = if_getflags(ifp) & IFF_ALLMULTI ? 1 : prm;
2414 cbp->gamla_rx = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0;
2415 cbp->vlan_strip_en = ((sc->flags & FXP_FLAG_EXT_RFA) != 0 &&
2416 (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0) ? 1 : 0;
2418 if (sc->revision == FXP_REV_82557) {
2420 * The 82557 has no hardware flow control, the values
2421 * below are the defaults for the chip.
2423 cbp->fc_delay_lsb = 0;
2424 cbp->fc_delay_msb = 0x40;
2425 cbp->pri_fc_thresh = 3;
2427 cbp->rx_fc_restop = 0;
2428 cbp->rx_fc_restart = 0;
2430 cbp->pri_fc_loc = 1;
2432 /* Set pause RX FIFO threshold to 1KB. */
2433 CSR_WRITE_1(sc, FXP_CSR_FC_THRESH, 1);
2434 /* Set pause time. */
2435 cbp->fc_delay_lsb = 0xff;
2436 cbp->fc_delay_msb = 0xff;
2437 cbp->pri_fc_thresh = 3;
2438 mii = device_get_softc(sc->miibus);
2439 if ((IFM_OPTIONS(mii->mii_media_active) &
2440 IFM_ETH_TXPAUSE) != 0)
2441 /* enable transmit FC */
2444 /* disable transmit FC */
2446 if ((IFM_OPTIONS(mii->mii_media_active) &
2447 IFM_ETH_RXPAUSE) != 0) {
2448 /* enable FC restart/restop frames */
2449 cbp->rx_fc_restart = 1;
2450 cbp->rx_fc_restop = 1;
2452 /* disable FC restart/restop frames */
2453 cbp->rx_fc_restart = 0;
2454 cbp->rx_fc_restop = 0;
2456 cbp->fc_filter = !prm; /* drop FC frames to host */
2457 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */
2460 /* Enable 82558 and 82559 extended statistics functionality. */
2461 if (sc->revision >= FXP_REV_82558_A4) {
2462 if (sc->revision >= FXP_REV_82559_A0) {
2464 * Extend configuration table size to 32
2465 * to include TCO configuration.
2467 cbp->byte_count = 32;
2468 cbp->ext_stats_dis = 1;
2469 /* Enable TCO stats. */
2470 cbp->tno_int_or_tco_en = 1;
2473 cbp->ext_stats_dis = 0;
2477 * Start the config command/DMA.
2480 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map,
2481 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2482 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr);
2483 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
2484 /* ...and wait for it to complete. */
2485 fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map);
2488 * Now initialize the station address. Temporarily use the TxCB
2489 * memory area like we did above for the config CB.
2491 cb_ias = (struct fxp_cb_ias *)sc->fxp_desc.cbl_list;
2492 cb_ias->cb_status = 0;
2493 cb_ias->cb_command = htole16(FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL);
2494 cb_ias->link_addr = 0xffffffff;
2495 bcopy(if_getlladdr(sc->ifp), cb_ias->macaddr, ETHER_ADDR_LEN);
2498 * Start the IAS (Individual Address Setup) command/DMA.
2501 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map,
2502 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2503 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr);
2504 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
2505 /* ...and wait for it to complete. */
2506 fxp_dma_wait(sc, &cb_ias->cb_status, sc->cbl_tag, sc->cbl_map);
2509 * Initialize the multicast address list.
2514 * Initialize transmit control block (TxCB) list.
2516 txp = sc->fxp_desc.tx_list;
2517 tcbp = sc->fxp_desc.cbl_list;
2518 bzero(tcbp, FXP_TXCB_SZ);
2519 for (i = 0; i < FXP_NTXCB; i++) {
2520 txp[i].tx_mbuf = NULL;
2521 tcbp[i].cb_status = htole16(FXP_CB_STATUS_C | FXP_CB_STATUS_OK);
2522 tcbp[i].cb_command = htole16(FXP_CB_COMMAND_NOP);
2523 tcbp[i].link_addr = htole32(sc->fxp_desc.cbl_addr +
2524 (((i + 1) & FXP_TXCB_MASK) * sizeof(struct fxp_cb_tx)));
2525 if (sc->flags & FXP_FLAG_EXT_TXCB)
2526 tcbp[i].tbd_array_addr =
2527 htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[2]));
2529 tcbp[i].tbd_array_addr =
2530 htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[0]));
2531 txp[i].tx_next = &txp[(i + 1) & FXP_TXCB_MASK];
2534 * Set the suspend flag on the first TxCB and start the control
2535 * unit. It will execute the NOP and then suspend.
2537 tcbp->cb_command = htole16(FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S);
2538 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map,
2539 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2540 sc->fxp_desc.tx_first = sc->fxp_desc.tx_last = txp;
2544 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr);
2545 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
2548 * Initialize receiver buffer area - RFA.
2551 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.rx_head->rx_addr);
2552 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START);
2554 if (sc->miibus != NULL && setmedia != 0)
2555 mii_mediachg(device_get_softc(sc->miibus));
2557 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE);
2560 * Enable interrupts.
2562 #ifdef DEVICE_POLLING
2564 * ... but only do that if we are not polling. And because (presumably)
2565 * the default is interrupts on, we need to disable them explicitly!
2567 if (if_getcapenable(ifp) & IFCAP_POLLING )
2568 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE);
2570 #endif /* DEVICE_POLLING */
2571 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0);
2574 * Start stats updater.
2576 callout_reset(&sc->stat_ch, hz, fxp_tick, sc);
2580 fxp_serial_ifmedia_upd(if_t ifp)
2587 fxp_serial_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr)
2590 ifmr->ifm_active = IFM_ETHER|IFM_MANUAL;
2594 * Change media according to request.
2597 fxp_ifmedia_upd(if_t ifp)
2599 struct fxp_softc *sc = if_getsoftc(ifp);
2600 struct mii_data *mii;
2601 struct mii_softc *miisc;
2603 mii = device_get_softc(sc->miibus);
2605 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
2613 * Notify the world which media we're using.
2616 fxp_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr)
2618 struct fxp_softc *sc = if_getsoftc(ifp);
2619 struct mii_data *mii;
2621 mii = device_get_softc(sc->miibus);
2624 ifmr->ifm_active = mii->mii_media_active;
2625 ifmr->ifm_status = mii->mii_media_status;
2630 * Add a buffer to the end of the RFA buffer list.
2631 * Return 0 if successful, 1 for failure. A failure results in
2632 * reusing the RFA buffer.
2633 * The RFA struct is stuck at the beginning of mbuf cluster and the
2634 * data pointer is fixed up to point just past it.
2637 fxp_new_rfabuf(struct fxp_softc *sc, struct fxp_rx *rxp)
2640 struct fxp_rfa *rfa;
2641 bus_dmamap_t tmp_map;
2644 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
2649 * Move the data pointer up so that the incoming data packet
2650 * will be 32-bit aligned.
2652 m->m_data += RFA_ALIGNMENT_FUDGE;
2655 * Get a pointer to the base of the mbuf cluster and move
2656 * data start past it.
2658 rfa = mtod(m, struct fxp_rfa *);
2659 m->m_data += sc->rfa_size;
2660 rfa->size = htole16(MCLBYTES - sc->rfa_size - RFA_ALIGNMENT_FUDGE);
2662 rfa->rfa_status = 0;
2663 rfa->rfa_control = htole16(FXP_RFA_CONTROL_EL);
2664 rfa->actual_size = 0;
2665 m->m_len = m->m_pkthdr.len = MCLBYTES - RFA_ALIGNMENT_FUDGE -
2669 * Initialize the rest of the RFA. Note that since the RFA
2670 * is misaligned, we cannot store values directly. We're thus
2671 * using the le32enc() function which handles endianness and
2672 * is also alignment-safe.
2674 le32enc(&rfa->link_addr, 0xffffffff);
2675 le32enc(&rfa->rbd_addr, 0xffffffff);
2677 /* Map the RFA into DMA memory. */
2678 error = bus_dmamap_load(sc->fxp_rxmtag, sc->spare_map, rfa,
2679 MCLBYTES - RFA_ALIGNMENT_FUDGE, fxp_dma_map_addr,
2680 &rxp->rx_addr, BUS_DMA_NOWAIT);
2686 if (rxp->rx_mbuf != NULL)
2687 bus_dmamap_unload(sc->fxp_rxmtag, rxp->rx_map);
2688 tmp_map = sc->spare_map;
2689 sc->spare_map = rxp->rx_map;
2690 rxp->rx_map = tmp_map;
2693 bus_dmamap_sync(sc->fxp_rxmtag, rxp->rx_map,
2694 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2699 fxp_add_rfabuf(struct fxp_softc *sc, struct fxp_rx *rxp)
2701 struct fxp_rfa *p_rfa;
2702 struct fxp_rx *p_rx;
2705 * If there are other buffers already on the list, attach this
2706 * one to the end by fixing up the tail to point to this one.
2708 if (sc->fxp_desc.rx_head != NULL) {
2709 p_rx = sc->fxp_desc.rx_tail;
2710 p_rfa = (struct fxp_rfa *)
2711 (p_rx->rx_mbuf->m_ext.ext_buf + RFA_ALIGNMENT_FUDGE);
2712 p_rx->rx_next = rxp;
2713 le32enc(&p_rfa->link_addr, rxp->rx_addr);
2714 p_rfa->rfa_control = 0;
2715 bus_dmamap_sync(sc->fxp_rxmtag, p_rx->rx_map,
2716 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2718 rxp->rx_next = NULL;
2719 sc->fxp_desc.rx_head = rxp;
2721 sc->fxp_desc.rx_tail = rxp;
2725 fxp_discard_rfabuf(struct fxp_softc *sc, struct fxp_rx *rxp)
2728 struct fxp_rfa *rfa;
2731 m->m_data = m->m_ext.ext_buf;
2733 * Move the data pointer up so that the incoming data packet
2734 * will be 32-bit aligned.
2736 m->m_data += RFA_ALIGNMENT_FUDGE;
2739 * Get a pointer to the base of the mbuf cluster and move
2740 * data start past it.
2742 rfa = mtod(m, struct fxp_rfa *);
2743 m->m_data += sc->rfa_size;
2744 rfa->size = htole16(MCLBYTES - sc->rfa_size - RFA_ALIGNMENT_FUDGE);
2746 rfa->rfa_status = 0;
2747 rfa->rfa_control = htole16(FXP_RFA_CONTROL_EL);
2748 rfa->actual_size = 0;
2751 * Initialize the rest of the RFA. Note that since the RFA
2752 * is misaligned, we cannot store values directly. We're thus
2753 * using the le32enc() function which handles endianness and
2754 * is also alignment-safe.
2756 le32enc(&rfa->link_addr, 0xffffffff);
2757 le32enc(&rfa->rbd_addr, 0xffffffff);
2759 bus_dmamap_sync(sc->fxp_rxmtag, rxp->rx_map,
2760 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2764 fxp_miibus_readreg(device_t dev, int phy, int reg)
2766 struct fxp_softc *sc = device_get_softc(dev);
2770 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL,
2771 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21));
2773 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0
2778 device_printf(dev, "fxp_miibus_readreg: timed out\n");
2780 return (value & 0xffff);
2784 fxp_miibus_writereg(device_t dev, int phy, int reg, int value)
2786 struct fxp_softc *sc = device_get_softc(dev);
2789 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL,
2790 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) |
2793 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 &&
2798 device_printf(dev, "fxp_miibus_writereg: timed out\n");
2803 fxp_miibus_statchg(device_t dev)
2805 struct fxp_softc *sc;
2806 struct mii_data *mii;
2809 sc = device_get_softc(dev);
2810 mii = device_get_softc(sc->miibus);
2812 if (mii == NULL || ifp == (void *)NULL ||
2813 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0 ||
2814 (mii->mii_media_status & (IFM_AVALID | IFM_ACTIVE)) !=
2815 (IFM_AVALID | IFM_ACTIVE))
2818 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T &&
2819 sc->flags & FXP_FLAG_CU_RESUME_BUG)
2820 sc->cu_resume_bug = 1;
2822 sc->cu_resume_bug = 0;
2824 * Call fxp_init_body in order to adjust the flow control settings.
2825 * Note that the 82557 doesn't support hardware flow control.
2827 if (sc->revision == FXP_REV_82557)
2829 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
2830 fxp_init_body(sc, 0);
2834 fxp_ioctl(if_t ifp, u_long command, caddr_t data)
2836 struct fxp_softc *sc = if_getsoftc(ifp);
2837 struct ifreq *ifr = (struct ifreq *)data;
2838 struct mii_data *mii;
2839 int flag, mask, error = 0, reinit;
2845 * If interface is marked up and not running, then start it.
2846 * If it is marked down and running, stop it.
2847 * XXX If it's up then re-initialize it. This is so flags
2848 * such as IFF_PROMISC are handled.
2850 if (if_getflags(ifp) & IFF_UP) {
2851 if (((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) &&
2852 ((if_getflags(ifp) ^ sc->if_flags) &
2853 (IFF_PROMISC | IFF_ALLMULTI | IFF_LINK0)) != 0) {
2854 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
2855 fxp_init_body(sc, 0);
2856 } else if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0)
2857 fxp_init_body(sc, 1);
2859 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0)
2862 sc->if_flags = if_getflags(ifp);
2869 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) {
2870 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
2871 fxp_init_body(sc, 0);
2878 if (sc->miibus != NULL) {
2879 mii = device_get_softc(sc->miibus);
2880 error = ifmedia_ioctl(ifp, ifr,
2881 &mii->mii_media, command);
2883 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command);
2889 mask = if_getcapenable(ifp) ^ ifr->ifr_reqcap;
2890 #ifdef DEVICE_POLLING
2891 if (mask & IFCAP_POLLING) {
2892 if (ifr->ifr_reqcap & IFCAP_POLLING) {
2893 error = ether_poll_register(fxp_poll, ifp);
2897 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL,
2898 FXP_SCB_INTR_DISABLE);
2899 if_setcapenablebit(ifp, IFCAP_POLLING, 0);
2902 error = ether_poll_deregister(ifp);
2903 /* Enable interrupts in any case */
2905 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0);
2906 if_setcapenablebit(ifp, 0, IFCAP_POLLING);
2912 if ((mask & IFCAP_TXCSUM) != 0 &&
2913 (if_getcapabilities(ifp) & IFCAP_TXCSUM) != 0) {
2914 if_togglecapenable(ifp, IFCAP_TXCSUM);
2915 if ((if_getcapenable(ifp) & IFCAP_TXCSUM) != 0)
2916 if_sethwassistbits(ifp, FXP_CSUM_FEATURES, 0);
2918 if_sethwassistbits(ifp, 0, FXP_CSUM_FEATURES);
2920 if ((mask & IFCAP_RXCSUM) != 0 &&
2921 (if_getcapabilities(ifp) & IFCAP_RXCSUM) != 0) {
2922 if_togglecapenable(ifp, IFCAP_RXCSUM);
2923 if ((sc->flags & FXP_FLAG_82559_RXCSUM) != 0)
2926 if ((mask & IFCAP_TSO4) != 0 &&
2927 (if_getcapabilities(ifp) & IFCAP_TSO4) != 0) {
2928 if_togglecapenable(ifp, IFCAP_TSO4);
2929 if ((if_getcapenable(ifp) & IFCAP_TSO4) != 0)
2930 if_sethwassistbits(ifp, CSUM_TSO, 0);
2932 if_sethwassistbits(ifp, 0, CSUM_TSO);
2934 if ((mask & IFCAP_WOL_MAGIC) != 0 &&
2935 (if_getcapabilities(ifp) & IFCAP_WOL_MAGIC) != 0)
2936 if_togglecapenable(ifp, IFCAP_WOL_MAGIC);
2937 if ((mask & IFCAP_VLAN_MTU) != 0 &&
2938 (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) != 0) {
2939 if_togglecapenable(ifp, IFCAP_VLAN_MTU);
2940 if (sc->revision != FXP_REV_82557)
2941 flag = FXP_FLAG_LONG_PKT_EN;
2942 else /* a hack to get long frames on the old chip */
2943 flag = FXP_FLAG_SAVE_BAD;
2945 if (if_getflags(ifp) & IFF_UP)
2948 if ((mask & IFCAP_VLAN_HWCSUM) != 0 &&
2949 (if_getcapabilities(ifp) & IFCAP_VLAN_HWCSUM) != 0)
2950 if_togglecapenable(ifp, IFCAP_VLAN_HWCSUM);
2951 if ((mask & IFCAP_VLAN_HWTSO) != 0 &&
2952 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTSO) != 0)
2953 if_togglecapenable(ifp, IFCAP_VLAN_HWTSO);
2954 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
2955 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTAGGING) != 0) {
2956 if_togglecapenable(ifp, IFCAP_VLAN_HWTAGGING);
2957 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) == 0)
2958 if_setcapenablebit(ifp, 0, IFCAP_VLAN_HWTSO |
2963 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) {
2964 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
2965 fxp_init_body(sc, 0);
2972 error = ether_ioctl(ifp, command, data);
2978 * Fill in the multicast address list and return number of entries.
2981 fxp_mc_addrs(struct fxp_softc *sc)
2983 struct fxp_cb_mcs *mcsp = sc->mcsp;
2987 if ((if_getflags(ifp) & IFF_ALLMULTI) == 0) {
2988 if_maddr_rlock(ifp);
2989 if_setupmultiaddr(ifp, mcsp->mc_addr, &nmcasts, MAXMCADDR);
2990 if (nmcasts >= MAXMCADDR) {
2991 if_setflagbits(ifp, IFF_ALLMULTI, 0);
2994 if_maddr_runlock(ifp);
2996 mcsp->mc_cnt = htole16(nmcasts * ETHER_ADDR_LEN);
3001 * Program the multicast filter.
3003 * We have an artificial restriction that the multicast setup command
3004 * must be the first command in the chain, so we take steps to ensure
3005 * this. By requiring this, it allows us to keep up the performance of
3006 * the pre-initialized command ring (esp. link pointers) by not actually
3007 * inserting the mcsetup command in the ring - i.e. its link pointer
3008 * points to the TxCB ring, but the mcsetup descriptor itself is not part
3009 * of it. We then can do 'CU_START' on the mcsetup descriptor and have it
3010 * lead into the regular TxCB ring when it completes.
3013 fxp_mc_setup(struct fxp_softc *sc)
3015 struct fxp_cb_mcs *mcsp;
3018 FXP_LOCK_ASSERT(sc, MA_OWNED);
3021 mcsp->cb_status = 0;
3022 mcsp->cb_command = htole16(FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL);
3023 mcsp->link_addr = 0xffffffff;
3027 * Wait until command unit is idle. This should never be the
3028 * case when nothing is queued, but make sure anyway.
3031 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) !=
3032 FXP_SCB_CUS_IDLE && --count)
3035 device_printf(sc->dev, "command queue timeout\n");
3040 * Start the multicast setup command.
3043 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map,
3044 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3045 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->mcs_addr);
3046 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
3047 /* ...and wait for it to complete. */
3048 fxp_dma_wait(sc, &mcsp->cb_status, sc->mcs_tag, sc->mcs_map);
3051 static uint32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE;
3052 static uint32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE;
3053 static uint32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE;
3054 static uint32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE;
3055 static uint32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE;
3056 static uint32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE;
3057 static uint32_t fxp_ucode_d102e[] = D102_E_RCVBUNDLE_UCODE;
3059 #define UCODE(x) x, sizeof(x)/sizeof(uint32_t)
3061 static const struct ucode {
3065 u_short int_delay_offset;
3066 u_short bundle_max_offset;
3068 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), D101_CPUSAVER_DWORD, 0 },
3069 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), D101_CPUSAVER_DWORD, 0 },
3070 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma),
3071 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD },
3072 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s),
3073 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD },
3074 { FXP_REV_82550, UCODE(fxp_ucode_d102),
3075 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD },
3076 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c),
3077 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD },
3078 { FXP_REV_82551_F, UCODE(fxp_ucode_d102e),
3079 D102_E_CPUSAVER_DWORD, D102_E_CPUSAVER_BUNDLE_MAX_DWORD },
3080 { FXP_REV_82551_10, UCODE(fxp_ucode_d102e),
3081 D102_E_CPUSAVER_DWORD, D102_E_CPUSAVER_BUNDLE_MAX_DWORD },
3082 { 0, NULL, 0, 0, 0 }
3086 fxp_load_ucode(struct fxp_softc *sc)
3088 const struct ucode *uc;
3089 struct fxp_cb_ucode *cbp;
3092 if (sc->flags & FXP_FLAG_NO_UCODE)
3095 for (uc = ucode_table; uc->ucode != NULL; uc++)
3096 if (sc->revision == uc->revision)
3098 if (uc->ucode == NULL)
3100 cbp = (struct fxp_cb_ucode *)sc->fxp_desc.cbl_list;
3102 cbp->cb_command = htole16(FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL);
3103 cbp->link_addr = 0xffffffff; /* (no) next command */
3104 for (i = 0; i < uc->length; i++)
3105 cbp->ucode[i] = htole32(uc->ucode[i]);
3106 if (uc->int_delay_offset)
3107 *(uint16_t *)&cbp->ucode[uc->int_delay_offset] =
3108 htole16(sc->tunable_int_delay + sc->tunable_int_delay / 2);
3109 if (uc->bundle_max_offset)
3110 *(uint16_t *)&cbp->ucode[uc->bundle_max_offset] =
3111 htole16(sc->tunable_bundle_max);
3113 * Download the ucode to the chip.
3116 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map,
3117 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3118 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr);
3119 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
3120 /* ...and wait for it to complete. */
3121 fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map);
3122 device_printf(sc->dev,
3123 "Microcode loaded, int_delay: %d usec bundle_max: %d\n",
3124 sc->tunable_int_delay,
3125 uc->bundle_max_offset == 0 ? 0 : sc->tunable_bundle_max);
3126 sc->flags |= FXP_FLAG_UCODE;
3127 bzero(cbp, FXP_TXCB_SZ);
3130 #define FXP_SYSCTL_STAT_ADD(c, h, n, p, d) \
3131 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d)
3134 fxp_sysctl_node(struct fxp_softc *sc)
3136 struct sysctl_ctx_list *ctx;
3137 struct sysctl_oid_list *child, *parent;
3138 struct sysctl_oid *tree;
3139 struct fxp_hwstats *hsp;
3141 ctx = device_get_sysctl_ctx(sc->dev);
3142 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev));
3144 SYSCTL_ADD_PROC(ctx, child,
3145 OID_AUTO, "int_delay", CTLTYPE_INT | CTLFLAG_RW,
3146 &sc->tunable_int_delay, 0, sysctl_hw_fxp_int_delay, "I",
3147 "FXP driver receive interrupt microcode bundling delay");
3148 SYSCTL_ADD_PROC(ctx, child,
3149 OID_AUTO, "bundle_max", CTLTYPE_INT | CTLFLAG_RW,
3150 &sc->tunable_bundle_max, 0, sysctl_hw_fxp_bundle_max, "I",
3151 "FXP driver receive interrupt microcode bundle size limit");
3152 SYSCTL_ADD_INT(ctx, child,OID_AUTO, "rnr", CTLFLAG_RD, &sc->rnr, 0,
3156 * Pull in device tunables.
3158 sc->tunable_int_delay = TUNABLE_INT_DELAY;
3159 sc->tunable_bundle_max = TUNABLE_BUNDLE_MAX;
3160 (void) resource_int_value(device_get_name(sc->dev),
3161 device_get_unit(sc->dev), "int_delay", &sc->tunable_int_delay);
3162 (void) resource_int_value(device_get_name(sc->dev),
3163 device_get_unit(sc->dev), "bundle_max", &sc->tunable_bundle_max);
3166 hsp = &sc->fxp_hwstats;
3167 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD,
3168 NULL, "FXP statistics");
3169 parent = SYSCTL_CHILDREN(tree);
3171 /* Rx MAC statistics. */
3172 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", CTLFLAG_RD,
3173 NULL, "Rx MAC statistics");
3174 child = SYSCTL_CHILDREN(tree);
3175 FXP_SYSCTL_STAT_ADD(ctx, child, "good_frames",
3176 &hsp->rx_good, "Good frames");
3177 FXP_SYSCTL_STAT_ADD(ctx, child, "crc_errors",
3178 &hsp->rx_crc_errors, "CRC errors");
3179 FXP_SYSCTL_STAT_ADD(ctx, child, "alignment_errors",
3180 &hsp->rx_alignment_errors, "Alignment errors");
3181 FXP_SYSCTL_STAT_ADD(ctx, child, "rnr_errors",
3182 &hsp->rx_rnr_errors, "RNR errors");
3183 FXP_SYSCTL_STAT_ADD(ctx, child, "overrun_errors",
3184 &hsp->rx_overrun_errors, "Overrun errors");
3185 FXP_SYSCTL_STAT_ADD(ctx, child, "cdt_errors",
3186 &hsp->rx_cdt_errors, "Collision detect errors");
3187 FXP_SYSCTL_STAT_ADD(ctx, child, "shortframes",
3188 &hsp->rx_shortframes, "Short frame errors");
3189 if (sc->revision >= FXP_REV_82558_A4) {
3190 FXP_SYSCTL_STAT_ADD(ctx, child, "pause",
3191 &hsp->rx_pause, "Pause frames");
3192 FXP_SYSCTL_STAT_ADD(ctx, child, "controls",
3193 &hsp->rx_controls, "Unsupported control frames");
3195 if (sc->revision >= FXP_REV_82559_A0)
3196 FXP_SYSCTL_STAT_ADD(ctx, child, "tco",
3197 &hsp->rx_tco, "TCO frames");
3199 /* Tx MAC statistics. */
3200 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", CTLFLAG_RD,
3201 NULL, "Tx MAC statistics");
3202 child = SYSCTL_CHILDREN(tree);
3203 FXP_SYSCTL_STAT_ADD(ctx, child, "good_frames",
3204 &hsp->tx_good, "Good frames");
3205 FXP_SYSCTL_STAT_ADD(ctx, child, "maxcols",
3206 &hsp->tx_maxcols, "Maximum collisions errors");
3207 FXP_SYSCTL_STAT_ADD(ctx, child, "latecols",
3208 &hsp->tx_latecols, "Late collisions errors");
3209 FXP_SYSCTL_STAT_ADD(ctx, child, "underruns",
3210 &hsp->tx_underruns, "Underrun errors");
3211 FXP_SYSCTL_STAT_ADD(ctx, child, "lostcrs",
3212 &hsp->tx_lostcrs, "Lost carrier sense");
3213 FXP_SYSCTL_STAT_ADD(ctx, child, "deffered",
3214 &hsp->tx_deffered, "Deferred");
3215 FXP_SYSCTL_STAT_ADD(ctx, child, "single_collisions",
3216 &hsp->tx_single_collisions, "Single collisions");
3217 FXP_SYSCTL_STAT_ADD(ctx, child, "multiple_collisions",
3218 &hsp->tx_multiple_collisions, "Multiple collisions");
3219 FXP_SYSCTL_STAT_ADD(ctx, child, "total_collisions",
3220 &hsp->tx_total_collisions, "Total collisions");
3221 if (sc->revision >= FXP_REV_82558_A4)
3222 FXP_SYSCTL_STAT_ADD(ctx, child, "pause",
3223 &hsp->tx_pause, "Pause frames");
3224 if (sc->revision >= FXP_REV_82559_A0)
3225 FXP_SYSCTL_STAT_ADD(ctx, child, "tco",
3226 &hsp->tx_tco, "TCO frames");
3229 #undef FXP_SYSCTL_STAT_ADD
3232 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high)
3236 value = *(int *)arg1;
3237 error = sysctl_handle_int(oidp, &value, 0, req);
3238 if (error || !req->newptr)
3240 if (value < low || value > high)
3242 *(int *)arg1 = value;
3247 * Interrupt delay is expressed in microseconds, a multiplier is used
3248 * to convert this to the appropriate clock ticks before using.
3251 sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS)
3254 return (sysctl_int_range(oidp, arg1, arg2, req, 300, 3000));
3258 sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS)
3261 return (sysctl_int_range(oidp, arg1, arg2, req, 1, 0xffff));