2 * Copyright (c) 1995, David Greenman
3 * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice unmodified, this list of conditions, and the following
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 #define FXP_VENDORID_INTEL 0x8086
33 #define FXP_PCI_MMBA 0x10
34 #define FXP_PCI_IOBA 0x14
37 * Control/status registers.
39 #define FXP_CSR_SCB_RUSCUS 0 /* scb_rus/scb_cus (1 byte) */
40 #define FXP_CSR_SCB_STATACK 1 /* scb_statack (1 byte) */
41 #define FXP_CSR_SCB_COMMAND 2 /* scb_command (1 byte) */
42 #define FXP_CSR_SCB_INTRCNTL 3 /* scb_intrcntl (1 byte) */
43 #define FXP_CSR_SCB_GENERAL 4 /* scb_general (4 bytes) */
44 #define FXP_CSR_PORT 8 /* port (4 bytes) */
45 #define FXP_CSR_FLASHCONTROL 12 /* flash control (2 bytes) */
46 #define FXP_CSR_EEPROMCONTROL 14 /* eeprom control (2 bytes) */
47 #define FXP_CSR_MDICONTROL 16 /* mdi control (4 bytes) */
48 #define FXP_CSR_FLOWCONTROL 0x19 /* flow control (2 bytes) */
49 #define FXP_CSR_GENCONTROL 0x1C /* general control (1 byte) */
52 * FOR REFERENCE ONLY, the old definition of FXP_CSR_SCB_RUSCUS:
54 * volatile u_int8_t :2,
59 #define FXP_PORT_SOFTWARE_RESET 0
60 #define FXP_PORT_SELFTEST 1
61 #define FXP_PORT_SELECTIVE_RESET 2
62 #define FXP_PORT_DUMP 3
64 #define FXP_SCB_RUS_IDLE 0
65 #define FXP_SCB_RUS_SUSPENDED 1
66 #define FXP_SCB_RUS_NORESOURCES 2
67 #define FXP_SCB_RUS_READY 4
68 #define FXP_SCB_RUS_SUSP_NORBDS 9
69 #define FXP_SCB_RUS_NORES_NORBDS 10
70 #define FXP_SCB_RUS_READY_NORBDS 12
72 #define FXP_SCB_CUS_IDLE 0
73 #define FXP_SCB_CUS_SUSPENDED 1
74 #define FXP_SCB_CUS_ACTIVE 2
76 #define FXP_SCB_INTR_DISABLE 0x01 /* Disable all interrupts */
77 #define FXP_SCB_INTR_SWI 0x02 /* Generate SWI */
78 #define FXP_SCB_INTMASK_FCP 0x04
79 #define FXP_SCB_INTMASK_ER 0x08
80 #define FXP_SCB_INTMASK_RNR 0x10
81 #define FXP_SCB_INTMASK_CNA 0x20
82 #define FXP_SCB_INTMASK_FR 0x40
83 #define FXP_SCB_INTMASK_CXTNO 0x80
85 #define FXP_SCB_STATACK_FCP 0x01 /* Flow Control Pause */
86 #define FXP_SCB_STATACK_ER 0x02 /* Early Receive */
87 #define FXP_SCB_STATACK_SWI 0x04
88 #define FXP_SCB_STATACK_MDI 0x08
89 #define FXP_SCB_STATACK_RNR 0x10
90 #define FXP_SCB_STATACK_CNA 0x20
91 #define FXP_SCB_STATACK_FR 0x40
92 #define FXP_SCB_STATACK_CXTNO 0x80
94 #define FXP_SCB_COMMAND_CU_NOP 0x00
95 #define FXP_SCB_COMMAND_CU_START 0x10
96 #define FXP_SCB_COMMAND_CU_RESUME 0x20
97 #define FXP_SCB_COMMAND_CU_DUMP_ADR 0x40
98 #define FXP_SCB_COMMAND_CU_DUMP 0x50
99 #define FXP_SCB_COMMAND_CU_BASE 0x60
100 #define FXP_SCB_COMMAND_CU_DUMPRESET 0x70
102 #define FXP_SCB_COMMAND_RU_NOP 0
103 #define FXP_SCB_COMMAND_RU_START 1
104 #define FXP_SCB_COMMAND_RU_RESUME 2
105 #define FXP_SCB_COMMAND_RU_ABORT 4
106 #define FXP_SCB_COMMAND_RU_LOADHDS 5
107 #define FXP_SCB_COMMAND_RU_BASE 6
108 #define FXP_SCB_COMMAND_RU_RBDRESUME 7
111 * Command block definitions
115 volatile u_int16_t cb_status;
116 volatile u_int16_t cb_command;
117 volatile u_int32_t link_addr;
121 volatile u_int16_t cb_status;
122 volatile u_int16_t cb_command;
123 volatile u_int32_t link_addr;
124 volatile u_int8_t macaddr[6];
126 /* I hate bit-fields :-( */
127 struct fxp_cb_config {
129 volatile u_int16_t cb_status;
130 volatile u_int16_t cb_command;
131 volatile u_int32_t link_addr;
132 volatile u_int byte_count:6,
134 volatile u_int rx_fifo_limit:4,
137 volatile u_int8_t adaptive_ifs;
138 volatile u_int mwi_enable:1, /* 8,9 */
139 type_enable:1, /* 8,9 */
140 read_align_en:1, /* 8,9 */
141 end_wr_on_cl:1, /* 8,9 */
143 volatile u_int rx_dma_bytecount:7,
145 volatile u_int tx_dma_bytecount:7,
147 volatile u_int late_scb:1, /* 7 */
148 direct_dma_dis:1, /* 8,9 */
149 tno_int_or_tco_en:1, /* 7,9 */
151 ext_txcb_dis:1, /* 8,9 */
152 ext_stats_dis:1, /* 8,9 */
155 volatile u_int disc_short_rx:1,
158 two_frames:1, /* 8,9 */
160 volatile u_int mediatype:1, /* 7 */
162 csma_dis:1; /* 8,9 */
163 volatile u_int tcp_udp_cksum:1, /* 9 */
165 vlan_tco:1, /* 8,9 */
166 link_wake_en:1, /* 8,9 */
167 arp_wake_en:1, /* 8 */
168 mc_wake_en:1; /* 8 */
173 volatile u_int linear_priority:3, /* 7 */
175 volatile u_int linear_pri_mode:1, /* 7 */
180 volatile u_int promiscuous:1,
182 wait_after_win:1, /* 8,9 */
184 ignore_ul:1, /* 8,9 */
188 volatile u_int fc_delay_lsb:8; /* 8,9 */
189 volatile u_int fc_delay_msb:8; /* 8,9 */
190 volatile u_int stripping:1,
193 long_rx_en:1, /* 8,9 */
194 pri_fc_thresh:3, /* 8,9 */
196 volatile u_int ia_wake_en:1, /* 8 */
197 magic_pkt_dis:1, /* 8,9,!9ER */
198 tx_fc_dis:1, /* 8,9 */
199 rx_fc_restop:1, /* 8,9 */
200 rx_fc_restart:1, /* 8,9 */
201 fc_filter:1, /* 8,9 */
205 pri_fc_loc:1, /* 8,9 */
215 struct fxp_cb_tx *next;
216 struct mbuf *mb_head;
217 volatile u_int16_t cb_status;
218 volatile u_int16_t cb_command;
219 volatile u_int32_t link_addr;
220 volatile u_int16_t mc_cnt;
221 volatile u_int8_t mc_addr[MAXMCADDR][6];
224 #define MAXUCODESIZE 192
225 struct fxp_cb_ucode {
228 u_int16_t cb_command;
230 u_int32_t ucode[MAXUCODESIZE];
234 * Number of DMA segments in a TxCB. Note that this is carefully
235 * chosen to make the total struct size an even power of two. It's
236 * critical that no TxCB be split across a page boundry since
237 * no attempt is made to allocate physically contiguous memory.
239 #define FXP_TXCB_FIXED 16 /* cb_status .. tbd_number */
240 #define FXP_NTXSEG ((256 - (sizeof(void *) * 2) - FXP_TXCB_FIXED) / 8)
243 volatile u_int32_t tb_addr;
244 volatile u_int32_t tb_size;
247 struct fxp_cb_tx *next;
248 struct mbuf *mb_head;
249 volatile u_int16_t cb_status;
250 volatile u_int16_t cb_command;
251 volatile u_int32_t link_addr;
252 volatile u_int32_t tbd_array_addr;
253 volatile u_int16_t byte_count;
254 volatile u_int8_t tx_threshold;
255 volatile u_int8_t tbd_number;
257 * The following structure isn't actually part of the TxCB,
258 * unless the extended TxCB feature is being used. In this
259 * case, the first two elements of the structure below are
260 * fetched along with the TxCB.
262 volatile struct fxp_tbd tbd[FXP_NTXSEG];
266 * Control Block (CB) definitions
270 #define FXP_CB_STATUS_OK 0x2000
271 #define FXP_CB_STATUS_C 0x8000
273 #define FXP_CB_COMMAND_NOP 0x0
274 #define FXP_CB_COMMAND_IAS 0x1
275 #define FXP_CB_COMMAND_CONFIG 0x2
276 #define FXP_CB_COMMAND_MCAS 0x3
277 #define FXP_CB_COMMAND_XMIT 0x4
278 #define FXP_CB_COMMAND_UCODE 0x5
279 #define FXP_CB_COMMAND_DUMP 0x6
280 #define FXP_CB_COMMAND_DIAG 0x7
282 #define FXP_CB_COMMAND_SF 0x0008 /* simple/flexible mode */
283 #define FXP_CB_COMMAND_I 0x2000 /* generate interrupt on completion */
284 #define FXP_CB_COMMAND_S 0x4000 /* suspend on completion */
285 #define FXP_CB_COMMAND_EL 0x8000 /* end of list */
292 volatile u_int16_t rfa_status;
293 volatile u_int16_t rfa_control;
294 volatile u_int8_t link_addr[4];
295 volatile u_int8_t rbd_addr[4];
296 volatile u_int16_t actual_size;
297 volatile u_int16_t size;
299 #define FXP_RFA_STATUS_RCOL 0x0001 /* receive collision */
300 #define FXP_RFA_STATUS_IAMATCH 0x0002 /* 0 = matches station address */
301 #define FXP_RFA_STATUS_S4 0x0010 /* receive error from PHY */
302 #define FXP_RFA_STATUS_TL 0x0020 /* type/length */
303 #define FXP_RFA_STATUS_FTS 0x0080 /* frame too short */
304 #define FXP_RFA_STATUS_OVERRUN 0x0100 /* DMA overrun */
305 #define FXP_RFA_STATUS_RNR 0x0200 /* no resources */
306 #define FXP_RFA_STATUS_ALIGN 0x0400 /* alignment error */
307 #define FXP_RFA_STATUS_CRC 0x0800 /* CRC error */
308 #define FXP_RFA_STATUS_OK 0x2000 /* packet received okay */
309 #define FXP_RFA_STATUS_C 0x8000 /* packet reception complete */
310 #define FXP_RFA_CONTROL_SF 0x08 /* simple/flexible memory mode */
311 #define FXP_RFA_CONTROL_H 0x10 /* header RFD */
312 #define FXP_RFA_CONTROL_S 0x4000 /* suspend after reception */
313 #define FXP_RFA_CONTROL_EL 0x8000 /* end of list */
316 * Statistics dump area definitions
319 volatile u_int32_t tx_good;
320 volatile u_int32_t tx_maxcols;
321 volatile u_int32_t tx_latecols;
322 volatile u_int32_t tx_underruns;
323 volatile u_int32_t tx_lostcrs;
324 volatile u_int32_t tx_deffered;
325 volatile u_int32_t tx_single_collisions;
326 volatile u_int32_t tx_multiple_collisions;
327 volatile u_int32_t tx_total_collisions;
328 volatile u_int32_t rx_good;
329 volatile u_int32_t rx_crc_errors;
330 volatile u_int32_t rx_alignment_errors;
331 volatile u_int32_t rx_rnr_errors;
332 volatile u_int32_t rx_overrun_errors;
333 volatile u_int32_t rx_cdt_errors;
334 volatile u_int32_t rx_shortframes;
335 volatile u_int32_t completion_status;
337 #define FXP_STATS_DUMP_COMPLETE 0xa005
338 #define FXP_STATS_DR_COMPLETE 0xa007
341 * Serial EEPROM control register bits
343 #define FXP_EEPROM_EESK 0x01 /* shift clock */
344 #define FXP_EEPROM_EECS 0x02 /* chip select */
345 #define FXP_EEPROM_EEDI 0x04 /* data in */
346 #define FXP_EEPROM_EEDO 0x08 /* data out */
349 * Serial EEPROM opcodes, including start bit
351 #define FXP_EEPROM_OPC_ERASE 0x4
352 #define FXP_EEPROM_OPC_WRITE 0x5
353 #define FXP_EEPROM_OPC_READ 0x6
356 * Management Data Interface opcodes
358 #define FXP_MDI_WRITE 0x1
359 #define FXP_MDI_READ 0x2
364 #define FXP_PHY_DEVICE_MASK 0x3f00
365 #define FXP_PHY_SERIAL_ONLY 0x8000
366 #define FXP_PHY_NONE 0
367 #define FXP_PHY_82553A 1
368 #define FXP_PHY_82553C 2
369 #define FXP_PHY_82503 3
370 #define FXP_PHY_DP83840 4
371 #define FXP_PHY_80C240 5
372 #define FXP_PHY_80C24 6
373 #define FXP_PHY_82555 7
374 #define FXP_PHY_DP83840A 10
375 #define FXP_PHY_82555B 11
378 * Chip revision values.
380 #define FXP_REV_82557 1 /* catchall 82557 chip type */
381 #define FXP_REV_82558_A4 4 /* 82558 A4 stepping */
382 #define FXP_REV_82558_B0 5 /* 82558 B0 stepping */
383 #define FXP_REV_82559_A0 8 /* 82559 A0 stepping */
384 #define FXP_REV_82559S_A 9 /* 82559S A stepping */
385 #define FXP_REV_82550 12
386 #define FXP_REV_82550_C 13 /* 82550 C stepping */