2 * Copyright (C) 2001 Eduardo Horvath.
3 * Copyright (c) 2001-2003 Thomas Moestl
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * from: NetBSD: gem.c,v 1.21 2002/06/01 23:50:58 lukem Exp
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
34 * Driver for Sun GEM ethernet controllers.
41 #if 0 /* XXX: In case of emergency, re-enable this. */
42 #define GEM_RINT_TIMEOUT
45 #include <sys/param.h>
46 #include <sys/systm.h>
48 #include <sys/callout.h>
49 #include <sys/endian.h>
51 #include <sys/malloc.h>
52 #include <sys/kernel.h>
54 #include <sys/module.h>
55 #include <sys/mutex.h>
56 #include <sys/socket.h>
57 #include <sys/sockio.h>
60 #include <net/ethernet.h>
62 #include <net/if_arp.h>
63 #include <net/if_dl.h>
64 #include <net/if_media.h>
65 #include <net/if_types.h>
66 #include <net/if_vlan_var.h>
68 #include <machine/bus.h>
70 #include <dev/mii/mii.h>
71 #include <dev/mii/miivar.h>
73 #include <dev/gem/if_gemreg.h>
74 #include <dev/gem/if_gemvar.h>
78 static void gem_start(struct ifnet *);
79 static void gem_start_locked(struct ifnet *);
80 static void gem_stop(struct ifnet *, int);
81 static int gem_ioctl(struct ifnet *, u_long, caddr_t);
82 static void gem_cddma_callback(void *, bus_dma_segment_t *, int, int);
83 static void gem_txdma_callback(void *, bus_dma_segment_t *, int,
85 static void gem_tick(void *);
86 static void gem_watchdog(struct ifnet *);
87 static void gem_init(void *);
88 static void gem_init_locked(struct gem_softc *sc);
89 static void gem_init_regs(struct gem_softc *sc);
90 static int gem_ringsize(int sz);
91 static int gem_meminit(struct gem_softc *);
92 static int gem_load_txmbuf(struct gem_softc *, struct mbuf *);
93 static void gem_mifinit(struct gem_softc *);
94 static int gem_bitwait(struct gem_softc *sc, bus_addr_t r,
95 u_int32_t clr, u_int32_t set);
96 static int gem_reset_rx(struct gem_softc *);
97 static int gem_reset_tx(struct gem_softc *);
98 static int gem_disable_rx(struct gem_softc *);
99 static int gem_disable_tx(struct gem_softc *);
100 static void gem_rxdrain(struct gem_softc *);
101 static int gem_add_rxbuf(struct gem_softc *, int);
102 static void gem_setladrf(struct gem_softc *);
104 struct mbuf *gem_get(struct gem_softc *, int, int);
105 static void gem_eint(struct gem_softc *, u_int);
106 static void gem_rint(struct gem_softc *);
107 #ifdef GEM_RINT_TIMEOUT
108 static void gem_rint_timeout(void *);
110 static void gem_tint(struct gem_softc *);
112 static void gem_power(int, void *);
115 devclass_t gem_devclass;
116 DRIVER_MODULE(miibus, gem, miibus_driver, miibus_devclass, 0, 0);
117 MODULE_DEPEND(gem, miibus, 1, 1, 1);
121 #define KTR_GEM KTR_CT2
124 #define GEM_NSEGS GEM_NTXDESC
129 * Attach a Gem interface to the system.
133 struct gem_softc *sc;
136 struct mii_softc *child;
140 ifp = sc->sc_ifp = if_alloc(IFT_ETHER);
144 callout_init_mtx(&sc->sc_tick_ch, &sc->sc_mtx, 0);
145 #ifdef GEM_RINT_TIMEOUT
146 callout_init_mtx(&sc->sc_rx_ch, &sc->sc_mtx, 0);
149 /* Make sure the chip is stopped. */
156 error = bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT,
157 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, GEM_NSEGS,
158 BUS_SPACE_MAXSIZE_32BIT, 0, NULL, NULL, &sc->sc_pdmatag);
162 error = bus_dma_tag_create(sc->sc_pdmatag, 1, 0,
163 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MAXBSIZE,
164 1, BUS_SPACE_MAXSIZE_32BIT, BUS_DMA_ALLOCNOW, NULL, NULL,
169 error = bus_dma_tag_create(sc->sc_pdmatag, 1, 0,
170 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
171 GEM_TD_BUFSIZE, GEM_NTXDESC, BUS_SPACE_MAXSIZE_32BIT,
172 BUS_DMA_ALLOCNOW, NULL, NULL, &sc->sc_tdmatag);
176 error = bus_dma_tag_create(sc->sc_pdmatag, PAGE_SIZE, 0,
177 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
178 sizeof(struct gem_control_data), 1,
179 sizeof(struct gem_control_data), BUS_DMA_ALLOCNOW,
180 busdma_lock_mutex, &sc->sc_mtx, &sc->sc_cdmatag);
185 * Allocate the control data structures, and create and load the
188 if ((error = bus_dmamem_alloc(sc->sc_cdmatag,
189 (void **)&sc->sc_control_data, 0, &sc->sc_cddmamap))) {
190 device_printf(sc->sc_dev, "unable to allocate control data,"
191 " error = %d\n", error);
196 if ((error = bus_dmamap_load(sc->sc_cdmatag, sc->sc_cddmamap,
197 sc->sc_control_data, sizeof(struct gem_control_data),
198 gem_cddma_callback, sc, 0)) != 0 || sc->sc_cddma == 0) {
199 device_printf(sc->sc_dev, "unable to load control data DMA "
200 "map, error = %d\n", error);
205 * Initialize the transmit job descriptors.
207 STAILQ_INIT(&sc->sc_txfreeq);
208 STAILQ_INIT(&sc->sc_txdirtyq);
211 * Create the transmit buffer DMA maps.
214 for (i = 0; i < GEM_TXQUEUELEN; i++) {
215 struct gem_txsoft *txs;
217 txs = &sc->sc_txsoft[i];
218 txs->txs_mbuf = NULL;
220 if ((error = bus_dmamap_create(sc->sc_tdmatag, 0,
221 &txs->txs_dmamap)) != 0) {
222 device_printf(sc->sc_dev, "unable to create tx DMA map "
223 "%d, error = %d\n", i, error);
226 STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q);
230 * Create the receive buffer DMA maps.
232 for (i = 0; i < GEM_NRXDESC; i++) {
233 if ((error = bus_dmamap_create(sc->sc_rdmatag, 0,
234 &sc->sc_rxsoft[i].rxs_dmamap)) != 0) {
235 device_printf(sc->sc_dev, "unable to create rx DMA map "
236 "%d, error = %d\n", i, error);
239 sc->sc_rxsoft[i].rxs_mbuf = NULL;
244 if ((error = mii_phy_probe(sc->sc_dev, &sc->sc_miibus, gem_mediachange,
245 gem_mediastatus)) != 0) {
246 device_printf(sc->sc_dev, "phy probe failed: %d\n", error);
249 sc->sc_mii = device_get_softc(sc->sc_miibus);
252 * From this point forward, the attachment cannot fail. A failure
253 * before this point releases all resources that may have been
257 /* Get RX FIFO size */
258 sc->sc_rxfifosize = 64 *
259 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_RX_FIFO_SIZE);
261 /* Get TX FIFO size */
262 v = bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_TX_FIFO_SIZE);
263 device_printf(sc->sc_dev, "%ukB RX FIFO, %ukB TX FIFO\n",
264 sc->sc_rxfifosize / 1024, v / 16);
266 /* Initialize ifnet structure. */
268 if_initname(ifp, device_get_name(sc->sc_dev),
269 device_get_unit(sc->sc_dev));
270 ifp->if_mtu = ETHERMTU;
271 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
272 ifp->if_start = gem_start;
273 ifp->if_ioctl = gem_ioctl;
274 ifp->if_watchdog = gem_watchdog;
275 ifp->if_init = gem_init;
276 ifp->if_snd.ifq_maxlen = GEM_TXQUEUELEN;
278 * Walk along the list of attached MII devices and
279 * establish an `MII instance' to `phy number'
280 * mapping. We'll use this mapping in media change
281 * requests to determine which phy to use to program
282 * the MIF configuration register.
284 for (child = LIST_FIRST(&sc->sc_mii->mii_phys); child != NULL;
285 child = LIST_NEXT(child, mii_list)) {
287 * Note: we support just two PHYs: the built-in
288 * internal device and an external on the MII
291 if (child->mii_phy > 1 || child->mii_inst > 1) {
292 device_printf(sc->sc_dev, "cannot accomodate "
293 "MII device %s at phy %d, instance %d\n",
294 device_get_name(child->mii_dev),
295 child->mii_phy, child->mii_inst);
299 sc->sc_phys[child->mii_inst] = child->mii_phy;
303 * Now select and activate the PHY we will use.
305 * The order of preference is External (MDI1),
306 * Internal (MDI0), Serial Link (no MII).
308 if (sc->sc_phys[1]) {
310 printf("using external phy\n");
312 sc->sc_mif_config |= GEM_MIF_CONFIG_PHY_SEL;
315 printf("using internal phy\n");
317 sc->sc_mif_config &= ~GEM_MIF_CONFIG_PHY_SEL;
319 bus_space_write_4(sc->sc_bustag, sc->sc_h, GEM_MIF_CONFIG,
321 /* Attach the interface. */
322 ether_ifattach(ifp, sc->sc_enaddr);
326 * Add a suspend hook to make sure we come back up after a
329 sc->sc_powerhook = powerhook_establish(gem_power, sc);
330 if (sc->sc_powerhook == NULL)
331 device_printf(sc->sc_dev, "WARNING: unable to establish power "
336 * Tell the upper layer(s) we support long frames.
338 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
339 ifp->if_capabilities |= IFCAP_VLAN_MTU;
340 ifp->if_capenable |= IFCAP_VLAN_MTU;
345 * Free any resources we've allocated during the failed attach
346 * attempt. Do this in reverse order and fall through.
349 for (i = 0; i < GEM_NRXDESC; i++) {
350 if (sc->sc_rxsoft[i].rxs_dmamap != NULL)
351 bus_dmamap_destroy(sc->sc_rdmatag,
352 sc->sc_rxsoft[i].rxs_dmamap);
355 for (i = 0; i < GEM_TXQUEUELEN; i++) {
356 if (sc->sc_txsoft[i].txs_dmamap != NULL)
357 bus_dmamap_destroy(sc->sc_tdmatag,
358 sc->sc_txsoft[i].txs_dmamap);
360 bus_dmamap_unload(sc->sc_cdmatag, sc->sc_cddmamap);
362 bus_dmamem_free(sc->sc_cdmatag, sc->sc_control_data,
365 bus_dma_tag_destroy(sc->sc_cdmatag);
367 bus_dma_tag_destroy(sc->sc_tdmatag);
369 bus_dma_tag_destroy(sc->sc_rdmatag);
371 bus_dma_tag_destroy(sc->sc_pdmatag);
379 struct gem_softc *sc;
381 struct ifnet *ifp = sc->sc_ifp;
387 callout_drain(&sc->sc_tick_ch);
388 #ifdef GEM_RINT_TIMEOUT
389 callout_drain(&sc->sc_rx_ch);
393 device_delete_child(sc->sc_dev, sc->sc_miibus);
395 for (i = 0; i < GEM_NRXDESC; i++) {
396 if (sc->sc_rxsoft[i].rxs_dmamap != NULL)
397 bus_dmamap_destroy(sc->sc_rdmatag,
398 sc->sc_rxsoft[i].rxs_dmamap);
400 for (i = 0; i < GEM_TXQUEUELEN; i++) {
401 if (sc->sc_txsoft[i].txs_dmamap != NULL)
402 bus_dmamap_destroy(sc->sc_tdmatag,
403 sc->sc_txsoft[i].txs_dmamap);
405 GEM_CDSYNC(sc, BUS_DMASYNC_POSTREAD);
406 GEM_CDSYNC(sc, BUS_DMASYNC_POSTWRITE);
407 bus_dmamap_unload(sc->sc_cdmatag, sc->sc_cddmamap);
408 bus_dmamem_free(sc->sc_cdmatag, sc->sc_control_data,
410 bus_dma_tag_destroy(sc->sc_cdmatag);
411 bus_dma_tag_destroy(sc->sc_tdmatag);
412 bus_dma_tag_destroy(sc->sc_rdmatag);
413 bus_dma_tag_destroy(sc->sc_pdmatag);
418 struct gem_softc *sc;
420 struct ifnet *ifp = sc->sc_ifp;
429 struct gem_softc *sc;
431 struct ifnet *ifp = sc->sc_ifp;
435 * On resume all registers have to be initialized again like
439 if (ifp->if_flags & IFF_UP)
445 gem_cddma_callback(xsc, segs, nsegs, error)
447 bus_dma_segment_t *segs;
451 struct gem_softc *sc = (struct gem_softc *)xsc;
456 /* can't happen... */
457 panic("gem_cddma_callback: bad control buffer segment count");
459 sc->sc_cddma = segs[0].ds_addr;
463 gem_txdma_callback(xsc, segs, nsegs, totsz, error)
465 bus_dma_segment_t *segs;
470 struct gem_txdma *txd = (struct gem_txdma *)xsc;
471 struct gem_softc *sc = txd->txd_sc;
472 struct gem_txsoft *txs = txd->txd_txs;
480 * Ensure we have enough descriptors free to describe
481 * the packet. Note, we always reserve one descriptor
482 * at the end of the ring as a termination point, to
483 * prevent wrap-around.
485 if (nsegs > sc->sc_txfree - 1) {
486 txs->txs_ndescs = -1;
489 txs->txs_ndescs = nsegs;
491 nexttx = txs->txs_firstdesc;
493 * Initialize the transmit descriptors.
495 for (seg = 0; seg < nsegs;
496 seg++, nexttx = GEM_NEXTTX(nexttx)) {
498 CTR5(KTR_GEM, "txdma_cb: mapping seg %d (txd %d), len "
499 "%lx, addr %#lx (%#lx)", seg, nexttx,
500 segs[seg].ds_len, segs[seg].ds_addr,
501 GEM_DMA_WRITE(sc, segs[seg].ds_addr));
504 if (segs[seg].ds_len == 0)
506 sc->sc_txdescs[nexttx].gd_addr =
507 GEM_DMA_WRITE(sc, segs[seg].ds_addr);
508 KASSERT(segs[seg].ds_len < GEM_TD_BUFSIZE,
509 ("gem_txdma_callback: segment size too large!"));
510 flags = segs[seg].ds_len & GEM_TD_BUFSIZE;
513 CTR2(KTR_GEM, "txdma_cb: start of packet at seg %d, "
514 "tx %d", seg, nexttx);
516 flags |= GEM_TD_START_OF_PACKET;
517 if (++sc->sc_txwin > GEM_NTXSEGS * 2 / 3) {
519 flags |= GEM_TD_INTERRUPT_ME;
522 if (len + segs[seg].ds_len == totsz) {
524 CTR2(KTR_GEM, "txdma_cb: end of packet at seg %d, "
525 "tx %d", seg, nexttx);
527 flags |= GEM_TD_END_OF_PACKET;
529 sc->sc_txdescs[nexttx].gd_flags = GEM_DMA_WRITE(sc, flags);
530 txs->txs_lastdesc = nexttx;
531 len += segs[seg].ds_len;
533 KASSERT((flags & GEM_TD_END_OF_PACKET) != 0,
534 ("gem_txdma_callback: missed end of packet!"));
541 struct gem_softc *sc = arg;
543 GEM_LOCK_ASSERT(sc, MA_OWNED);
544 mii_tick(sc->sc_mii);
546 callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc);
550 gem_bitwait(sc, r, clr, set)
551 struct gem_softc *sc;
559 for (i = TRIES; i--; DELAY(100)) {
560 reg = bus_space_read_4(sc->sc_bustag, sc->sc_h, r);
561 if ((r & clr) == 0 && (r & set) == set)
569 struct gem_softc *sc;
571 bus_space_tag_t t = sc->sc_bustag;
572 bus_space_handle_t h = sc->sc_h;
575 CTR1(KTR_GEM, "%s: gem_reset", device_get_name(sc->sc_dev));
580 /* Do a full reset */
581 bus_space_write_4(t, h, GEM_RESET, GEM_RESET_RX | GEM_RESET_TX);
582 if (!gem_bitwait(sc, GEM_RESET, GEM_RESET_RX | GEM_RESET_TX, 0))
583 device_printf(sc->sc_dev, "cannot reset device\n");
590 * Drain the receive queue.
594 struct gem_softc *sc;
596 struct gem_rxsoft *rxs;
599 for (i = 0; i < GEM_NRXDESC; i++) {
600 rxs = &sc->sc_rxsoft[i];
601 if (rxs->rxs_mbuf != NULL) {
602 bus_dmamap_sync(sc->sc_rdmatag, rxs->rxs_dmamap,
603 BUS_DMASYNC_POSTREAD);
604 bus_dmamap_unload(sc->sc_rdmatag, rxs->rxs_dmamap);
605 m_freem(rxs->rxs_mbuf);
606 rxs->rxs_mbuf = NULL;
612 * Reset the whole thing.
615 gem_stop(ifp, disable)
619 struct gem_softc *sc = (struct gem_softc *)ifp->if_softc;
620 struct gem_txsoft *txs;
623 CTR1(KTR_GEM, "%s: gem_stop", device_get_name(sc->sc_dev));
626 callout_stop(&sc->sc_tick_ch);
627 #ifdef GEM_RINT_TIMEOUT
628 callout_stop(&sc->sc_rx_ch);
631 /* XXX - Should we reset these instead? */
636 * Release any queued transmit buffers.
638 while ((txs = STAILQ_FIRST(&sc->sc_txdirtyq)) != NULL) {
639 STAILQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q);
640 if (txs->txs_ndescs != 0) {
641 bus_dmamap_sync(sc->sc_tdmatag, txs->txs_dmamap,
642 BUS_DMASYNC_POSTWRITE);
643 bus_dmamap_unload(sc->sc_tdmatag, txs->txs_dmamap);
644 if (txs->txs_mbuf != NULL) {
645 m_freem(txs->txs_mbuf);
646 txs->txs_mbuf = NULL;
649 STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q);
656 * Mark the interface down and cancel the watchdog timer.
658 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
667 struct gem_softc *sc;
669 bus_space_tag_t t = sc->sc_bustag;
670 bus_space_handle_t h = sc->sc_h;
673 * Resetting while DMA is in progress can cause a bus hang, so we
677 bus_space_write_4(t, h, GEM_RX_CONFIG, 0);
678 /* Wait till it finishes */
679 if (!gem_bitwait(sc, GEM_RX_CONFIG, 1, 0))
680 device_printf(sc->sc_dev, "cannot disable read dma\n");
682 /* Wait 5ms extra. */
685 /* Finally, reset the ERX */
686 bus_space_write_4(t, h, GEM_RESET, GEM_RESET_RX);
687 /* Wait till it finishes */
688 if (!gem_bitwait(sc, GEM_RESET, GEM_RESET_TX, 0)) {
689 device_printf(sc->sc_dev, "cannot reset receiver\n");
697 * Reset the transmitter
701 struct gem_softc *sc;
703 bus_space_tag_t t = sc->sc_bustag;
704 bus_space_handle_t h = sc->sc_h;
708 * Resetting while DMA is in progress can cause a bus hang, so we
712 bus_space_write_4(t, h, GEM_TX_CONFIG, 0);
713 /* Wait till it finishes */
714 if (!gem_bitwait(sc, GEM_TX_CONFIG, 1, 0))
715 device_printf(sc->sc_dev, "cannot disable read dma\n");
717 /* Wait 5ms extra. */
720 /* Finally, reset the ETX */
721 bus_space_write_4(t, h, GEM_RESET, GEM_RESET_TX);
722 /* Wait till it finishes */
723 for (i = TRIES; i--; DELAY(100))
724 if ((bus_space_read_4(t, h, GEM_RESET) & GEM_RESET_TX) == 0)
726 if (!gem_bitwait(sc, GEM_RESET, GEM_RESET_TX, 0)) {
727 device_printf(sc->sc_dev, "cannot reset receiver\n");
738 struct gem_softc *sc;
740 bus_space_tag_t t = sc->sc_bustag;
741 bus_space_handle_t h = sc->sc_h;
744 /* Flip the enable bit */
745 cfg = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG);
746 cfg &= ~GEM_MAC_RX_ENABLE;
747 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, cfg);
749 /* Wait for it to finish */
750 return (gem_bitwait(sc, GEM_MAC_RX_CONFIG, GEM_MAC_RX_ENABLE, 0));
754 * disable transmitter.
758 struct gem_softc *sc;
760 bus_space_tag_t t = sc->sc_bustag;
761 bus_space_handle_t h = sc->sc_h;
764 /* Flip the enable bit */
765 cfg = bus_space_read_4(t, h, GEM_MAC_TX_CONFIG);
766 cfg &= ~GEM_MAC_TX_ENABLE;
767 bus_space_write_4(t, h, GEM_MAC_TX_CONFIG, cfg);
769 /* Wait for it to finish */
770 return (gem_bitwait(sc, GEM_MAC_TX_CONFIG, GEM_MAC_TX_ENABLE, 0));
774 * Initialize interface.
778 struct gem_softc *sc;
780 struct gem_rxsoft *rxs;
784 * Initialize the transmit descriptor ring.
786 for (i = 0; i < GEM_NTXDESC; i++) {
787 sc->sc_txdescs[i].gd_flags = 0;
788 sc->sc_txdescs[i].gd_addr = 0;
790 sc->sc_txfree = GEM_MAXTXFREE;
795 * Initialize the receive descriptor and receive job
798 for (i = 0; i < GEM_NRXDESC; i++) {
799 rxs = &sc->sc_rxsoft[i];
800 if (rxs->rxs_mbuf == NULL) {
801 if ((error = gem_add_rxbuf(sc, i)) != 0) {
802 device_printf(sc->sc_dev, "unable to "
803 "allocate or map rx buffer %d, error = "
806 * XXX Should attempt to run with fewer receive
807 * XXX buffers instead of just failing.
813 GEM_INIT_RXDESC(sc, i);
816 GEM_CDSYNC(sc, BUS_DMASYNC_PREWRITE);
817 GEM_CDSYNC(sc, BUS_DMASYNC_PREREAD);
845 v = GEM_RING_SZ_1024;
848 v = GEM_RING_SZ_2048;
851 v = GEM_RING_SZ_4096;
854 v = GEM_RING_SZ_8192;
857 printf("gem: invalid Receive Descriptor ring size\n");
867 struct gem_softc *sc = (struct gem_softc *)xsc;
875 * Initialization of interface; set up initialization block
876 * and transmit/receive descriptor rings.
880 struct gem_softc *sc;
882 struct ifnet *ifp = sc->sc_ifp;
883 bus_space_tag_t t = sc->sc_bustag;
884 bus_space_handle_t h = sc->sc_h;
887 GEM_LOCK_ASSERT(sc, MA_OWNED);
890 CTR1(KTR_GEM, "%s: gem_init: calling stop", device_get_name(sc->sc_dev));
893 * Initialization sequence. The numbered steps below correspond
894 * to the sequence outlined in section 6.3.5.1 in the Ethernet
895 * Channel Engine manual (part of the PCIO manual).
896 * See also the STP2002-STQ document from Sun Microsystems.
899 /* step 1 & 2. Reset the Ethernet Channel */
900 gem_stop(sc->sc_ifp, 0);
903 CTR1(KTR_GEM, "%s: gem_init: restarting", device_get_name(sc->sc_dev));
906 /* Re-initialize the MIF */
909 /* step 3. Setup data structures in host memory */
912 /* step 4. TX MAC registers & counters */
915 /* step 5. RX MAC registers & counters */
918 /* step 6 & 7. Program Descriptor Ring Base Addresses */
919 /* NOTE: we use only 32-bit DMA addresses here. */
920 bus_space_write_4(t, h, GEM_TX_RING_PTR_HI, 0);
921 bus_space_write_4(t, h, GEM_TX_RING_PTR_LO, GEM_CDTXADDR(sc, 0));
923 bus_space_write_4(t, h, GEM_RX_RING_PTR_HI, 0);
924 bus_space_write_4(t, h, GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0));
926 CTR3(KTR_GEM, "loading rx ring %lx, tx ring %lx, cddma %lx",
927 GEM_CDRXADDR(sc, 0), GEM_CDTXADDR(sc, 0), sc->sc_cddma);
930 /* step 8. Global Configuration & Interrupt Mask */
931 bus_space_write_4(t, h, GEM_INTMASK,
934 GEM_INTR_RX_DONE|GEM_INTR_RX_NOBUF|
935 GEM_INTR_RX_TAG_ERR|GEM_INTR_PCS|
936 GEM_INTR_MAC_CONTROL|GEM_INTR_MIF|
938 bus_space_write_4(t, h, GEM_MAC_RX_MASK,
939 GEM_MAC_RX_DONE|GEM_MAC_RX_FRAME_CNT);
940 bus_space_write_4(t, h, GEM_MAC_TX_MASK, 0xffff); /* XXXX */
941 bus_space_write_4(t, h, GEM_MAC_CONTROL_MASK, 0); /* XXXX */
943 /* step 9. ETX Configuration: use mostly default values */
946 v = gem_ringsize(GEM_NTXDESC /*XXX*/);
947 bus_space_write_4(t, h, GEM_TX_CONFIG,
948 v|GEM_TX_CONFIG_TXDMA_EN|
949 ((0x400<<10)&GEM_TX_CONFIG_TXFIFO_TH));
951 /* step 10. ERX Configuration */
953 /* Encode Receive Descriptor ring size: four possible values */
954 v = gem_ringsize(GEM_NRXDESC /*XXX*/);
957 bus_space_write_4(t, h, GEM_RX_CONFIG,
958 v|(GEM_THRSH_1024<<GEM_RX_CONFIG_FIFO_THRS_SHIFT)|
959 (2<<GEM_RX_CONFIG_FBOFF_SHFT)|GEM_RX_CONFIG_RXDMA_EN|
960 (0<<GEM_RX_CONFIG_CXM_START_SHFT));
962 * The following value is for an OFF Threshold of about 3/4 full
963 * and an ON Threshold of 1/4 full.
965 bus_space_write_4(t, h, GEM_RX_PAUSE_THRESH,
966 (3 * sc->sc_rxfifosize / 256) |
967 ( (sc->sc_rxfifosize / 256) << 12));
968 bus_space_write_4(t, h, GEM_RX_BLANKING, (6<<12)|6);
970 /* step 11. Configure Media */
971 mii_mediachg(sc->sc_mii);
973 /* step 12. RX_MAC Configuration Register */
974 v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG);
975 v |= GEM_MAC_RX_ENABLE;
976 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v);
978 /* step 14. Issue Transmit Pending command */
980 /* step 15. Give the reciever a swift kick */
981 bus_space_write_4(t, h, GEM_RX_KICK, GEM_NRXDESC-4);
983 /* Start the one second timer. */
984 callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc);
986 ifp->if_drv_flags |= IFF_DRV_RUNNING;
987 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
989 sc->sc_ifflags = ifp->if_flags;
993 gem_load_txmbuf(sc, m0)
994 struct gem_softc *sc;
997 struct gem_txdma txd;
998 struct gem_txsoft *txs;
1001 /* Get a work queue entry. */
1002 if ((txs = STAILQ_FIRST(&sc->sc_txfreeq)) == NULL) {
1003 /* Ran out of descriptors. */
1008 txs->txs_firstdesc = sc->sc_txnext;
1009 error = bus_dmamap_load_mbuf(sc->sc_tdmatag, txs->txs_dmamap, m0,
1010 gem_txdma_callback, &txd, BUS_DMA_NOWAIT);
1013 if (txs->txs_ndescs == -1) {
1018 /* Sync the DMA map. */
1019 bus_dmamap_sync(sc->sc_tdmatag, txs->txs_dmamap,
1020 BUS_DMASYNC_PREWRITE);
1023 CTR3(KTR_GEM, "load_mbuf: setting firstdesc=%d, lastdesc=%d, "
1024 "ndescs=%d", txs->txs_firstdesc, txs->txs_lastdesc,
1027 STAILQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q);
1028 STAILQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q);
1031 sc->sc_txnext = GEM_NEXTTX(txs->txs_lastdesc);
1032 sc->sc_txfree -= txs->txs_ndescs;
1037 CTR1(KTR_GEM, "gem_load_txmbuf failed (%d)", error);
1039 bus_dmamap_unload(sc->sc_tdmatag, txs->txs_dmamap);
1045 struct gem_softc *sc;
1047 bus_space_tag_t t = sc->sc_bustag;
1048 bus_space_handle_t h = sc->sc_h;
1049 const u_char *laddr = IFP2ENADDR(sc->sc_ifp);
1052 /* These regs are not cleared on reset */
1053 if (!sc->sc_inited) {
1055 /* Wooo. Magic values. */
1056 bus_space_write_4(t, h, GEM_MAC_IPG0, 0);
1057 bus_space_write_4(t, h, GEM_MAC_IPG1, 8);
1058 bus_space_write_4(t, h, GEM_MAC_IPG2, 4);
1060 bus_space_write_4(t, h, GEM_MAC_MAC_MIN_FRAME, ETHER_MIN_LEN);
1061 /* Max frame and max burst size */
1062 bus_space_write_4(t, h, GEM_MAC_MAC_MAX_FRAME,
1063 (ETHER_MAX_LEN + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN) |
1066 bus_space_write_4(t, h, GEM_MAC_PREAMBLE_LEN, 0x7);
1067 bus_space_write_4(t, h, GEM_MAC_JAM_SIZE, 0x4);
1068 bus_space_write_4(t, h, GEM_MAC_ATTEMPT_LIMIT, 0x10);
1070 bus_space_write_4(t, h, GEM_MAC_CONTROL_TYPE, 0x8088);
1071 bus_space_write_4(t, h, GEM_MAC_RANDOM_SEED,
1072 ((laddr[5]<<8)|laddr[4])&0x3ff);
1074 /* Secondary MAC addr set to 0:0:0:0:0:0 */
1075 bus_space_write_4(t, h, GEM_MAC_ADDR3, 0);
1076 bus_space_write_4(t, h, GEM_MAC_ADDR4, 0);
1077 bus_space_write_4(t, h, GEM_MAC_ADDR5, 0);
1079 /* MAC control addr set to 01:80:c2:00:00:01 */
1080 bus_space_write_4(t, h, GEM_MAC_ADDR6, 0x0001);
1081 bus_space_write_4(t, h, GEM_MAC_ADDR7, 0xc200);
1082 bus_space_write_4(t, h, GEM_MAC_ADDR8, 0x0180);
1084 /* MAC filter addr set to 0:0:0:0:0:0 */
1085 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER0, 0);
1086 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER1, 0);
1087 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER2, 0);
1089 bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK1_2, 0);
1090 bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK0, 0);
1095 /* Counters need to be zeroed */
1096 bus_space_write_4(t, h, GEM_MAC_NORM_COLL_CNT, 0);
1097 bus_space_write_4(t, h, GEM_MAC_FIRST_COLL_CNT, 0);
1098 bus_space_write_4(t, h, GEM_MAC_EXCESS_COLL_CNT, 0);
1099 bus_space_write_4(t, h, GEM_MAC_LATE_COLL_CNT, 0);
1100 bus_space_write_4(t, h, GEM_MAC_DEFER_TMR_CNT, 0);
1101 bus_space_write_4(t, h, GEM_MAC_PEAK_ATTEMPTS, 0);
1102 bus_space_write_4(t, h, GEM_MAC_RX_FRAME_COUNT, 0);
1103 bus_space_write_4(t, h, GEM_MAC_RX_LEN_ERR_CNT, 0);
1104 bus_space_write_4(t, h, GEM_MAC_RX_ALIGN_ERR, 0);
1105 bus_space_write_4(t, h, GEM_MAC_RX_CRC_ERR_CNT, 0);
1106 bus_space_write_4(t, h, GEM_MAC_RX_CODE_VIOL, 0);
1108 /* Un-pause stuff */
1110 bus_space_write_4(t, h, GEM_MAC_SEND_PAUSE_CMD, 0x1BF0);
1112 bus_space_write_4(t, h, GEM_MAC_SEND_PAUSE_CMD, 0);
1116 * Set the station address.
1118 bus_space_write_4(t, h, GEM_MAC_ADDR0, (laddr[4]<<8)|laddr[5]);
1119 bus_space_write_4(t, h, GEM_MAC_ADDR1, (laddr[2]<<8)|laddr[3]);
1120 bus_space_write_4(t, h, GEM_MAC_ADDR2, (laddr[0]<<8)|laddr[1]);
1123 * Enable MII outputs. Enable GMII if there is a gigabit PHY.
1125 sc->sc_mif_config = bus_space_read_4(t, h, GEM_MIF_CONFIG);
1126 v = GEM_MAC_XIF_TX_MII_ENA;
1127 if (sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) {
1128 v |= GEM_MAC_XIF_FDPLX_LED;
1129 if (sc->sc_flags & GEM_GIGABIT)
1130 v |= GEM_MAC_XIF_GMII_MODE;
1132 bus_space_write_4(t, h, GEM_MAC_XIF_CONFIG, v);
1139 struct gem_softc *sc = (struct gem_softc *)ifp->if_softc;
1142 gem_start_locked(ifp);
1147 gem_start_locked(ifp)
1150 struct gem_softc *sc = (struct gem_softc *)ifp->if_softc;
1151 struct mbuf *m0 = NULL;
1152 int firsttx, ntx = 0, ofree, txmfail;
1154 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
1159 * Remember the previous number of free descriptors and
1160 * the first descriptor we'll use.
1162 ofree = sc->sc_txfree;
1163 firsttx = sc->sc_txnext;
1166 CTR3(KTR_GEM, "%s: gem_start: txfree %d, txnext %d",
1167 device_get_name(sc->sc_dev), ofree, firsttx);
1171 * Loop through the send queue, setting up transmit descriptors
1172 * until we drain the queue, or use up all available transmit
1178 * Grab a packet off the queue.
1180 IF_DEQUEUE(&ifp->if_snd, m0);
1184 txmfail = gem_load_txmbuf(sc, m0);
1186 /* Drop the mbuf and complain. */
1187 printf("gem_start: error %d while loading mbuf dma "
1191 /* Not enough descriptors. */
1192 if (txmfail == -1) {
1193 if (sc->sc_txfree == GEM_MAXTXFREE)
1194 panic("gem_start: mbuf chain too long!");
1195 IF_PREPEND(&ifp->if_snd, m0);
1200 /* Kick the transmitter. */
1202 CTR2(KTR_GEM, "%s: gem_start: kicking tx %d",
1203 device_get_name(sc->sc_dev), sc->sc_txnext);
1205 bus_space_write_4(sc->sc_bustag, sc->sc_h, GEM_TX_KICK,
1208 if (ifp->if_bpf != NULL)
1209 bpf_mtap(ifp->if_bpf, m0);
1212 if (txmfail == -1 || sc->sc_txfree == 0) {
1213 /* No more slots left; notify upper layer. */
1214 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1218 GEM_CDSYNC(sc, BUS_DMASYNC_PREWRITE);
1221 CTR2(KTR_GEM, "%s: packets enqueued, OWN on %d",
1222 device_get_name(sc->sc_dev), firsttx);
1225 /* Set a watchdog timer in case the chip flakes out. */
1228 CTR2(KTR_GEM, "%s: gem_start: watchdog %d",
1229 device_get_name(sc->sc_dev), ifp->if_timer);
1235 * Transmit interrupt.
1239 struct gem_softc *sc;
1241 struct ifnet *ifp = sc->sc_ifp;
1242 bus_space_tag_t t = sc->sc_bustag;
1243 bus_space_handle_t mac = sc->sc_h;
1244 struct gem_txsoft *txs;
1250 CTR1(KTR_GEM, "%s: gem_tint", device_get_name(sc->sc_dev));
1254 * Unload collision counters
1256 ifp->if_collisions +=
1257 bus_space_read_4(t, mac, GEM_MAC_NORM_COLL_CNT) +
1258 bus_space_read_4(t, mac, GEM_MAC_FIRST_COLL_CNT) +
1259 bus_space_read_4(t, mac, GEM_MAC_EXCESS_COLL_CNT) +
1260 bus_space_read_4(t, mac, GEM_MAC_LATE_COLL_CNT);
1263 * then clear the hardware counters.
1265 bus_space_write_4(t, mac, GEM_MAC_NORM_COLL_CNT, 0);
1266 bus_space_write_4(t, mac, GEM_MAC_FIRST_COLL_CNT, 0);
1267 bus_space_write_4(t, mac, GEM_MAC_EXCESS_COLL_CNT, 0);
1268 bus_space_write_4(t, mac, GEM_MAC_LATE_COLL_CNT, 0);
1271 * Go through our Tx list and free mbufs for those
1272 * frames that have been transmitted.
1274 GEM_CDSYNC(sc, BUS_DMASYNC_POSTREAD);
1275 while ((txs = STAILQ_FIRST(&sc->sc_txdirtyq)) != NULL) {
1278 if (ifp->if_flags & IFF_DEBUG) {
1280 printf(" txsoft %p transmit chain:\n", txs);
1281 for (i = txs->txs_firstdesc;; i = GEM_NEXTTX(i)) {
1282 printf("descriptor %d: ", i);
1283 printf("gd_flags: 0x%016llx\t", (long long)
1284 GEM_DMA_READ(sc, sc->sc_txdescs[i].gd_flags));
1285 printf("gd_addr: 0x%016llx\n", (long long)
1286 GEM_DMA_READ(sc, sc->sc_txdescs[i].gd_addr));
1287 if (i == txs->txs_lastdesc)
1294 * In theory, we could harveast some descriptors before
1295 * the ring is empty, but that's a bit complicated.
1297 * GEM_TX_COMPLETION points to the last descriptor
1300 txlast = bus_space_read_4(t, mac, GEM_TX_COMPLETION);
1302 CTR3(KTR_GEM, "gem_tint: txs->txs_firstdesc = %d, "
1303 "txs->txs_lastdesc = %d, txlast = %d",
1304 txs->txs_firstdesc, txs->txs_lastdesc, txlast);
1306 if (txs->txs_firstdesc <= txs->txs_lastdesc) {
1307 if ((txlast >= txs->txs_firstdesc) &&
1308 (txlast <= txs->txs_lastdesc))
1311 /* Ick -- this command wraps */
1312 if ((txlast >= txs->txs_firstdesc) ||
1313 (txlast <= txs->txs_lastdesc))
1318 CTR0(KTR_GEM, "gem_tint: releasing a desc");
1320 STAILQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q);
1322 sc->sc_txfree += txs->txs_ndescs;
1324 bus_dmamap_sync(sc->sc_tdmatag, txs->txs_dmamap,
1325 BUS_DMASYNC_POSTWRITE);
1326 bus_dmamap_unload(sc->sc_tdmatag, txs->txs_dmamap);
1327 if (txs->txs_mbuf != NULL) {
1328 m_freem(txs->txs_mbuf);
1329 txs->txs_mbuf = NULL;
1332 STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q);
1339 CTR3(KTR_GEM, "gem_tint: GEM_TX_STATE_MACHINE %x "
1340 "GEM_TX_DATA_PTR %llx "
1341 "GEM_TX_COMPLETION %x",
1342 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_TX_STATE_MACHINE),
1343 ((long long) bus_space_read_4(sc->sc_bustag, sc->sc_h,
1344 GEM_TX_DATA_PTR_HI) << 32) |
1345 bus_space_read_4(sc->sc_bustag, sc->sc_h,
1346 GEM_TX_DATA_PTR_LO),
1347 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_TX_COMPLETION));
1351 if (sc->sc_txfree == GEM_NTXDESC - 1)
1354 /* Freed some descriptors, so reset IFF_DRV_OACTIVE and restart. */
1355 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1356 gem_start_locked(ifp);
1358 if (STAILQ_EMPTY(&sc->sc_txdirtyq))
1363 CTR2(KTR_GEM, "%s: gem_tint: watchdog %d",
1364 device_get_name(sc->sc_dev), ifp->if_timer);
1368 #ifdef GEM_RINT_TIMEOUT
1370 gem_rint_timeout(arg)
1373 struct gem_softc *sc = (struct gem_softc *)arg;
1375 GEM_LOCK_ASSERT(sc, MA_OWNED);
1381 * Receive interrupt.
1385 struct gem_softc *sc;
1387 struct ifnet *ifp = sc->sc_ifp;
1388 bus_space_tag_t t = sc->sc_bustag;
1389 bus_space_handle_t h = sc->sc_h;
1390 struct gem_rxsoft *rxs;
1394 int i, len, progress = 0;
1396 #ifdef GEM_RINT_TIMEOUT
1397 callout_stop(&sc->sc_rx_ch);
1400 CTR1(KTR_GEM, "%s: gem_rint", device_get_name(sc->sc_dev));
1404 * Read the completion register once. This limits
1405 * how long the following loop can execute.
1407 rxcomp = bus_space_read_4(t, h, GEM_RX_COMPLETION);
1410 CTR2(KTR_GEM, "gem_rint: sc->rxptr %d, complete %d",
1411 sc->sc_rxptr, rxcomp);
1413 GEM_CDSYNC(sc, BUS_DMASYNC_POSTREAD);
1414 for (i = sc->sc_rxptr; i != rxcomp;
1415 i = GEM_NEXTRX(i)) {
1416 rxs = &sc->sc_rxsoft[i];
1418 rxstat = GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags);
1420 if (rxstat & GEM_RD_OWN) {
1421 #ifdef GEM_RINT_TIMEOUT
1423 * The descriptor is still marked as owned, although
1424 * it is supposed to have completed. This has been
1425 * observed on some machines. Just exiting here
1426 * might leave the packet sitting around until another
1427 * one arrives to trigger a new interrupt, which is
1428 * generally undesirable, so set up a timeout.
1430 callout_reset(&sc->sc_rx_ch, GEM_RXOWN_TICKS,
1431 gem_rint_timeout, sc);
1439 if (rxstat & GEM_RD_BAD_CRC) {
1441 device_printf(sc->sc_dev, "receive error: CRC error\n");
1442 GEM_INIT_RXDESC(sc, i);
1447 if (ifp->if_flags & IFF_DEBUG) {
1448 printf(" rxsoft %p descriptor %d: ", rxs, i);
1449 printf("gd_flags: 0x%016llx\t", (long long)
1450 GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags));
1451 printf("gd_addr: 0x%016llx\n", (long long)
1452 GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_addr));
1457 * No errors; receive the packet. Note the Gem
1458 * includes the CRC with every packet.
1460 len = GEM_RD_BUFLEN(rxstat);
1463 * Allocate a new mbuf cluster. If that fails, we are
1464 * out of memory, and must drop the packet and recycle
1465 * the buffer that's already attached to this descriptor.
1468 if (gem_add_rxbuf(sc, i) != 0) {
1470 GEM_INIT_RXDESC(sc, i);
1473 m->m_data += 2; /* We're already off by two */
1475 m->m_pkthdr.rcvif = ifp;
1476 m->m_pkthdr.len = m->m_len = len - ETHER_CRC_LEN;
1480 (*ifp->if_input)(ifp, m);
1485 GEM_CDSYNC(sc, BUS_DMASYNC_PREWRITE);
1486 /* Update the receive pointer. */
1487 if (i == sc->sc_rxptr) {
1488 device_printf(sc->sc_dev, "rint: ring wrap\n");
1491 bus_space_write_4(t, h, GEM_RX_KICK, GEM_PREVRX(i));
1495 CTR2(KTR_GEM, "gem_rint: done sc->rxptr %d, complete %d",
1496 sc->sc_rxptr, bus_space_read_4(t, h, GEM_RX_COMPLETION));
1504 * Add a receive buffer to the indicated descriptor.
1507 gem_add_rxbuf(sc, idx)
1508 struct gem_softc *sc;
1511 struct gem_rxsoft *rxs = &sc->sc_rxsoft[idx];
1513 bus_dma_segment_t segs[1];
1516 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
1519 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size;
1522 /* bzero the packet to check dma */
1523 memset(m->m_ext.ext_buf, 0, m->m_ext.ext_size);
1526 if (rxs->rxs_mbuf != NULL) {
1527 bus_dmamap_sync(sc->sc_rdmatag, rxs->rxs_dmamap,
1528 BUS_DMASYNC_POSTREAD);
1529 bus_dmamap_unload(sc->sc_rdmatag, rxs->rxs_dmamap);
1534 error = bus_dmamap_load_mbuf_sg(sc->sc_rdmatag, rxs->rxs_dmamap,
1535 m, segs, &nsegs, BUS_DMA_NOWAIT);
1536 /* If nsegs is wrong then the stack is corrupt. */
1537 KASSERT(nsegs == 1, ("Too many segments returned!"));
1539 device_printf(sc->sc_dev, "can't load rx DMA map %d, error = "
1540 "%d\n", idx, error);
1544 rxs->rxs_paddr = segs[0].ds_addr;
1546 bus_dmamap_sync(sc->sc_rdmatag, rxs->rxs_dmamap, BUS_DMASYNC_PREREAD);
1548 GEM_INIT_RXDESC(sc, idx);
1555 gem_eint(sc, status)
1556 struct gem_softc *sc;
1560 if ((status & GEM_INTR_MIF) != 0) {
1561 device_printf(sc->sc_dev, "XXXlink status changed\n");
1565 device_printf(sc->sc_dev, "status=%x\n", status);
1573 struct gem_softc *sc = (struct gem_softc *)v;
1574 bus_space_tag_t t = sc->sc_bustag;
1575 bus_space_handle_t seb = sc->sc_h;
1579 status = bus_space_read_4(t, seb, GEM_STATUS);
1581 CTR3(KTR_GEM, "%s: gem_intr: cplt %x, status %x",
1582 device_get_name(sc->sc_dev), (status>>19),
1586 if ((status & (GEM_INTR_RX_TAG_ERR | GEM_INTR_BERR)) != 0)
1587 gem_eint(sc, status);
1589 if ((status & (GEM_INTR_TX_EMPTY | GEM_INTR_TX_INTME)) != 0)
1592 if ((status & (GEM_INTR_RX_DONE | GEM_INTR_RX_NOBUF)) != 0)
1595 /* We should eventually do more than just print out error stats. */
1596 if (status & GEM_INTR_TX_MAC) {
1597 int txstat = bus_space_read_4(t, seb, GEM_MAC_TX_STATUS);
1598 if (txstat & ~GEM_MAC_TX_XMIT_DONE)
1599 device_printf(sc->sc_dev, "MAC tx fault, status %x\n",
1601 if (txstat & (GEM_MAC_TX_UNDERRUN | GEM_MAC_TX_PKT_TOO_LONG))
1602 gem_init_locked(sc);
1604 if (status & GEM_INTR_RX_MAC) {
1605 int rxstat = bus_space_read_4(t, seb, GEM_MAC_RX_STATUS);
1607 * On some chip revisions GEM_MAC_RX_OVERFLOW happen often
1608 * due to a silicon bug so handle them silently.
1610 if (rxstat & GEM_MAC_RX_OVERFLOW)
1611 gem_init_locked(sc);
1612 else if (rxstat & ~(GEM_MAC_RX_DONE | GEM_MAC_RX_FRAME_CNT))
1613 device_printf(sc->sc_dev, "MAC rx fault, status %x\n",
1624 struct gem_softc *sc = ifp->if_softc;
1628 CTR3(KTR_GEM, "gem_watchdog: GEM_RX_CONFIG %x GEM_MAC_RX_STATUS %x "
1629 "GEM_MAC_RX_CONFIG %x",
1630 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_RX_CONFIG),
1631 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_MAC_RX_STATUS),
1632 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_MAC_RX_CONFIG));
1633 CTR3(KTR_GEM, "gem_watchdog: GEM_TX_CONFIG %x GEM_MAC_TX_STATUS %x "
1634 "GEM_MAC_TX_CONFIG %x",
1635 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_TX_CONFIG),
1636 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_MAC_TX_STATUS),
1637 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_MAC_TX_CONFIG));
1640 device_printf(sc->sc_dev, "device timeout\n");
1643 /* Try to get more packets going. */
1644 gem_init_locked(sc);
1649 * Initialize the MII Management Interface
1653 struct gem_softc *sc;
1655 bus_space_tag_t t = sc->sc_bustag;
1656 bus_space_handle_t mif = sc->sc_h;
1658 /* Configure the MIF in frame mode */
1659 sc->sc_mif_config = bus_space_read_4(t, mif, GEM_MIF_CONFIG);
1660 sc->sc_mif_config &= ~GEM_MIF_CONFIG_BB_ENA;
1661 bus_space_write_4(t, mif, GEM_MIF_CONFIG, sc->sc_mif_config);
1667 * The GEM MII interface supports at least three different operating modes:
1669 * Bitbang mode is implemented using data, clock and output enable registers.
1671 * Frame mode is implemented by loading a complete frame into the frame
1672 * register and polling the valid bit for completion.
1674 * Polling mode uses the frame register but completion is indicated by
1679 gem_mii_readreg(dev, phy, reg)
1683 struct gem_softc *sc = device_get_softc(dev);
1684 bus_space_tag_t t = sc->sc_bustag;
1685 bus_space_handle_t mif = sc->sc_h;
1689 #ifdef GEM_DEBUG_PHY
1690 printf("gem_mii_readreg: phy %d reg %d\n", phy, reg);
1694 /* Select the desired PHY in the MIF configuration register */
1695 v = bus_space_read_4(t, mif, GEM_MIF_CONFIG);
1696 /* Clear PHY select bit */
1697 v &= ~GEM_MIF_CONFIG_PHY_SEL;
1698 if (phy == GEM_PHYAD_EXTERNAL)
1699 /* Set PHY select bit to get at external device */
1700 v |= GEM_MIF_CONFIG_PHY_SEL;
1701 bus_space_write_4(t, mif, GEM_MIF_CONFIG, v);
1704 /* Construct the frame command */
1705 v = (reg << GEM_MIF_REG_SHIFT) | (phy << GEM_MIF_PHY_SHIFT) |
1708 bus_space_write_4(t, mif, GEM_MIF_FRAME, v);
1709 for (n = 0; n < 100; n++) {
1711 v = bus_space_read_4(t, mif, GEM_MIF_FRAME);
1712 if (v & GEM_MIF_FRAME_TA0)
1713 return (v & GEM_MIF_FRAME_DATA);
1716 device_printf(sc->sc_dev, "mii_read timeout\n");
1721 gem_mii_writereg(dev, phy, reg, val)
1725 struct gem_softc *sc = device_get_softc(dev);
1726 bus_space_tag_t t = sc->sc_bustag;
1727 bus_space_handle_t mif = sc->sc_h;
1731 #ifdef GEM_DEBUG_PHY
1732 printf("gem_mii_writereg: phy %d reg %d val %x\n", phy, reg, val);
1736 /* Select the desired PHY in the MIF configuration register */
1737 v = bus_space_read_4(t, mif, GEM_MIF_CONFIG);
1738 /* Clear PHY select bit */
1739 v &= ~GEM_MIF_CONFIG_PHY_SEL;
1740 if (phy == GEM_PHYAD_EXTERNAL)
1741 /* Set PHY select bit to get at external device */
1742 v |= GEM_MIF_CONFIG_PHY_SEL;
1743 bus_space_write_4(t, mif, GEM_MIF_CONFIG, v);
1745 /* Construct the frame command */
1746 v = GEM_MIF_FRAME_WRITE |
1747 (phy << GEM_MIF_PHY_SHIFT) |
1748 (reg << GEM_MIF_REG_SHIFT) |
1749 (val & GEM_MIF_FRAME_DATA);
1751 bus_space_write_4(t, mif, GEM_MIF_FRAME, v);
1752 for (n = 0; n < 100; n++) {
1754 v = bus_space_read_4(t, mif, GEM_MIF_FRAME);
1755 if (v & GEM_MIF_FRAME_TA0)
1759 device_printf(sc->sc_dev, "mii_write timeout\n");
1764 gem_mii_statchg(dev)
1767 struct gem_softc *sc = device_get_softc(dev);
1771 bus_space_tag_t t = sc->sc_bustag;
1772 bus_space_handle_t mac = sc->sc_h;
1776 instance = IFM_INST(sc->sc_mii->mii_media.ifm_cur->ifm_media);
1778 printf("gem_mii_statchg: status change: phy = %d\n",
1779 sc->sc_phys[instance]);
1782 /* Set tx full duplex options */
1783 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, 0);
1784 DELAY(10000); /* reg must be cleared and delay before changing. */
1785 v = GEM_MAC_TX_ENA_IPG0|GEM_MAC_TX_NGU|GEM_MAC_TX_NGU_LIMIT|
1787 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) != 0) {
1788 v |= GEM_MAC_TX_IGN_CARRIER|GEM_MAC_TX_IGN_COLLIS;
1790 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, v);
1792 /* XIF Configuration */
1793 v = GEM_MAC_XIF_LINK_LED;
1794 v |= GEM_MAC_XIF_TX_MII_ENA;
1796 /* If an external transceiver is connected, enable its MII drivers */
1797 sc->sc_mif_config = bus_space_read_4(t, mac, GEM_MIF_CONFIG);
1798 if ((sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) != 0) {
1799 /* External MII needs echo disable if half duplex. */
1800 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) != 0)
1801 /* turn on full duplex LED */
1802 v |= GEM_MAC_XIF_FDPLX_LED;
1804 /* half duplex -- disable echo */
1805 v |= GEM_MAC_XIF_ECHO_DISABL;
1807 if (IFM_SUBTYPE(sc->sc_mii->mii_media_active) == IFM_1000_T)
1808 v |= GEM_MAC_XIF_GMII_MODE;
1810 v &= ~GEM_MAC_XIF_GMII_MODE;
1812 /* Internal MII needs buf enable */
1813 v |= GEM_MAC_XIF_MII_BUF_ENA;
1815 bus_space_write_4(t, mac, GEM_MAC_XIF_CONFIG, v);
1819 gem_mediachange(ifp)
1822 struct gem_softc *sc = ifp->if_softc;
1825 /* XXX Add support for serial media. */
1828 error = mii_mediachg(sc->sc_mii);
1834 gem_mediastatus(ifp, ifmr)
1836 struct ifmediareq *ifmr;
1838 struct gem_softc *sc = ifp->if_softc;
1841 if ((ifp->if_flags & IFF_UP) == 0) {
1846 mii_pollstat(sc->sc_mii);
1847 ifmr->ifm_active = sc->sc_mii->mii_media_active;
1848 ifmr->ifm_status = sc->sc_mii->mii_media_status;
1853 * Process an ioctl request.
1856 gem_ioctl(ifp, cmd, data)
1861 struct gem_softc *sc = ifp->if_softc;
1862 struct ifreq *ifr = (struct ifreq *)data;
1868 if (ifp->if_flags & IFF_UP) {
1869 if ((sc->sc_ifflags ^ ifp->if_flags) == IFF_PROMISC)
1872 gem_init_locked(sc);
1874 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1877 sc->sc_ifflags = ifp->if_flags;
1888 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii->mii_media, cmd);
1891 error = ether_ioctl(ifp, cmd, data);
1895 /* Try to get things going again */
1897 if (ifp->if_flags & IFF_UP)
1898 gem_start_locked(ifp);
1904 * Set up the logical address filter.
1908 struct gem_softc *sc;
1910 struct ifnet *ifp = sc->sc_ifp;
1911 struct ifmultiaddr *inm;
1912 bus_space_tag_t t = sc->sc_bustag;
1913 bus_space_handle_t h = sc->sc_h;
1919 GEM_LOCK_ASSERT(sc, MA_OWNED);
1921 /* Get current RX configuration */
1922 v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG);
1925 * Turn off promiscuous mode, promiscuous group mode (all multicast),
1926 * and hash filter. Depending on the case, the right bit will be
1929 v &= ~(GEM_MAC_RX_PROMISCUOUS|GEM_MAC_RX_HASH_FILTER|
1930 GEM_MAC_RX_PROMISC_GRP);
1932 if ((ifp->if_flags & IFF_PROMISC) != 0) {
1933 /* Turn on promiscuous mode */
1934 v |= GEM_MAC_RX_PROMISCUOUS;
1937 if ((ifp->if_flags & IFF_ALLMULTI) != 0) {
1938 hash[3] = hash[2] = hash[1] = hash[0] = 0xffff;
1939 ifp->if_flags |= IFF_ALLMULTI;
1940 v |= GEM_MAC_RX_PROMISC_GRP;
1945 * Set up multicast address filter by passing all multicast addresses
1946 * through a crc generator, and then using the high order 8 bits as an
1947 * index into the 256 bit logical address filter. The high order 4
1948 * bits selects the word, while the other 4 bits select the bit within
1949 * the word (where bit 0 is the MSB).
1952 /* Clear hash table */
1953 memset(hash, 0, sizeof(hash));
1956 TAILQ_FOREACH(inm, &ifp->if_multiaddrs, ifma_link) {
1957 if (inm->ifma_addr->sa_family != AF_LINK)
1959 crc = ether_crc32_le(LLADDR((struct sockaddr_dl *)
1960 inm->ifma_addr), ETHER_ADDR_LEN);
1962 /* Just want the 8 most significant bits. */
1965 /* Set the corresponding bit in the filter. */
1966 hash[crc >> 4] |= 1 << (15 - (crc & 15));
1968 IF_ADDR_UNLOCK(ifp);
1970 v |= GEM_MAC_RX_HASH_FILTER;
1971 ifp->if_flags &= ~IFF_ALLMULTI;
1973 /* Now load the hash table into the chip (if we are using it) */
1974 for (i = 0; i < 16; i++) {
1975 bus_space_write_4(t, h,
1976 GEM_MAC_HASH0 + i * (GEM_MAC_HASH1-GEM_MAC_HASH0),
1981 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v);