2 * Copyright (C) 2001 Eduardo Horvath.
3 * Copyright (c) 2001-2003 Thomas Moestl
4 * Copyright (c) 2007 Marius Strobl <marius@FreeBSD.org>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * from: NetBSD: gem.c,v 1.21 2002/06/01 23:50:58 lukem Exp
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
35 * Driver for Apple GMAC, Sun ERI and Sun GEM Ethernet controllers
42 #if 0 /* XXX: In case of emergency, re-enable this. */
43 #define GEM_RINT_TIMEOUT
46 #include <sys/param.h>
47 #include <sys/systm.h>
49 #include <sys/callout.h>
50 #include <sys/endian.h>
52 #include <sys/malloc.h>
53 #include <sys/kernel.h>
55 #include <sys/module.h>
56 #include <sys/mutex.h>
57 #include <sys/socket.h>
58 #include <sys/sockio.h>
62 #include <net/ethernet.h>
64 #include <net/if_var.h>
65 #include <net/if_arp.h>
66 #include <net/if_dl.h>
67 #include <net/if_media.h>
68 #include <net/if_types.h>
69 #include <net/if_vlan_var.h>
71 #include <netinet/in.h>
72 #include <netinet/in_systm.h>
73 #include <netinet/ip.h>
74 #include <netinet/tcp.h>
75 #include <netinet/udp.h>
77 #include <machine/bus.h>
79 #include <dev/mii/mii.h>
80 #include <dev/mii/miivar.h>
82 #include <dev/gem/if_gemreg.h>
83 #include <dev/gem/if_gemvar.h>
85 CTASSERT(powerof2(GEM_NRXDESC) && GEM_NRXDESC >= 32 && GEM_NRXDESC <= 8192);
86 CTASSERT(powerof2(GEM_NTXDESC) && GEM_NTXDESC >= 32 && GEM_NTXDESC <= 8192);
88 #define GEM_TRIES 10000
91 * The hardware supports basic TCP/UDP checksum offloading. However,
92 * the hardware doesn't compensate the checksum for UDP datagram which
93 * can yield to 0x0. As a safe guard, UDP checksum offload is disabled
94 * by default. It can be reactivated by setting special link option
95 * link0 with ifconfig(8).
97 #define GEM_CSUM_FEATURES (CSUM_TCP)
99 static int gem_add_rxbuf(struct gem_softc *sc, int idx);
100 static int gem_bitwait(struct gem_softc *sc, u_int bank, bus_addr_t r,
101 uint32_t clr, uint32_t set);
102 static void gem_cddma_callback(void *xsc, bus_dma_segment_t *segs,
103 int nsegs, int error);
104 static int gem_disable_rx(struct gem_softc *sc);
105 static int gem_disable_tx(struct gem_softc *sc);
106 static void gem_eint(struct gem_softc *sc, u_int status);
107 static void gem_init(void *xsc);
108 static void gem_init_locked(struct gem_softc *sc);
109 static void gem_init_regs(struct gem_softc *sc);
110 static int gem_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data);
111 static int gem_load_txmbuf(struct gem_softc *sc, struct mbuf **m_head);
112 static int gem_meminit(struct gem_softc *sc);
113 static void gem_mifinit(struct gem_softc *sc);
114 static void gem_reset(struct gem_softc *sc);
115 static int gem_reset_rx(struct gem_softc *sc);
116 static void gem_reset_rxdma(struct gem_softc *sc);
117 static int gem_reset_tx(struct gem_softc *sc);
118 static u_int gem_ringsize(u_int sz);
119 static void gem_rint(struct gem_softc *sc);
120 #ifdef GEM_RINT_TIMEOUT
121 static void gem_rint_timeout(void *arg);
123 static inline void gem_rxcksum(struct mbuf *m, uint64_t flags);
124 static void gem_rxdrain(struct gem_softc *sc);
125 static void gem_setladrf(struct gem_softc *sc);
126 static void gem_start(struct ifnet *ifp);
127 static void gem_start_locked(struct ifnet *ifp);
128 static void gem_stop(struct ifnet *ifp, int disable);
129 static void gem_tick(void *arg);
130 static void gem_tint(struct gem_softc *sc);
131 static inline void gem_txkick(struct gem_softc *sc);
132 static int gem_watchdog(struct gem_softc *sc);
134 devclass_t gem_devclass;
135 DRIVER_MODULE(miibus, gem, miibus_driver, miibus_devclass, 0, 0);
136 MODULE_DEPEND(gem, miibus, 1, 1, 1);
140 #define KTR_GEM KTR_SPARE2
143 #define GEM_BANK1_BITWAIT(sc, r, clr, set) \
144 gem_bitwait((sc), GEM_RES_BANK1, (r), (clr), (set))
145 #define GEM_BANK2_BITWAIT(sc, r, clr, set) \
146 gem_bitwait((sc), GEM_RES_BANK2, (r), (clr), (set))
149 gem_attach(struct gem_softc *sc)
151 struct gem_txsoft *txs;
157 device_printf(sc->sc_dev, "flags=0x%x\n", sc->sc_flags);
159 /* Set up ifnet structure. */
160 ifp = sc->sc_ifp = if_alloc(IFT_ETHER);
163 sc->sc_csum_features = GEM_CSUM_FEATURES;
165 if_initname(ifp, device_get_name(sc->sc_dev),
166 device_get_unit(sc->sc_dev));
167 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
168 ifp->if_start = gem_start;
169 ifp->if_ioctl = gem_ioctl;
170 ifp->if_init = gem_init;
171 IFQ_SET_MAXLEN(&ifp->if_snd, GEM_TXQUEUELEN);
172 ifp->if_snd.ifq_drv_maxlen = GEM_TXQUEUELEN;
173 IFQ_SET_READY(&ifp->if_snd);
175 callout_init_mtx(&sc->sc_tick_ch, &sc->sc_mtx, 0);
176 #ifdef GEM_RINT_TIMEOUT
177 callout_init_mtx(&sc->sc_rx_ch, &sc->sc_mtx, 0);
180 /* Make sure the chip is stopped. */
183 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0,
184 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
185 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, NULL,
186 NULL, &sc->sc_pdmatag);
190 error = bus_dma_tag_create(sc->sc_pdmatag, 1, 0,
191 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES,
192 1, MCLBYTES, BUS_DMA_ALLOCNOW, NULL, NULL, &sc->sc_rdmatag);
196 error = bus_dma_tag_create(sc->sc_pdmatag, 1, 0,
197 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
198 MCLBYTES * GEM_NTXSEGS, GEM_NTXSEGS, MCLBYTES,
199 BUS_DMA_ALLOCNOW, NULL, NULL, &sc->sc_tdmatag);
203 error = bus_dma_tag_create(sc->sc_pdmatag, PAGE_SIZE, 0,
204 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
205 sizeof(struct gem_control_data), 1,
206 sizeof(struct gem_control_data), 0,
207 NULL, NULL, &sc->sc_cdmatag);
212 * Allocate the control data structures, create and load the
215 if ((error = bus_dmamem_alloc(sc->sc_cdmatag,
216 (void **)&sc->sc_control_data,
217 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO,
218 &sc->sc_cddmamap)) != 0) {
219 device_printf(sc->sc_dev,
220 "unable to allocate control data, error = %d\n", error);
225 if ((error = bus_dmamap_load(sc->sc_cdmatag, sc->sc_cddmamap,
226 sc->sc_control_data, sizeof(struct gem_control_data),
227 gem_cddma_callback, sc, 0)) != 0 || sc->sc_cddma == 0) {
228 device_printf(sc->sc_dev,
229 "unable to load control data DMA map, error = %d\n",
235 * Initialize the transmit job descriptors.
237 STAILQ_INIT(&sc->sc_txfreeq);
238 STAILQ_INIT(&sc->sc_txdirtyq);
241 * Create the transmit buffer DMA maps.
244 for (i = 0; i < GEM_TXQUEUELEN; i++) {
245 txs = &sc->sc_txsoft[i];
246 txs->txs_mbuf = NULL;
248 if ((error = bus_dmamap_create(sc->sc_tdmatag, 0,
249 &txs->txs_dmamap)) != 0) {
250 device_printf(sc->sc_dev,
251 "unable to create TX DMA map %d, error = %d\n",
255 STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q);
259 * Create the receive buffer DMA maps.
261 for (i = 0; i < GEM_NRXDESC; i++) {
262 if ((error = bus_dmamap_create(sc->sc_rdmatag, 0,
263 &sc->sc_rxsoft[i].rxs_dmamap)) != 0) {
264 device_printf(sc->sc_dev,
265 "unable to create RX DMA map %d, error = %d\n",
269 sc->sc_rxsoft[i].rxs_mbuf = NULL;
272 /* Bypass probing PHYs if we already know for sure to use a SERDES. */
273 if ((sc->sc_flags & GEM_SERDES) != 0)
276 /* Bad things will happen when touching this register on ERI. */
277 if (sc->sc_variant != GEM_SUN_ERI) {
278 GEM_BANK1_WRITE_4(sc, GEM_MII_DATAPATH_MODE,
279 GEM_MII_DATAPATH_MII);
280 GEM_BANK1_BARRIER(sc, GEM_MII_DATAPATH_MODE, 4,
281 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
287 * Look for an external PHY.
290 v = GEM_BANK1_READ_4(sc, GEM_MIF_CONFIG);
291 if ((v & GEM_MIF_CONFIG_MDI1) != 0) {
292 v |= GEM_MIF_CONFIG_PHY_SEL;
293 GEM_BANK1_WRITE_4(sc, GEM_MIF_CONFIG, v);
294 GEM_BANK1_BARRIER(sc, GEM_MIF_CONFIG, 4,
295 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
296 switch (sc->sc_variant) {
298 phy = GEM_PHYAD_EXTERNAL;
304 error = mii_attach(sc->sc_dev, &sc->sc_miibus, ifp,
305 gem_mediachange, gem_mediastatus, BMSR_DEFCAPMASK, phy,
306 MII_OFFSET_ANY, MIIF_DOPAUSE);
310 * Fall back on an internal PHY if no external PHY was found.
311 * Note that with Apple (K2) GMACs GEM_MIF_CONFIG_MDI0 can't be
312 * trusted when the firmware has powered down the chip.
315 ((v & GEM_MIF_CONFIG_MDI0) != 0 || GEM_IS_APPLE(sc))) {
316 v &= ~GEM_MIF_CONFIG_PHY_SEL;
317 GEM_BANK1_WRITE_4(sc, GEM_MIF_CONFIG, v);
318 GEM_BANK1_BARRIER(sc, GEM_MIF_CONFIG, 4,
319 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
320 switch (sc->sc_variant) {
322 case GEM_APPLE_K2_GMAC:
323 phy = GEM_PHYAD_INTERNAL;
326 phy = GEM_PHYAD_EXTERNAL;
332 error = mii_attach(sc->sc_dev, &sc->sc_miibus, ifp,
333 gem_mediachange, gem_mediastatus, BMSR_DEFCAPMASK, phy,
334 MII_OFFSET_ANY, MIIF_DOPAUSE);
338 * Try the external PCS SERDES if we didn't find any PHYs.
340 if (error != 0 && sc->sc_variant == GEM_SUN_GEM) {
342 GEM_BANK1_WRITE_4(sc, GEM_MII_DATAPATH_MODE,
343 GEM_MII_DATAPATH_SERDES);
344 GEM_BANK1_BARRIER(sc, GEM_MII_DATAPATH_MODE, 4,
345 BUS_SPACE_BARRIER_WRITE);
346 GEM_BANK1_WRITE_4(sc, GEM_MII_SLINK_CONTROL,
347 GEM_MII_SLINK_LOOPBACK | GEM_MII_SLINK_EN_SYNC_D);
348 GEM_BANK1_BARRIER(sc, GEM_MII_SLINK_CONTROL, 4,
349 BUS_SPACE_BARRIER_WRITE);
350 GEM_BANK1_WRITE_4(sc, GEM_MII_CONFIG, GEM_MII_CONFIG_ENABLE);
351 GEM_BANK1_BARRIER(sc, GEM_MII_CONFIG, 4,
352 BUS_SPACE_BARRIER_WRITE);
353 sc->sc_flags |= GEM_SERDES;
354 error = mii_attach(sc->sc_dev, &sc->sc_miibus, ifp,
355 gem_mediachange, gem_mediastatus, BMSR_DEFCAPMASK,
356 GEM_PHYAD_EXTERNAL, MII_OFFSET_ANY, MIIF_DOPAUSE);
359 device_printf(sc->sc_dev, "attaching PHYs failed\n");
362 sc->sc_mii = device_get_softc(sc->sc_miibus);
365 * From this point forward, the attachment cannot fail. A failure
366 * before this point releases all resources that may have been
370 /* Get RX FIFO size. */
371 sc->sc_rxfifosize = 64 *
372 GEM_BANK1_READ_4(sc, GEM_RX_FIFO_SIZE);
374 /* Get TX FIFO size. */
375 v = GEM_BANK1_READ_4(sc, GEM_TX_FIFO_SIZE);
376 device_printf(sc->sc_dev, "%ukB RX FIFO, %ukB TX FIFO\n",
377 sc->sc_rxfifosize / 1024, v / 16);
379 /* Attach the interface. */
380 ether_ifattach(ifp, sc->sc_enaddr);
383 * Tell the upper layer(s) we support long frames/checksum offloads.
385 ifp->if_hdrlen = sizeof(struct ether_vlan_header);
386 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_HWCSUM;
387 ifp->if_hwassist |= sc->sc_csum_features;
388 ifp->if_capenable |= IFCAP_VLAN_MTU | IFCAP_HWCSUM;
393 * Free any resources we've allocated during the failed attach
394 * attempt. Do this in reverse order and fall through.
397 for (i = 0; i < GEM_NRXDESC; i++)
398 if (sc->sc_rxsoft[i].rxs_dmamap != NULL)
399 bus_dmamap_destroy(sc->sc_rdmatag,
400 sc->sc_rxsoft[i].rxs_dmamap);
402 for (i = 0; i < GEM_TXQUEUELEN; i++)
403 if (sc->sc_txsoft[i].txs_dmamap != NULL)
404 bus_dmamap_destroy(sc->sc_tdmatag,
405 sc->sc_txsoft[i].txs_dmamap);
406 bus_dmamap_unload(sc->sc_cdmatag, sc->sc_cddmamap);
408 bus_dmamem_free(sc->sc_cdmatag, sc->sc_control_data,
411 bus_dma_tag_destroy(sc->sc_cdmatag);
413 bus_dma_tag_destroy(sc->sc_tdmatag);
415 bus_dma_tag_destroy(sc->sc_rdmatag);
417 bus_dma_tag_destroy(sc->sc_pdmatag);
424 gem_detach(struct gem_softc *sc)
426 struct ifnet *ifp = sc->sc_ifp;
433 callout_drain(&sc->sc_tick_ch);
434 #ifdef GEM_RINT_TIMEOUT
435 callout_drain(&sc->sc_rx_ch);
438 device_delete_child(sc->sc_dev, sc->sc_miibus);
440 for (i = 0; i < GEM_NRXDESC; i++)
441 if (sc->sc_rxsoft[i].rxs_dmamap != NULL)
442 bus_dmamap_destroy(sc->sc_rdmatag,
443 sc->sc_rxsoft[i].rxs_dmamap);
444 for (i = 0; i < GEM_TXQUEUELEN; i++)
445 if (sc->sc_txsoft[i].txs_dmamap != NULL)
446 bus_dmamap_destroy(sc->sc_tdmatag,
447 sc->sc_txsoft[i].txs_dmamap);
448 GEM_CDSYNC(sc, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
449 bus_dmamap_unload(sc->sc_cdmatag, sc->sc_cddmamap);
450 bus_dmamem_free(sc->sc_cdmatag, sc->sc_control_data,
452 bus_dma_tag_destroy(sc->sc_cdmatag);
453 bus_dma_tag_destroy(sc->sc_tdmatag);
454 bus_dma_tag_destroy(sc->sc_rdmatag);
455 bus_dma_tag_destroy(sc->sc_pdmatag);
459 gem_suspend(struct gem_softc *sc)
461 struct ifnet *ifp = sc->sc_ifp;
469 gem_resume(struct gem_softc *sc)
471 struct ifnet *ifp = sc->sc_ifp;
475 * On resume all registers have to be initialized again like
478 sc->sc_flags &= ~GEM_INITED;
479 if (ifp->if_flags & IFF_UP)
485 gem_rxcksum(struct mbuf *m, uint64_t flags)
487 struct ether_header *eh;
491 int32_t hlen, len, pktlen;
495 pktlen = m->m_pkthdr.len;
496 if (pktlen < sizeof(struct ether_header) + sizeof(struct ip))
498 eh = mtod(m, struct ether_header *);
499 if (eh->ether_type != htons(ETHERTYPE_IP))
501 ip = (struct ip *)(eh + 1);
502 if (ip->ip_v != IPVERSION)
505 hlen = ip->ip_hl << 2;
506 pktlen -= sizeof(struct ether_header);
507 if (hlen < sizeof(struct ip))
509 if (ntohs(ip->ip_len) < hlen)
511 if (ntohs(ip->ip_len) != pktlen)
513 if (ip->ip_off & htons(IP_MF | IP_OFFMASK))
514 return; /* Cannot handle fragmented packet. */
518 if (pktlen < (hlen + sizeof(struct tcphdr)))
522 if (pktlen < (hlen + sizeof(struct udphdr)))
524 uh = (struct udphdr *)((uint8_t *)ip + hlen);
526 return; /* no checksum */
532 cksum = ~(flags & GEM_RD_CHECKSUM);
533 /* checksum fixup for IP options */
534 len = hlen - sizeof(struct ip);
536 opts = (uint16_t *)(ip + 1);
537 for (; len > 0; len -= sizeof(uint16_t), opts++) {
538 temp32 = cksum - *opts;
539 temp32 = (temp32 >> 16) + (temp32 & 65535);
540 cksum = temp32 & 65535;
543 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID;
544 m->m_pkthdr.csum_data = cksum;
548 gem_cddma_callback(void *xsc, bus_dma_segment_t *segs, int nsegs, int error)
550 struct gem_softc *sc = xsc;
555 panic("%s: bad control buffer segment count", __func__);
556 sc->sc_cddma = segs[0].ds_addr;
562 struct gem_softc *sc = arg;
563 struct ifnet *ifp = sc->sc_ifp;
566 GEM_LOCK_ASSERT(sc, MA_OWNED);
569 * Unload collision and error counters.
571 if_inc_counter(ifp, IFCOUNTER_COLLISIONS,
572 GEM_BANK1_READ_4(sc, GEM_MAC_NORM_COLL_CNT) +
573 GEM_BANK1_READ_4(sc, GEM_MAC_FIRST_COLL_CNT));
574 v = GEM_BANK1_READ_4(sc, GEM_MAC_EXCESS_COLL_CNT) +
575 GEM_BANK1_READ_4(sc, GEM_MAC_LATE_COLL_CNT);
576 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, v);
577 if_inc_counter(ifp, IFCOUNTER_OERRORS, v);
578 if_inc_counter(ifp, IFCOUNTER_IERRORS,
579 GEM_BANK1_READ_4(sc, GEM_MAC_RX_LEN_ERR_CNT) +
580 GEM_BANK1_READ_4(sc, GEM_MAC_RX_ALIGN_ERR) +
581 GEM_BANK1_READ_4(sc, GEM_MAC_RX_CRC_ERR_CNT) +
582 GEM_BANK1_READ_4(sc, GEM_MAC_RX_CODE_VIOL));
585 * Then clear the hardware counters.
587 GEM_BANK1_WRITE_4(sc, GEM_MAC_NORM_COLL_CNT, 0);
588 GEM_BANK1_WRITE_4(sc, GEM_MAC_FIRST_COLL_CNT, 0);
589 GEM_BANK1_WRITE_4(sc, GEM_MAC_EXCESS_COLL_CNT, 0);
590 GEM_BANK1_WRITE_4(sc, GEM_MAC_LATE_COLL_CNT, 0);
591 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_LEN_ERR_CNT, 0);
592 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_ALIGN_ERR, 0);
593 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CRC_ERR_CNT, 0);
594 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CODE_VIOL, 0);
596 mii_tick(sc->sc_mii);
598 if (gem_watchdog(sc) == EJUSTRETURN)
601 callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc);
605 gem_bitwait(struct gem_softc *sc, u_int bank, bus_addr_t r, uint32_t clr,
611 for (i = GEM_TRIES; i--; DELAY(100)) {
612 reg = GEM_BANKN_READ_M(bank, 4, sc, r);
613 if ((reg & clr) == 0 && (reg & set) == set)
620 gem_reset(struct gem_softc *sc)
624 CTR2(KTR_GEM, "%s: %s", device_get_name(sc->sc_dev), __func__);
629 /* Do a full reset. */
630 GEM_BANK2_WRITE_4(sc, GEM_RESET, GEM_RESET_RX | GEM_RESET_TX |
631 (sc->sc_variant == GEM_SUN_ERI ? GEM_ERI_CACHE_LINE_SIZE <<
632 GEM_RESET_CLSZ_SHFT : 0));
633 GEM_BANK2_BARRIER(sc, GEM_RESET, 4,
634 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
635 if (!GEM_BANK2_BITWAIT(sc, GEM_RESET, GEM_RESET_RX | GEM_RESET_TX, 0))
636 device_printf(sc->sc_dev, "cannot reset device\n");
640 gem_rxdrain(struct gem_softc *sc)
642 struct gem_rxsoft *rxs;
645 for (i = 0; i < GEM_NRXDESC; i++) {
646 rxs = &sc->sc_rxsoft[i];
647 if (rxs->rxs_mbuf != NULL) {
648 bus_dmamap_sync(sc->sc_rdmatag, rxs->rxs_dmamap,
649 BUS_DMASYNC_POSTREAD);
650 bus_dmamap_unload(sc->sc_rdmatag, rxs->rxs_dmamap);
651 m_freem(rxs->rxs_mbuf);
652 rxs->rxs_mbuf = NULL;
658 gem_stop(struct ifnet *ifp, int disable)
660 struct gem_softc *sc = ifp->if_softc;
661 struct gem_txsoft *txs;
664 CTR2(KTR_GEM, "%s: %s", device_get_name(sc->sc_dev), __func__);
667 callout_stop(&sc->sc_tick_ch);
668 #ifdef GEM_RINT_TIMEOUT
669 callout_stop(&sc->sc_rx_ch);
676 * Release any queued transmit buffers.
678 while ((txs = STAILQ_FIRST(&sc->sc_txdirtyq)) != NULL) {
679 STAILQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q);
680 if (txs->txs_ndescs != 0) {
681 bus_dmamap_sync(sc->sc_tdmatag, txs->txs_dmamap,
682 BUS_DMASYNC_POSTWRITE);
683 bus_dmamap_unload(sc->sc_tdmatag, txs->txs_dmamap);
684 if (txs->txs_mbuf != NULL) {
685 m_freem(txs->txs_mbuf);
686 txs->txs_mbuf = NULL;
689 STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q);
696 * Mark the interface down and cancel the watchdog timer.
698 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
699 sc->sc_flags &= ~GEM_LINK;
700 sc->sc_wdog_timer = 0;
704 gem_reset_rx(struct gem_softc *sc)
708 * Resetting while DMA is in progress can cause a bus hang, so we
711 (void)gem_disable_rx(sc);
712 GEM_BANK1_WRITE_4(sc, GEM_RX_CONFIG, 0);
713 GEM_BANK1_BARRIER(sc, GEM_RX_CONFIG, 4,
714 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
715 if (!GEM_BANK1_BITWAIT(sc, GEM_RX_CONFIG, GEM_RX_CONFIG_RXDMA_EN, 0))
716 device_printf(sc->sc_dev, "cannot disable RX DMA\n");
718 /* Wait 5ms extra. */
722 GEM_BANK2_WRITE_4(sc, GEM_RESET, GEM_RESET_RX |
723 (sc->sc_variant == GEM_SUN_ERI ? GEM_ERI_CACHE_LINE_SIZE <<
724 GEM_RESET_CLSZ_SHFT : 0));
725 GEM_BANK2_BARRIER(sc, GEM_RESET, 4,
726 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
727 if (!GEM_BANK2_BITWAIT(sc, GEM_RESET, GEM_RESET_RX, 0)) {
728 device_printf(sc->sc_dev, "cannot reset receiver\n");
732 /* Finally, reset RX MAC. */
733 GEM_BANK1_WRITE_4(sc, GEM_MAC_RXRESET, 1);
734 GEM_BANK1_BARRIER(sc, GEM_MAC_RXRESET, 4,
735 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
736 if (!GEM_BANK1_BITWAIT(sc, GEM_MAC_RXRESET, 1, 0)) {
737 device_printf(sc->sc_dev, "cannot reset RX MAC\n");
745 * Reset the receiver DMA engine.
747 * Intended to be used in case of GEM_INTR_RX_TAG_ERR, GEM_MAC_RX_OVERFLOW
748 * etc in order to reset the receiver DMA engine only and not do a full
749 * reset which amongst others also downs the link and clears the FIFOs.
752 gem_reset_rxdma(struct gem_softc *sc)
756 if (gem_reset_rx(sc) != 0) {
757 sc->sc_ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
758 return (gem_init_locked(sc));
760 for (i = 0; i < GEM_NRXDESC; i++)
761 if (sc->sc_rxsoft[i].rxs_mbuf != NULL)
762 GEM_UPDATE_RXDESC(sc, i);
764 GEM_CDSYNC(sc, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
766 /* NOTE: we use only 32-bit DMA addresses here. */
767 GEM_BANK1_WRITE_4(sc, GEM_RX_RING_PTR_HI, 0);
768 GEM_BANK1_WRITE_4(sc, GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0));
769 GEM_BANK1_WRITE_4(sc, GEM_RX_KICK, GEM_NRXDESC - 4);
770 GEM_BANK1_WRITE_4(sc, GEM_RX_CONFIG,
771 gem_ringsize(GEM_NRXDESC /* XXX */) |
772 ((ETHER_HDR_LEN + sizeof(struct ip)) <<
773 GEM_RX_CONFIG_CXM_START_SHFT) |
774 (GEM_THRSH_1024 << GEM_RX_CONFIG_FIFO_THRS_SHIFT) |
775 (ETHER_ALIGN << GEM_RX_CONFIG_FBOFF_SHFT));
776 /* Adjusting for the SBus clock probably isn't worth the fuzz. */
777 GEM_BANK1_WRITE_4(sc, GEM_RX_BLANKING,
778 ((6 * (sc->sc_flags & GEM_PCI66) != 0 ? 2 : 1) <<
779 GEM_RX_BLANKING_TIME_SHIFT) | 6);
780 GEM_BANK1_WRITE_4(sc, GEM_RX_PAUSE_THRESH,
781 (3 * sc->sc_rxfifosize / 256) |
782 ((sc->sc_rxfifosize / 256) << 12));
783 GEM_BANK1_WRITE_4(sc, GEM_RX_CONFIG,
784 GEM_BANK1_READ_4(sc, GEM_RX_CONFIG) | GEM_RX_CONFIG_RXDMA_EN);
785 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_MASK,
786 GEM_MAC_RX_DONE | GEM_MAC_RX_FRAME_CNT);
788 * Clear the RX filter and reprogram it. This will also set the
789 * current RX MAC configuration and enable it.
795 gem_reset_tx(struct gem_softc *sc)
799 * Resetting while DMA is in progress can cause a bus hang, so we
802 (void)gem_disable_tx(sc);
803 GEM_BANK1_WRITE_4(sc, GEM_TX_CONFIG, 0);
804 GEM_BANK1_BARRIER(sc, GEM_TX_CONFIG, 4,
805 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
806 if (!GEM_BANK1_BITWAIT(sc, GEM_TX_CONFIG, GEM_TX_CONFIG_TXDMA_EN, 0))
807 device_printf(sc->sc_dev, "cannot disable TX DMA\n");
809 /* Wait 5ms extra. */
812 /* Finally, reset the ETX. */
813 GEM_BANK2_WRITE_4(sc, GEM_RESET, GEM_RESET_TX |
814 (sc->sc_variant == GEM_SUN_ERI ? GEM_ERI_CACHE_LINE_SIZE <<
815 GEM_RESET_CLSZ_SHFT : 0));
816 GEM_BANK2_BARRIER(sc, GEM_RESET, 4,
817 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
818 if (!GEM_BANK2_BITWAIT(sc, GEM_RESET, GEM_RESET_TX, 0)) {
819 device_printf(sc->sc_dev, "cannot reset transmitter\n");
826 gem_disable_rx(struct gem_softc *sc)
829 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CONFIG,
830 GEM_BANK1_READ_4(sc, GEM_MAC_RX_CONFIG) & ~GEM_MAC_RX_ENABLE);
831 GEM_BANK1_BARRIER(sc, GEM_MAC_RX_CONFIG, 4,
832 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
833 if (GEM_BANK1_BITWAIT(sc, GEM_MAC_RX_CONFIG, GEM_MAC_RX_ENABLE, 0))
835 device_printf(sc->sc_dev, "cannot disable RX MAC\n");
840 gem_disable_tx(struct gem_softc *sc)
843 GEM_BANK1_WRITE_4(sc, GEM_MAC_TX_CONFIG,
844 GEM_BANK1_READ_4(sc, GEM_MAC_TX_CONFIG) & ~GEM_MAC_TX_ENABLE);
845 GEM_BANK1_BARRIER(sc, GEM_MAC_TX_CONFIG, 4,
846 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
847 if (GEM_BANK1_BITWAIT(sc, GEM_MAC_TX_CONFIG, GEM_MAC_TX_ENABLE, 0))
849 device_printf(sc->sc_dev, "cannot disable TX MAC\n");
854 gem_meminit(struct gem_softc *sc)
856 struct gem_rxsoft *rxs;
859 GEM_LOCK_ASSERT(sc, MA_OWNED);
862 * Initialize the transmit descriptor ring.
864 for (i = 0; i < GEM_NTXDESC; i++) {
865 sc->sc_txdescs[i].gd_flags = 0;
866 sc->sc_txdescs[i].gd_addr = 0;
868 sc->sc_txfree = GEM_MAXTXFREE;
873 * Initialize the receive descriptor and receive job
876 for (i = 0; i < GEM_NRXDESC; i++) {
877 rxs = &sc->sc_rxsoft[i];
878 if (rxs->rxs_mbuf == NULL) {
879 if ((error = gem_add_rxbuf(sc, i)) != 0) {
880 device_printf(sc->sc_dev,
881 "unable to allocate or map RX buffer %d, "
882 "error = %d\n", i, error);
884 * XXX we should attempt to run with fewer
885 * receive buffers instead of just failing.
891 GEM_INIT_RXDESC(sc, i);
895 GEM_CDSYNC(sc, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
901 gem_ringsize(u_int sz)
906 return (GEM_RING_SZ_32);
908 return (GEM_RING_SZ_64);
910 return (GEM_RING_SZ_128);
912 return (GEM_RING_SZ_256);
914 return (GEM_RING_SZ_512);
916 return (GEM_RING_SZ_1024);
918 return (GEM_RING_SZ_2048);
920 return (GEM_RING_SZ_4096);
922 return (GEM_RING_SZ_8192);
924 printf("%s: invalid ring size %d\n", __func__, sz);
925 return (GEM_RING_SZ_32);
932 struct gem_softc *sc = xsc;
940 * Initialization of interface; set up initialization block
941 * and transmit/receive descriptor rings.
944 gem_init_locked(struct gem_softc *sc)
946 struct ifnet *ifp = sc->sc_ifp;
949 GEM_LOCK_ASSERT(sc, MA_OWNED);
951 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
955 CTR2(KTR_GEM, "%s: %s: calling stop", device_get_name(sc->sc_dev),
959 * Initialization sequence. The numbered steps below correspond
960 * to the sequence outlined in section 6.3.5.1 in the Ethernet
961 * Channel Engine manual (part of the PCIO manual).
962 * See also the STP2002-STQ document from Sun Microsystems.
965 /* step 1 & 2. Reset the Ethernet Channel. */
969 CTR2(KTR_GEM, "%s: %s: restarting", device_get_name(sc->sc_dev),
973 if ((sc->sc_flags & GEM_SERDES) == 0)
974 /* Re-initialize the MIF. */
977 /* step 3. Setup data structures in host memory. */
978 if (gem_meminit(sc) != 0)
981 /* step 4. TX MAC registers & counters */
984 /* step 5. RX MAC registers & counters */
986 /* step 6 & 7. Program Descriptor Ring Base Addresses. */
987 /* NOTE: we use only 32-bit DMA addresses here. */
988 GEM_BANK1_WRITE_4(sc, GEM_TX_RING_PTR_HI, 0);
989 GEM_BANK1_WRITE_4(sc, GEM_TX_RING_PTR_LO, GEM_CDTXADDR(sc, 0));
991 GEM_BANK1_WRITE_4(sc, GEM_RX_RING_PTR_HI, 0);
992 GEM_BANK1_WRITE_4(sc, GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0));
994 CTR3(KTR_GEM, "loading RX ring %lx, TX ring %lx, cddma %lx",
995 GEM_CDRXADDR(sc, 0), GEM_CDTXADDR(sc, 0), sc->sc_cddma);
998 /* step 8. Global Configuration & Interrupt Mask */
1001 * Set the internal arbitration to "infinite" bursts of the
1002 * maximum length of 31 * 64 bytes so DMA transfers aren't
1003 * split up in cache line size chunks. This greatly improves
1005 * Enable silicon bug workarounds for the Apple variants.
1007 GEM_BANK1_WRITE_4(sc, GEM_CONFIG,
1008 GEM_CONFIG_TXDMA_LIMIT | GEM_CONFIG_RXDMA_LIMIT |
1009 ((sc->sc_flags & GEM_PCI) != 0 ? GEM_CONFIG_BURST_INF :
1010 GEM_CONFIG_BURST_64) | (GEM_IS_APPLE(sc) ?
1011 GEM_CONFIG_RONPAULBIT | GEM_CONFIG_BUG2FIX : 0));
1013 GEM_BANK1_WRITE_4(sc, GEM_INTMASK,
1014 ~(GEM_INTR_TX_INTME | GEM_INTR_TX_EMPTY | GEM_INTR_RX_DONE |
1015 GEM_INTR_RX_NOBUF | GEM_INTR_RX_TAG_ERR | GEM_INTR_PERR |
1018 | GEM_INTR_PCS | GEM_INTR_MIF
1021 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_MASK,
1022 GEM_MAC_RX_DONE | GEM_MAC_RX_FRAME_CNT);
1023 GEM_BANK1_WRITE_4(sc, GEM_MAC_TX_MASK,
1024 GEM_MAC_TX_XMIT_DONE | GEM_MAC_TX_DEFER_EXP |
1025 GEM_MAC_TX_PEAK_EXP);
1027 GEM_BANK1_WRITE_4(sc, GEM_MAC_CONTROL_MASK,
1028 ~(GEM_MAC_PAUSED | GEM_MAC_PAUSE | GEM_MAC_RESUME));
1030 GEM_BANK1_WRITE_4(sc, GEM_MAC_CONTROL_MASK,
1031 GEM_MAC_PAUSED | GEM_MAC_PAUSE | GEM_MAC_RESUME);
1034 /* step 9. ETX Configuration: use mostly default values. */
1037 v = gem_ringsize(GEM_NTXDESC);
1038 /* Set TX FIFO threshold and enable DMA. */
1039 v |= ((sc->sc_variant == GEM_SUN_ERI ? 0x100 : 0x4ff) << 10) &
1040 GEM_TX_CONFIG_TXFIFO_TH;
1041 GEM_BANK1_WRITE_4(sc, GEM_TX_CONFIG, v | GEM_TX_CONFIG_TXDMA_EN);
1043 /* step 10. ERX Configuration */
1045 /* Encode Receive Descriptor ring size. */
1046 v = gem_ringsize(GEM_NRXDESC /* XXX */);
1047 /* RX TCP/UDP checksum offset */
1048 v |= ((ETHER_HDR_LEN + sizeof(struct ip)) <<
1049 GEM_RX_CONFIG_CXM_START_SHFT);
1050 /* Set RX FIFO threshold, set first byte offset and enable DMA. */
1051 GEM_BANK1_WRITE_4(sc, GEM_RX_CONFIG,
1052 v | (GEM_THRSH_1024 << GEM_RX_CONFIG_FIFO_THRS_SHIFT) |
1053 (ETHER_ALIGN << GEM_RX_CONFIG_FBOFF_SHFT) |
1054 GEM_RX_CONFIG_RXDMA_EN);
1056 /* Adjusting for the SBus clock probably isn't worth the fuzz. */
1057 GEM_BANK1_WRITE_4(sc, GEM_RX_BLANKING,
1058 ((6 * (sc->sc_flags & GEM_PCI66) != 0 ? 2 : 1) <<
1059 GEM_RX_BLANKING_TIME_SHIFT) | 6);
1062 * The following value is for an OFF Threshold of about 3/4 full
1063 * and an ON Threshold of 1/4 full.
1065 GEM_BANK1_WRITE_4(sc, GEM_RX_PAUSE_THRESH,
1066 (3 * sc->sc_rxfifosize / 256) |
1067 ((sc->sc_rxfifosize / 256) << 12));
1069 /* step 11. Configure Media. */
1071 /* step 12. RX_MAC Configuration Register */
1072 v = GEM_BANK1_READ_4(sc, GEM_MAC_RX_CONFIG);
1073 v &= ~GEM_MAC_RX_ENABLE;
1074 v |= GEM_MAC_RX_STRIP_CRC;
1075 sc->sc_mac_rxcfg = v;
1077 * Clear the RX filter and reprogram it. This will also set the
1078 * current RX MAC configuration and enable it.
1082 /* step 13. TX_MAC Configuration Register */
1083 v = GEM_BANK1_READ_4(sc, GEM_MAC_TX_CONFIG);
1084 v |= GEM_MAC_TX_ENABLE;
1085 (void)gem_disable_tx(sc);
1086 GEM_BANK1_WRITE_4(sc, GEM_MAC_TX_CONFIG, v);
1088 /* step 14. Issue Transmit Pending command. */
1090 /* step 15. Give the receiver a swift kick. */
1091 GEM_BANK1_WRITE_4(sc, GEM_RX_KICK, GEM_NRXDESC - 4);
1093 ifp->if_drv_flags |= IFF_DRV_RUNNING;
1094 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1096 mii_mediachg(sc->sc_mii);
1098 /* Start the one second timer. */
1099 sc->sc_wdog_timer = 0;
1100 callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc);
1104 gem_load_txmbuf(struct gem_softc *sc, struct mbuf **m_head)
1106 bus_dma_segment_t txsegs[GEM_NTXSEGS];
1107 struct gem_txsoft *txs;
1110 uint64_t cflags, flags;
1111 int error, nexttx, nsegs, offset, seg;
1113 GEM_LOCK_ASSERT(sc, MA_OWNED);
1115 /* Get a work queue entry. */
1116 if ((txs = STAILQ_FIRST(&sc->sc_txfreeq)) == NULL) {
1117 /* Ran out of descriptors. */
1122 if (((*m_head)->m_pkthdr.csum_flags & sc->sc_csum_features) != 0) {
1123 if (M_WRITABLE(*m_head) == 0) {
1124 m = m_dup(*m_head, M_NOWAIT);
1130 offset = sizeof(struct ether_header);
1131 m = m_pullup(*m_head, offset + sizeof(struct ip));
1136 ip = (struct ip *)(mtod(m, caddr_t) + offset);
1137 offset += (ip->ip_hl << 2);
1138 cflags = offset << GEM_TD_CXSUM_STARTSHFT |
1139 ((offset + m->m_pkthdr.csum_data) <<
1140 GEM_TD_CXSUM_STUFFSHFT) | GEM_TD_CXSUM_ENABLE;
1144 error = bus_dmamap_load_mbuf_sg(sc->sc_tdmatag, txs->txs_dmamap,
1145 *m_head, txsegs, &nsegs, BUS_DMA_NOWAIT);
1146 if (error == EFBIG) {
1147 m = m_collapse(*m_head, M_NOWAIT, GEM_NTXSEGS);
1154 error = bus_dmamap_load_mbuf_sg(sc->sc_tdmatag,
1155 txs->txs_dmamap, *m_head, txsegs, &nsegs,
1162 } else if (error != 0)
1164 /* If nsegs is wrong then the stack is corrupt. */
1165 KASSERT(nsegs <= GEM_NTXSEGS,
1166 ("%s: too many DMA segments (%d)", __func__, nsegs));
1174 * Ensure we have enough descriptors free to describe
1175 * the packet. Note, we always reserve one descriptor
1176 * at the end of the ring as a termination point, in
1177 * order to prevent wrap-around.
1179 if (nsegs > sc->sc_txfree - 1) {
1180 txs->txs_ndescs = 0;
1181 bus_dmamap_unload(sc->sc_tdmatag, txs->txs_dmamap);
1185 txs->txs_ndescs = nsegs;
1186 txs->txs_firstdesc = sc->sc_txnext;
1187 nexttx = txs->txs_firstdesc;
1188 for (seg = 0; seg < nsegs; seg++, nexttx = GEM_NEXTTX(nexttx)) {
1191 "%s: mapping seg %d (txd %d), len %lx, addr %#lx (%#lx)",
1192 __func__, seg, nexttx, txsegs[seg].ds_len,
1193 txsegs[seg].ds_addr,
1194 GEM_DMA_WRITE(sc, txsegs[seg].ds_addr));
1196 sc->sc_txdescs[nexttx].gd_addr =
1197 GEM_DMA_WRITE(sc, txsegs[seg].ds_addr);
1198 KASSERT(txsegs[seg].ds_len < GEM_TD_BUFSIZE,
1199 ("%s: segment size too large!", __func__));
1200 flags = txsegs[seg].ds_len & GEM_TD_BUFSIZE;
1201 sc->sc_txdescs[nexttx].gd_flags =
1202 GEM_DMA_WRITE(sc, flags | cflags);
1203 txs->txs_lastdesc = nexttx;
1206 /* Set EOP on the last descriptor. */
1208 CTR3(KTR_GEM, "%s: end of packet at segment %d, TX %d",
1209 __func__, seg, nexttx);
1211 sc->sc_txdescs[txs->txs_lastdesc].gd_flags |=
1212 GEM_DMA_WRITE(sc, GEM_TD_END_OF_PACKET);
1214 /* Lastly set SOP on the first descriptor. */
1216 CTR3(KTR_GEM, "%s: start of packet at segment %d, TX %d",
1217 __func__, seg, nexttx);
1219 if (++sc->sc_txwin > GEM_NTXSEGS * 2 / 3) {
1221 sc->sc_txdescs[txs->txs_firstdesc].gd_flags |=
1222 GEM_DMA_WRITE(sc, GEM_TD_INTERRUPT_ME |
1223 GEM_TD_START_OF_PACKET);
1225 sc->sc_txdescs[txs->txs_firstdesc].gd_flags |=
1226 GEM_DMA_WRITE(sc, GEM_TD_START_OF_PACKET);
1228 /* Sync the DMA map. */
1229 bus_dmamap_sync(sc->sc_tdmatag, txs->txs_dmamap,
1230 BUS_DMASYNC_PREWRITE);
1233 CTR4(KTR_GEM, "%s: setting firstdesc=%d, lastdesc=%d, ndescs=%d",
1234 __func__, txs->txs_firstdesc, txs->txs_lastdesc,
1237 STAILQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q);
1238 STAILQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q);
1239 txs->txs_mbuf = *m_head;
1241 sc->sc_txnext = GEM_NEXTTX(txs->txs_lastdesc);
1242 sc->sc_txfree -= txs->txs_ndescs;
1248 gem_init_regs(struct gem_softc *sc)
1250 const u_char *laddr = IF_LLADDR(sc->sc_ifp);
1252 GEM_LOCK_ASSERT(sc, MA_OWNED);
1254 /* These registers are not cleared on reset. */
1255 if ((sc->sc_flags & GEM_INITED) == 0) {
1257 GEM_BANK1_WRITE_4(sc, GEM_MAC_IPG0, 0);
1258 GEM_BANK1_WRITE_4(sc, GEM_MAC_IPG1, 8);
1259 GEM_BANK1_WRITE_4(sc, GEM_MAC_IPG2, 4);
1261 /* min frame length */
1262 GEM_BANK1_WRITE_4(sc, GEM_MAC_MAC_MIN_FRAME, ETHER_MIN_LEN);
1263 /* max frame length and max burst size */
1264 GEM_BANK1_WRITE_4(sc, GEM_MAC_MAC_MAX_FRAME,
1265 (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN) | (0x2000 << 16));
1267 /* more magic values */
1268 GEM_BANK1_WRITE_4(sc, GEM_MAC_PREAMBLE_LEN, 0x7);
1269 GEM_BANK1_WRITE_4(sc, GEM_MAC_JAM_SIZE, 0x4);
1270 GEM_BANK1_WRITE_4(sc, GEM_MAC_ATTEMPT_LIMIT, 0x10);
1271 GEM_BANK1_WRITE_4(sc, GEM_MAC_CONTROL_TYPE, 0x8808);
1273 /* random number seed */
1274 GEM_BANK1_WRITE_4(sc, GEM_MAC_RANDOM_SEED,
1275 ((laddr[5] << 8) | laddr[4]) & 0x3ff);
1277 /* secondary MAC address: 0:0:0:0:0:0 */
1278 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR3, 0);
1279 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR4, 0);
1280 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR5, 0);
1282 /* MAC control address: 01:80:c2:00:00:01 */
1283 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR6, 0x0001);
1284 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR7, 0xc200);
1285 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR8, 0x0180);
1287 /* MAC filter address: 0:0:0:0:0:0 */
1288 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR_FILTER0, 0);
1289 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR_FILTER1, 0);
1290 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR_FILTER2, 0);
1291 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADR_FLT_MASK1_2, 0);
1292 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADR_FLT_MASK0, 0);
1294 sc->sc_flags |= GEM_INITED;
1297 /* Counters need to be zeroed. */
1298 GEM_BANK1_WRITE_4(sc, GEM_MAC_NORM_COLL_CNT, 0);
1299 GEM_BANK1_WRITE_4(sc, GEM_MAC_FIRST_COLL_CNT, 0);
1300 GEM_BANK1_WRITE_4(sc, GEM_MAC_EXCESS_COLL_CNT, 0);
1301 GEM_BANK1_WRITE_4(sc, GEM_MAC_LATE_COLL_CNT, 0);
1302 GEM_BANK1_WRITE_4(sc, GEM_MAC_DEFER_TMR_CNT, 0);
1303 GEM_BANK1_WRITE_4(sc, GEM_MAC_PEAK_ATTEMPTS, 0);
1304 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_FRAME_COUNT, 0);
1305 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_LEN_ERR_CNT, 0);
1306 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_ALIGN_ERR, 0);
1307 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CRC_ERR_CNT, 0);
1308 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CODE_VIOL, 0);
1310 /* Set XOFF PAUSE time. */
1311 GEM_BANK1_WRITE_4(sc, GEM_MAC_SEND_PAUSE_CMD, 0x1BF0);
1313 /* Set the station address. */
1314 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR0, (laddr[4] << 8) | laddr[5]);
1315 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR1, (laddr[2] << 8) | laddr[3]);
1316 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR2, (laddr[0] << 8) | laddr[1]);
1318 /* Enable MII outputs. */
1319 GEM_BANK1_WRITE_4(sc, GEM_MAC_XIF_CONFIG, GEM_MAC_XIF_TX_MII_ENA);
1323 gem_start(struct ifnet *ifp)
1325 struct gem_softc *sc = ifp->if_softc;
1328 gem_start_locked(ifp);
1333 gem_txkick(struct gem_softc *sc)
1337 * Update the TX kick register. This register has to point to the
1338 * descriptor after the last valid one and for optimum performance
1339 * should be incremented in multiples of 4 (the DMA engine fetches/
1340 * updates descriptors in batches of 4).
1343 CTR3(KTR_GEM, "%s: %s: kicking TX %d",
1344 device_get_name(sc->sc_dev), __func__, sc->sc_txnext);
1346 GEM_CDSYNC(sc, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1347 GEM_BANK1_WRITE_4(sc, GEM_TX_KICK, sc->sc_txnext);
1351 gem_start_locked(struct ifnet *ifp)
1353 struct gem_softc *sc = ifp->if_softc;
1357 GEM_LOCK_ASSERT(sc, MA_OWNED);
1359 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
1360 IFF_DRV_RUNNING || (sc->sc_flags & GEM_LINK) == 0)
1364 CTR4(KTR_GEM, "%s: %s: txfree %d, txnext %d",
1365 device_get_name(sc->sc_dev), __func__, sc->sc_txfree,
1370 for (; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && sc->sc_txfree > 1;) {
1371 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
1374 if (gem_load_txmbuf(sc, &m) != 0) {
1377 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1378 IFQ_DRV_PREPEND(&ifp->if_snd, m);
1381 if ((sc->sc_txnext % 4) == 0) {
1394 CTR2(KTR_GEM, "%s: packets enqueued, OWN on %d",
1395 device_get_name(sc->sc_dev), sc->sc_txnext);
1398 /* Set a watchdog timer in case the chip flakes out. */
1399 sc->sc_wdog_timer = 5;
1401 CTR3(KTR_GEM, "%s: %s: watchdog %d",
1402 device_get_name(sc->sc_dev), __func__,
1409 gem_tint(struct gem_softc *sc)
1411 struct ifnet *ifp = sc->sc_ifp;
1412 struct gem_txsoft *txs;
1418 GEM_LOCK_ASSERT(sc, MA_OWNED);
1420 CTR2(KTR_GEM, "%s: %s", device_get_name(sc->sc_dev), __func__);
1424 * Go through our TX list and free mbufs for those
1425 * frames that have been transmitted.
1428 GEM_CDSYNC(sc, BUS_DMASYNC_POSTREAD);
1429 while ((txs = STAILQ_FIRST(&sc->sc_txdirtyq)) != NULL) {
1431 if ((ifp->if_flags & IFF_DEBUG) != 0) {
1432 printf(" txsoft %p transmit chain:\n", txs);
1433 for (i = txs->txs_firstdesc;; i = GEM_NEXTTX(i)) {
1434 printf("descriptor %d: ", i);
1435 printf("gd_flags: 0x%016llx\t",
1436 (long long)GEM_DMA_READ(sc,
1437 sc->sc_txdescs[i].gd_flags));
1438 printf("gd_addr: 0x%016llx\n",
1439 (long long)GEM_DMA_READ(sc,
1440 sc->sc_txdescs[i].gd_addr));
1441 if (i == txs->txs_lastdesc)
1448 * In theory, we could harvest some descriptors before
1449 * the ring is empty, but that's a bit complicated.
1451 * GEM_TX_COMPLETION points to the last descriptor
1454 txlast = GEM_BANK1_READ_4(sc, GEM_TX_COMPLETION);
1456 CTR4(KTR_GEM, "%s: txs->txs_firstdesc = %d, "
1457 "txs->txs_lastdesc = %d, txlast = %d",
1458 __func__, txs->txs_firstdesc, txs->txs_lastdesc, txlast);
1460 if (txs->txs_firstdesc <= txs->txs_lastdesc) {
1461 if ((txlast >= txs->txs_firstdesc) &&
1462 (txlast <= txs->txs_lastdesc))
1465 /* Ick -- this command wraps. */
1466 if ((txlast >= txs->txs_firstdesc) ||
1467 (txlast <= txs->txs_lastdesc))
1472 CTR1(KTR_GEM, "%s: releasing a descriptor", __func__);
1474 STAILQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q);
1476 sc->sc_txfree += txs->txs_ndescs;
1478 bus_dmamap_sync(sc->sc_tdmatag, txs->txs_dmamap,
1479 BUS_DMASYNC_POSTWRITE);
1480 bus_dmamap_unload(sc->sc_tdmatag, txs->txs_dmamap);
1481 if (txs->txs_mbuf != NULL) {
1482 m_freem(txs->txs_mbuf);
1483 txs->txs_mbuf = NULL;
1486 STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q);
1488 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
1493 CTR4(KTR_GEM, "%s: GEM_TX_STATE_MACHINE %x GEM_TX_DATA_PTR %llx "
1494 "GEM_TX_COMPLETION %x",
1495 __func__, GEM_BANK1_READ_4(sc, GEM_TX_STATE_MACHINE),
1496 ((long long)GEM_BANK1_READ_4(sc, GEM_TX_DATA_PTR_HI) << 32) |
1497 GEM_BANK1_READ_4(sc, GEM_TX_DATA_PTR_LO),
1498 GEM_BANK1_READ_4(sc, GEM_TX_COMPLETION));
1502 if (sc->sc_txfree == GEM_NTXDESC - 1)
1506 * We freed some descriptors, so reset IFF_DRV_OACTIVE
1509 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1510 if (STAILQ_EMPTY(&sc->sc_txdirtyq))
1511 sc->sc_wdog_timer = 0;
1512 gem_start_locked(ifp);
1516 CTR3(KTR_GEM, "%s: %s: watchdog %d",
1517 device_get_name(sc->sc_dev), __func__, sc->sc_wdog_timer);
1521 #ifdef GEM_RINT_TIMEOUT
1523 gem_rint_timeout(void *arg)
1525 struct gem_softc *sc = arg;
1527 GEM_LOCK_ASSERT(sc, MA_OWNED);
1534 gem_rint(struct gem_softc *sc)
1536 struct ifnet *ifp = sc->sc_ifp;
1541 GEM_LOCK_ASSERT(sc, MA_OWNED);
1543 #ifdef GEM_RINT_TIMEOUT
1544 callout_stop(&sc->sc_rx_ch);
1547 CTR2(KTR_GEM, "%s: %s", device_get_name(sc->sc_dev), __func__);
1551 * Read the completion register once. This limits
1552 * how long the following loop can execute.
1554 rxcomp = GEM_BANK1_READ_4(sc, GEM_RX_COMPLETION);
1556 CTR3(KTR_GEM, "%s: sc->sc_rxptr %d, complete %d",
1557 __func__, sc->sc_rxptr, rxcomp);
1559 GEM_CDSYNC(sc, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1560 for (; sc->sc_rxptr != rxcomp;) {
1561 m = sc->sc_rxsoft[sc->sc_rxptr].rxs_mbuf;
1562 rxstat = GEM_DMA_READ(sc,
1563 sc->sc_rxdescs[sc->sc_rxptr].gd_flags);
1565 if (rxstat & GEM_RD_OWN) {
1566 #ifdef GEM_RINT_TIMEOUT
1568 * The descriptor is still marked as owned, although
1569 * it is supposed to have completed. This has been
1570 * observed on some machines. Just exiting here
1571 * might leave the packet sitting around until another
1572 * one arrives to trigger a new interrupt, which is
1573 * generally undesirable, so set up a timeout.
1575 callout_reset(&sc->sc_rx_ch, GEM_RXOWN_TICKS,
1576 gem_rint_timeout, sc);
1582 if (rxstat & GEM_RD_BAD_CRC) {
1583 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1584 device_printf(sc->sc_dev, "receive error: CRC error\n");
1585 GEM_INIT_RXDESC(sc, sc->sc_rxptr);
1591 if ((ifp->if_flags & IFF_DEBUG) != 0) {
1592 printf(" rxsoft %p descriptor %d: ",
1593 &sc->sc_rxsoft[sc->sc_rxptr], sc->sc_rxptr);
1594 printf("gd_flags: 0x%016llx\t",
1595 (long long)GEM_DMA_READ(sc,
1596 sc->sc_rxdescs[sc->sc_rxptr].gd_flags));
1597 printf("gd_addr: 0x%016llx\n",
1598 (long long)GEM_DMA_READ(sc,
1599 sc->sc_rxdescs[sc->sc_rxptr].gd_addr));
1604 * Allocate a new mbuf cluster. If that fails, we are
1605 * out of memory, and must drop the packet and recycle
1606 * the buffer that's already attached to this descriptor.
1608 if (gem_add_rxbuf(sc, sc->sc_rxptr) != 0) {
1609 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
1610 GEM_INIT_RXDESC(sc, sc->sc_rxptr);
1616 * Update the RX kick register. This register has to point
1617 * to the descriptor after the last valid one (before the
1618 * current batch) and for optimum performance should be
1619 * incremented in multiples of 4 (the DMA engine fetches/
1620 * updates descriptors in batches of 4).
1622 sc->sc_rxptr = GEM_NEXTRX(sc->sc_rxptr);
1623 if ((sc->sc_rxptr % 4) == 0) {
1625 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1626 GEM_BANK1_WRITE_4(sc, GEM_RX_KICK,
1627 (sc->sc_rxptr + GEM_NRXDESC - 4) &
1632 if (rxstat & GEM_RD_OWN)
1637 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
1638 m->m_data += ETHER_ALIGN; /* first byte offset */
1639 m->m_pkthdr.rcvif = ifp;
1640 m->m_pkthdr.len = m->m_len = GEM_RD_BUFLEN(rxstat);
1642 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0)
1643 gem_rxcksum(m, rxstat);
1647 (*ifp->if_input)(ifp, m);
1652 CTR3(KTR_GEM, "%s: done sc->sc_rxptr %d, complete %d", __func__,
1653 sc->sc_rxptr, GEM_BANK1_READ_4(sc, GEM_RX_COMPLETION));
1658 gem_add_rxbuf(struct gem_softc *sc, int idx)
1660 struct gem_rxsoft *rxs = &sc->sc_rxsoft[idx];
1662 bus_dma_segment_t segs[1];
1665 GEM_LOCK_ASSERT(sc, MA_OWNED);
1667 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
1670 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size;
1673 /* Bzero the packet to check DMA. */
1674 memset(m->m_ext.ext_buf, 0, m->m_ext.ext_size);
1677 if (rxs->rxs_mbuf != NULL) {
1678 bus_dmamap_sync(sc->sc_rdmatag, rxs->rxs_dmamap,
1679 BUS_DMASYNC_POSTREAD);
1680 bus_dmamap_unload(sc->sc_rdmatag, rxs->rxs_dmamap);
1683 error = bus_dmamap_load_mbuf_sg(sc->sc_rdmatag, rxs->rxs_dmamap,
1684 m, segs, &nsegs, BUS_DMA_NOWAIT);
1686 device_printf(sc->sc_dev,
1687 "cannot load RS DMA map %d, error = %d\n", idx, error);
1691 /* If nsegs is wrong then the stack is corrupt. */
1693 ("%s: too many DMA segments (%d)", __func__, nsegs));
1695 rxs->rxs_paddr = segs[0].ds_addr;
1697 bus_dmamap_sync(sc->sc_rdmatag, rxs->rxs_dmamap,
1698 BUS_DMASYNC_PREREAD);
1700 GEM_INIT_RXDESC(sc, idx);
1706 gem_eint(struct gem_softc *sc, u_int status)
1709 if_inc_counter(sc->sc_ifp, IFCOUNTER_IERRORS, 1);
1710 if ((status & GEM_INTR_RX_TAG_ERR) != 0) {
1711 gem_reset_rxdma(sc);
1715 device_printf(sc->sc_dev, "%s: status 0x%x", __func__, status);
1716 if ((status & GEM_INTR_BERR) != 0) {
1717 if ((sc->sc_flags & GEM_PCI) != 0)
1718 printf(", PCI bus error 0x%x\n",
1719 GEM_BANK1_READ_4(sc, GEM_PCI_ERROR_STATUS));
1721 printf(", SBus error 0x%x\n",
1722 GEM_BANK1_READ_4(sc, GEM_SBUS_STATUS));
1729 struct gem_softc *sc = v;
1730 uint32_t status, status2;
1733 status = GEM_BANK1_READ_4(sc, GEM_STATUS);
1736 CTR4(KTR_GEM, "%s: %s: cplt %x, status %x",
1737 device_get_name(sc->sc_dev), __func__,
1738 (status >> GEM_STATUS_TX_COMPLETION_SHFT), (u_int)status);
1741 * PCS interrupts must be cleared, otherwise no traffic is passed!
1743 if ((status & GEM_INTR_PCS) != 0) {
1745 GEM_BANK1_READ_4(sc, GEM_MII_INTERRUP_STATUS) |
1746 GEM_BANK1_READ_4(sc, GEM_MII_INTERRUP_STATUS);
1747 if ((status2 & GEM_MII_INTERRUP_LINK) != 0)
1748 device_printf(sc->sc_dev,
1749 "%s: PCS link status changed\n", __func__);
1751 if ((status & GEM_MAC_CONTROL_STATUS) != 0) {
1752 status2 = GEM_BANK1_READ_4(sc, GEM_MAC_CONTROL_STATUS);
1753 if ((status2 & GEM_MAC_PAUSED) != 0)
1754 device_printf(sc->sc_dev,
1755 "%s: PAUSE received (PAUSE time %d slots)\n",
1756 __func__, GEM_MAC_PAUSE_TIME(status2));
1757 if ((status2 & GEM_MAC_PAUSE) != 0)
1758 device_printf(sc->sc_dev,
1759 "%s: transited to PAUSE state\n", __func__);
1760 if ((status2 & GEM_MAC_RESUME) != 0)
1761 device_printf(sc->sc_dev,
1762 "%s: transited to non-PAUSE state\n", __func__);
1764 if ((status & GEM_INTR_MIF) != 0)
1765 device_printf(sc->sc_dev, "%s: MIF interrupt\n", __func__);
1768 if (__predict_false(status &
1769 (GEM_INTR_RX_TAG_ERR | GEM_INTR_PERR | GEM_INTR_BERR)) != 0)
1770 gem_eint(sc, status);
1772 if ((status & (GEM_INTR_RX_DONE | GEM_INTR_RX_NOBUF)) != 0)
1775 if ((status & (GEM_INTR_TX_EMPTY | GEM_INTR_TX_INTME)) != 0)
1778 if (__predict_false((status & GEM_INTR_TX_MAC) != 0)) {
1779 status2 = GEM_BANK1_READ_4(sc, GEM_MAC_TX_STATUS);
1781 ~(GEM_MAC_TX_XMIT_DONE | GEM_MAC_TX_DEFER_EXP |
1782 GEM_MAC_TX_PEAK_EXP)) != 0)
1783 device_printf(sc->sc_dev,
1784 "MAC TX fault, status %x\n", status2);
1786 (GEM_MAC_TX_UNDERRUN | GEM_MAC_TX_PKT_TOO_LONG)) != 0) {
1787 if_inc_counter(sc->sc_ifp, IFCOUNTER_OERRORS, 1);
1788 sc->sc_ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1789 gem_init_locked(sc);
1792 if (__predict_false((status & GEM_INTR_RX_MAC) != 0)) {
1793 status2 = GEM_BANK1_READ_4(sc, GEM_MAC_RX_STATUS);
1795 * At least with GEM_SUN_GEM and some GEM_SUN_ERI
1796 * revisions GEM_MAC_RX_OVERFLOW happen often due to a
1797 * silicon bug so handle them silently. Moreover, it's
1798 * likely that the receiver has hung so we reset it.
1800 if ((status2 & GEM_MAC_RX_OVERFLOW) != 0) {
1801 if_inc_counter(sc->sc_ifp, IFCOUNTER_IERRORS, 1);
1802 gem_reset_rxdma(sc);
1803 } else if ((status2 &
1804 ~(GEM_MAC_RX_DONE | GEM_MAC_RX_FRAME_CNT)) != 0)
1805 device_printf(sc->sc_dev,
1806 "MAC RX fault, status %x\n", status2);
1812 gem_watchdog(struct gem_softc *sc)
1814 struct ifnet *ifp = sc->sc_ifp;
1816 GEM_LOCK_ASSERT(sc, MA_OWNED);
1820 "%s: GEM_RX_CONFIG %x GEM_MAC_RX_STATUS %x GEM_MAC_RX_CONFIG %x",
1821 __func__, GEM_BANK1_READ_4(sc, GEM_RX_CONFIG),
1822 GEM_BANK1_READ_4(sc, GEM_MAC_RX_STATUS),
1823 GEM_BANK1_READ_4(sc, GEM_MAC_RX_CONFIG));
1825 "%s: GEM_TX_CONFIG %x GEM_MAC_TX_STATUS %x GEM_MAC_TX_CONFIG %x",
1826 __func__, GEM_BANK1_READ_4(sc, GEM_TX_CONFIG),
1827 GEM_BANK1_READ_4(sc, GEM_MAC_TX_STATUS),
1828 GEM_BANK1_READ_4(sc, GEM_MAC_TX_CONFIG));
1831 if (sc->sc_wdog_timer == 0 || --sc->sc_wdog_timer != 0)
1834 if ((sc->sc_flags & GEM_LINK) != 0)
1835 device_printf(sc->sc_dev, "device timeout\n");
1836 else if (bootverbose)
1837 device_printf(sc->sc_dev, "device timeout (no link)\n");
1838 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
1840 /* Try to get more packets going. */
1841 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1842 gem_init_locked(sc);
1843 gem_start_locked(ifp);
1844 return (EJUSTRETURN);
1848 gem_mifinit(struct gem_softc *sc)
1851 /* Configure the MIF in frame mode. */
1852 GEM_BANK1_WRITE_4(sc, GEM_MIF_CONFIG,
1853 GEM_BANK1_READ_4(sc, GEM_MIF_CONFIG) & ~GEM_MIF_CONFIG_BB_ENA);
1854 GEM_BANK1_BARRIER(sc, GEM_MIF_CONFIG, 4,
1855 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
1861 * The MII interface supports at least three different operating modes:
1863 * Bitbang mode is implemented using data, clock and output enable registers.
1865 * Frame mode is implemented by loading a complete frame into the frame
1866 * register and polling the valid bit for completion.
1868 * Polling mode uses the frame register but completion is indicated by
1873 gem_mii_readreg(device_t dev, int phy, int reg)
1875 struct gem_softc *sc;
1879 #ifdef GEM_DEBUG_PHY
1880 printf("%s: phy %d reg %d\n", __func__, phy, reg);
1883 sc = device_get_softc(dev);
1884 if ((sc->sc_flags & GEM_SERDES) != 0) {
1887 reg = GEM_MII_CONTROL;
1890 reg = GEM_MII_STATUS;
1899 reg = GEM_MII_ANLPAR;
1902 return (EXTSR_1000XFDX | EXTSR_1000XHDX);
1904 device_printf(sc->sc_dev,
1905 "%s: unhandled register %d\n", __func__, reg);
1908 return (GEM_BANK1_READ_4(sc, reg));
1911 /* Construct the frame command. */
1912 v = GEM_MIF_FRAME_READ |
1913 (phy << GEM_MIF_PHY_SHIFT) |
1914 (reg << GEM_MIF_REG_SHIFT);
1916 GEM_BANK1_WRITE_4(sc, GEM_MIF_FRAME, v);
1917 GEM_BANK1_BARRIER(sc, GEM_MIF_FRAME, 4,
1918 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
1919 for (n = 0; n < 100; n++) {
1921 v = GEM_BANK1_READ_4(sc, GEM_MIF_FRAME);
1922 if (v & GEM_MIF_FRAME_TA0)
1923 return (v & GEM_MIF_FRAME_DATA);
1926 device_printf(sc->sc_dev, "%s: timed out\n", __func__);
1931 gem_mii_writereg(device_t dev, int phy, int reg, int val)
1933 struct gem_softc *sc;
1937 #ifdef GEM_DEBUG_PHY
1938 printf("%s: phy %d reg %d val %x\n", phy, reg, val, __func__);
1941 sc = device_get_softc(dev);
1942 if ((sc->sc_flags & GEM_SERDES) != 0) {
1945 reg = GEM_MII_STATUS;
1948 reg = GEM_MII_CONTROL;
1949 if ((val & GEM_MII_CONTROL_RESET) == 0)
1951 GEM_BANK1_WRITE_4(sc, GEM_MII_CONTROL, val);
1952 GEM_BANK1_BARRIER(sc, GEM_MII_CONTROL, 4,
1953 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
1954 if (!GEM_BANK1_BITWAIT(sc, GEM_MII_CONTROL,
1955 GEM_MII_CONTROL_RESET, 0))
1956 device_printf(sc->sc_dev,
1957 "cannot reset PCS\n");
1960 GEM_BANK1_WRITE_4(sc, GEM_MII_CONFIG, 0);
1961 GEM_BANK1_BARRIER(sc, GEM_MII_CONFIG, 4,
1962 BUS_SPACE_BARRIER_WRITE);
1963 GEM_BANK1_WRITE_4(sc, GEM_MII_ANAR, val);
1964 GEM_BANK1_BARRIER(sc, GEM_MII_ANAR, 4,
1965 BUS_SPACE_BARRIER_WRITE);
1966 GEM_BANK1_WRITE_4(sc, GEM_MII_SLINK_CONTROL,
1967 GEM_MII_SLINK_LOOPBACK | GEM_MII_SLINK_EN_SYNC_D);
1968 GEM_BANK1_BARRIER(sc, GEM_MII_SLINK_CONTROL, 4,
1969 BUS_SPACE_BARRIER_WRITE);
1970 GEM_BANK1_WRITE_4(sc, GEM_MII_CONFIG,
1971 GEM_MII_CONFIG_ENABLE);
1972 GEM_BANK1_BARRIER(sc, GEM_MII_CONFIG, 4,
1973 BUS_SPACE_BARRIER_WRITE);
1976 reg = GEM_MII_ANLPAR;
1979 device_printf(sc->sc_dev,
1980 "%s: unhandled register %d\n", __func__, reg);
1983 GEM_BANK1_WRITE_4(sc, reg, val);
1984 GEM_BANK1_BARRIER(sc, reg, 4,
1985 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
1989 /* Construct the frame command. */
1990 v = GEM_MIF_FRAME_WRITE |
1991 (phy << GEM_MIF_PHY_SHIFT) |
1992 (reg << GEM_MIF_REG_SHIFT) |
1993 (val & GEM_MIF_FRAME_DATA);
1995 GEM_BANK1_WRITE_4(sc, GEM_MIF_FRAME, v);
1996 GEM_BANK1_BARRIER(sc, GEM_MIF_FRAME, 4,
1997 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
1998 for (n = 0; n < 100; n++) {
2000 v = GEM_BANK1_READ_4(sc, GEM_MIF_FRAME);
2001 if (v & GEM_MIF_FRAME_TA0)
2005 device_printf(sc->sc_dev, "%s: timed out\n", __func__);
2010 gem_mii_statchg(device_t dev)
2012 struct gem_softc *sc;
2014 uint32_t rxcfg, txcfg, v;
2016 sc = device_get_softc(dev);
2018 GEM_LOCK_ASSERT(sc, MA_OWNED);
2021 if ((sc->sc_ifp->if_flags & IFF_DEBUG) != 0)
2022 device_printf(sc->sc_dev, "%s: status change\n", __func__);
2025 if ((sc->sc_mii->mii_media_status & IFM_ACTIVE) != 0 &&
2026 IFM_SUBTYPE(sc->sc_mii->mii_media_active) != IFM_NONE)
2027 sc->sc_flags |= GEM_LINK;
2029 sc->sc_flags &= ~GEM_LINK;
2031 switch (IFM_SUBTYPE(sc->sc_mii->mii_media_active)) {
2043 * The configuration done here corresponds to the steps F) and
2044 * G) and as far as enabling of RX and TX MAC goes also step H)
2045 * of the initialization sequence outlined in section 3.2.1 of
2046 * the GEM Gigabit Ethernet ASIC Specification.
2049 rxcfg = sc->sc_mac_rxcfg;
2050 rxcfg &= ~GEM_MAC_RX_CARR_EXTEND;
2051 txcfg = GEM_MAC_TX_ENA_IPG0 | GEM_MAC_TX_NGU | GEM_MAC_TX_NGU_LIMIT;
2052 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) != 0)
2053 txcfg |= GEM_MAC_TX_IGN_CARRIER | GEM_MAC_TX_IGN_COLLIS;
2054 else if (gigabit != 0) {
2055 rxcfg |= GEM_MAC_RX_CARR_EXTEND;
2056 txcfg |= GEM_MAC_TX_CARR_EXTEND;
2058 (void)gem_disable_tx(sc);
2059 GEM_BANK1_WRITE_4(sc, GEM_MAC_TX_CONFIG, txcfg);
2060 (void)gem_disable_rx(sc);
2061 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CONFIG, rxcfg);
2063 v = GEM_BANK1_READ_4(sc, GEM_MAC_CONTROL_CONFIG) &
2064 ~(GEM_MAC_CC_RX_PAUSE | GEM_MAC_CC_TX_PAUSE);
2065 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) &
2066 IFM_ETH_RXPAUSE) != 0)
2067 v |= GEM_MAC_CC_RX_PAUSE;
2068 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) &
2069 IFM_ETH_TXPAUSE) != 0)
2070 v |= GEM_MAC_CC_TX_PAUSE;
2071 GEM_BANK1_WRITE_4(sc, GEM_MAC_CONTROL_CONFIG, v);
2073 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) == 0 &&
2075 GEM_BANK1_WRITE_4(sc, GEM_MAC_SLOT_TIME,
2076 GEM_MAC_SLOT_TIME_CARR_EXTEND);
2078 GEM_BANK1_WRITE_4(sc, GEM_MAC_SLOT_TIME,
2079 GEM_MAC_SLOT_TIME_NORMAL);
2081 /* XIF Configuration */
2082 v = GEM_MAC_XIF_LINK_LED;
2083 v |= GEM_MAC_XIF_TX_MII_ENA;
2084 if ((sc->sc_flags & GEM_SERDES) == 0) {
2085 if ((GEM_BANK1_READ_4(sc, GEM_MIF_CONFIG) &
2086 GEM_MIF_CONFIG_PHY_SEL) != 0) {
2087 /* External MII needs echo disable if half duplex. */
2088 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) &
2090 v |= GEM_MAC_XIF_ECHO_DISABL;
2093 * Internal MII needs buffer enable.
2094 * XXX buffer enable makes only sense for an
2097 v |= GEM_MAC_XIF_MII_BUF_ENA;
2100 v |= GEM_MAC_XIF_GMII_MODE;
2101 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) != 0)
2102 v |= GEM_MAC_XIF_FDPLX_LED;
2103 GEM_BANK1_WRITE_4(sc, GEM_MAC_XIF_CONFIG, v);
2105 sc->sc_mac_rxcfg = rxcfg;
2106 if ((sc->sc_ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 &&
2107 (sc->sc_flags & GEM_LINK) != 0) {
2108 GEM_BANK1_WRITE_4(sc, GEM_MAC_TX_CONFIG,
2109 txcfg | GEM_MAC_TX_ENABLE);
2110 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CONFIG,
2111 rxcfg | GEM_MAC_RX_ENABLE);
2116 gem_mediachange(struct ifnet *ifp)
2118 struct gem_softc *sc = ifp->if_softc;
2121 /* XXX add support for serial media. */
2124 error = mii_mediachg(sc->sc_mii);
2130 gem_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
2132 struct gem_softc *sc = ifp->if_softc;
2135 if ((ifp->if_flags & IFF_UP) == 0) {
2140 mii_pollstat(sc->sc_mii);
2141 ifmr->ifm_active = sc->sc_mii->mii_media_active;
2142 ifmr->ifm_status = sc->sc_mii->mii_media_status;
2147 gem_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
2149 struct gem_softc *sc = ifp->if_softc;
2150 struct ifreq *ifr = (struct ifreq *)data;
2157 if ((ifp->if_flags & IFF_UP) != 0) {
2158 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 &&
2159 ((ifp->if_flags ^ sc->sc_ifflags) &
2160 (IFF_ALLMULTI | IFF_PROMISC)) != 0)
2163 gem_init_locked(sc);
2164 } else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
2166 if ((ifp->if_flags & IFF_LINK0) != 0)
2167 sc->sc_csum_features |= CSUM_UDP;
2169 sc->sc_csum_features &= ~CSUM_UDP;
2170 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0)
2171 ifp->if_hwassist = sc->sc_csum_features;
2172 sc->sc_ifflags = ifp->if_flags;
2178 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
2184 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii->mii_media, cmd);
2188 ifp->if_capenable = ifr->ifr_reqcap;
2189 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0)
2190 ifp->if_hwassist = sc->sc_csum_features;
2192 ifp->if_hwassist = 0;
2196 error = ether_ioctl(ifp, cmd, data);
2204 gem_setladrf(struct gem_softc *sc)
2206 struct ifnet *ifp = sc->sc_ifp;
2207 struct ifmultiaddr *inm;
2212 GEM_LOCK_ASSERT(sc, MA_OWNED);
2215 * Turn off the RX MAC and the hash filter as required by the Sun GEM
2216 * programming restrictions.
2218 v = sc->sc_mac_rxcfg & ~GEM_MAC_RX_HASH_FILTER;
2219 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CONFIG, v);
2220 GEM_BANK1_BARRIER(sc, GEM_MAC_RX_CONFIG, 4,
2221 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
2222 if (!GEM_BANK1_BITWAIT(sc, GEM_MAC_RX_CONFIG, GEM_MAC_RX_HASH_FILTER |
2223 GEM_MAC_RX_ENABLE, 0))
2224 device_printf(sc->sc_dev,
2225 "cannot disable RX MAC or hash filter\n");
2227 v &= ~(GEM_MAC_RX_PROMISCUOUS | GEM_MAC_RX_PROMISC_GRP);
2228 if ((ifp->if_flags & IFF_PROMISC) != 0) {
2229 v |= GEM_MAC_RX_PROMISCUOUS;
2232 if ((ifp->if_flags & IFF_ALLMULTI) != 0) {
2233 v |= GEM_MAC_RX_PROMISC_GRP;
2238 * Set up multicast address filter by passing all multicast
2239 * addresses through a crc generator, and then using the high
2240 * order 8 bits as an index into the 256 bit logical address
2241 * filter. The high order 4 bits selects the word, while the
2242 * other 4 bits select the bit within the word (where bit 0
2246 /* Clear the hash table. */
2247 memset(hash, 0, sizeof(hash));
2249 if_maddr_rlock(ifp);
2250 TAILQ_FOREACH(inm, &ifp->if_multiaddrs, ifma_link) {
2251 if (inm->ifma_addr->sa_family != AF_LINK)
2253 crc = ether_crc32_le(LLADDR((struct sockaddr_dl *)
2254 inm->ifma_addr), ETHER_ADDR_LEN);
2256 /* We just want the 8 most significant bits. */
2259 /* Set the corresponding bit in the filter. */
2260 hash[crc >> 4] |= 1 << (15 - (crc & 15));
2262 if_maddr_runlock(ifp);
2264 v |= GEM_MAC_RX_HASH_FILTER;
2266 /* Now load the hash table into the chip (if we are using it). */
2267 for (i = 0; i < 16; i++)
2268 GEM_BANK1_WRITE_4(sc,
2269 GEM_MAC_HASH0 + i * (GEM_MAC_HASH1 - GEM_MAC_HASH0),
2273 sc->sc_mac_rxcfg = v;
2274 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CONFIG, v | GEM_MAC_RX_ENABLE);