2 * Copyright (C) 2001 Eduardo Horvath.
3 * Copyright (c) 2007 Marius Strobl <marius@FreeBSD.org>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * from: NetBSD: if_gem_pci.c,v 1.7 2001/10/18 15:09:15 thorpej Exp
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
35 * PCI bindings for Apple GMAC, Sun ERI and Sun GEM Ethernet controllers
38 #include <sys/param.h>
39 #include <sys/systm.h>
41 #include <sys/kernel.h>
43 #include <sys/malloc.h>
44 #include <sys/module.h>
45 #include <sys/mutex.h>
46 #include <sys/resource.h>
48 #include <sys/socket.h>
50 #include <net/ethernet.h>
53 #include <machine/bus.h>
54 #if defined(__powerpc__) || defined(__sparc64__)
55 #include <dev/ofw/ofw_bus.h>
56 #include <dev/ofw/openfirm.h>
57 #include <machine/ofw_machdep.h>
59 #include <machine/resource.h>
61 #include <dev/gem/if_gemreg.h>
62 #include <dev/gem/if_gemvar.h>
64 #include <dev/pci/pcireg.h>
65 #include <dev/pci/pcivar.h>
67 #include "miibus_if.h"
69 static int gem_pci_attach(device_t dev);
70 static int gem_pci_detach(device_t dev);
71 static int gem_pci_probe(device_t dev);
72 static int gem_pci_resume(device_t dev);
73 static int gem_pci_suspend(device_t dev);
75 static device_method_t gem_pci_methods[] = {
76 /* Device interface */
77 DEVMETHOD(device_probe, gem_pci_probe),
78 DEVMETHOD(device_attach, gem_pci_attach),
79 DEVMETHOD(device_detach, gem_pci_detach),
80 DEVMETHOD(device_suspend, gem_pci_suspend),
81 DEVMETHOD(device_resume, gem_pci_resume),
82 /* Use the suspend handler here, it is all that is required. */
83 DEVMETHOD(device_shutdown, gem_pci_suspend),
86 DEVMETHOD(bus_print_child, bus_generic_print_child),
87 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
90 DEVMETHOD(miibus_readreg, gem_mii_readreg),
91 DEVMETHOD(miibus_writereg, gem_mii_writereg),
92 DEVMETHOD(miibus_statchg, gem_mii_statchg),
97 static driver_t gem_pci_driver = {
100 sizeof(struct gem_softc)
103 DRIVER_MODULE(gem, pci, gem_pci_driver, gem_devclass, 0, 0);
104 MODULE_DEPEND(gem, pci, 1, 1, 1);
105 MODULE_DEPEND(gem, ether, 1, 1, 1);
107 static const struct gem_pci_dev {
110 const char *gpd_desc;
111 } const gem_pci_devlist[] = {
112 { 0x1101108e, GEM_SUN_ERI, "Sun ERI 10/100 Ethernet" },
113 { 0x2bad108e, GEM_SUN_GEM, "Sun GEM Gigabit Ethernet" },
114 { 0x0021106b, GEM_APPLE_GMAC, "Apple UniNorth GMAC Ethernet" },
115 { 0x0024106b, GEM_APPLE_GMAC, "Apple Pangea GMAC Ethernet" },
116 { 0x0032106b, GEM_APPLE_GMAC, "Apple UniNorth2 GMAC Ethernet" },
117 { 0x004c106b, GEM_APPLE_K2_GMAC,"Apple K2 GMAC Ethernet" },
118 { 0x0051106b, GEM_APPLE_GMAC, "Apple Shasta GMAC Ethernet" },
119 { 0x006b106b, GEM_APPLE_GMAC, "Apple Intrepid 2 GMAC Ethernet" },
124 gem_pci_probe(device_t dev)
128 for (i = 0; gem_pci_devlist[i].gpd_desc != NULL; i++) {
129 if (pci_get_devid(dev) == gem_pci_devlist[i].gpd_devid) {
130 device_set_desc(dev, gem_pci_devlist[i].gpd_desc);
131 return (BUS_PROBE_DEFAULT);
138 static struct resource_spec gem_pci_res_spec[] = {
139 { SYS_RES_IRQ, 0, RF_SHAREABLE | RF_ACTIVE }, /* GEM_RES_INTR */
140 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, /* GEM_RES_BANK1 */
144 #define GEM_SHARED_PINS "shared-pins"
145 #define GEM_SHARED_PINS_SERDES "serdes"
148 gem_pci_attach(device_t dev)
150 struct gem_softc *sc;
152 #if defined(__powerpc__) || defined(__sparc64__)
153 char buf[sizeof(GEM_SHARED_PINS)];
158 sc = device_get_softc(dev);
159 sc->sc_variant = GEM_UNKNOWN;
160 for (i = 0; gem_pci_devlist[i].gpd_desc != NULL; i++) {
161 if (pci_get_devid(dev) == gem_pci_devlist[i].gpd_devid) {
162 sc->sc_variant = gem_pci_devlist[i].gpd_variant;
166 if (sc->sc_variant == GEM_UNKNOWN) {
167 device_printf(dev, "unknown adaptor\n");
171 pci_enable_busmaster(dev);
174 * Some Sun GEMs/ERIs do have their intpin register bogusly set to 0,
175 * although it should be 1. Correct that.
177 if (pci_get_intpin(dev) == 0)
178 pci_set_intpin(dev, 1);
180 /* Set the PCI latency timer for Sun ERIs. */
181 if (sc->sc_variant == GEM_SUN_ERI)
182 pci_write_config(dev, PCIR_LATTIMER, GEM_ERI_LATENCY_TIMER, 1);
185 sc->sc_flags |= GEM_PCI;
187 if (bus_alloc_resources(dev, gem_pci_res_spec, sc->sc_res)) {
188 device_printf(dev, "failed to allocate resources\n");
189 bus_release_resources(dev, gem_pci_res_spec, sc->sc_res);
193 GEM_LOCK_INIT(sc, device_get_nameunit(dev));
196 * Derive GEM_RES_BANK2 from GEM_RES_BANK1. This seemed cleaner
197 * with the old way of using copies of the bus tag and handle in
198 * the softc along with bus_space_*()...
200 sc->sc_res[GEM_RES_BANK2] = malloc(sizeof(*sc->sc_res[GEM_RES_BANK2]),
201 M_DEVBUF, M_NOWAIT | M_ZERO);
202 if (sc->sc_res[GEM_RES_BANK2] == NULL) {
203 device_printf(dev, "failed to allocate bank2 resource\n");
206 rman_set_bustag(sc->sc_res[GEM_RES_BANK2],
207 rman_get_bustag(sc->sc_res[GEM_RES_BANK1]));
208 bus_space_subregion(rman_get_bustag(sc->sc_res[GEM_RES_BANK1]),
209 rman_get_bushandle(sc->sc_res[GEM_RES_BANK1]),
210 GEM_PCI_BANK2_OFFSET, GEM_PCI_BANK2_SIZE,
211 &sc->sc_res[GEM_RES_BANK2]->r_bushandle);
213 /* Determine whether we're running at 66MHz. */
214 if ((GEM_BANK2_READ_4(sc, GEM_PCI_BIF_CONFIG) &
215 GEM_PCI_BIF_CNF_M66EN) != 0)
216 sc->sc_flags |= GEM_PCI66;
218 #if defined(__powerpc__) || defined(__sparc64__)
219 OF_getetheraddr(dev, sc->sc_enaddr);
220 if (OF_getprop(ofw_bus_get_node(dev), GEM_SHARED_PINS, buf,
222 buf[sizeof(buf) - 1] = '\0';
223 if (strcmp(buf, GEM_SHARED_PINS_SERDES) == 0)
224 sc->sc_flags |= GEM_SERDES;
228 * Dig out VPD (vital product data) and read NA (network address).
229 * The VPD resides in the PCI Expansion ROM (PCI FCode) and can't
230 * be accessed via the PCI capability pointer.
231 * ``Writing FCode 3.x Programs'' (newer ones, dated 1997 and later)
232 * chapter 2 describes the data structure.
235 #define PCI_ROMHDR_SIZE 0x1c
236 #define PCI_ROMHDR_SIG 0x00
237 #define PCI_ROMHDR_SIG_MAGIC 0xaa55 /* little endian */
238 #define PCI_ROMHDR_PTR_DATA 0x18
239 #define PCI_ROM_SIZE 0x18
240 #define PCI_ROM_SIG 0x00
241 #define PCI_ROM_SIG_MAGIC 0x52494350 /* "PCIR", endian */
243 #define PCI_ROM_VENDOR 0x04
244 #define PCI_ROM_DEVICE 0x06
245 #define PCI_ROM_PTR_VPD 0x08
246 #define PCI_VPDRES_BYTE0 0x00
247 #define PCI_VPDRES_ISLARGE(x) ((x) & 0x80)
248 #define PCI_VPDRES_LARGE_NAME(x) ((x) & 0x7f)
249 #define PCI_VPDRES_LARGE_LEN_LSB 0x01
250 #define PCI_VPDRES_LARGE_LEN_MSB 0x02
251 #define PCI_VPDRES_LARGE_SIZE 0x03
252 #define PCI_VPDRES_TYPE_VPD 0x10 /* large */
253 #define PCI_VPD_KEY0 0x00
254 #define PCI_VPD_KEY1 0x01
255 #define PCI_VPD_LEN 0x02
256 #define PCI_VPD_SIZE 0x03
258 #define GEM_ROM_READ_1(sc, offs) \
259 GEM_BANK1_READ_1((sc), GEM_PCI_ROM_OFFSET + (offs))
260 #define GEM_ROM_READ_2(sc, offs) \
261 GEM_BANK1_READ_2((sc), GEM_PCI_ROM_OFFSET + (offs))
262 #define GEM_ROM_READ_4(sc, offs) \
263 GEM_BANK1_READ_4((sc), GEM_PCI_ROM_OFFSET + (offs))
265 /* Read PCI Expansion ROM header. */
266 if (GEM_ROM_READ_2(sc, PCI_ROMHDR_SIG) != PCI_ROMHDR_SIG_MAGIC ||
267 (i = GEM_ROM_READ_2(sc, PCI_ROMHDR_PTR_DATA)) <
269 device_printf(dev, "unexpected PCI Expansion ROM header\n");
273 /* Read PCI Expansion ROM data. */
274 if (GEM_ROM_READ_4(sc, i + PCI_ROM_SIG) != PCI_ROM_SIG_MAGIC ||
275 GEM_ROM_READ_2(sc, i + PCI_ROM_VENDOR) != pci_get_vendor(dev) ||
276 GEM_ROM_READ_2(sc, i + PCI_ROM_DEVICE) != pci_get_device(dev) ||
277 (j = GEM_ROM_READ_2(sc, i + PCI_ROM_PTR_VPD)) <
279 device_printf(dev, "unexpected PCI Expansion ROM data\n");
285 * SUNW,pci-gem cards have a single large resource VPD-R tag
286 * containing one NA. The VPD used is not in PCI 2.2 standard
287 * format however. The length in the resource header is in big
288 * endian and the end tag is non-standard (0x79) and followed
289 * by an all-zero "checksum" byte. Sun calls this a "Fresh
290 * Choice Ethernet" VPD...
292 if (PCI_VPDRES_ISLARGE(GEM_ROM_READ_1(sc,
293 j + PCI_VPDRES_BYTE0)) == 0 ||
294 PCI_VPDRES_LARGE_NAME(GEM_ROM_READ_1(sc,
295 j + PCI_VPDRES_BYTE0)) != PCI_VPDRES_TYPE_VPD ||
296 ((GEM_ROM_READ_1(sc, j + PCI_VPDRES_LARGE_LEN_LSB) << 8) |
297 GEM_ROM_READ_1(sc, j + PCI_VPDRES_LARGE_LEN_MSB)) !=
298 PCI_VPD_SIZE + ETHER_ADDR_LEN ||
299 GEM_ROM_READ_1(sc, j + PCI_VPDRES_LARGE_SIZE + PCI_VPD_KEY0) !=
301 GEM_ROM_READ_1(sc, j + PCI_VPDRES_LARGE_SIZE + PCI_VPD_KEY1) !=
303 GEM_ROM_READ_1(sc, j + PCI_VPDRES_LARGE_SIZE + PCI_VPD_LEN) !=
305 GEM_ROM_READ_1(sc, j + PCI_VPDRES_LARGE_SIZE + PCI_VPD_SIZE +
306 ETHER_ADDR_LEN) != 0x79) {
307 device_printf(dev, "unexpected PCI VPD\n");
310 bus_read_region_1(sc->sc_res[GEM_RES_BANK1],
311 GEM_PCI_ROM_OFFSET + j + PCI_VPDRES_LARGE_SIZE + PCI_VPD_SIZE,
312 sc->sc_enaddr, ETHER_ADDR_LEN);
315 * The Xserve G5 has a fake GMAC with an all-zero MAC address.
316 * Check for this, and don't attach in this case.
319 for (i = 0; i < ETHER_ADDR_LEN && sc->sc_enaddr[i] == 0; i++) {}
320 if (i == ETHER_ADDR_LEN) {
321 device_printf(dev, "invalid MAC address\n");
325 if (gem_attach(sc) != 0) {
326 device_printf(dev, "could not be attached\n");
330 if (bus_setup_intr(dev, sc->sc_res[GEM_RES_INTR], INTR_TYPE_NET |
331 INTR_MPSAFE, NULL, gem_intr, sc, &sc->sc_ih) != 0) {
332 device_printf(dev, "failed to set up interrupt\n");
339 if (sc->sc_res[GEM_RES_BANK2] != NULL)
340 free(sc->sc_res[GEM_RES_BANK2], M_DEVBUF);
341 GEM_LOCK_DESTROY(sc);
342 bus_release_resources(dev, gem_pci_res_spec, sc->sc_res);
347 gem_pci_detach(device_t dev)
349 struct gem_softc *sc;
351 sc = device_get_softc(dev);
352 bus_teardown_intr(dev, sc->sc_res[GEM_RES_INTR], sc->sc_ih);
354 free(sc->sc_res[GEM_RES_BANK2], M_DEVBUF);
355 GEM_LOCK_DESTROY(sc);
356 bus_release_resources(dev, gem_pci_res_spec, sc->sc_res);
361 gem_pci_suspend(device_t dev)
364 gem_suspend(device_get_softc(dev));
369 gem_pci_resume(device_t dev)
372 gem_resume(device_get_softc(dev));