2 * Copyright (C) 2001 Eduardo Horvath.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * from: NetBSD: gemreg.h,v 1.9 2006/11/24 13:01:07 martin Exp
35 /* Register definitions for Sun GEM gigabit ethernet */
38 * First bank: this registers live at the start of the PCI
39 * mapping, and at the start of the second bank of the SBus
42 #define GEM_SEB_STATE 0x0000 /* SEB state reg, R/O */
43 #define GEM_CONFIG 0x0004 /* config reg */
44 #define GEM_STATUS 0x000c /* status reg */
45 /* Note: Reading the status reg clears bits 0-6. */
46 #define GEM_INTMASK 0x0010
47 #define GEM_INTACK 0x0014 /* Interrupt acknowledge, W/O */
48 #define GEM_STATUS_ALIAS 0x001c
51 * Second bank: this registers live at offset 0x1000 of the PCI
52 * mapping, and at the start of the first bank of the SBus
55 #define GEM_PCI_BANK2_OFFSET 0x1000
56 #define GEM_PCI_BANK2_SIZE 0x14
57 /* This is the same as the GEM_STATUS reg but reading it does not clear bits. */
58 #define GEM_ERROR_STATUS 0x0000 /* PCI error status R/C */
59 #define GEM_ERROR_MASK 0x0004
60 #define GEM_SBUS_CONFIG 0x0004
61 #define GEM_BIF_CONFIG 0x0008 /* BIF config reg */
62 #define GEM_BIF_DIAG 0x000c
63 #define GEM_RESET 0x0010 /* Software reset register */
66 /* Bits in GEM_SEB register */
67 #define GEM_SEB_ARB 0x000000002 /* Arbitration status */
68 #define GEM_SEB_RXWON 0x000000004
70 /* Bits in GEM_SBUS_CONFIG register */
71 #define GEM_SBUS_CFG_BMODE64 0x00000008
72 #define GEM_SBUS_CFG_PARITY 0x00000200
74 /* Bits in GEM_CONFIG register */
75 #define GEM_CONFIG_BURST_64 0x000000000 /* maximum burst size 64KB */
76 #define GEM_CONFIG_BURST_INF 0x000000001 /* infinite for entire packet */
77 #define GEM_CONFIG_TXDMA_LIMIT 0x00000003e
78 #define GEM_CONFIG_RXDMA_LIMIT 0x0000007c0
79 /* GEM_CONFIG_RONPAULBIT and GEM_CONFIG_BUG2FIX are Apple only. */
80 #define GEM_CONFIG_RONPAULBIT 0x000000800 /* after infinite burst use */
81 /* memory read multiple for */
83 #define GEM_CONFIG_BUG2FIX 0x000001000 /* fix RX hang after overflow */
85 #define GEM_CONFIG_TXDMA_LIMIT_SHIFT 1
86 #define GEM_CONFIG_RXDMA_LIMIT_SHIFT 6
89 /* Top part of GEM_STATUS has TX completion information */
90 #define GEM_STATUS_TX_COMPL 0xfff800000 /* TX completion reg. */
94 * Interrupt bits, for both the GEM_STATUS and GEM_INTMASK regs
95 * Bits 0-6 auto-clear when read.
97 #define GEM_INTR_TX_INTME 0x000000001 /* Frame w/INTME bit set sent */
98 #define GEM_INTR_TX_EMPTY 0x000000002 /* TX ring empty */
99 #define GEM_INTR_TX_DONE 0x000000004 /* TX complete */
100 #define GEM_INTR_RX_DONE 0x000000010 /* Got a packet */
101 #define GEM_INTR_RX_NOBUF 0x000000020
102 #define GEM_INTR_RX_TAG_ERR 0x000000040
103 #define GEM_INTR_PERR 0x000000080 /* Parity error */
104 #define GEM_INTR_PCS 0x000002000 /* Physical Code Sub-layer */
105 #define GEM_INTR_TX_MAC 0x000004000
106 #define GEM_INTR_RX_MAC 0x000008000
107 #define GEM_INTR_MAC_CONTROL 0x000010000 /* MAC control interrupt */
108 #define GEM_INTR_MIF 0x000020000
109 #define GEM_INTR_BERR 0x000040000 /* Bus error interrupt */
110 #define GEM_INTR_BITS "\177\020" \
111 "b\0INTME\0b\1TXEMPTY\0b\2TXDONE\0" \
112 "b\4RXDONE\0b\5RXNOBUF\0b\6RX_TAG_ERR\0" \
113 "b\xdPCS\0b\xeTXMAC\0b\xfRXMAC\0" \
114 "b\x10MAC_CONTROL\0b\x11MIF\0b\x12IBERR\0\0"
117 /* GEM_ERROR_STATUS and GEM_ERROR_MASK PCI error bits */
118 #define GEM_ERROR_STAT_BADACK 0x000000001 /* No ACK64# */
119 #define GEM_ERROR_STAT_DTRTO 0x000000002 /* Delayed xaction timeout */
120 #define GEM_ERROR_STAT_OTHERS 0x000000004
121 #define GEM_ERROR_BITS "\177\020b\0ACKBAD\0b\1DTRTO\0b\2OTHER\0\0"
124 /* GEM_BIF_CONFIG register bits */
125 #define GEM_BIF_CONFIG_SLOWCLK 0x000000001 /* Parity error timing */
126 #define GEM_BIF_CONFIG_HOST_64 0x000000002 /* 64-bit host */
127 #define GEM_BIF_CONFIG_B64D_DIS 0x000000004 /* no 64-bit data cycle */
128 #define GEM_BIF_CONFIG_M66EN 0x000000008
129 #define GEM_BIF_CONFIG_BITS "\177\020b\0SLOWCLK\0b\1HOST64\0" \
130 "b\2B64DIS\0b\3M66EN\0\0"
133 /* GEM_RESET register bits -- TX and RX self clear when complete. */
134 #define GEM_RESET_TX 0x000000001 /* Reset TX half */
135 #define GEM_RESET_RX 0x000000002 /* Reset RX half */
136 #define GEM_RESET_RSTOUT 0x000000004 /* Force PCI RSTOUT# */
139 /* The rest of the registers live in the first bank again. */
140 /* GEM TX DMA registers */
141 #define GEM_TX_KICK 0x2000 /* Write last valid desc + 1 */
142 #define GEM_TX_CONFIG 0x2004
143 #define GEM_TX_RING_PTR_LO 0x2008
144 #define GEM_TX_RING_PTR_HI 0x200c
146 #define GEM_TX_FIFO_WR_PTR 0x2014 /* FIFO write pointer */
147 #define GEM_TX_FIFO_SDWR_PTR 0x2018 /* FIFO shadow write pointer */
148 #define GEM_TX_FIFO_RD_PTR 0x201c /* FIFO read pointer */
149 #define GEM_TX_FIFO_SDRD_PTR 0x2020 /* FIFO shadow read pointer */
150 #define GEM_TX_FIFO_PKT_CNT 0x2024 /* FIFO packet counter */
152 #define GEM_TX_STATE_MACHINE 0x2028 /* ETX state machine reg */
153 #define GEM_TX_DATA_PTR_LO 0x2030
154 #define GEM_TX_DATA_PTR_HI 0x2034
156 #define GEM_TX_COMPLETION 0x2100
157 #define GEM_TX_FIFO_ADDRESS 0x2104
158 #define GEM_TX_FIFO_TAG 0x2108
159 #define GEM_TX_FIFO_DATA_LO 0x210c
160 #define GEM_TX_FIFO_DATA_HI_T1 0x2110
161 #define GEM_TX_FIFO_DATA_HI_T0 0x2114
162 #define GEM_TX_FIFO_SIZE 0x2118
163 #define GEM_TX_DEBUG 0x3028
166 /* GEM_TX_CONFIG register bits */
167 #define GEM_TX_CONFIG_TXDMA_EN 0x00000001 /* TX DMA enable */
168 #define GEM_TX_CONFIG_TXRING_SZ 0x0000001e /* TX ring size */
169 #define GEM_TX_CONFIG_TXFIFO_TH 0x001ffc00 /* TX fifo threshold */
170 #define GEM_TX_CONFIG_PACED 0x00200000 /* TX_all_int modifier */
172 #define GEM_RING_SZ_32 (0<<1) /* 32 descriptors */
173 #define GEM_RING_SZ_64 (1<<1)
174 #define GEM_RING_SZ_128 (2<<1)
175 #define GEM_RING_SZ_256 (3<<1)
176 #define GEM_RING_SZ_512 (4<<1)
177 #define GEM_RING_SZ_1024 (5<<1)
178 #define GEM_RING_SZ_2048 (6<<1)
179 #define GEM_RING_SZ_4096 (7<<1)
180 #define GEM_RING_SZ_8192 (8<<1)
183 /* GEM_TX_COMPLETION register bits */
184 #define GEM_TX_COMPLETION_MASK 0x00001fff /* # of last descriptor */
187 /* GEM RX DMA registers */
188 #define GEM_RX_CONFIG 0x4000
189 #define GEM_RX_RING_PTR_LO 0x4004 /* 64-bits unaligned GAK! */
190 #define GEM_RX_RING_PTR_HI 0x4008 /* 64-bits unaligned GAK! */
192 #define GEM_RX_FIFO_WR_PTR 0x400c /* FIFO write pointer */
193 #define GEM_RX_FIFO_SDWR_PTR 0x4010 /* FIFO shadow write pointer */
194 #define GEM_RX_FIFO_RD_PTR 0x4014 /* FIFO read pointer */
195 #define GEM_RX_FIFO_PKT_CNT 0x4018 /* FIFO packet counter */
197 #define GEM_RX_STATE_MACHINE 0x401c /* ERX state machine reg */
198 #define GEM_RX_PAUSE_THRESH 0x4020
200 #define GEM_RX_DATA_PTR_LO 0x4024 /* ERX state machine reg */
201 #define GEM_RX_DATA_PTR_HI 0x4028 /* Damn thing is unaligned */
203 #define GEM_RX_KICK 0x4100 /* Write last valid desc + 1 */
204 #define GEM_RX_COMPLETION 0x4104 /* First pending desc */
205 #define GEM_RX_BLANKING 0x4108 /* Interrupt blanking reg */
207 #define GEM_RX_FIFO_ADDRESS 0x410c
208 #define GEM_RX_FIFO_TAG 0x4110
209 #define GEM_RX_FIFO_DATA_LO 0x4114
210 #define GEM_RX_FIFO_DATA_HI_T1 0x4118
211 #define GEM_RX_FIFO_DATA_HI_T0 0x411c
212 #define GEM_RX_FIFO_SIZE 0x4120
215 /* GEM_RX_CONFIG register bits */
216 #define GEM_RX_CONFIG_RXDMA_EN 0x00000001 /* RX DMA enable */
217 #define GEM_RX_CONFIG_RXRING_SZ 0x0000001e /* RX ring size */
218 #define GEM_RX_CONFIG_BATCH_DIS 0x00000020 /* desc batching disable */
219 #define GEM_RX_CONFIG_FBOFF 0x00001c00 /* first byte offset */
220 #define GEM_RX_CONFIG_CXM_START 0x000fe000 /* cksum start offset bytes */
221 #define GEM_RX_CONFIG_FIFO_THRS 0x07000000 /* fifo threshold size */
223 #define GEM_THRSH_64 0
224 #define GEM_THRSH_128 1
225 #define GEM_THRSH_256 2
226 #define GEM_THRSH_512 3
227 #define GEM_THRSH_1024 4
228 #define GEM_THRSH_2048 5
230 #define GEM_RX_CONFIG_FIFO_THRS_SHIFT 24
231 #define GEM_RX_CONFIG_FBOFF_SHFT 10
232 #define GEM_RX_CONFIG_CXM_START_SHFT 13
235 /* GEM_RX_PAUSE_THRESH register bits -- sizes in multiples of 64 bytes */
236 #define GEM_RX_PTH_XOFF_THRESH 0x000001ff
237 #define GEM_RX_PTH_XON_THRESH 0x001ff000
240 /* GEM_RX_BLANKING register bits */
241 #define GEM_RX_BLANKING_PACKETS 0x000001ff /* Delay intr for x packets */
242 #define GEM_RX_BLANKING_TIME 0x000ff000 /* Delay intr for x ticks */
243 #define GEM_RX_BLANKING_TIME_SHIFT 12
244 /* One tick is 2048 PCI clocks, or 16us at 66MHz */
247 /* GEM_MAC registers */
248 #define GEM_MAC_TXRESET 0x6000 /* Store 1, cleared when done */
249 #define GEM_MAC_RXRESET 0x6004 /* ditto */
250 #define GEM_MAC_SEND_PAUSE_CMD 0x6008
251 #define GEM_MAC_TX_STATUS 0x6010
252 #define GEM_MAC_RX_STATUS 0x6014
253 #define GEM_MAC_CONTROL_STATUS 0x6018 /* MAC control status reg */
254 #define GEM_MAC_TX_MASK 0x6020 /* TX MAC mask register */
255 #define GEM_MAC_RX_MASK 0x6024
256 #define GEM_MAC_CONTROL_MASK 0x6028
257 #define GEM_MAC_TX_CONFIG 0x6030
258 #define GEM_MAC_RX_CONFIG 0x6034
259 #define GEM_MAC_CONTROL_CONFIG 0x6038
260 #define GEM_MAC_XIF_CONFIG 0x603c
261 #define GEM_MAC_IPG0 0x6040 /* inter packet gap 0 */
262 #define GEM_MAC_IPG1 0x6044 /* inter packet gap 1 */
263 #define GEM_MAC_IPG2 0x6048 /* inter packet gap 2 */
264 #define GEM_MAC_SLOT_TIME 0x604c /* slot time, bits 0-7 */
265 #define GEM_MAC_MAC_MIN_FRAME 0x6050
266 #define GEM_MAC_MAC_MAX_FRAME 0x6054
267 #define GEM_MAC_PREAMBLE_LEN 0x6058
268 #define GEM_MAC_JAM_SIZE 0x605c
269 #define GEM_MAC_ATTEMPT_LIMIT 0x6060
270 #define GEM_MAC_CONTROL_TYPE 0x6064
272 #define GEM_MAC_ADDR0 0x6080 /* Normal MAC address 0 */
273 #define GEM_MAC_ADDR1 0x6084
274 #define GEM_MAC_ADDR2 0x6088
275 #define GEM_MAC_ADDR3 0x608c /* Alternate MAC address 0 */
276 #define GEM_MAC_ADDR4 0x6090
277 #define GEM_MAC_ADDR5 0x6094
278 #define GEM_MAC_ADDR6 0x6098 /* Control MAC address 0 */
279 #define GEM_MAC_ADDR7 0x609c
280 #define GEM_MAC_ADDR8 0x60a0
282 #define GEM_MAC_ADDR_FILTER0 0x60a4
283 #define GEM_MAC_ADDR_FILTER1 0x60a8
284 #define GEM_MAC_ADDR_FILTER2 0x60ac
285 #define GEM_MAC_ADR_FLT_MASK1_2 0x60b0 /* Address filter mask 1,2 */
286 #define GEM_MAC_ADR_FLT_MASK0 0x60b4 /* Address filter mask 0 reg */
288 #define GEM_MAC_HASH0 0x60c0 /* Hash table 0 */
289 #define GEM_MAC_HASH1 0x60c4
290 #define GEM_MAC_HASH2 0x60c8
291 #define GEM_MAC_HASH3 0x60cc
292 #define GEM_MAC_HASH4 0x60d0
293 #define GEM_MAC_HASH5 0x60d4
294 #define GEM_MAC_HASH6 0x60d8
295 #define GEM_MAC_HASH7 0x60dc
296 #define GEM_MAC_HASH8 0x60e0
297 #define GEM_MAC_HASH9 0x60e4
298 #define GEM_MAC_HASH10 0x60e8
299 #define GEM_MAC_HASH11 0x60ec
300 #define GEM_MAC_HASH12 0x60f0
301 #define GEM_MAC_HASH13 0x60f4
302 #define GEM_MAC_HASH14 0x60f8
303 #define GEM_MAC_HASH15 0x60fc
305 #define GEM_MAC_NORM_COLL_CNT 0x6100 /* Normal collision counter */
306 #define GEM_MAC_FIRST_COLL_CNT 0x6104 /* 1st successful collision cntr */
307 #define GEM_MAC_EXCESS_COLL_CNT 0x6108 /* Excess collision counter */
308 #define GEM_MAC_LATE_COLL_CNT 0x610c /* Late collision counter */
309 #define GEM_MAC_DEFER_TMR_CNT 0x6110 /* defer timer counter */
310 #define GEM_MAC_PEAK_ATTEMPTS 0x6114
311 #define GEM_MAC_RX_FRAME_COUNT 0x6118
312 #define GEM_MAC_RX_LEN_ERR_CNT 0x611c
313 #define GEM_MAC_RX_ALIGN_ERR 0x6120
314 #define GEM_MAC_RX_CRC_ERR_CNT 0x6124
315 #define GEM_MAC_RX_CODE_VIOL 0x6128
316 #define GEM_MAC_RANDOM_SEED 0x6130
317 #define GEM_MAC_MAC_STATE 0x6134 /* MAC state machine reg */
320 /* GEM_MAC_SEND_PAUSE_CMD register bits */
321 #define GEM_MAC_PAUSE_CMD_TIME 0x0000ffff
322 #define GEM_MAC_PAUSE_CMD_SEND 0x00010000
325 /* GEM_MAC_TX_STATUS and _MASK register bits */
326 #define GEM_MAC_TX_XMIT_DONE 0x00000001
327 #define GEM_MAC_TX_UNDERRUN 0x00000002
328 #define GEM_MAC_TX_PKT_TOO_LONG 0x00000004
329 #define GEM_MAC_TX_NCC_EXP 0x00000008 /* Normal collision cnt exp */
330 #define GEM_MAC_TX_ECC_EXP 0x00000010
331 #define GEM_MAC_TX_LCC_EXP 0x00000020
332 #define GEM_MAC_TX_FCC_EXP 0x00000040
333 #define GEM_MAC_TX_DEFER_EXP 0x00000080
334 #define GEM_MAC_TX_PEAK_EXP 0x00000100
337 /* GEM_MAC_RX_STATUS and _MASK register bits */
338 #define GEM_MAC_RX_DONE 0x00000001
339 #define GEM_MAC_RX_OVERFLOW 0x00000002
340 #define GEM_MAC_RX_FRAME_CNT 0x00000004
341 #define GEM_MAC_RX_ALIGN_EXP 0x00000008
342 #define GEM_MAC_RX_CRC_EXP 0x00000010
343 #define GEM_MAC_RX_LEN_EXP 0x00000020
344 #define GEM_MAC_RX_CVI_EXP 0x00000040 /* Code violation */
347 /* GEM_MAC_CONTROL_STATUS and GEM_MAC_CONTROL_MASK register bits */
348 #define GEM_MAC_PAUSED 0x00000001 /* Pause received */
349 #define GEM_MAC_PAUSE 0x00000002 /* enter pause state */
350 #define GEM_MAC_RESUME 0x00000004 /* exit pause state */
351 #define GEM_MAC_PAUSE_TIME_SLTS 0xffff0000 /* pause time in slots */
352 #define GEM_MAC_STATUS_BITS "\177\020b\0PAUSED\0b\1PAUSE\0b\2RESUME\0\0"
354 #define GEM_MAC_PAUSE_TIME_SHFT 16
355 #define GEM_MAC_PAUSE_TIME(x) \
356 (((x) & GEM_MAC_PAUSE_TIME_SLTS) >> GEM_MAC_PAUSE_TIME_SHFT)
358 /* GEM_MAC_XIF_CONFIG register bits */
359 #define GEM_MAC_XIF_TX_MII_ENA 0x00000001 /* Enable XIF output drivers */
360 #define GEM_MAC_XIF_MII_LOOPBK 0x00000002 /* Enable MII loopback mode */
361 #define GEM_MAC_XIF_ECHO_DISABL 0x00000004 /* Disable echo */
362 #define GEM_MAC_XIF_GMII_MODE 0x00000008 /* Select GMII/MII mode */
363 #define GEM_MAC_XIF_MII_BUF_ENA 0x00000010 /* Enable MII recv buffers */
364 #define GEM_MAC_XIF_LINK_LED 0x00000020 /* force link LED active */
365 #define GEM_MAC_XIF_FDPLX_LED 0x00000040 /* force FDPLX LED active */
366 #define GEM_MAC_XIF_BITS "\177\020b\0TXMIIENA\0b\1MIILOOP\0b\2NOECHO" \
367 "\0b\3GMII\0b\4MIIBUFENA\0b\5LINKLED\0" \
371 * GEM_MAC_SLOT_TIME register
372 * The slot time is used as PAUSE time unit, value depends on whether carrier
373 * extension is enabled.
375 #define GEM_MAC_SLOT_TIME_CARR_EXTEND 0x200
376 #define GEM_MAC_SLOT_TIME_NORMAL 0x40
378 /* GEM_MAC_TX_CONFIG register bits */
379 #define GEM_MAC_TX_ENABLE 0x00000001 /* TX enable */
380 #define GEM_MAC_TX_IGN_CARRIER 0x00000002 /* Ignore carrier sense */
381 #define GEM_MAC_TX_IGN_COLLIS 0x00000004 /* ignore collisions */
382 #define GEM_MAC_TX_ENA_IPG0 0x00000008 /* extend RX-to-TX IPG */
383 #define GEM_MAC_TX_NGU 0x00000010 /* Never give up */
384 #define GEM_MAC_TX_NGU_LIMIT 0x00000020 /* Never give up limit */
385 #define GEM_MAC_TX_NO_BACKOFF 0x00000040
386 #define GEM_MAC_TX_SLOWDOWN 0x00000080
387 #define GEM_MAC_TX_NO_FCS 0x00000100 /* no FCS will be generated */
388 #define GEM_MAC_TX_CARR_EXTEND 0x00000200 /* Ena TX Carrier Extension */
389 /* Carrier Extension is required for half duplex Gbps operation */
390 #define GEM_MAC_TX_CONFIG_BITS "\177\020" \
391 "b\0TXENA\0b\1IGNCAR\0b\2IGNCOLLIS\0" \
392 "b\3IPG0ENA\0b\4TXNGU\0b\5TXNGULIM\0" \
393 "b\6NOBKOFF\0b\7SLOWDN\0b\x8NOFCS\0" \
397 /* GEM_MAC_RX_CONFIG register bits */
398 #define GEM_MAC_RX_ENABLE 0x00000001 /* RX enable */
399 #define GEM_MAC_RX_STRIP_PAD 0x00000002 /* strip pad bytes */
400 #define GEM_MAC_RX_STRIP_CRC 0x00000004
401 #define GEM_MAC_RX_PROMISCUOUS 0x00000008 /* promiscuous mode */
402 #define GEM_MAC_RX_PROMISC_GRP 0x00000010 /* promiscuous group mode */
403 #define GEM_MAC_RX_HASH_FILTER 0x00000020 /* enable hash filter */
404 #define GEM_MAC_RX_ADDR_FILTER 0x00000040 /* enable address filter */
405 #define GEM_MAC_RX_ERRCHK_DIS 0x00000080 /* disable error checking */
406 #define GEM_MAC_RX_CARR_EXTEND 0x00000100 /* Ena RX Carrier Extension */
408 * Carrier Extension enables reception of packet bursts generated by
409 * senders with carrier extension enabled.
411 #define GEM_MAC_RX_CONFIG_BITS "\177\020" \
412 "b\0RXENA\0b\1STRPAD\0b\2STRCRC\0" \
413 "b\3PROMIS\0b\4PROMISCGRP\0b\5HASHFLTR\0" \
414 "b\6ADDRFLTR\0b\7ERRCHKDIS\0b\x9TXCARREXT\0\0"
417 /* GEM_MAC_CONTROL_CONFIG bits */
418 #define GEM_MAC_CC_TX_PAUSE 0x00000001 /* send pause enabled */
419 #define GEM_MAC_CC_RX_PAUSE 0x00000002 /* receive pause enabled */
420 #define GEM_MAC_CC_PASS_PAUSE 0x00000004 /* pass pause up */
421 #define GEM_MAC_CC_BITS "\177\020b\0TXPAUSE\0b\1RXPAUSE\0b\2NOPAUSE\0\0"
424 /* GEM MIF registers */
425 /* Bit bang registers use low bit only. */
426 #define GEM_MIF_BB_CLOCK 0x6200 /* bit bang clock */
427 #define GEM_MIF_BB_DATA 0x6204 /* bit bang data */
428 #define GEM_MIF_BB_OUTPUT_ENAB 0x6208
429 #define GEM_MIF_FRAME 0x620c /* MIF frame - ctl and data */
430 #define GEM_MIF_CONFIG 0x6210
431 #define GEM_MIF_INTERRUPT_MASK 0x6214
432 #define GEM_MIF_BASIC_STATUS 0x6218
433 #define GEM_MIF_STATE_MACHINE 0x621c
436 /* GEM_MIF_FRAME bits */
437 #define GEM_MIF_FRAME_DATA 0x0000ffff
438 #define GEM_MIF_FRAME_TA0 0x00010000 /* TA bit, 1 for completion */
439 #define GEM_MIF_FRAME_TA1 0x00020000 /* TA bits */
440 #define GEM_MIF_FRAME_REG_ADDR 0x007c0000
441 #define GEM_MIF_FRAME_PHY_ADDR 0x0f800000 /* phy address, should be 0 */
442 #define GEM_MIF_FRAME_OP 0x30000000 /* operation - write/read */
443 #define GEM_MIF_FRAME_START 0xc0000000 /* START bits */
445 #define GEM_MIF_FRAME_READ 0x60020000
446 #define GEM_MIF_FRAME_WRITE 0x50020000
448 #define GEM_MIF_REG_SHIFT 18
449 #define GEM_MIF_PHY_SHIFT 23
452 /* GEM_MIF_CONFIG register bits */
453 #define GEM_MIF_CONFIG_PHY_SEL 0x00000001 /* PHY select, 0=MDIO0 */
454 #define GEM_MIF_CONFIG_POLL_ENA 0x00000002 /* poll enable */
455 #define GEM_MIF_CONFIG_BB_ENA 0x00000004 /* bit bang enable */
456 #define GEM_MIF_CONFIG_REG_ADR 0x000000f8 /* poll register address */
457 #define GEM_MIF_CONFIG_MDI0 0x00000100 /* MDIO_0 Data/MDIO_0 atached */
458 #define GEM_MIF_CONFIG_MDI1 0x00000200 /* MDIO_1 Data/MDIO_1 atached */
459 #define GEM_MIF_CONFIG_PHY_ADR 0x00007c00 /* poll PHY address */
460 /* MDI0 is the onboard transceiver, MDI1 is external, PHYAD for both is 0. */
461 #define GEM_MIF_CONFIG_BITS "\177\020b\0PHYSEL\0b\1POLL\0b\2BBENA\0" \
462 "b\x8MDIO0\0b\x9MDIO1\0\0"
465 /* GEM_MIF_BASIC_STATUS and GEM_MIF_INTERRUPT_MASK bits */
466 #define GEM_MIF_STATUS 0x0000ffff
467 #define GEM_MIF_BASIC 0xffff0000
469 * The Basic part is the last value read in the POLL field of the config
472 * The status part indicates the bits that have changed.
476 /* GEM PCS/Serial link registers */
477 /* DO NOT TOUCH THESE REGISTERS ON ERI -- IT HARD HANGS. */
478 #define GEM_MII_CONTROL 0x9000
479 #define GEM_MII_STATUS 0x9004
480 #define GEM_MII_ANAR 0x9008 /* MII advertisement reg */
481 #define GEM_MII_ANLPAR 0x900c /* Link Partner Ability Reg */
482 #define GEM_MII_CONFIG 0x9010
483 #define GEM_MII_STATE_MACHINE 0x9014
484 #define GEM_MII_INTERRUP_STATUS 0x9018 /* PCS interrupt state */
485 #define GEM_MII_DATAPATH_MODE 0x9050
486 #define GEM_MII_SLINK_CONTROL 0x9054 /* Serial link control */
487 #define GEM_MII_OUTPUT_SELECT 0x9058
488 #define GEM_MII_SLINK_STATUS 0x905c /* serial link status */
491 /* GEM_MII_CONTROL bits - PCS "BMCR" (Basic Mode Control Reg) */
492 #define GEM_MII_CONTROL_RESET 0x00008000
493 #define GEM_MII_CONTROL_LOOPBK 0x00004000 /* 10-bit i/f loopback */
494 #define GEM_MII_CONTROL_1000M 0x00002000 /* speed select, always 0 */
495 #define GEM_MII_CONTROL_AUTONEG 0x00001000 /* auto negotiation enabled */
496 #define GEM_MII_CONTROL_POWERDN 0x00000800
497 #define GEM_MII_CONTROL_ISOLATE 0x00000400 /* isolate phy from mii */
498 #define GEM_MII_CONTROL_RAN 0x00000200 /* restart auto negotiation */
499 #define GEM_MII_CONTROL_FDUPLEX 0x00000100 /* full duplex, always 0 */
500 #define GEM_MII_CONTROL_COL_TST 0x00000080 /* collision test */
501 #define GEM_MII_CONTROL_BITS "\177\020b\7COLTST\0b\x8_FD\0b\x9RAN\0" \
502 "b\xaISOLATE\0b\xbPWRDWN\0b\xc_ANEG\0" \
503 "b\xdGIGE\0b\xeLOOP\0b\xfRESET\0\0"
506 /* GEM_MII_STATUS reg - PCS "BMSR" (Basic Mode Status Reg) */
507 #define GEM_MII_STATUS_GB_FDX 0x00000400 /* can perform GBit FDX */
508 #define GEM_MII_STATUS_GB_HDX 0x00000200 /* can perform GBit HDX */
509 #define GEM_MII_STATUS_UNK 0x00000100
510 #define GEM_MII_STATUS_ANEG_CPT 0x00000020 /* auto negotiate compete */
511 #define GEM_MII_STATUS_REM_FLT 0x00000010 /* remote fault detected */
512 #define GEM_MII_STATUS_ACFG 0x00000008 /* can auto negotiate */
513 #define GEM_MII_STATUS_LINK_STS 0x00000004 /* link status */
514 #define GEM_MII_STATUS_JABBER 0x00000002 /* jabber condition detected */
515 #define GEM_MII_STATUS_EXTCAP 0x00000001 /* extended register capability */
516 #define GEM_MII_STATUS_BITS "\177\020b\0EXTCAP\0b\1JABBER\0b\2LINKSTS\0" \
517 "b\3ACFG\0b\4REMFLT\0b\5ANEGCPT\0b\x9GBHDX\0" \
521 /* GEM_MII_ANAR and GEM_MII_ANLPAR reg bits */
522 #define GEM_MII_ANEG_NP 0x00008000 /* next page bit */
523 #define GEM_MII_ANEG_ACK 0x00004000 /* ack reception of */
524 /* Link Partner Capability */
525 #define GEM_MII_ANEG_RF 0x00003000 /* advertise remote fault cap */
526 #define GEM_MII_ANEG_ASYM_PAUSE 0x00000100 /* asymmetric pause */
527 #define GEM_MII_ANEG_SYM_PAUSE 0x00000080 /* symmetric pause */
528 #define GEM_MII_ANEG_HLF_DUPLX 0x00000040
529 #define GEM_MII_ANEG_FUL_DUPLX 0x00000020
530 #define GEM_MII_ANEG_BITS "\177\020b\5FDX\0b\6HDX\0b\7SYMPAUSE\0" \
531 "\b\x8_ASYMPAUSE\0\b\xdREMFLT\0\b\xeLPACK\0" \
535 /* GEM_MII_CONFIG reg */
536 #define GEM_MII_CONFIG_TIMER 0x0000000e /* link monitor timer values */
537 #define GEM_MII_CONFIG_ANTO 0x00000020 /* 10ms ANEG timer override */
538 #define GEM_MII_CONFIG_JS 0x00000018 /* Jitter Study, 0 normal
539 * 1 high freq, 2 low freq */
540 #define GEM_MII_CONFIG_SDL 0x00000004 /* Signal Detect active low */
541 #define GEM_MII_CONFIG_SDO 0x00000002 /* Signal Detect Override */
542 #define GEM_MII_CONFIG_ENABLE 0x00000001 /* Enable PCS */
543 #define GEM_MII_CONFIG_BITS "\177\020b\0PCSENA\0\0"
547 * GEM_MII_STATE_MACHINE
548 * XXX These are best guesses from observed behavior.
550 #define GEM_MII_FSM_STOP 0x00000000 /* stopped */
551 #define GEM_MII_FSM_RUN 0x00000001 /* running */
552 #define GEM_MII_FSM_UNKWN 0x00000100 /* unknown */
553 #define GEM_MII_FSM_DONE 0x00000101 /* complete */
557 * GEM_MII_INTERRUP_STATUS reg
558 * No mask register; mask with the global interrupt mask register.
560 #define GEM_MII_INTERRUP_LINK 0x00000004 /* PCS link status change */
563 /* GEM_MII_DATAPATH_MODE reg */
564 #define GEM_MII_DATAPATH_SERIAL 0x00000001 /* Serial link */
565 #define GEM_MII_DATAPATH_SERDES 0x00000002 /* Use PCS via 10bit interfac */
566 #define GEM_MII_DATAPATH_MII 0x00000004 /* Use {G}MII, not PCS */
567 #define GEM_MII_DATAPATH_MIIOUT 0x00000008 /* enable serial output on GMII */
568 #define GEM_MII_DATAPATH_BITS "\177\020" \
569 "b\0SERIAL\0b\1SERDES\0b\2MII\0b\3MIIOUT\0\0"
572 /* GEM_MII_SLINK_CONTROL reg */
573 #define GEM_MII_SLINK_LOOPBACK 0x00000001 /* enable loopback at sl, logic
574 * reversed for SERDES */
575 #define GEM_MII_SLINK_EN_SYNC_D 0x00000002 /* enable sync detection */
576 #define GEM_MII_SLINK_LOCK_REF 0x00000004 /* lock reference clock */
577 #define GEM_MII_SLINK_EMPHASIS 0x00000008 /* enable emphasis */
578 #define GEM_MII_SLINK_SELFTEST 0x000001c0
579 #define GEM_MII_SLINK_POWER_OFF 0x00000200 /* Power down serial link */
580 #define GEM_MII_SLINK_CONTROL_BITS \
581 "\177\020b\0LOOP\0b\1ENASYNC\0b\2LOCKREF" \
582 "\0b\3EMPHASIS\0b\x9PWRDWN\0\0"
585 /* GEM_MII_SLINK_STATUS reg */
586 #define GEM_MII_SLINK_TEST 0x00000000 /* undergoing test */
587 #define GEM_MII_SLINK_LOCKED 0x00000001 /* waiting 500us lockrefn */
588 #define GEM_MII_SLINK_COMMA 0x00000002 /* waiting for comma detect */
589 #define GEM_MII_SLINK_SYNC 0x00000003 /* recv data synchronized */
592 * PCI Expansion ROM runtime access
593 * Sun GEMs map a 1MB space for the PCI Expansion ROM as the second half
594 * of the first register bank, although they only support up to 64KB ROMs.
596 #define GEM_PCI_ROM_OFFSET 0x100000
597 #define GEM_PCI_ROM_SIZE 0x10000
599 /* Wired GEM PHY addresses */
600 #define GEM_PHYAD_INTERNAL 1
601 #define GEM_PHYAD_EXTERNAL 0
604 * GEM descriptor table structures
612 #define GEM_TD_BUFSIZE 0x0000000000007fffLL
613 #define GEM_TD_CXSUM_START 0x00000000001f8000LL /* Cxsum start offset */
614 #define GEM_TD_CXSUM_STARTSHFT 15
615 #define GEM_TD_CXSUM_STUFF 0x000000001fe00000LL /* Cxsum stuff offset */
616 #define GEM_TD_CXSUM_STUFFSHFT 21
617 #define GEM_TD_CXSUM_ENABLE 0x0000000020000000LL /* Cxsum generation enable */
618 #define GEM_TD_END_OF_PACKET 0x0000000040000000LL
619 #define GEM_TD_START_OF_PACKET 0x0000000080000000LL
620 #define GEM_TD_INTERRUPT_ME 0x0000000100000000LL /* Interrupt me now */
621 #define GEM_TD_NO_CRC 0x0000000200000000LL /* do not insert crc */
623 * Only need to set GEM_TD_CXSUM_ENABLE, GEM_TD_CXSUM_STUFF,
624 * GEM_TD_CXSUM_START, and GEM_TD_INTERRUPT_ME in 1st descriptor of a group.
628 #define GEM_RD_CHECKSUM 0x000000000000ffffLL /* is the complement */
629 #define GEM_RD_BUFSIZE 0x000000007fff0000LL
630 #define GEM_RD_OWN 0x0000000080000000LL /* 1 - owned by h/w */
631 #define GEM_RD_HASHVAL 0x0ffff00000000000LL
632 #define GEM_RD_HASH_PASS 0x1000000000000000LL /* passed hash filter */
633 #define GEM_RD_ALTERNATE_MAC 0x2000000000000000LL /* Alternate MAC adrs */
634 #define GEM_RD_BAD_CRC 0x4000000000000000LL
636 #define GEM_RD_BUFSHIFT 16
637 #define GEM_RD_BUFLEN(x) (((x) & GEM_RD_BUFSIZE) >> GEM_RD_BUFSHIFT)