2 * Copyright (C) 2001 Eduardo Horvath.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * from: NetBSD: gemvar.h,v 1.8 2002/05/15 02:36:12 matt Exp
35 #include <sys/queue.h>
36 #include <sys/callout.h>
39 * Misc. definitions for the Sun ``Gem'' Ethernet controller family driver.
43 * Transmit descriptor list size. This is arbitrary, but allocate
44 * enough descriptors for 64 pending transmissions and 16 segments
45 * per packet. This limit is not actually enforced (packets with more segments
46 * can be sent, depending on the busdma backend); it is however used as an
47 * estimate for the tx window size.
49 #define GEM_NTXSEGS 16
51 #define GEM_TXQUEUELEN 64
52 #define GEM_NTXDESC (GEM_TXQUEUELEN * GEM_NTXSEGS)
53 #define GEM_MAXTXFREE (GEM_NTXDESC - 1)
54 #define GEM_NTXDESC_MASK (GEM_NTXDESC - 1)
55 #define GEM_NEXTTX(x) ((x + 1) & GEM_NTXDESC_MASK)
58 * Receive descriptor list size. We have one Rx buffer per incoming
59 * packet, so this logic is a little simpler.
61 #define GEM_NRXDESC 128
62 #define GEM_NRXDESC_MASK (GEM_NRXDESC - 1)
63 #define GEM_PREVRX(x) ((x - 1) & GEM_NRXDESC_MASK)
64 #define GEM_NEXTRX(x) ((x + 1) & GEM_NRXDESC_MASK)
67 * How many ticks to wait until to retry on a RX descriptor that is still owned
70 #define GEM_RXOWN_TICKS (hz / 50)
73 * Control structures are DMA'd to the GEM chip. We allocate them in
74 * a single clump that maps to a single DMA segment to make several things
77 struct gem_control_data {
79 * The transmit descriptors.
81 struct gem_desc gcd_txdescs[GEM_NTXDESC];
84 * The receive descriptors.
86 struct gem_desc gcd_rxdescs[GEM_NRXDESC];
89 #define GEM_CDOFF(x) offsetof(struct gem_control_data, x)
90 #define GEM_CDTXOFF(x) GEM_CDOFF(gcd_txdescs[(x)])
91 #define GEM_CDRXOFF(x) GEM_CDOFF(gcd_rxdescs[(x)])
94 * Software state for transmit job mbufs (may be elements of mbuf chains).
97 struct mbuf *txs_mbuf; /* head of our mbuf chain */
98 bus_dmamap_t txs_dmamap; /* our DMA map */
99 int txs_firstdesc; /* first descriptor in packet */
100 int txs_lastdesc; /* last descriptor in packet */
101 int txs_ndescs; /* number of descriptors */
102 STAILQ_ENTRY(gem_txsoft) txs_q;
105 STAILQ_HEAD(gem_txsq, gem_txsoft);
107 /* Argument structure for busdma callback */
109 struct gem_softc *txd_sc;
110 struct gem_txsoft *txd_txs;
114 * Software state for receive jobs.
117 struct mbuf *rxs_mbuf; /* head of our mbuf chain */
118 bus_dmamap_t rxs_dmamap; /* our DMA map */
119 bus_addr_t rxs_paddr; /* physical address of the segment */
123 * Software state per device.
126 struct ifnet *sc_ifp;
128 struct mii_data *sc_mii; /* MII media control */
129 device_t sc_dev; /* generic device information */
131 struct callout sc_tick_ch; /* tick callout */
132 struct callout sc_rx_ch; /* delayed rx callout */
134 /* The following bus handles are to be provided by the bus front-end */
135 bus_space_tag_t sc_bustag; /* bus tag */
136 bus_dma_tag_t sc_pdmatag; /* parent bus dma tag */
137 bus_dma_tag_t sc_rdmatag; /* RX bus dma tag */
138 bus_dma_tag_t sc_tdmatag; /* TX bus dma tag */
139 bus_dma_tag_t sc_cdmatag; /* control data bus dma tag */
140 bus_dmamap_t sc_dmamap; /* bus dma handle */
141 bus_space_handle_t sc_h; /* bus space handle for all regs */
143 int sc_phys[2]; /* MII instance -> PHY map */
145 int sc_mif_config; /* Selected MII reg setting */
147 int sc_pci; /* XXXXX -- PCI buses are LE. */
148 u_int sc_variant; /* which GEM are we dealing with? */
149 #define GEM_UNKNOWN 0 /* don't know */
150 #define GEM_SUN_GEM 1 /* Sun GEM variant */
151 #define GEM_APPLE_GMAC 2 /* Apple GMAC variant */
153 u_int sc_flags; /* */
154 #define GEM_GIGABIT 0x0001 /* has a gigabit PHY */
157 * Ring buffer DMA stuff.
159 bus_dma_segment_t sc_cdseg; /* control data memory */
160 int sc_cdnseg; /* number of segments */
161 bus_dmamap_t sc_cddmamap; /* control data DMA map */
165 * Software state for transmit and receive descriptors.
167 struct gem_txsoft sc_txsoft[GEM_TXQUEUELEN];
168 struct gem_rxsoft sc_rxsoft[GEM_NRXDESC];
171 * Control data structures.
173 struct gem_control_data *sc_control_data;
174 #define sc_txdescs sc_control_data->gcd_txdescs
175 #define sc_rxdescs sc_control_data->gcd_rxdescs
177 int sc_txfree; /* number of free Tx descriptors */
178 int sc_txnext; /* next ready Tx descriptor */
179 int sc_txwin; /* Tx descriptors since last Tx int */
181 struct gem_txsq sc_txfreeq; /* free Tx descsofts */
182 struct gem_txsq sc_txdirtyq; /* dirty Tx descsofts */
184 int sc_rxptr; /* next ready RX descriptor/descsoft */
185 int sc_rxfifosize; /* Rx FIFO size (bytes) */
195 #define GEM_DMA_READ(sc, v) (((sc)->sc_pci) ? le64toh(v) : be64toh(v))
196 #define GEM_DMA_WRITE(sc, v) (((sc)->sc_pci) ? htole64(v) : htobe64(v))
198 #define GEM_CDTXADDR(sc, x) ((sc)->sc_cddma + GEM_CDTXOFF((x)))
199 #define GEM_CDRXADDR(sc, x) ((sc)->sc_cddma + GEM_CDRXOFF((x)))
201 #define GEM_CDSYNC(sc, ops) \
202 bus_dmamap_sync((sc)->sc_cdmatag, (sc)->sc_cddmamap, (ops)); \
204 #define GEM_INIT_RXDESC(sc, x) \
206 struct gem_rxsoft *__rxs = &sc->sc_rxsoft[(x)]; \
207 struct gem_desc *__rxd = &sc->sc_rxdescs[(x)]; \
208 struct mbuf *__m = __rxs->rxs_mbuf; \
210 __m->m_data = __m->m_ext.ext_buf; \
212 GEM_DMA_WRITE((sc), __rxs->rxs_paddr); \
214 GEM_DMA_WRITE((sc), \
215 (((__m->m_ext.ext_size)<<GEM_RD_BUFSHIFT) \
216 & GEM_RD_BUFSIZE) | GEM_RD_OWN); \
219 #define GEM_LOCK_INIT(_sc, _name) \
220 mtx_init(&(_sc)->sc_mtx, _name, MTX_NETWORK_LOCK, MTX_DEF)
221 #define GEM_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
222 #define GEM_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
223 #define GEM_LOCK_ASSERT(_sc, _what) mtx_assert(&(_sc)->sc_mtx, (_what))
224 #define GEM_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx)
227 extern devclass_t gem_devclass;
229 int gem_attach(struct gem_softc *);
230 void gem_detach(struct gem_softc *);
231 void gem_suspend(struct gem_softc *);
232 void gem_resume(struct gem_softc *);
233 void gem_intr(void *);
235 int gem_mediachange(struct ifnet *);
236 void gem_mediastatus(struct ifnet *, struct ifmediareq *);
238 void gem_reset(struct gem_softc *);
240 /* MII methods & callbacks */
241 int gem_mii_readreg(device_t, int, int);
242 int gem_mii_writereg(device_t, int, int, int);
243 void gem_mii_statchg(device_t);