2 * Copyright (C) 2001 Eduardo Horvath.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * from: NetBSD: gemvar.h,v 1.8 2002/05/15 02:36:12 matt Exp
35 #include <sys/queue.h>
36 #include <sys/callout.h>
39 * Misc. definitions for the Sun ``Gem'' Ethernet controller family driver.
43 * Transmit descriptor list size. This is arbitrary, but allocate
44 * enough descriptors for 64 pending transmissions and 16 segments
45 * per packet. This limit is not actually enforced (packets with more segments
46 * can be sent, depending on the busdma backend); it is however used as an
47 * estimate for the tx window size.
49 #define GEM_NTXSEGS 16
51 #define GEM_TXQUEUELEN 64
52 #define GEM_NTXDESC (GEM_TXQUEUELEN * GEM_NTXSEGS)
53 #define GEM_MAXTXFREE (GEM_NTXDESC - 1)
54 #define GEM_NTXDESC_MASK (GEM_NTXDESC - 1)
55 #define GEM_NEXTTX(x) ((x + 1) & GEM_NTXDESC_MASK)
58 * Receive descriptor list size. We have one Rx buffer per incoming
59 * packet, so this logic is a little simpler.
61 #define GEM_NRXDESC 256
62 #define GEM_NRXDESC_MASK (GEM_NRXDESC - 1)
63 #define GEM_NEXTRX(x) ((x + 1) & GEM_NRXDESC_MASK)
66 * How many ticks to wait until to retry on a RX descriptor that is still owned
69 #define GEM_RXOWN_TICKS (hz / 50)
72 * Control structures are DMA'd to the GEM chip. We allocate them in
73 * a single clump that maps to a single DMA segment to make several things
76 struct gem_control_data {
78 * The transmit descriptors.
80 struct gem_desc gcd_txdescs[GEM_NTXDESC];
83 * The receive descriptors.
85 struct gem_desc gcd_rxdescs[GEM_NRXDESC];
88 #define GEM_CDOFF(x) offsetof(struct gem_control_data, x)
89 #define GEM_CDTXOFF(x) GEM_CDOFF(gcd_txdescs[(x)])
90 #define GEM_CDRXOFF(x) GEM_CDOFF(gcd_rxdescs[(x)])
93 * Software state for transmit job mbufs (may be elements of mbuf chains).
96 struct mbuf *txs_mbuf; /* head of our mbuf chain */
97 bus_dmamap_t txs_dmamap; /* our DMA map */
98 int txs_firstdesc; /* first descriptor in packet */
99 int txs_lastdesc; /* last descriptor in packet */
100 int txs_ndescs; /* number of descriptors */
101 STAILQ_ENTRY(gem_txsoft) txs_q;
104 STAILQ_HEAD(gem_txsq, gem_txsoft);
107 * Software state for receive jobs.
110 struct mbuf *rxs_mbuf; /* head of our mbuf chain */
111 bus_dmamap_t rxs_dmamap; /* our DMA map */
112 bus_addr_t rxs_paddr; /* physical address of the segment */
116 * Software state per device.
119 struct ifnet *sc_ifp;
122 struct mii_data *sc_mii; /* MII media control */
123 device_t sc_dev; /* generic device information */
124 u_char sc_enaddr[ETHER_ADDR_LEN];
125 struct callout sc_tick_ch; /* tick callout */
126 struct callout sc_rx_ch; /* delayed rx callout */
127 int sc_wdog_timer; /* watchdog timer */
130 struct resource *sc_res[2];
131 bus_dma_tag_t sc_pdmatag; /* parent bus dma tag */
132 bus_dma_tag_t sc_rdmatag; /* RX bus dma tag */
133 bus_dma_tag_t sc_tdmatag; /* TX bus dma tag */
134 bus_dma_tag_t sc_cdmatag; /* control data bus dma tag */
135 bus_dmamap_t sc_dmamap; /* bus dma handle */
137 int sc_phyad; /* addr. of PHY to use or -1 for any */
139 u_int sc_variant; /* which GEM are we dealing with? */
140 #define GEM_UNKNOWN 0 /* don't know */
141 #define GEM_SUN_GEM 1 /* Sun GEM */
142 #define GEM_SUN_ERI 2 /* Sun ERI */
143 #define GEM_APPLE_GMAC 3 /* Apple GMAC */
144 #define GEM_APPLE_K2_GMAC 4 /* Apple K2 GMAC */
146 #define GEM_IS_APPLE(sc) \
147 ((sc)->sc_variant == GEM_APPLE_GMAC || \
148 (sc)->sc_variant == GEM_APPLE_K2_GMAC)
150 u_int sc_flags; /* */
151 #define GEM_INITED (1 << 0) /* reset persistent regs initialized */
152 #define GEM_LINK (1 << 1) /* link is up */
153 #define GEM_PCI (1 << 2) /* XXX PCI busses are little-endian */
154 #define GEM_SERDES (1 << 3) /* use the SERDES */
157 * Ring buffer DMA stuff.
159 bus_dma_segment_t sc_cdseg; /* control data memory */
160 int sc_cdnseg; /* number of segments */
161 bus_dmamap_t sc_cddmamap; /* control data DMA map */
165 * Software state for transmit and receive descriptors.
167 struct gem_txsoft sc_txsoft[GEM_TXQUEUELEN];
168 struct gem_rxsoft sc_rxsoft[GEM_NRXDESC];
171 * Control data structures.
173 struct gem_control_data *sc_control_data;
174 #define sc_txdescs sc_control_data->gcd_txdescs
175 #define sc_rxdescs sc_control_data->gcd_rxdescs
177 int sc_txfree; /* number of free Tx descriptors */
178 int sc_txnext; /* next ready Tx descriptor */
179 int sc_txwin; /* Tx descriptors since last Tx int */
181 struct gem_txsq sc_txfreeq; /* free Tx descsofts */
182 struct gem_txsq sc_txdirtyq; /* dirty Tx descsofts */
184 int sc_rxptr; /* next ready RX descriptor/descsoft */
185 int sc_rxfifosize; /* Rx FIFO size (bytes) */
189 int sc_csum_features;
192 #define GEM_DMA_READ(sc, v) \
193 ((((sc)->sc_flags & GEM_PCI) != 0) ? le64toh(v) : be64toh(v))
194 #define GEM_DMA_WRITE(sc, v) \
195 ((((sc)->sc_flags & GEM_PCI) != 0) ? htole64(v) : htobe64(v))
197 #define GEM_CDTXADDR(sc, x) ((sc)->sc_cddma + GEM_CDTXOFF((x)))
198 #define GEM_CDRXADDR(sc, x) ((sc)->sc_cddma + GEM_CDRXOFF((x)))
200 #define GEM_CDSYNC(sc, ops) \
201 bus_dmamap_sync((sc)->sc_cdmatag, (sc)->sc_cddmamap, (ops));
203 #define GEM_INIT_RXDESC(sc, x) \
205 struct gem_rxsoft *__rxs = &sc->sc_rxsoft[(x)]; \
206 struct gem_desc *__rxd = &sc->sc_rxdescs[(x)]; \
207 struct mbuf *__m = __rxs->rxs_mbuf; \
209 __m->m_data = __m->m_ext.ext_buf; \
211 GEM_DMA_WRITE((sc), __rxs->rxs_paddr); \
213 GEM_DMA_WRITE((sc), \
214 (((__m->m_ext.ext_size) << GEM_RD_BUFSHIFT) \
215 & GEM_RD_BUFSIZE) | GEM_RD_OWN); \
218 #define GEM_UPDATE_RXDESC(sc, x) \
220 struct gem_rxsoft *__rxs = &sc->sc_rxsoft[(x)]; \
221 struct gem_desc *__rxd = &sc->sc_rxdescs[(x)]; \
222 struct mbuf *__m = __rxs->rxs_mbuf; \
225 GEM_DMA_WRITE((sc), \
226 (((__m->m_ext.ext_size) << GEM_RD_BUFSHIFT) \
227 & GEM_RD_BUFSIZE) | GEM_RD_OWN); \
230 #define GEM_LOCK_INIT(_sc, _name) \
231 mtx_init(&(_sc)->sc_mtx, _name, MTX_NETWORK_LOCK, MTX_DEF)
232 #define GEM_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
233 #define GEM_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
234 #define GEM_LOCK_ASSERT(_sc, _what) mtx_assert(&(_sc)->sc_mtx, (_what))
235 #define GEM_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx)
238 extern devclass_t gem_devclass;
240 int gem_attach(struct gem_softc *);
241 void gem_detach(struct gem_softc *);
242 void gem_suspend(struct gem_softc *);
243 void gem_resume(struct gem_softc *);
244 void gem_intr(void *);
246 int gem_mediachange(struct ifnet *);
247 void gem_mediastatus(struct ifnet *, struct ifmediareq *);
249 /* MII methods & callbacks */
250 int gem_mii_readreg(device_t, int, int);
251 int gem_mii_writereg(device_t, int, int, int);
252 void gem_mii_statchg(device_t);