2 * Copyright (c) 2011 Henrik Brix Andersen <brix@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
20 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
21 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 #include <sys/cdefs.h>
27 __FBSDID("$FreeBSD$");
29 * AMD Geode LX CS5536 System Management Bus controller.
31 * Although AMD refers to this device as an SMBus controller, it
32 * really is an I2C controller (It lacks SMBus ALERT# and Alert
35 * The driver is implemented as an interrupt-driven state machine,
36 * supporting both master and slave mode.
38 #include <sys/param.h>
39 #include <sys/systm.h>
41 #include <sys/kernel.h>
42 #include <sys/module.h>
44 #include <sys/mutex.h>
45 #include <sys/sysctl.h>
47 #include <sys/syslog.h>
50 #include <dev/pci/pcireg.h>
51 #include <dev/pci/pcivar.h>
53 #include <machine/bus.h>
55 #include <machine/resource.h>
57 #include <dev/iicbus/iiconf.h>
58 #include <dev/iicbus/iicbus.h>
60 #include "iicbus_if.h"
62 /* CS5536 PCI-ISA ID. */
63 #define GLXIIC_CS5536_DEV_ID 0x20901022
66 #define GLXIIC_MSR_PIC_YSEL_HIGH 0x51400021
69 #define GLXIIC_SLOW 0x0258 /* 10 kHz. */
70 #define GLXIIC_FAST 0x0078 /* 50 kHz. */
71 #define GLXIIC_FASTEST 0x003c /* 100 kHz. */
73 /* Default bus activity timeout in milliseconds. */
74 #define GLXIIC_DEFAULT_TIMEOUT 35
76 /* GPIO register offsets. */
77 #define GLXIIC_GPIOL_OUT_AUX1_SEL 0x10
78 #define GLXIIC_GPIOL_IN_AUX1_SEL 0x34
80 /* GPIO 14 (SMB_CLK) and 15 (SMB_DATA) bitmasks. */
81 #define GLXIIC_GPIO_14_15_ENABLE 0x0000c000
82 #define GLXIIC_GPIO_14_15_DISABLE 0xc0000000
84 /* SMB register offsets. */
85 #define GLXIIC_SMB_SDA 0x00
86 #define GLXIIC_SMB_STS 0x01
87 #define GLXIIC_SMB_STS_SLVSTP_BIT (1 << 7)
88 #define GLXIIC_SMB_STS_SDAST_BIT (1 << 6)
89 #define GLXIIC_SMB_STS_BER_BIT (1 << 5)
90 #define GLXIIC_SMB_STS_NEGACK_BIT (1 << 4)
91 #define GLXIIC_SMB_STS_STASTR_BIT (1 << 3)
92 #define GLXIIC_SMB_STS_NMATCH_BIT (1 << 2)
93 #define GLXIIC_SMB_STS_MASTER_BIT (1 << 1)
94 #define GLXIIC_SMB_STS_XMIT_BIT (1 << 0)
95 #define GLXIIC_SMB_CTRL_STS 0x02
96 #define GLXIIC_SMB_CTRL_STS_TGSCL_BIT (1 << 5)
97 #define GLXIIC_SMB_CTRL_STS_TSDA_BIT (1 << 4)
98 #define GLXIIC_SMB_CTRL_STS_GCMTCH_BIT (1 << 3)
99 #define GLXIIC_SMB_CTRL_STS_MATCH_BIT (1 << 2)
100 #define GLXIIC_SMB_CTRL_STS_BB_BIT (1 << 1)
101 #define GLXIIC_SMB_CTRL_STS_BUSY_BIT (1 << 0)
102 #define GLXIIC_SMB_CTRL1 0x03
103 #define GLXIIC_SMB_CTRL1_STASTRE_BIT (1 << 7)
104 #define GLXIIC_SMB_CTRL1_NMINTE_BIT (1 << 6)
105 #define GLXIIC_SMB_CTRL1_GCMEN_BIT (1 << 5)
106 #define GLXIIC_SMB_CTRL1_ACK_BIT (1 << 4)
107 #define GLXIIC_SMB_CTRL1_INTEN_BIT (1 << 2)
108 #define GLXIIC_SMB_CTRL1_STOP_BIT (1 << 1)
109 #define GLXIIC_SMB_CTRL1_START_BIT (1 << 0)
110 #define GLXIIC_SMB_ADDR 0x04
111 #define GLXIIC_SMB_ADDR_SAEN_BIT (1 << 7)
112 #define GLXIIC_SMB_CTRL2 0x05
113 #define GLXIIC_SMB_CTRL2_EN_BIT (1 << 0)
114 #define GLXIIC_SMB_CTRL3 0x06
118 GLXIIC_STATE_SLAVE_TX,
119 GLXIIC_STATE_SLAVE_RX,
120 GLXIIC_STATE_MASTER_ADDR,
121 GLXIIC_STATE_MASTER_TX,
122 GLXIIC_STATE_MASTER_RX,
123 GLXIIC_STATE_MASTER_STOP,
127 struct glxiic_softc {
128 device_t dev; /* Myself. */
129 device_t iicbus; /* IIC bus. */
130 struct mtx mtx; /* Lock. */
131 glxiic_state_t state; /* Driver state. */
132 struct callout callout; /* Driver state timeout callout. */
133 int timeout; /* Driver state timeout (ms). */
135 int smb_rid; /* SMB controller resource ID. */
136 struct resource *smb_res; /* SMB controller resource. */
137 int gpio_rid; /* GPIO resource ID. */
138 struct resource *gpio_res; /* GPIO resource. */
140 int irq_rid; /* IRQ resource ID. */
141 struct resource *irq_res; /* IRQ resource. */
142 void *irq_handler; /* IRQ handler cookie. */
143 int old_irq; /* IRQ mapped by board firmware. */
145 struct iic_msg *msg; /* Current master mode message. */
146 uint32_t nmsgs; /* Number of messages remaining. */
147 uint8_t *data; /* Current master mode data byte. */
148 uint16_t ndata; /* Number of data bytes remaining. */
149 int error; /* Last master mode error. */
151 uint8_t addr; /* Own address. */
152 uint16_t sclfrq; /* Bus frequency. */
156 #define GLXIIC_DEBUG_LOG(fmt, args...) \
157 log(LOG_DEBUG, "%s: " fmt "\n" , __func__ , ## args)
159 #define GLXIIC_DEBUG_LOG(fmt, args...)
162 #define GLXIIC_SCLFRQ(n) ((n << 1))
163 #define GLXIIC_SMBADDR(n) ((n >> 1))
164 #define GLXIIC_SMB_IRQ_TO_MAP(n) ((n << 16))
165 #define GLXIIC_MAP_TO_SMB_IRQ(n) ((n >> 16) & 0xf)
167 #define GLXIIC_LOCK(_sc) mtx_lock(&_sc->mtx)
168 #define GLXIIC_UNLOCK(_sc) mtx_unlock(&_sc->mtx)
169 #define GLXIIC_LOCK_INIT(_sc) \
170 mtx_init(&_sc->mtx, device_get_nameunit(_sc->dev), "glxiic", MTX_DEF)
171 #define GLXIIC_SLEEP(_sc) \
172 mtx_sleep(_sc, &_sc->mtx, IICPRI, "glxiic", 0)
173 #define GLXIIC_WAKEUP(_sc) wakeup(_sc);
174 #define GLXIIC_LOCK_DESTROY(_sc) mtx_destroy(&_sc->mtx);
175 #define GLXIIC_ASSERT_LOCKED(_sc) mtx_assert(&_sc->mtx, MA_OWNED);
177 typedef int (glxiic_state_callback_t)(struct glxiic_softc *sc,
180 static glxiic_state_callback_t glxiic_state_idle_callback;
181 static glxiic_state_callback_t glxiic_state_slave_tx_callback;
182 static glxiic_state_callback_t glxiic_state_slave_rx_callback;
183 static glxiic_state_callback_t glxiic_state_master_addr_callback;
184 static glxiic_state_callback_t glxiic_state_master_tx_callback;
185 static glxiic_state_callback_t glxiic_state_master_rx_callback;
186 static glxiic_state_callback_t glxiic_state_master_stop_callback;
188 struct glxiic_state_table_entry {
189 glxiic_state_callback_t *callback;
192 typedef struct glxiic_state_table_entry glxiic_state_table_entry_t;
194 static glxiic_state_table_entry_t glxiic_state_table[GLXIIC_STATE_MAX] = {
195 [GLXIIC_STATE_IDLE] = {
196 .callback = &glxiic_state_idle_callback,
200 [GLXIIC_STATE_SLAVE_TX] = {
201 .callback = &glxiic_state_slave_tx_callback,
205 [GLXIIC_STATE_SLAVE_RX] = {
206 .callback = &glxiic_state_slave_rx_callback,
210 [GLXIIC_STATE_MASTER_ADDR] = {
211 .callback = &glxiic_state_master_addr_callback,
215 [GLXIIC_STATE_MASTER_TX] = {
216 .callback = &glxiic_state_master_tx_callback,
220 [GLXIIC_STATE_MASTER_RX] = {
221 .callback = &glxiic_state_master_rx_callback,
225 [GLXIIC_STATE_MASTER_STOP] = {
226 .callback = &glxiic_state_master_stop_callback,
231 static void glxiic_identify(driver_t *driver, device_t parent);
232 static int glxiic_probe(device_t dev);
233 static int glxiic_attach(device_t dev);
234 static int glxiic_detach(device_t dev);
236 static uint8_t glxiic_read_status_locked(struct glxiic_softc *sc);
237 static void glxiic_stop_locked(struct glxiic_softc *sc);
238 static void glxiic_timeout(void *arg);
239 static void glxiic_start_timeout_locked(struct glxiic_softc *sc);
240 static void glxiic_set_state_locked(struct glxiic_softc *sc,
241 glxiic_state_t state);
242 static int glxiic_handle_slave_match_locked(struct glxiic_softc *sc,
244 static void glxiic_intr(void *arg);
246 static int glxiic_reset(device_t dev, u_char speed, u_char addr,
248 static int glxiic_transfer(device_t dev, struct iic_msg *msgs,
251 static void glxiic_smb_map_interrupt(int irq);
252 static void glxiic_gpio_enable(struct glxiic_softc *sc);
253 static void glxiic_gpio_disable(struct glxiic_softc *sc);
254 static void glxiic_smb_enable(struct glxiic_softc *sc, uint8_t speed,
256 static void glxiic_smb_disable(struct glxiic_softc *sc);
258 static device_method_t glxiic_methods[] = {
259 DEVMETHOD(device_identify, glxiic_identify),
260 DEVMETHOD(device_probe, glxiic_probe),
261 DEVMETHOD(device_attach, glxiic_attach),
262 DEVMETHOD(device_detach, glxiic_detach),
264 DEVMETHOD(iicbus_reset, glxiic_reset),
265 DEVMETHOD(iicbus_transfer, glxiic_transfer),
266 DEVMETHOD(iicbus_callback, iicbus_null_callback),
271 static driver_t glxiic_driver = {
274 sizeof(struct glxiic_softc),
277 static devclass_t glxiic_devclass;
279 DRIVER_MODULE(glxiic, isab, glxiic_driver, glxiic_devclass, 0, 0);
280 DRIVER_MODULE(iicbus, glxiic, iicbus_driver, iicbus_devclass, 0, 0);
281 MODULE_DEPEND(glxiic, iicbus, 1, 1, 1);
284 glxiic_identify(driver_t *driver, device_t parent)
287 /* Prevent child from being added more than once. */
288 if (device_find_child(parent, driver->name, -1) != NULL)
291 if (pci_get_devid(parent) == GLXIIC_CS5536_DEV_ID) {
292 if (device_add_child(parent, driver->name, -1) == NULL)
293 device_printf(parent, "Could not add glxiic child\n");
298 glxiic_probe(device_t dev)
301 if (resource_disabled("glxiic", device_get_unit(dev)))
304 device_set_desc(dev, "AMD Geode CS5536 SMBus controller");
306 return (BUS_PROBE_DEFAULT);
310 glxiic_attach(device_t dev)
312 struct glxiic_softc *sc;
313 struct sysctl_ctx_list *ctx;
314 struct sysctl_oid *tree;
315 int error, irq, unit;
318 sc = device_get_softc(dev);
320 sc->state = GLXIIC_STATE_IDLE;
323 GLXIIC_LOCK_INIT(sc);
324 callout_init_mtx(&sc->callout, &sc->mtx, 0);
326 sc->smb_rid = PCIR_BAR(0);
327 sc->smb_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &sc->smb_rid,
329 if (sc->smb_res == NULL) {
330 device_printf(dev, "Could not allocate SMBus I/O port\n");
335 sc->gpio_rid = PCIR_BAR(1);
336 sc->gpio_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT,
337 &sc->gpio_rid, RF_SHAREABLE | RF_ACTIVE);
338 if (sc->gpio_res == NULL) {
339 device_printf(dev, "Could not allocate GPIO I/O port\n");
344 /* Ensure the controller is not enabled by firmware. */
345 glxiic_smb_disable(sc);
347 /* Read the existing IRQ map. */
348 irq_map = rdmsr(GLXIIC_MSR_PIC_YSEL_HIGH);
349 sc->old_irq = GLXIIC_MAP_TO_SMB_IRQ(irq_map);
351 unit = device_get_unit(dev);
352 if (resource_int_value("glxiic", unit, "irq", &irq) == 0) {
353 if (irq < 1 || irq > 15) {
354 device_printf(dev, "Bad value %d for glxiic.%d.irq\n",
361 device_printf(dev, "Using irq %d set by hint\n", irq);
362 } else if (sc->old_irq != 0) {
364 device_printf(dev, "Using irq %d set by firmware\n",
368 device_printf(dev, "No irq mapped by firmware");
369 printf(" and no glxiic.%d.irq hint provided\n", unit);
374 /* Map the SMBus interrupt to the requested legacy IRQ. */
375 glxiic_smb_map_interrupt(irq);
378 sc->irq_res = bus_alloc_resource(dev, SYS_RES_IRQ, &sc->irq_rid,
379 irq, irq, 1, RF_SHAREABLE | RF_ACTIVE);
380 if (sc->irq_res == NULL) {
381 device_printf(dev, "Could not allocate IRQ %d\n", irq);
386 error = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
387 NULL, glxiic_intr, sc, &(sc->irq_handler));
389 device_printf(dev, "Could not setup IRQ handler\n");
394 if ((sc->iicbus = device_add_child(dev, "iicbus", -1)) == NULL) {
395 device_printf(dev, "Could not allocate iicbus instance\n");
400 ctx = device_get_sysctl_ctx(dev);
401 tree = device_get_sysctl_tree(dev);
403 sc->timeout = GLXIIC_DEFAULT_TIMEOUT;
404 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
405 "timeout", CTLFLAG_RWTUN, &sc->timeout, 0,
406 "activity timeout in ms");
408 glxiic_gpio_enable(sc);
409 glxiic_smb_enable(sc, IIC_FASTEST, 0);
411 error = bus_generic_attach(dev);
413 device_printf(dev, "Could not probe and attach children\n");
418 callout_drain(&sc->callout);
420 if (sc->iicbus != NULL)
421 device_delete_child(dev, sc->iicbus);
422 if (sc->smb_res != NULL) {
423 glxiic_smb_disable(sc);
424 bus_release_resource(dev, SYS_RES_IOPORT, sc->smb_rid,
427 if (sc->gpio_res != NULL) {
428 glxiic_gpio_disable(sc);
429 bus_release_resource(dev, SYS_RES_IOPORT, sc->gpio_rid,
432 if (sc->irq_handler != NULL)
433 bus_teardown_intr(dev, sc->irq_res, sc->irq_handler);
434 if (sc->irq_res != NULL)
435 bus_release_resource(dev, SYS_RES_IRQ, sc->irq_rid,
438 /* Restore the old SMBus interrupt mapping. */
439 glxiic_smb_map_interrupt(sc->old_irq);
441 GLXIIC_LOCK_DESTROY(sc);
448 glxiic_detach(device_t dev)
450 struct glxiic_softc *sc;
453 sc = device_get_softc(dev);
455 error = bus_generic_detach(dev);
458 if (sc->iicbus != NULL)
459 error = device_delete_child(dev, sc->iicbus);
462 callout_drain(&sc->callout);
464 if (sc->smb_res != NULL) {
465 glxiic_smb_disable(sc);
466 bus_release_resource(dev, SYS_RES_IOPORT, sc->smb_rid,
469 if (sc->gpio_res != NULL) {
470 glxiic_gpio_disable(sc);
471 bus_release_resource(dev, SYS_RES_IOPORT, sc->gpio_rid,
474 if (sc->irq_handler != NULL)
475 bus_teardown_intr(dev, sc->irq_res, sc->irq_handler);
476 if (sc->irq_res != NULL)
477 bus_release_resource(dev, SYS_RES_IRQ, sc->irq_rid,
480 /* Restore the old SMBus interrupt mapping. */
481 glxiic_smb_map_interrupt(sc->old_irq);
483 GLXIIC_LOCK_DESTROY(sc);
489 glxiic_read_status_locked(struct glxiic_softc *sc)
493 GLXIIC_ASSERT_LOCKED(sc);
495 status = bus_read_1(sc->smb_res, GLXIIC_SMB_STS);
497 /* Clear all status flags except SDAST and STASTR after reading. */
498 bus_write_1(sc->smb_res, GLXIIC_SMB_STS, (GLXIIC_SMB_STS_SLVSTP_BIT |
499 GLXIIC_SMB_STS_BER_BIT | GLXIIC_SMB_STS_NEGACK_BIT |
500 GLXIIC_SMB_STS_NMATCH_BIT));
506 glxiic_stop_locked(struct glxiic_softc *sc)
508 uint8_t status, ctrl1;
510 GLXIIC_ASSERT_LOCKED(sc);
512 status = glxiic_read_status_locked(sc);
514 ctrl1 = bus_read_1(sc->smb_res, GLXIIC_SMB_CTRL1);
515 bus_write_1(sc->smb_res, GLXIIC_SMB_CTRL1,
516 ctrl1 | GLXIIC_SMB_CTRL1_STOP_BIT);
519 * Perform a dummy read of SDA in master receive mode to clear
522 if ((status & GLXIIC_SMB_STS_XMIT_BIT) == 0 &&
523 (status & GLXIIC_SMB_STS_SDAST_BIT) != 0)
524 bus_read_1(sc->smb_res, GLXIIC_SMB_SDA);
526 /* Check stall after start bit and clear if needed */
527 if ((status & GLXIIC_SMB_STS_STASTR_BIT) != 0) {
528 bus_write_1(sc->smb_res, GLXIIC_SMB_STS,
529 GLXIIC_SMB_STS_STASTR_BIT);
534 glxiic_timeout(void *arg)
536 struct glxiic_softc *sc;
539 sc = (struct glxiic_softc *)arg;
541 GLXIIC_DEBUG_LOG("timeout in state %d", sc->state);
543 if (glxiic_state_table[sc->state].master) {
544 sc->error = IIC_ETIMEOUT;
547 error = IIC_ETIMEOUT;
548 iicbus_intr(sc->iicbus, INTR_ERROR, &error);
551 glxiic_smb_disable(sc);
552 glxiic_smb_enable(sc, IIC_UNKNOWN, sc->addr);
553 glxiic_set_state_locked(sc, GLXIIC_STATE_IDLE);
557 glxiic_start_timeout_locked(struct glxiic_softc *sc)
560 GLXIIC_ASSERT_LOCKED(sc);
562 callout_reset_sbt(&sc->callout, SBT_1MS * sc->timeout, 0,
563 glxiic_timeout, sc, 0);
567 glxiic_set_state_locked(struct glxiic_softc *sc, glxiic_state_t state)
570 GLXIIC_ASSERT_LOCKED(sc);
572 if (state == GLXIIC_STATE_IDLE)
573 callout_stop(&sc->callout);
574 else if (sc->timeout > 0)
575 glxiic_start_timeout_locked(sc);
581 glxiic_handle_slave_match_locked(struct glxiic_softc *sc, uint8_t status)
583 uint8_t ctrl_sts, addr;
585 GLXIIC_ASSERT_LOCKED(sc);
587 ctrl_sts = bus_read_1(sc->smb_res, GLXIIC_SMB_CTRL_STS);
589 if ((ctrl_sts & GLXIIC_SMB_CTRL_STS_MATCH_BIT) != 0) {
590 if ((status & GLXIIC_SMB_STS_XMIT_BIT) != 0) {
591 addr = sc->addr | LSB;
592 glxiic_set_state_locked(sc,
593 GLXIIC_STATE_SLAVE_TX);
595 addr = sc->addr & ~LSB;
596 glxiic_set_state_locked(sc,
597 GLXIIC_STATE_SLAVE_RX);
599 iicbus_intr(sc->iicbus, INTR_START, &addr);
600 } else if ((ctrl_sts & GLXIIC_SMB_CTRL_STS_GCMTCH_BIT) != 0) {
602 glxiic_set_state_locked(sc, GLXIIC_STATE_SLAVE_RX);
603 iicbus_intr(sc->iicbus, INTR_GENERAL, &addr);
605 GLXIIC_DEBUG_LOG("unknown slave match");
606 return (IIC_ESTATUS);
613 glxiic_state_idle_callback(struct glxiic_softc *sc, uint8_t status)
616 GLXIIC_ASSERT_LOCKED(sc);
618 if ((status & GLXIIC_SMB_STS_BER_BIT) != 0) {
619 GLXIIC_DEBUG_LOG("bus error in idle");
620 return (IIC_EBUSERR);
623 if ((status & GLXIIC_SMB_STS_NMATCH_BIT) != 0) {
624 return (glxiic_handle_slave_match_locked(sc, status));
631 glxiic_state_slave_tx_callback(struct glxiic_softc *sc, uint8_t status)
635 GLXIIC_ASSERT_LOCKED(sc);
637 if ((status & GLXIIC_SMB_STS_BER_BIT) != 0) {
638 GLXIIC_DEBUG_LOG("bus error in slave tx");
639 return (IIC_EBUSERR);
642 if ((status & GLXIIC_SMB_STS_SLVSTP_BIT) != 0) {
643 iicbus_intr(sc->iicbus, INTR_STOP, NULL);
644 glxiic_set_state_locked(sc, GLXIIC_STATE_IDLE);
648 if ((status & GLXIIC_SMB_STS_NEGACK_BIT) != 0) {
649 iicbus_intr(sc->iicbus, INTR_NOACK, NULL);
653 if ((status & GLXIIC_SMB_STS_NMATCH_BIT) != 0) {
654 /* Handle repeated start in slave mode. */
655 return (glxiic_handle_slave_match_locked(sc, status));
658 if ((status & GLXIIC_SMB_STS_SDAST_BIT) == 0) {
659 GLXIIC_DEBUG_LOG("not awaiting data in slave tx");
660 return (IIC_ESTATUS);
663 iicbus_intr(sc->iicbus, INTR_TRANSMIT, &data);
664 bus_write_1(sc->smb_res, GLXIIC_SMB_SDA, data);
666 glxiic_start_timeout_locked(sc);
672 glxiic_state_slave_rx_callback(struct glxiic_softc *sc, uint8_t status)
676 GLXIIC_ASSERT_LOCKED(sc);
678 if ((status & GLXIIC_SMB_STS_BER_BIT) != 0) {
679 GLXIIC_DEBUG_LOG("bus error in slave rx");
680 return (IIC_EBUSERR);
683 if ((status & GLXIIC_SMB_STS_SLVSTP_BIT) != 0) {
684 iicbus_intr(sc->iicbus, INTR_STOP, NULL);
685 glxiic_set_state_locked(sc, GLXIIC_STATE_IDLE);
689 if ((status & GLXIIC_SMB_STS_NMATCH_BIT) != 0) {
690 /* Handle repeated start in slave mode. */
691 return (glxiic_handle_slave_match_locked(sc, status));
694 if ((status & GLXIIC_SMB_STS_SDAST_BIT) == 0) {
695 GLXIIC_DEBUG_LOG("no pending data in slave rx");
696 return (IIC_ESTATUS);
699 data = bus_read_1(sc->smb_res, GLXIIC_SMB_SDA);
700 iicbus_intr(sc->iicbus, INTR_RECEIVE, &data);
702 glxiic_start_timeout_locked(sc);
708 glxiic_state_master_addr_callback(struct glxiic_softc *sc, uint8_t status)
713 GLXIIC_ASSERT_LOCKED(sc);
715 if ((status & GLXIIC_SMB_STS_BER_BIT) != 0) {
716 GLXIIC_DEBUG_LOG("bus error after master start");
717 return (IIC_EBUSERR);
720 if ((status & GLXIIC_SMB_STS_MASTER_BIT) == 0) {
721 GLXIIC_DEBUG_LOG("not bus master after master start");
722 return (IIC_ESTATUS);
725 if ((status & GLXIIC_SMB_STS_SDAST_BIT) == 0) {
726 GLXIIC_DEBUG_LOG("not awaiting address in master addr");
727 return (IIC_ESTATUS);
730 if ((sc->msg->flags & IIC_M_RD) != 0) {
731 slave = sc->msg->slave | LSB;
732 glxiic_set_state_locked(sc, GLXIIC_STATE_MASTER_RX);
734 slave = sc->msg->slave & ~LSB;
735 glxiic_set_state_locked(sc, GLXIIC_STATE_MASTER_TX);
738 sc->data = sc->msg->buf;
739 sc->ndata = sc->msg->len;
741 /* Handle address-only transfer. */
743 glxiic_set_state_locked(sc, GLXIIC_STATE_MASTER_STOP);
745 bus_write_1(sc->smb_res, GLXIIC_SMB_SDA, slave);
747 if ((sc->msg->flags & IIC_M_RD) != 0 && sc->ndata == 1) {
748 /* Last byte from slave, set NACK. */
749 ctrl1 = bus_read_1(sc->smb_res, GLXIIC_SMB_CTRL1);
750 bus_write_1(sc->smb_res, GLXIIC_SMB_CTRL1,
751 ctrl1 | GLXIIC_SMB_CTRL1_ACK_BIT);
758 glxiic_state_master_tx_callback(struct glxiic_softc *sc, uint8_t status)
761 GLXIIC_ASSERT_LOCKED(sc);
763 if ((status & GLXIIC_SMB_STS_BER_BIT) != 0) {
764 GLXIIC_DEBUG_LOG("bus error in master tx");
765 return (IIC_EBUSERR);
768 if ((status & GLXIIC_SMB_STS_MASTER_BIT) == 0) {
769 GLXIIC_DEBUG_LOG("not bus master in master tx");
770 return (IIC_ESTATUS);
773 if ((status & GLXIIC_SMB_STS_NEGACK_BIT) != 0) {
774 GLXIIC_DEBUG_LOG("slave nack in master tx");
778 if ((status & GLXIIC_SMB_STS_STASTR_BIT) != 0) {
779 bus_write_1(sc->smb_res, GLXIIC_SMB_STS,
780 GLXIIC_SMB_STS_STASTR_BIT);
783 if ((status & GLXIIC_SMB_STS_SDAST_BIT) == 0) {
784 GLXIIC_DEBUG_LOG("not awaiting data in master tx");
785 return (IIC_ESTATUS);
788 bus_write_1(sc->smb_res, GLXIIC_SMB_SDA, *sc->data++);
789 if (--sc->ndata == 0)
790 glxiic_set_state_locked(sc, GLXIIC_STATE_MASTER_STOP);
792 glxiic_start_timeout_locked(sc);
798 glxiic_state_master_rx_callback(struct glxiic_softc *sc, uint8_t status)
802 GLXIIC_ASSERT_LOCKED(sc);
804 if ((status & GLXIIC_SMB_STS_BER_BIT) != 0) {
805 GLXIIC_DEBUG_LOG("bus error in master rx");
806 return (IIC_EBUSERR);
809 if ((status & GLXIIC_SMB_STS_MASTER_BIT) == 0) {
810 GLXIIC_DEBUG_LOG("not bus master in master rx");
811 return (IIC_ESTATUS);
814 if ((status & GLXIIC_SMB_STS_NEGACK_BIT) != 0) {
815 GLXIIC_DEBUG_LOG("slave nack in rx");
819 if ((status & GLXIIC_SMB_STS_STASTR_BIT) != 0) {
820 /* Bus is stalled, clear and wait for data. */
821 bus_write_1(sc->smb_res, GLXIIC_SMB_STS,
822 GLXIIC_SMB_STS_STASTR_BIT);
826 if ((status & GLXIIC_SMB_STS_SDAST_BIT) == 0) {
827 GLXIIC_DEBUG_LOG("no pending data in master rx");
828 return (IIC_ESTATUS);
831 *sc->data++ = bus_read_1(sc->smb_res, GLXIIC_SMB_SDA);
832 if (--sc->ndata == 0) {
833 /* Proceed with stop on reading last byte. */
834 glxiic_set_state_locked(sc, GLXIIC_STATE_MASTER_STOP);
835 return (glxiic_state_table[sc->state].callback(sc, status));
838 if (sc->ndata == 1) {
839 /* Last byte from slave, set NACK. */
840 ctrl1 = bus_read_1(sc->smb_res, GLXIIC_SMB_CTRL1);
841 bus_write_1(sc->smb_res, GLXIIC_SMB_CTRL1,
842 ctrl1 | GLXIIC_SMB_CTRL1_ACK_BIT);
845 glxiic_start_timeout_locked(sc);
851 glxiic_state_master_stop_callback(struct glxiic_softc *sc, uint8_t status)
855 GLXIIC_ASSERT_LOCKED(sc);
857 if ((status & GLXIIC_SMB_STS_BER_BIT) != 0) {
858 GLXIIC_DEBUG_LOG("bus error in master stop");
859 return (IIC_EBUSERR);
862 if ((status & GLXIIC_SMB_STS_MASTER_BIT) == 0) {
863 GLXIIC_DEBUG_LOG("not bus master in master stop");
864 return (IIC_ESTATUS);
867 if ((status & GLXIIC_SMB_STS_NEGACK_BIT) != 0) {
868 GLXIIC_DEBUG_LOG("slave nack in master stop");
872 if (--sc->nmsgs > 0) {
873 /* Start transfer of next message. */
874 if ((sc->msg->flags & IIC_M_NOSTOP) == 0) {
875 glxiic_stop_locked(sc);
878 ctrl1 = bus_read_1(sc->smb_res, GLXIIC_SMB_CTRL1);
879 bus_write_1(sc->smb_res, GLXIIC_SMB_CTRL1,
880 ctrl1 | GLXIIC_SMB_CTRL1_START_BIT);
882 glxiic_set_state_locked(sc, GLXIIC_STATE_MASTER_ADDR);
886 glxiic_stop_locked(sc);
887 glxiic_set_state_locked(sc, GLXIIC_STATE_IDLE);
888 sc->error = IIC_NOERR;
896 glxiic_intr(void *arg)
898 struct glxiic_softc *sc;
900 uint8_t status, data;
902 sc = (struct glxiic_softc *)arg;
906 status = glxiic_read_status_locked(sc);
908 /* Check if this interrupt originated from the SMBus. */
910 ~(GLXIIC_SMB_STS_MASTER_BIT | GLXIIC_SMB_STS_XMIT_BIT)) != 0) {
912 error = glxiic_state_table[sc->state].callback(sc, status);
914 if (error != IIC_NOERR) {
915 if (glxiic_state_table[sc->state].master) {
916 glxiic_stop_locked(sc);
917 glxiic_set_state_locked(sc, GLXIIC_STATE_IDLE);
922 iicbus_intr(sc->iicbus, INTR_ERROR, &data);
923 glxiic_set_state_locked(sc, GLXIIC_STATE_IDLE);
932 glxiic_reset(device_t dev, u_char speed, u_char addr, u_char *oldaddr)
934 struct glxiic_softc *sc;
936 sc = device_get_softc(dev);
944 /* A disable/enable cycle resets the controller. */
945 glxiic_smb_disable(sc);
946 glxiic_smb_enable(sc, speed, addr);
948 if (glxiic_state_table[sc->state].master) {
949 sc->error = IIC_ESTATUS;
952 glxiic_set_state_locked(sc, GLXIIC_STATE_IDLE);
960 glxiic_transfer(device_t dev, struct iic_msg *msgs, uint32_t nmsgs)
962 struct glxiic_softc *sc;
966 sc = device_get_softc(dev);
970 if (sc->state != GLXIIC_STATE_IDLE) {
977 glxiic_set_state_locked(sc, GLXIIC_STATE_MASTER_ADDR);
979 /* Set start bit and let glxiic_intr() handle the transfer. */
980 ctrl1 = bus_read_1(sc->smb_res, GLXIIC_SMB_CTRL1);
981 bus_write_1(sc->smb_res, GLXIIC_SMB_CTRL1,
982 ctrl1 | GLXIIC_SMB_CTRL1_START_BIT);
993 glxiic_smb_map_interrupt(int irq)
998 /* Protect the read-modify-write operation. */
1001 irq_map = rdmsr(GLXIIC_MSR_PIC_YSEL_HIGH);
1002 old_irq = GLXIIC_MAP_TO_SMB_IRQ(irq_map);
1004 if (irq != old_irq) {
1005 irq_map &= ~GLXIIC_SMB_IRQ_TO_MAP(old_irq);
1006 irq_map |= GLXIIC_SMB_IRQ_TO_MAP(irq);
1007 wrmsr(GLXIIC_MSR_PIC_YSEL_HIGH, irq_map);
1014 glxiic_gpio_enable(struct glxiic_softc *sc)
1017 bus_write_4(sc->gpio_res, GLXIIC_GPIOL_IN_AUX1_SEL,
1018 GLXIIC_GPIO_14_15_ENABLE);
1019 bus_write_4(sc->gpio_res, GLXIIC_GPIOL_OUT_AUX1_SEL,
1020 GLXIIC_GPIO_14_15_ENABLE);
1024 glxiic_gpio_disable(struct glxiic_softc *sc)
1027 bus_write_4(sc->gpio_res, GLXIIC_GPIOL_OUT_AUX1_SEL,
1028 GLXIIC_GPIO_14_15_DISABLE);
1029 bus_write_4(sc->gpio_res, GLXIIC_GPIOL_IN_AUX1_SEL,
1030 GLXIIC_GPIO_14_15_DISABLE);
1034 glxiic_smb_enable(struct glxiic_softc *sc, uint8_t speed, uint8_t addr)
1042 sc->sclfrq = GLXIIC_SLOW;
1045 sc->sclfrq = GLXIIC_FAST;
1048 sc->sclfrq = GLXIIC_FASTEST;
1052 /* Reuse last frequency. */
1056 /* Set bus speed and enable controller. */
1057 bus_write_2(sc->smb_res, GLXIIC_SMB_CTRL2,
1058 GLXIIC_SCLFRQ(sc->sclfrq) | GLXIIC_SMB_CTRL2_EN_BIT);
1061 /* Enable new match and global call match interrupts. */
1062 ctrl1 |= GLXIIC_SMB_CTRL1_NMINTE_BIT |
1063 GLXIIC_SMB_CTRL1_GCMEN_BIT;
1064 bus_write_1(sc->smb_res, GLXIIC_SMB_ADDR,
1065 GLXIIC_SMB_ADDR_SAEN_BIT | GLXIIC_SMBADDR(addr));
1067 bus_write_1(sc->smb_res, GLXIIC_SMB_ADDR, 0);
1070 /* Enable stall after start and interrupt. */
1071 bus_write_1(sc->smb_res, GLXIIC_SMB_CTRL1,
1072 ctrl1 | GLXIIC_SMB_CTRL1_STASTRE_BIT | GLXIIC_SMB_CTRL1_INTEN_BIT);
1076 glxiic_smb_disable(struct glxiic_softc *sc)
1080 sclfrq = bus_read_2(sc->smb_res, GLXIIC_SMB_CTRL2);
1081 bus_write_2(sc->smb_res, GLXIIC_SMB_CTRL2,
1082 sclfrq & ~GLXIIC_SMB_CTRL2_EN_BIT);