2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2011 Henrik Brix Andersen <brix@FreeBSD.org>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
31 * AMD Geode LX CS5536 System Management Bus controller.
33 * Although AMD refers to this device as an SMBus controller, it
34 * really is an I2C controller (It lacks SMBus ALERT# and Alert
37 * The driver is implemented as an interrupt-driven state machine,
38 * supporting both master and slave mode.
40 #include <sys/param.h>
41 #include <sys/systm.h>
43 #include <sys/kernel.h>
44 #include <sys/module.h>
46 #include <sys/mutex.h>
47 #include <sys/sysctl.h>
49 #include <sys/syslog.h>
52 #include <dev/pci/pcireg.h>
53 #include <dev/pci/pcivar.h>
55 #include <machine/bus.h>
57 #include <machine/resource.h>
59 #include <dev/iicbus/iiconf.h>
60 #include <dev/iicbus/iicbus.h>
62 #include "iicbus_if.h"
64 /* CS5536 PCI-ISA ID. */
65 #define GLXIIC_CS5536_DEV_ID 0x20901022
68 #define GLXIIC_MSR_PIC_YSEL_HIGH 0x51400021
71 #define GLXIIC_SLOW 0x0258 /* 10 kHz. */
72 #define GLXIIC_FAST 0x0078 /* 50 kHz. */
73 #define GLXIIC_FASTEST 0x003c /* 100 kHz. */
75 /* Default bus activity timeout in milliseconds. */
76 #define GLXIIC_DEFAULT_TIMEOUT 35
78 /* GPIO register offsets. */
79 #define GLXIIC_GPIOL_OUT_AUX1_SEL 0x10
80 #define GLXIIC_GPIOL_IN_AUX1_SEL 0x34
82 /* GPIO 14 (SMB_CLK) and 15 (SMB_DATA) bitmasks. */
83 #define GLXIIC_GPIO_14_15_ENABLE 0x0000c000
84 #define GLXIIC_GPIO_14_15_DISABLE 0xc0000000
86 /* SMB register offsets. */
87 #define GLXIIC_SMB_SDA 0x00
88 #define GLXIIC_SMB_STS 0x01
89 #define GLXIIC_SMB_STS_SLVSTP_BIT (1 << 7)
90 #define GLXIIC_SMB_STS_SDAST_BIT (1 << 6)
91 #define GLXIIC_SMB_STS_BER_BIT (1 << 5)
92 #define GLXIIC_SMB_STS_NEGACK_BIT (1 << 4)
93 #define GLXIIC_SMB_STS_STASTR_BIT (1 << 3)
94 #define GLXIIC_SMB_STS_NMATCH_BIT (1 << 2)
95 #define GLXIIC_SMB_STS_MASTER_BIT (1 << 1)
96 #define GLXIIC_SMB_STS_XMIT_BIT (1 << 0)
97 #define GLXIIC_SMB_CTRL_STS 0x02
98 #define GLXIIC_SMB_CTRL_STS_TGSCL_BIT (1 << 5)
99 #define GLXIIC_SMB_CTRL_STS_TSDA_BIT (1 << 4)
100 #define GLXIIC_SMB_CTRL_STS_GCMTCH_BIT (1 << 3)
101 #define GLXIIC_SMB_CTRL_STS_MATCH_BIT (1 << 2)
102 #define GLXIIC_SMB_CTRL_STS_BB_BIT (1 << 1)
103 #define GLXIIC_SMB_CTRL_STS_BUSY_BIT (1 << 0)
104 #define GLXIIC_SMB_CTRL1 0x03
105 #define GLXIIC_SMB_CTRL1_STASTRE_BIT (1 << 7)
106 #define GLXIIC_SMB_CTRL1_NMINTE_BIT (1 << 6)
107 #define GLXIIC_SMB_CTRL1_GCMEN_BIT (1 << 5)
108 #define GLXIIC_SMB_CTRL1_ACK_BIT (1 << 4)
109 #define GLXIIC_SMB_CTRL1_INTEN_BIT (1 << 2)
110 #define GLXIIC_SMB_CTRL1_STOP_BIT (1 << 1)
111 #define GLXIIC_SMB_CTRL1_START_BIT (1 << 0)
112 #define GLXIIC_SMB_ADDR 0x04
113 #define GLXIIC_SMB_ADDR_SAEN_BIT (1 << 7)
114 #define GLXIIC_SMB_CTRL2 0x05
115 #define GLXIIC_SMB_CTRL2_EN_BIT (1 << 0)
116 #define GLXIIC_SMB_CTRL3 0x06
120 GLXIIC_STATE_SLAVE_TX,
121 GLXIIC_STATE_SLAVE_RX,
122 GLXIIC_STATE_MASTER_ADDR,
123 GLXIIC_STATE_MASTER_TX,
124 GLXIIC_STATE_MASTER_RX,
125 GLXIIC_STATE_MASTER_STOP,
129 struct glxiic_softc {
130 device_t dev; /* Myself. */
131 device_t iicbus; /* IIC bus. */
132 struct mtx mtx; /* Lock. */
133 glxiic_state_t state; /* Driver state. */
134 struct callout callout; /* Driver state timeout callout. */
135 int timeout; /* Driver state timeout (ms). */
137 int smb_rid; /* SMB controller resource ID. */
138 struct resource *smb_res; /* SMB controller resource. */
139 int gpio_rid; /* GPIO resource ID. */
140 struct resource *gpio_res; /* GPIO resource. */
142 int irq_rid; /* IRQ resource ID. */
143 struct resource *irq_res; /* IRQ resource. */
144 void *irq_handler; /* IRQ handler cookie. */
145 int old_irq; /* IRQ mapped by board firmware. */
147 struct iic_msg *msg; /* Current master mode message. */
148 uint32_t nmsgs; /* Number of messages remaining. */
149 uint8_t *data; /* Current master mode data byte. */
150 uint16_t ndata; /* Number of data bytes remaining. */
151 int error; /* Last master mode error. */
153 uint8_t addr; /* Own address. */
154 uint16_t sclfrq; /* Bus frequency. */
158 #define GLXIIC_DEBUG_LOG(fmt, args...) \
159 log(LOG_DEBUG, "%s: " fmt "\n" , __func__ , ## args)
161 #define GLXIIC_DEBUG_LOG(fmt, args...)
164 #define GLXIIC_SCLFRQ(n) ((n << 1))
165 #define GLXIIC_SMBADDR(n) ((n >> 1))
166 #define GLXIIC_SMB_IRQ_TO_MAP(n) ((n << 16))
167 #define GLXIIC_MAP_TO_SMB_IRQ(n) ((n >> 16) & 0xf)
169 #define GLXIIC_LOCK(_sc) mtx_lock(&_sc->mtx)
170 #define GLXIIC_UNLOCK(_sc) mtx_unlock(&_sc->mtx)
171 #define GLXIIC_LOCK_INIT(_sc) \
172 mtx_init(&_sc->mtx, device_get_nameunit(_sc->dev), "glxiic", MTX_DEF)
173 #define GLXIIC_SLEEP(_sc) \
174 mtx_sleep(_sc, &_sc->mtx, IICPRI, "glxiic", 0)
175 #define GLXIIC_WAKEUP(_sc) wakeup(_sc);
176 #define GLXIIC_LOCK_DESTROY(_sc) mtx_destroy(&_sc->mtx);
177 #define GLXIIC_ASSERT_LOCKED(_sc) mtx_assert(&_sc->mtx, MA_OWNED);
179 typedef int (glxiic_state_callback_t)(struct glxiic_softc *sc,
182 static glxiic_state_callback_t glxiic_state_idle_callback;
183 static glxiic_state_callback_t glxiic_state_slave_tx_callback;
184 static glxiic_state_callback_t glxiic_state_slave_rx_callback;
185 static glxiic_state_callback_t glxiic_state_master_addr_callback;
186 static glxiic_state_callback_t glxiic_state_master_tx_callback;
187 static glxiic_state_callback_t glxiic_state_master_rx_callback;
188 static glxiic_state_callback_t glxiic_state_master_stop_callback;
190 struct glxiic_state_table_entry {
191 glxiic_state_callback_t *callback;
194 typedef struct glxiic_state_table_entry glxiic_state_table_entry_t;
196 static glxiic_state_table_entry_t glxiic_state_table[GLXIIC_STATE_MAX] = {
197 [GLXIIC_STATE_IDLE] = {
198 .callback = &glxiic_state_idle_callback,
202 [GLXIIC_STATE_SLAVE_TX] = {
203 .callback = &glxiic_state_slave_tx_callback,
207 [GLXIIC_STATE_SLAVE_RX] = {
208 .callback = &glxiic_state_slave_rx_callback,
212 [GLXIIC_STATE_MASTER_ADDR] = {
213 .callback = &glxiic_state_master_addr_callback,
217 [GLXIIC_STATE_MASTER_TX] = {
218 .callback = &glxiic_state_master_tx_callback,
222 [GLXIIC_STATE_MASTER_RX] = {
223 .callback = &glxiic_state_master_rx_callback,
227 [GLXIIC_STATE_MASTER_STOP] = {
228 .callback = &glxiic_state_master_stop_callback,
233 static void glxiic_identify(driver_t *driver, device_t parent);
234 static int glxiic_probe(device_t dev);
235 static int glxiic_attach(device_t dev);
236 static int glxiic_detach(device_t dev);
238 static uint8_t glxiic_read_status_locked(struct glxiic_softc *sc);
239 static void glxiic_stop_locked(struct glxiic_softc *sc);
240 static void glxiic_timeout(void *arg);
241 static void glxiic_start_timeout_locked(struct glxiic_softc *sc);
242 static void glxiic_set_state_locked(struct glxiic_softc *sc,
243 glxiic_state_t state);
244 static int glxiic_handle_slave_match_locked(struct glxiic_softc *sc,
246 static void glxiic_intr(void *arg);
248 static int glxiic_reset(device_t dev, u_char speed, u_char addr,
250 static int glxiic_transfer(device_t dev, struct iic_msg *msgs,
253 static void glxiic_smb_map_interrupt(int irq);
254 static void glxiic_gpio_enable(struct glxiic_softc *sc);
255 static void glxiic_gpio_disable(struct glxiic_softc *sc);
256 static void glxiic_smb_enable(struct glxiic_softc *sc, uint8_t speed,
258 static void glxiic_smb_disable(struct glxiic_softc *sc);
260 static device_method_t glxiic_methods[] = {
261 DEVMETHOD(device_identify, glxiic_identify),
262 DEVMETHOD(device_probe, glxiic_probe),
263 DEVMETHOD(device_attach, glxiic_attach),
264 DEVMETHOD(device_detach, glxiic_detach),
266 DEVMETHOD(iicbus_reset, glxiic_reset),
267 DEVMETHOD(iicbus_transfer, glxiic_transfer),
268 DEVMETHOD(iicbus_callback, iicbus_null_callback),
273 static driver_t glxiic_driver = {
276 sizeof(struct glxiic_softc),
279 static devclass_t glxiic_devclass;
281 DRIVER_MODULE(glxiic, isab, glxiic_driver, glxiic_devclass, 0, 0);
282 DRIVER_MODULE(iicbus, glxiic, iicbus_driver, iicbus_devclass, 0, 0);
283 MODULE_DEPEND(glxiic, iicbus, 1, 1, 1);
286 glxiic_identify(driver_t *driver, device_t parent)
289 /* Prevent child from being added more than once. */
290 if (device_find_child(parent, driver->name, -1) != NULL)
293 if (pci_get_devid(parent) == GLXIIC_CS5536_DEV_ID) {
294 if (device_add_child(parent, driver->name, -1) == NULL)
295 device_printf(parent, "Could not add glxiic child\n");
300 glxiic_probe(device_t dev)
303 if (resource_disabled("glxiic", device_get_unit(dev)))
306 device_set_desc(dev, "AMD Geode CS5536 SMBus controller");
308 return (BUS_PROBE_DEFAULT);
312 glxiic_attach(device_t dev)
314 struct glxiic_softc *sc;
315 struct sysctl_ctx_list *ctx;
316 struct sysctl_oid *tree;
317 int error, irq, unit;
320 sc = device_get_softc(dev);
322 sc->state = GLXIIC_STATE_IDLE;
325 GLXIIC_LOCK_INIT(sc);
326 callout_init_mtx(&sc->callout, &sc->mtx, 0);
328 sc->smb_rid = PCIR_BAR(0);
329 sc->smb_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &sc->smb_rid,
331 if (sc->smb_res == NULL) {
332 device_printf(dev, "Could not allocate SMBus I/O port\n");
337 sc->gpio_rid = PCIR_BAR(1);
338 sc->gpio_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT,
339 &sc->gpio_rid, RF_SHAREABLE | RF_ACTIVE);
340 if (sc->gpio_res == NULL) {
341 device_printf(dev, "Could not allocate GPIO I/O port\n");
346 /* Ensure the controller is not enabled by firmware. */
347 glxiic_smb_disable(sc);
349 /* Read the existing IRQ map. */
350 irq_map = rdmsr(GLXIIC_MSR_PIC_YSEL_HIGH);
351 sc->old_irq = GLXIIC_MAP_TO_SMB_IRQ(irq_map);
353 unit = device_get_unit(dev);
354 if (resource_int_value("glxiic", unit, "irq", &irq) == 0) {
355 if (irq < 1 || irq > 15) {
356 device_printf(dev, "Bad value %d for glxiic.%d.irq\n",
363 device_printf(dev, "Using irq %d set by hint\n", irq);
364 } else if (sc->old_irq != 0) {
366 device_printf(dev, "Using irq %d set by firmware\n",
370 device_printf(dev, "No irq mapped by firmware");
371 printf(" and no glxiic.%d.irq hint provided\n", unit);
376 /* Map the SMBus interrupt to the requested legacy IRQ. */
377 glxiic_smb_map_interrupt(irq);
380 sc->irq_res = bus_alloc_resource(dev, SYS_RES_IRQ, &sc->irq_rid,
381 irq, irq, 1, RF_SHAREABLE | RF_ACTIVE);
382 if (sc->irq_res == NULL) {
383 device_printf(dev, "Could not allocate IRQ %d\n", irq);
388 error = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
389 NULL, glxiic_intr, sc, &(sc->irq_handler));
391 device_printf(dev, "Could not setup IRQ handler\n");
396 if ((sc->iicbus = device_add_child(dev, "iicbus", -1)) == NULL) {
397 device_printf(dev, "Could not allocate iicbus instance\n");
402 ctx = device_get_sysctl_ctx(dev);
403 tree = device_get_sysctl_tree(dev);
405 sc->timeout = GLXIIC_DEFAULT_TIMEOUT;
406 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
407 "timeout", CTLFLAG_RWTUN, &sc->timeout, 0,
408 "activity timeout in ms");
410 glxiic_gpio_enable(sc);
411 glxiic_smb_enable(sc, IIC_FASTEST, 0);
413 /* Probe and attach the iicbus when interrupts are available. */
414 config_intrhook_oneshot((ich_func_t)bus_generic_attach, dev);
419 callout_drain(&sc->callout);
421 if (sc->iicbus != NULL)
422 device_delete_child(dev, sc->iicbus);
423 if (sc->smb_res != NULL) {
424 glxiic_smb_disable(sc);
425 bus_release_resource(dev, SYS_RES_IOPORT, sc->smb_rid,
428 if (sc->gpio_res != NULL) {
429 glxiic_gpio_disable(sc);
430 bus_release_resource(dev, SYS_RES_IOPORT, sc->gpio_rid,
433 if (sc->irq_handler != NULL)
434 bus_teardown_intr(dev, sc->irq_res, sc->irq_handler);
435 if (sc->irq_res != NULL)
436 bus_release_resource(dev, SYS_RES_IRQ, sc->irq_rid,
439 /* Restore the old SMBus interrupt mapping. */
440 glxiic_smb_map_interrupt(sc->old_irq);
442 GLXIIC_LOCK_DESTROY(sc);
449 glxiic_detach(device_t dev)
451 struct glxiic_softc *sc;
454 sc = device_get_softc(dev);
456 error = bus_generic_detach(dev);
459 if (sc->iicbus != NULL)
460 error = device_delete_child(dev, sc->iicbus);
463 callout_drain(&sc->callout);
465 if (sc->smb_res != NULL) {
466 glxiic_smb_disable(sc);
467 bus_release_resource(dev, SYS_RES_IOPORT, sc->smb_rid,
470 if (sc->gpio_res != NULL) {
471 glxiic_gpio_disable(sc);
472 bus_release_resource(dev, SYS_RES_IOPORT, sc->gpio_rid,
475 if (sc->irq_handler != NULL)
476 bus_teardown_intr(dev, sc->irq_res, sc->irq_handler);
477 if (sc->irq_res != NULL)
478 bus_release_resource(dev, SYS_RES_IRQ, sc->irq_rid,
481 /* Restore the old SMBus interrupt mapping. */
482 glxiic_smb_map_interrupt(sc->old_irq);
484 GLXIIC_LOCK_DESTROY(sc);
490 glxiic_read_status_locked(struct glxiic_softc *sc)
494 GLXIIC_ASSERT_LOCKED(sc);
496 status = bus_read_1(sc->smb_res, GLXIIC_SMB_STS);
498 /* Clear all status flags except SDAST and STASTR after reading. */
499 bus_write_1(sc->smb_res, GLXIIC_SMB_STS, (GLXIIC_SMB_STS_SLVSTP_BIT |
500 GLXIIC_SMB_STS_BER_BIT | GLXIIC_SMB_STS_NEGACK_BIT |
501 GLXIIC_SMB_STS_NMATCH_BIT));
507 glxiic_stop_locked(struct glxiic_softc *sc)
509 uint8_t status, ctrl1;
511 GLXIIC_ASSERT_LOCKED(sc);
513 status = glxiic_read_status_locked(sc);
515 ctrl1 = bus_read_1(sc->smb_res, GLXIIC_SMB_CTRL1);
516 bus_write_1(sc->smb_res, GLXIIC_SMB_CTRL1,
517 ctrl1 | GLXIIC_SMB_CTRL1_STOP_BIT);
520 * Perform a dummy read of SDA in master receive mode to clear
523 if ((status & GLXIIC_SMB_STS_XMIT_BIT) == 0 &&
524 (status & GLXIIC_SMB_STS_SDAST_BIT) != 0)
525 bus_read_1(sc->smb_res, GLXIIC_SMB_SDA);
527 /* Check stall after start bit and clear if needed */
528 if ((status & GLXIIC_SMB_STS_STASTR_BIT) != 0) {
529 bus_write_1(sc->smb_res, GLXIIC_SMB_STS,
530 GLXIIC_SMB_STS_STASTR_BIT);
535 glxiic_timeout(void *arg)
537 struct glxiic_softc *sc;
540 sc = (struct glxiic_softc *)arg;
542 GLXIIC_DEBUG_LOG("timeout in state %d", sc->state);
544 if (glxiic_state_table[sc->state].master) {
545 sc->error = IIC_ETIMEOUT;
548 error = IIC_ETIMEOUT;
549 iicbus_intr(sc->iicbus, INTR_ERROR, &error);
552 glxiic_smb_disable(sc);
553 glxiic_smb_enable(sc, IIC_UNKNOWN, sc->addr);
554 glxiic_set_state_locked(sc, GLXIIC_STATE_IDLE);
558 glxiic_start_timeout_locked(struct glxiic_softc *sc)
561 GLXIIC_ASSERT_LOCKED(sc);
563 callout_reset_sbt(&sc->callout, SBT_1MS * sc->timeout, 0,
564 glxiic_timeout, sc, 0);
568 glxiic_set_state_locked(struct glxiic_softc *sc, glxiic_state_t state)
571 GLXIIC_ASSERT_LOCKED(sc);
573 if (state == GLXIIC_STATE_IDLE)
574 callout_stop(&sc->callout);
575 else if (sc->timeout > 0)
576 glxiic_start_timeout_locked(sc);
582 glxiic_handle_slave_match_locked(struct glxiic_softc *sc, uint8_t status)
584 uint8_t ctrl_sts, addr;
586 GLXIIC_ASSERT_LOCKED(sc);
588 ctrl_sts = bus_read_1(sc->smb_res, GLXIIC_SMB_CTRL_STS);
590 if ((ctrl_sts & GLXIIC_SMB_CTRL_STS_MATCH_BIT) != 0) {
591 if ((status & GLXIIC_SMB_STS_XMIT_BIT) != 0) {
592 addr = sc->addr | LSB;
593 glxiic_set_state_locked(sc,
594 GLXIIC_STATE_SLAVE_TX);
596 addr = sc->addr & ~LSB;
597 glxiic_set_state_locked(sc,
598 GLXIIC_STATE_SLAVE_RX);
600 iicbus_intr(sc->iicbus, INTR_START, &addr);
601 } else if ((ctrl_sts & GLXIIC_SMB_CTRL_STS_GCMTCH_BIT) != 0) {
603 glxiic_set_state_locked(sc, GLXIIC_STATE_SLAVE_RX);
604 iicbus_intr(sc->iicbus, INTR_GENERAL, &addr);
606 GLXIIC_DEBUG_LOG("unknown slave match");
607 return (IIC_ESTATUS);
614 glxiic_state_idle_callback(struct glxiic_softc *sc, uint8_t status)
617 GLXIIC_ASSERT_LOCKED(sc);
619 if ((status & GLXIIC_SMB_STS_BER_BIT) != 0) {
620 GLXIIC_DEBUG_LOG("bus error in idle");
621 return (IIC_EBUSERR);
624 if ((status & GLXIIC_SMB_STS_NMATCH_BIT) != 0) {
625 return (glxiic_handle_slave_match_locked(sc, status));
632 glxiic_state_slave_tx_callback(struct glxiic_softc *sc, uint8_t status)
636 GLXIIC_ASSERT_LOCKED(sc);
638 if ((status & GLXIIC_SMB_STS_BER_BIT) != 0) {
639 GLXIIC_DEBUG_LOG("bus error in slave tx");
640 return (IIC_EBUSERR);
643 if ((status & GLXIIC_SMB_STS_SLVSTP_BIT) != 0) {
644 iicbus_intr(sc->iicbus, INTR_STOP, NULL);
645 glxiic_set_state_locked(sc, GLXIIC_STATE_IDLE);
649 if ((status & GLXIIC_SMB_STS_NEGACK_BIT) != 0) {
650 iicbus_intr(sc->iicbus, INTR_NOACK, NULL);
654 if ((status & GLXIIC_SMB_STS_NMATCH_BIT) != 0) {
655 /* Handle repeated start in slave mode. */
656 return (glxiic_handle_slave_match_locked(sc, status));
659 if ((status & GLXIIC_SMB_STS_SDAST_BIT) == 0) {
660 GLXIIC_DEBUG_LOG("not awaiting data in slave tx");
661 return (IIC_ESTATUS);
664 iicbus_intr(sc->iicbus, INTR_TRANSMIT, &data);
665 bus_write_1(sc->smb_res, GLXIIC_SMB_SDA, data);
667 glxiic_start_timeout_locked(sc);
673 glxiic_state_slave_rx_callback(struct glxiic_softc *sc, uint8_t status)
677 GLXIIC_ASSERT_LOCKED(sc);
679 if ((status & GLXIIC_SMB_STS_BER_BIT) != 0) {
680 GLXIIC_DEBUG_LOG("bus error in slave rx");
681 return (IIC_EBUSERR);
684 if ((status & GLXIIC_SMB_STS_SLVSTP_BIT) != 0) {
685 iicbus_intr(sc->iicbus, INTR_STOP, NULL);
686 glxiic_set_state_locked(sc, GLXIIC_STATE_IDLE);
690 if ((status & GLXIIC_SMB_STS_NMATCH_BIT) != 0) {
691 /* Handle repeated start in slave mode. */
692 return (glxiic_handle_slave_match_locked(sc, status));
695 if ((status & GLXIIC_SMB_STS_SDAST_BIT) == 0) {
696 GLXIIC_DEBUG_LOG("no pending data in slave rx");
697 return (IIC_ESTATUS);
700 data = bus_read_1(sc->smb_res, GLXIIC_SMB_SDA);
701 iicbus_intr(sc->iicbus, INTR_RECEIVE, &data);
703 glxiic_start_timeout_locked(sc);
709 glxiic_state_master_addr_callback(struct glxiic_softc *sc, uint8_t status)
714 GLXIIC_ASSERT_LOCKED(sc);
716 if ((status & GLXIIC_SMB_STS_BER_BIT) != 0) {
717 GLXIIC_DEBUG_LOG("bus error after master start");
718 return (IIC_EBUSERR);
721 if ((status & GLXIIC_SMB_STS_MASTER_BIT) == 0) {
722 GLXIIC_DEBUG_LOG("not bus master after master start");
723 return (IIC_ESTATUS);
726 if ((status & GLXIIC_SMB_STS_SDAST_BIT) == 0) {
727 GLXIIC_DEBUG_LOG("not awaiting address in master addr");
728 return (IIC_ESTATUS);
731 if ((sc->msg->flags & IIC_M_RD) != 0) {
732 slave = sc->msg->slave | LSB;
733 glxiic_set_state_locked(sc, GLXIIC_STATE_MASTER_RX);
735 slave = sc->msg->slave & ~LSB;
736 glxiic_set_state_locked(sc, GLXIIC_STATE_MASTER_TX);
739 sc->data = sc->msg->buf;
740 sc->ndata = sc->msg->len;
742 /* Handle address-only transfer. */
744 glxiic_set_state_locked(sc, GLXIIC_STATE_MASTER_STOP);
746 bus_write_1(sc->smb_res, GLXIIC_SMB_SDA, slave);
748 if ((sc->msg->flags & IIC_M_RD) != 0 && sc->ndata == 1) {
749 /* Last byte from slave, set NACK. */
750 ctrl1 = bus_read_1(sc->smb_res, GLXIIC_SMB_CTRL1);
751 bus_write_1(sc->smb_res, GLXIIC_SMB_CTRL1,
752 ctrl1 | GLXIIC_SMB_CTRL1_ACK_BIT);
759 glxiic_state_master_tx_callback(struct glxiic_softc *sc, uint8_t status)
762 GLXIIC_ASSERT_LOCKED(sc);
764 if ((status & GLXIIC_SMB_STS_BER_BIT) != 0) {
765 GLXIIC_DEBUG_LOG("bus error in master tx");
766 return (IIC_EBUSERR);
769 if ((status & GLXIIC_SMB_STS_MASTER_BIT) == 0) {
770 GLXIIC_DEBUG_LOG("not bus master in master tx");
771 return (IIC_ESTATUS);
774 if ((status & GLXIIC_SMB_STS_NEGACK_BIT) != 0) {
775 GLXIIC_DEBUG_LOG("slave nack in master tx");
779 if ((status & GLXIIC_SMB_STS_STASTR_BIT) != 0) {
780 bus_write_1(sc->smb_res, GLXIIC_SMB_STS,
781 GLXIIC_SMB_STS_STASTR_BIT);
784 if ((status & GLXIIC_SMB_STS_SDAST_BIT) == 0) {
785 GLXIIC_DEBUG_LOG("not awaiting data in master tx");
786 return (IIC_ESTATUS);
789 bus_write_1(sc->smb_res, GLXIIC_SMB_SDA, *sc->data++);
790 if (--sc->ndata == 0)
791 glxiic_set_state_locked(sc, GLXIIC_STATE_MASTER_STOP);
793 glxiic_start_timeout_locked(sc);
799 glxiic_state_master_rx_callback(struct glxiic_softc *sc, uint8_t status)
803 GLXIIC_ASSERT_LOCKED(sc);
805 if ((status & GLXIIC_SMB_STS_BER_BIT) != 0) {
806 GLXIIC_DEBUG_LOG("bus error in master rx");
807 return (IIC_EBUSERR);
810 if ((status & GLXIIC_SMB_STS_MASTER_BIT) == 0) {
811 GLXIIC_DEBUG_LOG("not bus master in master rx");
812 return (IIC_ESTATUS);
815 if ((status & GLXIIC_SMB_STS_NEGACK_BIT) != 0) {
816 GLXIIC_DEBUG_LOG("slave nack in rx");
820 if ((status & GLXIIC_SMB_STS_STASTR_BIT) != 0) {
821 /* Bus is stalled, clear and wait for data. */
822 bus_write_1(sc->smb_res, GLXIIC_SMB_STS,
823 GLXIIC_SMB_STS_STASTR_BIT);
827 if ((status & GLXIIC_SMB_STS_SDAST_BIT) == 0) {
828 GLXIIC_DEBUG_LOG("no pending data in master rx");
829 return (IIC_ESTATUS);
832 *sc->data++ = bus_read_1(sc->smb_res, GLXIIC_SMB_SDA);
833 if (--sc->ndata == 0) {
834 /* Proceed with stop on reading last byte. */
835 glxiic_set_state_locked(sc, GLXIIC_STATE_MASTER_STOP);
836 return (glxiic_state_table[sc->state].callback(sc, status));
839 if (sc->ndata == 1) {
840 /* Last byte from slave, set NACK. */
841 ctrl1 = bus_read_1(sc->smb_res, GLXIIC_SMB_CTRL1);
842 bus_write_1(sc->smb_res, GLXIIC_SMB_CTRL1,
843 ctrl1 | GLXIIC_SMB_CTRL1_ACK_BIT);
846 glxiic_start_timeout_locked(sc);
852 glxiic_state_master_stop_callback(struct glxiic_softc *sc, uint8_t status)
856 GLXIIC_ASSERT_LOCKED(sc);
858 if ((status & GLXIIC_SMB_STS_BER_BIT) != 0) {
859 GLXIIC_DEBUG_LOG("bus error in master stop");
860 return (IIC_EBUSERR);
863 if ((status & GLXIIC_SMB_STS_MASTER_BIT) == 0) {
864 GLXIIC_DEBUG_LOG("not bus master in master stop");
865 return (IIC_ESTATUS);
868 if ((status & GLXIIC_SMB_STS_NEGACK_BIT) != 0) {
869 GLXIIC_DEBUG_LOG("slave nack in master stop");
873 if (--sc->nmsgs > 0) {
874 /* Start transfer of next message. */
875 if ((sc->msg->flags & IIC_M_NOSTOP) == 0) {
876 glxiic_stop_locked(sc);
879 ctrl1 = bus_read_1(sc->smb_res, GLXIIC_SMB_CTRL1);
880 bus_write_1(sc->smb_res, GLXIIC_SMB_CTRL1,
881 ctrl1 | GLXIIC_SMB_CTRL1_START_BIT);
883 glxiic_set_state_locked(sc, GLXIIC_STATE_MASTER_ADDR);
887 glxiic_stop_locked(sc);
888 glxiic_set_state_locked(sc, GLXIIC_STATE_IDLE);
889 sc->error = IIC_NOERR;
897 glxiic_intr(void *arg)
899 struct glxiic_softc *sc;
901 uint8_t status, data;
903 sc = (struct glxiic_softc *)arg;
907 status = glxiic_read_status_locked(sc);
909 /* Check if this interrupt originated from the SMBus. */
911 ~(GLXIIC_SMB_STS_MASTER_BIT | GLXIIC_SMB_STS_XMIT_BIT)) != 0) {
913 error = glxiic_state_table[sc->state].callback(sc, status);
915 if (error != IIC_NOERR) {
916 if (glxiic_state_table[sc->state].master) {
917 glxiic_stop_locked(sc);
918 glxiic_set_state_locked(sc, GLXIIC_STATE_IDLE);
923 iicbus_intr(sc->iicbus, INTR_ERROR, &data);
924 glxiic_set_state_locked(sc, GLXIIC_STATE_IDLE);
933 glxiic_reset(device_t dev, u_char speed, u_char addr, u_char *oldaddr)
935 struct glxiic_softc *sc;
937 sc = device_get_softc(dev);
945 /* A disable/enable cycle resets the controller. */
946 glxiic_smb_disable(sc);
947 glxiic_smb_enable(sc, speed, addr);
949 if (glxiic_state_table[sc->state].master) {
950 sc->error = IIC_ESTATUS;
953 glxiic_set_state_locked(sc, GLXIIC_STATE_IDLE);
961 glxiic_transfer(device_t dev, struct iic_msg *msgs, uint32_t nmsgs)
963 struct glxiic_softc *sc;
967 sc = device_get_softc(dev);
971 if (sc->state != GLXIIC_STATE_IDLE) {
978 glxiic_set_state_locked(sc, GLXIIC_STATE_MASTER_ADDR);
980 /* Set start bit and let glxiic_intr() handle the transfer. */
981 ctrl1 = bus_read_1(sc->smb_res, GLXIIC_SMB_CTRL1);
982 bus_write_1(sc->smb_res, GLXIIC_SMB_CTRL1,
983 ctrl1 | GLXIIC_SMB_CTRL1_START_BIT);
994 glxiic_smb_map_interrupt(int irq)
999 /* Protect the read-modify-write operation. */
1002 irq_map = rdmsr(GLXIIC_MSR_PIC_YSEL_HIGH);
1003 old_irq = GLXIIC_MAP_TO_SMB_IRQ(irq_map);
1005 if (irq != old_irq) {
1006 irq_map &= ~GLXIIC_SMB_IRQ_TO_MAP(old_irq);
1007 irq_map |= GLXIIC_SMB_IRQ_TO_MAP(irq);
1008 wrmsr(GLXIIC_MSR_PIC_YSEL_HIGH, irq_map);
1015 glxiic_gpio_enable(struct glxiic_softc *sc)
1018 bus_write_4(sc->gpio_res, GLXIIC_GPIOL_IN_AUX1_SEL,
1019 GLXIIC_GPIO_14_15_ENABLE);
1020 bus_write_4(sc->gpio_res, GLXIIC_GPIOL_OUT_AUX1_SEL,
1021 GLXIIC_GPIO_14_15_ENABLE);
1025 glxiic_gpio_disable(struct glxiic_softc *sc)
1028 bus_write_4(sc->gpio_res, GLXIIC_GPIOL_OUT_AUX1_SEL,
1029 GLXIIC_GPIO_14_15_DISABLE);
1030 bus_write_4(sc->gpio_res, GLXIIC_GPIOL_IN_AUX1_SEL,
1031 GLXIIC_GPIO_14_15_DISABLE);
1035 glxiic_smb_enable(struct glxiic_softc *sc, uint8_t speed, uint8_t addr)
1043 sc->sclfrq = GLXIIC_SLOW;
1046 sc->sclfrq = GLXIIC_FAST;
1049 sc->sclfrq = GLXIIC_FASTEST;
1053 /* Reuse last frequency. */
1057 /* Set bus speed and enable controller. */
1058 bus_write_2(sc->smb_res, GLXIIC_SMB_CTRL2,
1059 GLXIIC_SCLFRQ(sc->sclfrq) | GLXIIC_SMB_CTRL2_EN_BIT);
1062 /* Enable new match and global call match interrupts. */
1063 ctrl1 |= GLXIIC_SMB_CTRL1_NMINTE_BIT |
1064 GLXIIC_SMB_CTRL1_GCMEN_BIT;
1065 bus_write_1(sc->smb_res, GLXIIC_SMB_ADDR,
1066 GLXIIC_SMB_ADDR_SAEN_BIT | GLXIIC_SMBADDR(addr));
1068 bus_write_1(sc->smb_res, GLXIIC_SMB_ADDR, 0);
1071 /* Enable stall after start and interrupt. */
1072 bus_write_1(sc->smb_res, GLXIIC_SMB_CTRL1,
1073 ctrl1 | GLXIIC_SMB_CTRL1_STASTRE_BIT | GLXIIC_SMB_CTRL1_INTEN_BIT);
1077 glxiic_smb_disable(struct glxiic_softc *sc)
1081 sclfrq = bus_read_2(sc->smb_res, GLXIIC_SMB_CTRL2);
1082 bus_write_2(sc->smb_res, GLXIIC_SMB_CTRL2,
1083 sclfrq & ~GLXIIC_SMB_CTRL2_EN_BIT);