2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2017 Tom Jones <tj@enoti.me>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 * Copyright (c) 2016 Mark Kettenis
33 * Permission to use, copy, modify, and distribute this software for any
34 * purpose with or without fee is hereby granted, provided that the above
35 * copyright notice and this permission notice appear in all copies.
37 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
38 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
39 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
40 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
41 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
42 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
43 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
45 #include <sys/cdefs.h>
46 #include <sys/param.h>
47 #include <sys/systm.h>
50 #include <sys/clock.h>
51 #include <sys/kernel.h>
52 #include <sys/module.h>
53 #include <sys/endian.h>
55 #include <sys/types.h>
56 #include <sys/malloc.h>
58 #include <machine/bus.h>
59 #include <machine/resource.h>
61 #include <contrib/dev/acpica/include/acpi.h>
62 #include <contrib/dev/acpica/include/accommon.h>
64 #include <dev/acpica/acpivar.h>
65 #include <dev/gpio/gpiobusvar.h>
67 #include "opt_platform.h"
71 #include "chvgpio_reg.h"
74 * Macros for driver mutex locking
76 #define CHVGPIO_LOCK(_sc) mtx_lock_spin(&(_sc)->sc_mtx)
77 #define CHVGPIO_UNLOCK(_sc) mtx_unlock_spin(&(_sc)->sc_mtx)
78 #define CHVGPIO_LOCK_INIT(_sc) \
79 mtx_init(&_sc->sc_mtx, device_get_nameunit((_sc)->sc_dev), \
81 #define CHVGPIO_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx)
82 #define CHVGPIO_ASSERT_LOCKED(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED)
83 #define CHVGPIO_ASSERT_UNLOCKED(_sc) mtx_assert(&(_sc)->sc_mtx, MA_NOTOWNED)
85 struct chvgpio_softc {
90 ACPI_HANDLE sc_handle;
93 struct resource *sc_mem_res;
96 struct resource *sc_irq_res;
99 const char *sc_bank_prefix;
103 const char **sc_pin_names;
106 static void chvgpio_intr(void *);
107 static int chvgpio_probe(device_t);
108 static int chvgpio_attach(device_t);
109 static int chvgpio_detach(device_t);
112 chvgpio_pad_cfg0_offset(int pin)
114 return (CHVGPIO_PAD_CFG0 + 1024 * (pin / 15) + 8 * (pin % 15));
118 chvgpio_read_pad_cfg0(struct chvgpio_softc *sc, int pin)
120 return bus_read_4(sc->sc_mem_res, chvgpio_pad_cfg0_offset(pin));
124 chvgpio_write_pad_cfg0(struct chvgpio_softc *sc, int pin, uint32_t val)
126 bus_write_4(sc->sc_mem_res, chvgpio_pad_cfg0_offset(pin), val);
130 chvgpio_read_pad_cfg1(struct chvgpio_softc *sc, int pin)
132 return bus_read_4(sc->sc_mem_res, chvgpio_pad_cfg0_offset(pin) + 4);
136 chvgpio_get_bus(device_t dev)
138 struct chvgpio_softc *sc;
140 sc = device_get_softc(dev);
142 return (sc->sc_busdev);
146 chvgpio_pin_max(device_t dev, int *maxpin)
148 struct chvgpio_softc *sc;
150 sc = device_get_softc(dev);
152 *maxpin = sc->sc_npins - 1;
158 chvgpio_valid_pin(struct chvgpio_softc *sc, int pin)
162 if ((pin / 15) >= sc->sc_ngroups)
164 if ((pin % 15) >= sc->sc_pins[pin / 15])
170 chvgpio_pin_getname(device_t dev, uint32_t pin, char *name)
172 struct chvgpio_softc *sc;
174 sc = device_get_softc(dev);
175 if (chvgpio_valid_pin(sc, pin) != 0)
178 /* return pin name from datasheet */
179 snprintf(name, GPIOMAXNAME, "%s", sc->sc_pin_names[pin]);
180 name[GPIOMAXNAME - 1] = '\0';
185 chvgpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps)
187 struct chvgpio_softc *sc;
189 sc = device_get_softc(dev);
190 if (chvgpio_valid_pin(sc, pin) != 0)
194 if (chvgpio_valid_pin(sc, pin))
195 *caps = GPIO_PIN_INPUT | GPIO_PIN_OUTPUT;
201 chvgpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags)
203 struct chvgpio_softc *sc;
206 sc = device_get_softc(dev);
207 if (chvgpio_valid_pin(sc, pin) != 0)
212 /* Get the current pin state */
214 val = chvgpio_read_pad_cfg0(sc, pin);
216 if (val & CHVGPIO_PAD_CFG0_GPIOCFG_GPIO ||
217 val & CHVGPIO_PAD_CFG0_GPIOCFG_GPO)
218 *flags |= GPIO_PIN_OUTPUT;
220 if (val & CHVGPIO_PAD_CFG0_GPIOCFG_GPIO ||
221 val & CHVGPIO_PAD_CFG0_GPIOCFG_GPI)
222 *flags |= GPIO_PIN_INPUT;
224 val = chvgpio_read_pad_cfg1(sc, pin);
231 chvgpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags)
233 struct chvgpio_softc *sc;
237 sc = device_get_softc(dev);
238 if (chvgpio_valid_pin(sc, pin) != 0)
241 allowed = GPIO_PIN_INPUT | GPIO_PIN_OUTPUT;
244 * Only direction flag allowed
246 if (flags & ~allowed)
250 * Not both directions simultaneously
252 if ((flags & allowed) == allowed)
255 /* Set the GPIO mode and state */
257 val = chvgpio_read_pad_cfg0(sc, pin);
258 if (flags & GPIO_PIN_INPUT)
259 val = val & CHVGPIO_PAD_CFG0_GPIOCFG_GPI;
260 if (flags & GPIO_PIN_OUTPUT)
261 val = val & CHVGPIO_PAD_CFG0_GPIOCFG_GPO;
262 chvgpio_write_pad_cfg0(sc, pin, val);
269 chvgpio_pin_set(device_t dev, uint32_t pin, unsigned int value)
271 struct chvgpio_softc *sc;
274 sc = device_get_softc(dev);
275 if (chvgpio_valid_pin(sc, pin) != 0)
279 val = chvgpio_read_pad_cfg0(sc, pin);
280 if (value == GPIO_PIN_LOW)
281 val = val & ~CHVGPIO_PAD_CFG0_GPIOTXSTATE;
283 val = val | CHVGPIO_PAD_CFG0_GPIOTXSTATE;
284 chvgpio_write_pad_cfg0(sc, pin, val);
291 chvgpio_pin_get(device_t dev, uint32_t pin, unsigned int *value)
293 struct chvgpio_softc *sc;
296 sc = device_get_softc(dev);
297 if (chvgpio_valid_pin(sc, pin) != 0)
303 val = chvgpio_read_pad_cfg0(sc, pin);
304 if (val & CHVGPIO_PAD_CFG0_GPIORXSTATE)
305 *value = GPIO_PIN_HIGH;
307 *value = GPIO_PIN_LOW;
315 chvgpio_pin_toggle(device_t dev, uint32_t pin)
317 struct chvgpio_softc *sc;
320 sc = device_get_softc(dev);
321 if (chvgpio_valid_pin(sc, pin) != 0)
327 val = chvgpio_read_pad_cfg0(sc, pin);
328 val = val ^ CHVGPIO_PAD_CFG0_GPIOTXSTATE;
329 chvgpio_write_pad_cfg0(sc, pin, val);
336 static char *chvgpio_hids[] = {
342 chvgpio_probe(device_t dev)
346 if (acpi_disabled("chvgpio"))
348 rv = ACPI_ID_PROBE(device_get_parent(dev), dev, chvgpio_hids, NULL);
350 device_set_desc(dev, "Intel Cherry View GPIO");
355 chvgpio_attach(device_t dev)
357 struct chvgpio_softc *sc;
363 sc = device_get_softc(dev);
365 sc->sc_handle = acpi_get_handle(dev);
367 status = acpi_GetInteger(sc->sc_handle, "_UID", &uid);
368 if (ACPI_FAILURE(status)) {
369 device_printf(dev, "failed to read _UID\n");
373 CHVGPIO_LOCK_INIT(sc);
377 sc->sc_bank_prefix = SW_BANK_PREFIX;
378 sc->sc_pins = chv_southwest_pins;
379 sc->sc_pin_names = chv_southwest_pin_names;
382 sc->sc_bank_prefix = N_BANK_PREFIX;
383 sc->sc_pins = chv_north_pins;
384 sc->sc_pin_names = chv_north_pin_names;
387 sc->sc_bank_prefix = E_BANK_PREFIX;
388 sc->sc_pins = chv_east_pins;
389 sc->sc_pin_names = chv_east_pin_names;
392 sc->sc_bank_prefix = SE_BANK_PREFIX;
393 sc->sc_pins = chv_southeast_pins;
394 sc->sc_pin_names = chv_southeast_pin_names;
397 device_printf(dev, "invalid _UID value: %d\n", uid);
401 for (i = 0; sc->sc_pins[i] >= 0; i++) {
402 sc->sc_npins += sc->sc_pins[i];
407 sc->sc_mem_res = bus_alloc_resource_any(sc->sc_dev, SYS_RES_MEMORY,
408 &sc->sc_mem_rid, RF_ACTIVE);
409 if (sc->sc_mem_res == NULL) {
410 CHVGPIO_LOCK_DESTROY(sc);
411 device_printf(dev, "can't allocate memory resource\n");
415 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
416 &sc->sc_irq_rid, RF_ACTIVE);
418 if (!sc->sc_irq_res) {
419 CHVGPIO_LOCK_DESTROY(sc);
420 bus_release_resource(dev, SYS_RES_MEMORY,
421 sc->sc_mem_rid, sc->sc_mem_res);
422 device_printf(dev, "can't allocate irq resource\n");
426 error = bus_setup_intr(sc->sc_dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
427 NULL, chvgpio_intr, sc, &sc->intr_handle);
431 device_printf(sc->sc_dev, "unable to setup irq: error %d\n", error);
432 CHVGPIO_LOCK_DESTROY(sc);
433 bus_release_resource(dev, SYS_RES_MEMORY,
434 sc->sc_mem_rid, sc->sc_mem_res);
435 bus_release_resource(dev, SYS_RES_IRQ,
436 sc->sc_irq_rid, sc->sc_irq_res);
440 /* Mask and ack all interrupts. */
441 bus_write_4(sc->sc_mem_res, CHVGPIO_INTERRUPT_MASK, 0);
442 bus_write_4(sc->sc_mem_res, CHVGPIO_INTERRUPT_STATUS, 0xffff);
444 sc->sc_busdev = gpiobus_attach_bus(dev);
445 if (sc->sc_busdev == NULL) {
446 CHVGPIO_LOCK_DESTROY(sc);
447 bus_release_resource(dev, SYS_RES_MEMORY,
448 sc->sc_mem_rid, sc->sc_mem_res);
449 bus_release_resource(dev, SYS_RES_IRQ,
450 sc->sc_irq_rid, sc->sc_irq_res);
458 chvgpio_intr(void *arg)
460 struct chvgpio_softc *sc = arg;
464 reg = bus_read_4(sc->sc_mem_res, CHVGPIO_INTERRUPT_STATUS);
465 for (line = 0; line < 16; line++) {
466 if ((reg & (1 << line)) == 0)
468 bus_write_4(sc->sc_mem_res, CHVGPIO_INTERRUPT_STATUS, 1 << line);
473 chvgpio_detach(device_t dev)
475 struct chvgpio_softc *sc;
476 sc = device_get_softc(dev);
479 gpiobus_detach_bus(dev);
481 if (sc->intr_handle != NULL)
482 bus_teardown_intr(sc->sc_dev, sc->sc_irq_res, sc->intr_handle);
483 if (sc->sc_irq_res != NULL)
484 bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irq_rid, sc->sc_irq_res);
485 if (sc->sc_mem_res != NULL)
486 bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_mem_rid, sc->sc_mem_res);
488 CHVGPIO_LOCK_DESTROY(sc);
493 static device_method_t chvgpio_methods[] = {
494 DEVMETHOD(device_probe, chvgpio_probe),
495 DEVMETHOD(device_attach, chvgpio_attach),
496 DEVMETHOD(device_detach, chvgpio_detach),
499 DEVMETHOD(gpio_get_bus, chvgpio_get_bus),
500 DEVMETHOD(gpio_pin_max, chvgpio_pin_max),
501 DEVMETHOD(gpio_pin_getname, chvgpio_pin_getname),
502 DEVMETHOD(gpio_pin_getflags, chvgpio_pin_getflags),
503 DEVMETHOD(gpio_pin_getcaps, chvgpio_pin_getcaps),
504 DEVMETHOD(gpio_pin_setflags, chvgpio_pin_setflags),
505 DEVMETHOD(gpio_pin_get, chvgpio_pin_get),
506 DEVMETHOD(gpio_pin_set, chvgpio_pin_set),
507 DEVMETHOD(gpio_pin_toggle, chvgpio_pin_toggle),
512 static driver_t chvgpio_driver = {
514 .methods = chvgpio_methods,
515 .size = sizeof(struct chvgpio_softc)
518 DRIVER_MODULE(chvgpio, acpi, chvgpio_driver, NULL, NULL);
519 MODULE_DEPEND(chvgpio, acpi, 1, 1, 1);
520 MODULE_DEPEND(chvgpio, gpiobus, 1, 1, 1);
522 MODULE_VERSION(chvgpio, 1);