2 * Copyright (c) 2001-2003
3 * Fraunhofer Institute for Open Communication Systems (FhG Fokus).
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * Author: Hartmut Brandt <harti@freebsd.org>
31 * This file contains the module and driver infrastructure stuff as well
32 * as a couple of utility functions and the entire initialisation.
35 #include <sys/cdefs.h>
36 __FBSDID("$FreeBSD$");
41 #include <sys/types.h>
42 #include <sys/param.h>
43 #include <sys/systm.h>
44 #include <sys/malloc.h>
45 #include <sys/kernel.h>
47 #include <sys/errno.h>
49 #include <sys/module.h>
50 #include <sys/queue.h>
51 #include <sys/syslog.h>
53 #include <sys/mutex.h>
54 #include <sys/condvar.h>
55 #include <sys/sysctl.h>
58 #include <sys/sockio.h>
60 #include <sys/socket.h>
63 #include <net/if_var.h>
64 #include <net/if_media.h>
65 #include <net/if_atm.h>
66 #include <net/if_types.h>
67 #include <net/route.h>
71 #include <netinet/in.h>
72 #include <netinet/if_atm.h>
74 #include <machine/bus.h>
75 #include <machine/resource.h>
78 #include <dev/pci/pcireg.h>
79 #include <dev/pci/pcivar.h>
81 #include <dev/utopia/utopia.h>
82 #include <dev/hatm/if_hatmconf.h>
83 #include <dev/hatm/if_hatmreg.h>
84 #include <dev/hatm/if_hatmvar.h>
98 MODULE_DEPEND(hatm, utopia, 1, 1, 1);
99 MODULE_DEPEND(hatm, pci, 1, 1, 1);
100 MODULE_DEPEND(hatm, atm, 1, 1, 1);
102 #define EEPROM_DELAY 400 /* microseconds */
104 /* Read from EEPROM 0000 0011b */
105 static const uint32_t readtab[] = {
106 HE_REGM_HOST_PROM_SEL | HE_REGM_HOST_PROM_CLOCK,
108 HE_REGM_HOST_PROM_CLOCK,
110 HE_REGM_HOST_PROM_CLOCK,
112 HE_REGM_HOST_PROM_CLOCK,
114 HE_REGM_HOST_PROM_CLOCK,
116 HE_REGM_HOST_PROM_CLOCK,
118 HE_REGM_HOST_PROM_CLOCK,
119 HE_REGM_HOST_PROM_DATA_IN, /* 0 */
120 HE_REGM_HOST_PROM_CLOCK | HE_REGM_HOST_PROM_DATA_IN,
121 HE_REGM_HOST_PROM_DATA_IN, /* 1 */
122 HE_REGM_HOST_PROM_CLOCK | HE_REGM_HOST_PROM_DATA_IN,
123 HE_REGM_HOST_PROM_DATA_IN, /* 1 */
125 static const uint32_t clocktab[] = {
126 0, HE_REGM_HOST_PROM_CLOCK,
127 0, HE_REGM_HOST_PROM_CLOCK,
128 0, HE_REGM_HOST_PROM_CLOCK,
129 0, HE_REGM_HOST_PROM_CLOCK,
130 0, HE_REGM_HOST_PROM_CLOCK,
131 0, HE_REGM_HOST_PROM_CLOCK,
132 0, HE_REGM_HOST_PROM_CLOCK,
133 0, HE_REGM_HOST_PROM_CLOCK,
138 * Convert cell rate to ATM Forum format
141 hatm_cps2atmf(uint32_t pcr)
149 while (pcr > (1024 - 1)) {
153 return ((1 << 14) | (e << 9) | (pcr & 0x1ff));
156 hatm_atmf2cps(uint32_t fcr)
160 return ((1 << ((fcr >> 9) & 0x1f)) * (512 + (fcr & 0x1ff)) / 512
164 /************************************************************
169 * Probe for a HE controller
172 hatm_probe(device_t dev)
176 for (i = 0; hatm_devs[i].name; i++)
177 if (pci_get_vendor(dev) == hatm_devs[i].vid &&
178 pci_get_device(dev) == hatm_devs[i].did) {
179 device_set_desc(dev, hatm_devs[i].name);
180 return (BUS_PROBE_DEFAULT);
186 * Allocate and map DMA-able memory. We support only contiguous mappings.
189 dmaload_helper(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
193 KASSERT(nsegs == 1, ("too many segments for DMA: %d", nsegs));
194 KASSERT(segs[0].ds_addr <= 0xffffffffUL,
195 ("phys addr too large %lx", (u_long)segs[0].ds_addr));
197 *(bus_addr_t *)arg = segs[0].ds_addr;
200 hatm_alloc_dmamem(struct hatm_softc *sc, const char *what, struct dmamem *mem)
207 * Alignement does not work in the bus_dmamem_alloc function below
208 * on FreeBSD. malloc seems to align objects at least to the object
209 * size so increase the size to the alignment if the size is lesser
210 * than the alignemnt.
211 * XXX on sparc64 this is (probably) not needed.
213 if (mem->size < mem->align)
214 mem->size = mem->align;
216 error = bus_dma_tag_create(sc->parent_tag, mem->align, 0,
217 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
218 NULL, NULL, mem->size, 1,
219 BUS_SPACE_MAXSIZE_32BIT, BUS_DMA_ALLOCNOW,
220 NULL, NULL, &mem->tag);
222 if_printf(sc->ifp, "DMA tag create (%s)\n", what);
226 error = bus_dmamem_alloc(mem->tag, &mem->base, 0, &mem->map);
228 if_printf(sc->ifp, "DMA mem alloc (%s): %d\n",
230 bus_dma_tag_destroy(mem->tag);
235 error = bus_dmamap_load(mem->tag, mem->map, mem->base, mem->size,
236 dmaload_helper, &mem->paddr, BUS_DMA_NOWAIT);
238 if_printf(sc->ifp, "DMA map load (%s): %d\n",
240 bus_dmamem_free(mem->tag, mem->base, mem->map);
241 bus_dma_tag_destroy(mem->tag);
246 DBG(sc, DMA, ("%s S/A/V/P 0x%x 0x%x %p 0x%lx", what, mem->size,
247 mem->align, mem->base, (u_long)mem->paddr));
253 * Destroy all the resources of an DMA-able memory region.
256 hatm_destroy_dmamem(struct dmamem *mem)
258 if (mem->base != NULL) {
259 bus_dmamap_unload(mem->tag, mem->map);
260 bus_dmamem_free(mem->tag, mem->base, mem->map);
261 (void)bus_dma_tag_destroy(mem->tag);
267 * Initialize/destroy DMA maps for the large pool 0
270 hatm_destroy_rmaps(struct hatm_softc *sc)
274 DBG(sc, ATTACH, ("destroying rmaps and lbuf pointers..."));
275 if (sc->rmaps != NULL) {
276 for (b = 0; b < sc->lbufs_size; b++)
277 bus_dmamap_destroy(sc->mbuf_tag, sc->rmaps[b]);
278 free(sc->rmaps, M_DEVBUF);
280 if (sc->lbufs != NULL)
281 free(sc->lbufs, M_DEVBUF);
285 hatm_init_rmaps(struct hatm_softc *sc)
290 DBG(sc, ATTACH, ("allocating rmaps and lbuf pointers..."));
291 sc->lbufs = malloc(sizeof(sc->lbufs[0]) * sc->lbufs_size,
292 M_DEVBUF, M_ZERO | M_WAITOK);
294 /* allocate and create the DMA maps for the large pool */
295 sc->rmaps = malloc(sizeof(sc->rmaps[0]) * sc->lbufs_size,
297 for (b = 0; b < sc->lbufs_size; b++) {
298 err = bus_dmamap_create(sc->mbuf_tag, 0, &sc->rmaps[b]);
300 panic("bus_dmamap_create: %d\n", err);
305 * Initialize and destroy small mbuf page pointers and pages
308 hatm_destroy_smbufs(struct hatm_softc *sc)
311 struct mbuf_page *pg;
312 struct mbuf_chunk_hdr *h;
314 if (sc->mbuf_pages != NULL) {
315 for (i = 0; i < sc->mbuf_npages; i++) {
316 pg = sc->mbuf_pages[i];
317 for (b = 0; b < pg->hdr.nchunks; b++) {
318 h = (struct mbuf_chunk_hdr *) ((char *)pg +
319 b * pg->hdr.chunksize + pg->hdr.hdroff);
320 if (h->flags & MBUF_CARD)
322 "%s -- mbuf page=%u card buf %u\n",
324 if (h->flags & MBUF_USED)
326 "%s -- mbuf page=%u used buf %u\n",
329 bus_dmamap_unload(sc->mbuf_tag, pg->hdr.map);
330 bus_dmamap_destroy(sc->mbuf_tag, pg->hdr.map);
333 free(sc->mbuf_pages, M_DEVBUF);
338 hatm_init_smbufs(struct hatm_softc *sc)
340 sc->mbuf_pages = malloc(sizeof(sc->mbuf_pages[0]) *
341 sc->mbuf_max_pages, M_DEVBUF, M_WAITOK);
346 * Initialize/destroy TPDs. This is called from attach/detach.
349 hatm_destroy_tpds(struct hatm_softc *sc)
353 if (sc->tpds.base == NULL)
356 DBG(sc, ATTACH, ("releasing TPDs ..."));
357 if (sc->tpd_nfree != sc->tpd_total)
358 if_printf(sc->ifp, "%u tpds still in use from %u\n",
359 sc->tpd_total - sc->tpd_nfree, sc->tpd_total);
360 while ((t = SLIST_FIRST(&sc->tpd_free)) != NULL) {
361 SLIST_REMOVE_HEAD(&sc->tpd_free, link);
362 bus_dmamap_destroy(sc->tx_tag, t->map);
364 hatm_destroy_dmamem(&sc->tpds);
365 free(sc->tpd_used, M_DEVBUF);
366 DBG(sc, ATTACH, ("... done"));
369 hatm_init_tpds(struct hatm_softc *sc)
375 DBG(sc, ATTACH, ("allocating %u TPDs and maps ...", sc->tpd_total));
376 error = hatm_alloc_dmamem(sc, "TPD memory", &sc->tpds);
378 DBG(sc, ATTACH, ("... dmamem error=%d", error));
382 /* put all the TPDs on the free list and allocate DMA maps */
383 for (i = 0; i < sc->tpd_total; i++) {
387 error = bus_dmamap_create(sc->tx_tag, 0, &t->map);
389 DBG(sc, ATTACH, ("... dmamap error=%d", error));
390 while ((t = SLIST_FIRST(&sc->tpd_free)) != NULL) {
391 SLIST_REMOVE_HEAD(&sc->tpd_free, link);
392 bus_dmamap_destroy(sc->tx_tag, t->map);
394 hatm_destroy_dmamem(&sc->tpds);
398 SLIST_INSERT_HEAD(&sc->tpd_free, t, link);
401 /* allocate and zero bitmap */
402 sc->tpd_used = malloc(sizeof(uint8_t) * (sc->tpd_total + 7) / 8,
403 M_DEVBUF, M_ZERO | M_WAITOK);
404 sc->tpd_nfree = sc->tpd_total;
406 DBG(sc, ATTACH, ("... done"));
412 * Free all the TPDs that where given to the card.
413 * An mbuf chain may be attached to a TPD - free it also and
414 * unload its associated DMA map.
417 hatm_stop_tpds(struct hatm_softc *sc)
422 DBG(sc, ATTACH, ("free TPDs ..."));
423 for (i = 0; i < sc->tpd_total; i++) {
424 if (TPD_TST_USED(sc, i)) {
429 bus_dmamap_unload(sc->tx_tag, t->map);
432 SLIST_INSERT_HEAD(&sc->tpd_free, t, link);
439 * This frees ALL resources of this interface and leaves the structure
440 * in an indeterminate state. This is called just before detaching or
441 * on a failed attach. No lock should be held.
444 hatm_destroy(struct hatm_softc *sc)
448 bus_teardown_intr(sc->dev, sc->irqres, sc->ih);
450 hatm_destroy_rmaps(sc);
451 hatm_destroy_smbufs(sc);
452 hatm_destroy_tpds(sc);
454 if (sc->vcc_zone != NULL) {
455 for (cid = 0; cid < HE_MAX_VCCS; cid++)
456 if (sc->vccs[cid] != NULL)
457 uma_zfree(sc->vcc_zone, sc->vccs[cid]);
458 uma_zdestroy(sc->vcc_zone);
462 * Release all memory allocated to the various queues and
463 * Status pages. These have there own flag which shows whether
464 * they are really allocated.
466 hatm_destroy_dmamem(&sc->irq_0.mem);
467 hatm_destroy_dmamem(&sc->rbp_s0.mem);
468 hatm_destroy_dmamem(&sc->rbp_l0.mem);
469 hatm_destroy_dmamem(&sc->rbp_s1.mem);
470 hatm_destroy_dmamem(&sc->rbrq_0.mem);
471 hatm_destroy_dmamem(&sc->rbrq_1.mem);
472 hatm_destroy_dmamem(&sc->tbrq.mem);
473 hatm_destroy_dmamem(&sc->tpdrq.mem);
474 hatm_destroy_dmamem(&sc->hsp_mem);
476 if (sc->irqres != NULL)
477 bus_release_resource(sc->dev, SYS_RES_IRQ,
478 sc->irqid, sc->irqres);
480 if (sc->tx_tag != NULL)
481 if (bus_dma_tag_destroy(sc->tx_tag))
482 if_printf(sc->ifp, "mbuf DMA tag busy\n");
484 if (sc->mbuf_tag != NULL)
485 if (bus_dma_tag_destroy(sc->mbuf_tag))
486 if_printf(sc->ifp, "mbuf DMA tag busy\n");
488 if (sc->parent_tag != NULL)
489 if (bus_dma_tag_destroy(sc->parent_tag))
490 if_printf(sc->ifp, "parent DMA tag busy\n");
492 if (sc->memres != NULL)
493 bus_release_resource(sc->dev, SYS_RES_MEMORY,
494 sc->memid, sc->memres);
496 sysctl_ctx_free(&sc->sysctl_ctx);
498 cv_destroy(&sc->cv_rcclose);
499 cv_destroy(&sc->vcc_cv);
500 mtx_destroy(&sc->mtx);
510 hatm_reset(struct hatm_softc *sc)
514 WRITE4(sc, HE_REGO_RESET_CNTL, 0x00);
516 WRITE4(sc, HE_REGO_RESET_CNTL, 0xff);
519 while (((v = READ4(sc, HE_REGO_RESET_CNTL)) & HE_REGM_RESET_STATE) == 0) {
521 if (++count == 100) {
522 if_printf(sc->ifp, "reset failed\n");
534 hatm_init_bus_width(struct hatm_softc *sc)
538 v = READ4(sc, HE_REGO_HOST_CNTL);
540 if (v & HE_REGM_HOST_BUS64) {
542 v1 = pci_read_config(sc->dev, HE_PCIR_GEN_CNTL_0, 4);
543 v1 |= HE_PCIM_CTL0_64BIT;
544 pci_write_config(sc->dev, HE_PCIR_GEN_CNTL_0, v1, 4);
546 v |= HE_REGM_HOST_DESC_RD64
547 | HE_REGM_HOST_DATA_RD64
548 | HE_REGM_HOST_DATA_WR64;
549 WRITE4(sc, HE_REGO_HOST_CNTL, v);
553 v = pci_read_config(sc->dev, HE_PCIR_GEN_CNTL_0, 4);
554 v &= ~HE_PCIM_CTL0_64BIT;
555 pci_write_config(sc->dev, HE_PCIR_GEN_CNTL_0, v, 4);
560 * 4.6 Set Host Endianess
563 hatm_init_endianess(struct hatm_softc *sc)
567 v = READ4(sc, HE_REGO_LB_SWAP);
569 #if BYTE_ORDER == BIG_ENDIAN
570 v |= HE_REGM_LBSWAP_INTR_SWAP |
571 HE_REGM_LBSWAP_DESC_WR_SWAP |
572 HE_REGM_LBSWAP_BIG_ENDIAN;
573 v &= ~(HE_REGM_LBSWAP_DATA_WR_SWAP |
574 HE_REGM_LBSWAP_DESC_RD_SWAP |
575 HE_REGM_LBSWAP_DATA_RD_SWAP);
577 v &= ~(HE_REGM_LBSWAP_DATA_WR_SWAP |
578 HE_REGM_LBSWAP_DESC_RD_SWAP |
579 HE_REGM_LBSWAP_DATA_RD_SWAP |
580 HE_REGM_LBSWAP_INTR_SWAP |
581 HE_REGM_LBSWAP_DESC_WR_SWAP |
582 HE_REGM_LBSWAP_BIG_ENDIAN);
586 v |= HE_REGM_LBSWAP_XFER_SIZE;
588 WRITE4(sc, HE_REGO_LB_SWAP, v);
596 hatm_read_prom_byte(struct hatm_softc *sc, u_int addr)
598 uint32_t val, tmp_read, byte_read;
602 val = READ4(sc, HE_REGO_HOST_CNTL);
603 val &= HE_REGM_HOST_PROM_BITS;
606 val |= HE_REGM_HOST_PROM_WREN;
607 WRITE4(sc, HE_REGO_HOST_CNTL, val);
611 for (i = 0; i < sizeof(readtab) / sizeof(readtab[0]); i++) {
612 WRITE4(sc, HE_REGO_HOST_CNTL, val | readtab[i]);
618 for (n = 7, j = 0; n >= 0; n--) {
619 WRITE4(sc, HE_REGO_HOST_CNTL, val | clocktab[j++] |
620 (((addr >> n) & 1 ) << HE_REGS_HOST_PROM_DATA_IN));
623 WRITE4(sc, HE_REGO_HOST_CNTL, val | clocktab[j++] |
624 (((addr >> n) & 1 ) << HE_REGS_HOST_PROM_DATA_IN));
629 val &= ~HE_REGM_HOST_PROM_WREN;
630 WRITE4(sc, HE_REGO_HOST_CNTL, val);
635 for (n = 7, j = 0; n >= 0; n--) {
636 WRITE4(sc, HE_REGO_HOST_CNTL, val | clocktab[j++]);
639 tmp_read = READ4(sc, HE_REGO_HOST_CNTL);
640 byte_read |= (uint8_t)(((tmp_read & HE_REGM_HOST_PROM_DATA_OUT)
641 >> HE_REGS_HOST_PROM_DATA_OUT) << n);
642 WRITE4(sc, HE_REGO_HOST_CNTL, val | clocktab[j++]);
646 WRITE4(sc, HE_REGO_HOST_CNTL, val | clocktab[j++]);
654 hatm_init_read_eeprom(struct hatm_softc *sc)
660 for (n = count = 0; count < HE_EEPROM_PROD_ID_LEN; count++) {
661 byte = hatm_read_prom_byte(sc, HE_EEPROM_PROD_ID + count);
662 if (n > 0 || byte != ' ')
663 sc->prod_id[n++] = byte;
665 while (n > 0 && sc->prod_id[n-1] == ' ')
667 sc->prod_id[n] = '\0';
669 for (n = count = 0; count < HE_EEPROM_REV_LEN; count++) {
670 byte = hatm_read_prom_byte(sc, HE_EEPROM_REV + count);
671 if (n > 0 || byte != ' ')
674 while (n > 0 && sc->rev[n-1] == ' ')
677 IFP2IFATM(sc->ifp)->mib.hw_version = sc->rev[0];
679 IFP2IFATM(sc->ifp)->mib.serial = hatm_read_prom_byte(sc, HE_EEPROM_M_SN + 0) << 0;
680 IFP2IFATM(sc->ifp)->mib.serial |= hatm_read_prom_byte(sc, HE_EEPROM_M_SN + 1) << 8;
681 IFP2IFATM(sc->ifp)->mib.serial |= hatm_read_prom_byte(sc, HE_EEPROM_M_SN + 2) << 16;
682 IFP2IFATM(sc->ifp)->mib.serial |= hatm_read_prom_byte(sc, HE_EEPROM_M_SN + 3) << 24;
684 v = hatm_read_prom_byte(sc, HE_EEPROM_MEDIA + 0) << 0;
685 v |= hatm_read_prom_byte(sc, HE_EEPROM_MEDIA + 1) << 8;
686 v |= hatm_read_prom_byte(sc, HE_EEPROM_MEDIA + 2) << 16;
687 v |= hatm_read_prom_byte(sc, HE_EEPROM_MEDIA + 3) << 24;
690 case HE_MEDIA_UTP155:
691 IFP2IFATM(sc->ifp)->mib.media = IFM_ATM_UTP_155;
692 IFP2IFATM(sc->ifp)->mib.pcr = ATM_RATE_155M;
695 case HE_MEDIA_MMF155:
696 IFP2IFATM(sc->ifp)->mib.media = IFM_ATM_MM_155;
697 IFP2IFATM(sc->ifp)->mib.pcr = ATM_RATE_155M;
700 case HE_MEDIA_MMF622:
701 IFP2IFATM(sc->ifp)->mib.media = IFM_ATM_MM_622;
702 IFP2IFATM(sc->ifp)->mib.device = ATM_DEVICE_HE622;
703 IFP2IFATM(sc->ifp)->mib.pcr = ATM_RATE_622M;
707 case HE_MEDIA_SMF155:
708 IFP2IFATM(sc->ifp)->mib.media = IFM_ATM_SM_155;
709 IFP2IFATM(sc->ifp)->mib.pcr = ATM_RATE_155M;
712 case HE_MEDIA_SMF622:
713 IFP2IFATM(sc->ifp)->mib.media = IFM_ATM_SM_622;
714 IFP2IFATM(sc->ifp)->mib.device = ATM_DEVICE_HE622;
715 IFP2IFATM(sc->ifp)->mib.pcr = ATM_RATE_622M;
720 IFP2IFATM(sc->ifp)->mib.esi[0] = hatm_read_prom_byte(sc, HE_EEPROM_MAC + 0);
721 IFP2IFATM(sc->ifp)->mib.esi[1] = hatm_read_prom_byte(sc, HE_EEPROM_MAC + 1);
722 IFP2IFATM(sc->ifp)->mib.esi[2] = hatm_read_prom_byte(sc, HE_EEPROM_MAC + 2);
723 IFP2IFATM(sc->ifp)->mib.esi[3] = hatm_read_prom_byte(sc, HE_EEPROM_MAC + 3);
724 IFP2IFATM(sc->ifp)->mib.esi[4] = hatm_read_prom_byte(sc, HE_EEPROM_MAC + 4);
725 IFP2IFATM(sc->ifp)->mib.esi[5] = hatm_read_prom_byte(sc, HE_EEPROM_MAC + 5);
729 * Clear unused interrupt queue
732 hatm_clear_irq(struct hatm_softc *sc, u_int group)
734 WRITE4(sc, HE_REGO_IRQ_BASE(group), 0);
735 WRITE4(sc, HE_REGO_IRQ_HEAD(group), 0);
736 WRITE4(sc, HE_REGO_IRQ_CNTL(group), 0);
737 WRITE4(sc, HE_REGO_IRQ_DATA(group), 0);
741 * 4.10 Initialize interrupt queues
744 hatm_init_irq(struct hatm_softc *sc, struct heirq *q, u_int group)
749 hatm_clear_irq(sc, group);
755 q->irq = q->mem.base;
757 q->tailp = q->irq + (q->size - 1);
760 for (i = 0; i < q->size; i++)
761 q->irq[i] = HE_REGM_ITYPE_INVALID;
763 WRITE4(sc, HE_REGO_IRQ_BASE(group), q->mem.paddr);
764 WRITE4(sc, HE_REGO_IRQ_HEAD(group),
765 ((q->size - 1) << HE_REGS_IRQ_HEAD_SIZE) |
766 (q->thresh << HE_REGS_IRQ_HEAD_THRESH));
767 WRITE4(sc, HE_REGO_IRQ_CNTL(group), q->line);
768 WRITE4(sc, HE_REGO_IRQ_DATA(group), 0);
772 * 5.1.3 Initialize connection memory
775 hatm_init_cm(struct hatm_softc *sc)
777 u_int rsra, mlbm, rabr, numbuffs;
778 u_int tsra, tabr, mtpd;
781 for (n = 0; n < HE_CONFIG_TXMEM; n++)
782 WRITE_TCM4(sc, n, 0);
783 for (n = 0; n < HE_CONFIG_RXMEM; n++)
784 WRITE_RCM4(sc, n, 0);
786 numbuffs = sc->r0_numbuffs + sc->r1_numbuffs + sc->tx_numbuffs;
789 mlbm = ((rsra + IFP2IFATM(sc->ifp)->mib.max_vccs * 8) + 0x7ff) & ~0x7ff;
790 rabr = ((mlbm + numbuffs * 2) + 0x7ff) & ~0x7ff;
791 sc->rsrb = ((rabr + 2048) + (2 * IFP2IFATM(sc->ifp)->mib.max_vccs - 1)) &
792 ~(2 * IFP2IFATM(sc->ifp)->mib.max_vccs - 1);
795 sc->tsrb = tsra + IFP2IFATM(sc->ifp)->mib.max_vccs * 8;
796 sc->tsrc = sc->tsrb + IFP2IFATM(sc->ifp)->mib.max_vccs * 4;
797 sc->tsrd = sc->tsrc + IFP2IFATM(sc->ifp)->mib.max_vccs * 2;
798 tabr = sc->tsrd + IFP2IFATM(sc->ifp)->mib.max_vccs * 1;
799 mtpd = ((tabr + 1024) + (16 * IFP2IFATM(sc->ifp)->mib.max_vccs - 1)) &
800 ~(16 * IFP2IFATM(sc->ifp)->mib.max_vccs - 1);
802 DBG(sc, ATTACH, ("rsra=%x mlbm=%x rabr=%x rsrb=%x",
803 rsra, mlbm, rabr, sc->rsrb));
804 DBG(sc, ATTACH, ("tsra=%x tsrb=%x tsrc=%x tsrd=%x tabr=%x mtpd=%x",
805 tsra, sc->tsrb, sc->tsrc, sc->tsrd, tabr, mtpd));
807 WRITE4(sc, HE_REGO_TSRB_BA, sc->tsrb);
808 WRITE4(sc, HE_REGO_TSRC_BA, sc->tsrc);
809 WRITE4(sc, HE_REGO_TSRD_BA, sc->tsrd);
810 WRITE4(sc, HE_REGO_TMABR_BA, tabr);
811 WRITE4(sc, HE_REGO_TPD_BA, mtpd);
813 WRITE4(sc, HE_REGO_RCMRSRB_BA, sc->rsrb);
814 WRITE4(sc, HE_REGO_RCMLBM_BA, mlbm);
815 WRITE4(sc, HE_REGO_RCMABR_BA, rabr);
821 * 5.1.4 Initialize Local buffer Pools
824 hatm_init_rx_buffer_pool(struct hatm_softc *sc,
825 u_int num, /* bank */
826 u_int start, /* start row */
827 u_int numbuffs /* number of entries */
830 u_int row_size; /* bytes per row */
831 uint32_t row_addr; /* start address of this row */
832 u_int lbuf_size; /* bytes per lbuf */
833 u_int lbufs_per_row; /* number of lbufs per memory row */
834 uint32_t lbufd_index; /* index of lbuf descriptor */
835 uint32_t lbufd_addr; /* address of lbuf descriptor */
836 u_int lbuf_row_cnt; /* current lbuf in current row */
837 uint32_t lbuf_addr; /* address of current buffer */
840 row_size = sc->bytes_per_row;
841 row_addr = start * row_size;
842 lbuf_size = sc->cells_per_lbuf * 48;
843 lbufs_per_row = sc->cells_per_row / sc->cells_per_lbuf;
845 /* descriptor index */
848 /* 2 words per entry */
849 lbufd_addr = READ4(sc, HE_REGO_RCMLBM_BA) + lbufd_index * 2;
851 /* write head of queue */
852 WRITE4(sc, HE_REGO_RLBF_H(num), lbufd_index);
855 for (i = 0; i < numbuffs; i++) {
856 lbuf_addr = (row_addr + lbuf_row_cnt * lbuf_size) / 32;
858 WRITE_RCM4(sc, lbufd_addr, lbuf_addr);
861 WRITE_RCM4(sc, lbufd_addr + 1, lbufd_index);
863 if (++lbuf_row_cnt == lbufs_per_row) {
865 row_addr += row_size;
871 WRITE4(sc, HE_REGO_RLBF_T(num), lbufd_index - 2);
872 WRITE4(sc, HE_REGO_RLBF_C(num), numbuffs);
878 hatm_init_tx_buffer_pool(struct hatm_softc *sc,
879 u_int start, /* start row */
880 u_int numbuffs /* number of entries */
883 u_int row_size; /* bytes per row */
884 uint32_t row_addr; /* start address of this row */
885 u_int lbuf_size; /* bytes per lbuf */
886 u_int lbufs_per_row; /* number of lbufs per memory row */
887 uint32_t lbufd_index; /* index of lbuf descriptor */
888 uint32_t lbufd_addr; /* address of lbuf descriptor */
889 u_int lbuf_row_cnt; /* current lbuf in current row */
890 uint32_t lbuf_addr; /* address of current buffer */
893 row_size = sc->bytes_per_row;
894 row_addr = start * row_size;
895 lbuf_size = sc->cells_per_lbuf * 48;
896 lbufs_per_row = sc->cells_per_row / sc->cells_per_lbuf;
898 /* descriptor index */
899 lbufd_index = sc->r0_numbuffs + sc->r1_numbuffs;
901 /* 2 words per entry */
902 lbufd_addr = READ4(sc, HE_REGO_RCMLBM_BA) + lbufd_index * 2;
904 /* write head of queue */
905 WRITE4(sc, HE_REGO_TLBF_H, lbufd_index);
908 for (i = 0; i < numbuffs; i++) {
909 lbuf_addr = (row_addr + lbuf_row_cnt * lbuf_size) / 32;
911 WRITE_RCM4(sc, lbufd_addr, lbuf_addr);
913 WRITE_RCM4(sc, lbufd_addr + 1, lbufd_index);
915 if (++lbuf_row_cnt == lbufs_per_row) {
917 row_addr += row_size;
923 WRITE4(sc, HE_REGO_TLBF_T, lbufd_index - 1);
928 * 5.1.5 Initialize Intermediate Receive Queues
931 hatm_init_imed_queues(struct hatm_softc *sc)
936 for (n = 0; n < 8; n++) {
937 WRITE4(sc, HE_REGO_INMQ_S(n), 0x10*n+0x000f);
938 WRITE4(sc, HE_REGO_INMQ_L(n), 0x10*n+0x200f);
941 for (n = 0; n < 8; n++) {
942 WRITE4(sc, HE_REGO_INMQ_S(n), n);
943 WRITE4(sc, HE_REGO_INMQ_L(n), n+0x8);
949 * 5.1.7 Init CS block
952 hatm_init_cs_block(struct hatm_softc *sc)
955 u_int clkfreg, cellrate, decr, tmp;
956 static const uint32_t erthr[2][5][3] = HE_REGT_CS_ERTHR;
957 static const uint32_t erctl[2][3] = HE_REGT_CS_ERCTL;
958 static const uint32_t erstat[2][2] = HE_REGT_CS_ERSTAT;
959 static const uint32_t rtfwr[2] = HE_REGT_CS_RTFWR;
960 static const uint32_t rtatr[2] = HE_REGT_CS_RTATR;
961 static const uint32_t bwalloc[2][6] = HE_REGT_CS_BWALLOC;
962 static const uint32_t orcf[2][2] = HE_REGT_CS_ORCF;
964 /* Clear Rate Controller Start Times and Occupied Flags */
965 for (n = 0; n < 32; n++)
966 WRITE_MBOX4(sc, HE_REGO_CS_STTIM(n), 0);
968 clkfreg = sc->he622 ? HE_622_CLOCK : HE_155_CLOCK;
969 cellrate = sc->he622 ? ATM_RATE_622M : ATM_RATE_155M;
970 decr = cellrate / 32;
972 for (n = 0; n < 16; n++) {
973 tmp = clkfreg / cellrate;
974 WRITE_MBOX4(sc, HE_REGO_CS_TGRLD(n), tmp - 1);
978 i = (sc->cells_per_lbuf == 2) ? 0
979 :(sc->cells_per_lbuf == 4) ? 1
983 WRITE_MBOX4(sc, HE_REGO_CS_ERTHR0, erthr[sc->he622][0][i]);
984 WRITE_MBOX4(sc, HE_REGO_CS_ERTHR1, erthr[sc->he622][1][i]);
985 WRITE_MBOX4(sc, HE_REGO_CS_ERTHR2, erthr[sc->he622][2][i]);
986 WRITE_MBOX4(sc, HE_REGO_CS_ERTHR3, erthr[sc->he622][3][i]);
987 WRITE_MBOX4(sc, HE_REGO_CS_ERTHR4, erthr[sc->he622][4][i]);
989 WRITE_MBOX4(sc, HE_REGO_CS_ERCTL0, erctl[sc->he622][0]);
990 WRITE_MBOX4(sc, HE_REGO_CS_ERCTL1, erctl[sc->he622][1]);
991 WRITE_MBOX4(sc, HE_REGO_CS_ERCTL2, erctl[sc->he622][2]);
993 WRITE_MBOX4(sc, HE_REGO_CS_ERSTAT0, erstat[sc->he622][0]);
994 WRITE_MBOX4(sc, HE_REGO_CS_ERSTAT1, erstat[sc->he622][1]);
996 WRITE_MBOX4(sc, HE_REGO_CS_RTFWR, rtfwr[sc->he622]);
997 WRITE_MBOX4(sc, HE_REGO_CS_RTATR, rtatr[sc->he622]);
999 WRITE_MBOX4(sc, HE_REGO_CS_TFBSET, bwalloc[sc->he622][0]);
1000 WRITE_MBOX4(sc, HE_REGO_CS_WCRMAX, bwalloc[sc->he622][1]);
1001 WRITE_MBOX4(sc, HE_REGO_CS_WCRMIN, bwalloc[sc->he622][2]);
1002 WRITE_MBOX4(sc, HE_REGO_CS_WCRINC, bwalloc[sc->he622][3]);
1003 WRITE_MBOX4(sc, HE_REGO_CS_WCRDEC, bwalloc[sc->he622][4]);
1004 WRITE_MBOX4(sc, HE_REGO_CS_WCRCEIL, bwalloc[sc->he622][5]);
1006 WRITE_MBOX4(sc, HE_REGO_CS_OTPPER, orcf[sc->he622][0]);
1007 WRITE_MBOX4(sc, HE_REGO_CS_OTWPER, orcf[sc->he622][1]);
1009 WRITE_MBOX4(sc, HE_REGO_CS_OTTLIM, 8);
1011 for (n = 0; n < 8; n++)
1012 WRITE_MBOX4(sc, HE_REGO_CS_HGRRT(n), 0);
1016 * 5.1.8 CS Block Connection Memory Initialisation
1019 hatm_init_cs_block_cm(struct hatm_softc *sc)
1022 u_int expt, mant, etrm, wcr, ttnrm, tnrm;
1024 uint32_t clkfreq, cellrate, decr;
1025 uint32_t *rg, rtg, val = 0;
1027 u_int buf, buf_limit;
1028 uint32_t base = READ4(sc, HE_REGO_RCMABR_BA);
1030 for (n = 0; n < HE_REGL_CM_GQTBL; n++)
1031 WRITE_RCM4(sc, base + HE_REGO_CM_GQTBL + n, 0);
1032 for (n = 0; n < HE_REGL_CM_RGTBL; n++)
1033 WRITE_RCM4(sc, base + HE_REGO_CM_RGTBL + n, 0);
1036 for (n = 0; n < HE_REGL_CM_TNRMTBL * 4; n++) {
1037 expt = (n >> 5) & 0x1f;
1038 mant = ((n & 0x18) << 4) | 0x7f;
1039 wcr = (1 << expt) * (mant + 512) / 512;
1041 ttnrm = wcr / 10 / (1 << etrm);
1046 tnrm = (tnrm << 8) | (ttnrm & 0xff);
1048 WRITE_RCM4(sc, base + HE_REGO_CM_TNRMTBL + (n/4), tnrm);
1051 clkfreq = sc->he622 ? HE_622_CLOCK : HE_155_CLOCK;
1054 cellrate = sc->he622 ? ATM_RATE_622M : ATM_RATE_155M;
1055 decr = cellrate / 32;
1057 /* compute GRID top row in 1000 * cps */
1058 for (n = 0; n < 16; n++) {
1059 u_int interval = clkfreq / cellrate;
1060 sc->rate_grid[0][n] = (u_int64_t)clkfreq * 1000 / interval;
1064 /* compute the other rows according to 2.4 */
1065 for (i = 1; i < 16; i++)
1066 for (n = 0; n < 16; n++)
1067 sc->rate_grid[i][n] = sc->rate_grid[i-1][n] /
1070 /* first entry is line rate */
1071 n = hatm_cps2atmf(sc->he622 ? ATM_RATE_622M : ATM_RATE_155M);
1072 expt = (n >> 9) & 0x1f;
1074 sc->rate_grid[0][0] = (u_int64_t)(1<<expt) * 1000 * (mant+512) / 512;
1076 /* now build the conversion table - each 32 bit word contains
1077 * two entries - this gives a total of 0x400 16 bit entries.
1078 * This table maps the truncated ATMF rate version into a grid index */
1079 cellrate = sc->he622 ? ATM_RATE_622M : ATM_RATE_155M;
1080 rg = &sc->rate_grid[15][15];
1082 for (rate = 0; rate < 2 * HE_REGL_CM_RTGTBL; rate++) {
1083 /* unpack the ATMF rate */
1085 mant = (rate & 0x1f) << 4;
1087 /* get the cell rate - minimum is 10 per second */
1088 drate = (uint64_t)(1 << expt) * 1000 * (mant + 512) / 512;
1089 if (drate < 10 * 1000)
1092 /* now look up the grid index */
1093 while (drate >= *rg && rg-- > &sc->rate_grid[0][0])
1096 rtg = rg - &sc->rate_grid[0][0];
1098 /* now compute the buffer limit */
1099 buf = drate * sc->tx_numbuffs / (cellrate * 2) / 1000;
1102 else if (buf > buf_limit)
1106 val = (val << 16) | (rtg << 8) | buf;
1110 WRITE_RCM4(sc, base + HE_REGO_CM_RTGTBL + rate/2, val);
1115 * Clear an unused receive group buffer pool
1118 hatm_clear_rpool(struct hatm_softc *sc, u_int group, u_int large)
1120 WRITE4(sc, HE_REGO_RBP_S(large, group), 0);
1121 WRITE4(sc, HE_REGO_RBP_T(large, group), 0);
1122 WRITE4(sc, HE_REGO_RBP_QI(large, group), 1);
1123 WRITE4(sc, HE_REGO_RBP_BL(large, group), 0);
1127 * Initialize a receive group buffer pool
1130 hatm_init_rpool(struct hatm_softc *sc, struct herbp *q, u_int group,
1134 hatm_clear_rpool(sc, group, large);
1138 bzero(q->mem.base, q->mem.size);
1139 q->rbp = q->mem.base;
1140 q->head = q->tail = 0;
1142 DBG(sc, ATTACH, ("RBP%u%c=0x%lx", group, "SL"[large],
1143 (u_long)q->mem.paddr));
1145 WRITE4(sc, HE_REGO_RBP_S(large, group), q->mem.paddr);
1146 WRITE4(sc, HE_REGO_RBP_T(large, group), 0);
1147 WRITE4(sc, HE_REGO_RBP_QI(large, group),
1148 ((q->size - 1) << HE_REGS_RBP_SIZE) |
1149 HE_REGM_RBP_INTR_ENB |
1150 (q->thresh << HE_REGS_RBP_THRESH));
1151 WRITE4(sc, HE_REGO_RBP_BL(large, group), (q->bsize >> 2) & ~1);
1155 * Clear an unused receive buffer return queue
1158 hatm_clear_rbrq(struct hatm_softc *sc, u_int group)
1160 WRITE4(sc, HE_REGO_RBRQ_ST(group), 0);
1161 WRITE4(sc, HE_REGO_RBRQ_H(group), 0);
1162 WRITE4(sc, HE_REGO_RBRQ_Q(group), (1 << HE_REGS_RBRQ_THRESH));
1163 WRITE4(sc, HE_REGO_RBRQ_I(group), 0);
1167 * Initialize receive buffer return queue
1170 hatm_init_rbrq(struct hatm_softc *sc, struct herbrq *rq, u_int group)
1172 if (rq->size == 0) {
1173 hatm_clear_rbrq(sc, group);
1177 rq->rbrq = rq->mem.base;
1180 DBG(sc, ATTACH, ("RBRQ%u=0x%lx", group, (u_long)rq->mem.paddr));
1182 WRITE4(sc, HE_REGO_RBRQ_ST(group), rq->mem.paddr);
1183 WRITE4(sc, HE_REGO_RBRQ_H(group), 0);
1184 WRITE4(sc, HE_REGO_RBRQ_Q(group),
1185 (rq->thresh << HE_REGS_RBRQ_THRESH) |
1186 ((rq->size - 1) << HE_REGS_RBRQ_SIZE));
1187 WRITE4(sc, HE_REGO_RBRQ_I(group),
1188 (rq->tout << HE_REGS_RBRQ_TIME) |
1189 (rq->pcnt << HE_REGS_RBRQ_COUNT));
1193 * Clear an unused transmit buffer return queue N
1196 hatm_clear_tbrq(struct hatm_softc *sc, u_int group)
1198 WRITE4(sc, HE_REGO_TBRQ_B_T(group), 0);
1199 WRITE4(sc, HE_REGO_TBRQ_H(group), 0);
1200 WRITE4(sc, HE_REGO_TBRQ_S(group), 0);
1201 WRITE4(sc, HE_REGO_TBRQ_THRESH(group), 1);
1205 * Initialize transmit buffer return queue N
1208 hatm_init_tbrq(struct hatm_softc *sc, struct hetbrq *tq, u_int group)
1210 if (tq->size == 0) {
1211 hatm_clear_tbrq(sc, group);
1215 tq->tbrq = tq->mem.base;
1218 DBG(sc, ATTACH, ("TBRQ%u=0x%lx", group, (u_long)tq->mem.paddr));
1220 WRITE4(sc, HE_REGO_TBRQ_B_T(group), tq->mem.paddr);
1221 WRITE4(sc, HE_REGO_TBRQ_H(group), 0);
1222 WRITE4(sc, HE_REGO_TBRQ_S(group), tq->size - 1);
1223 WRITE4(sc, HE_REGO_TBRQ_THRESH(group), tq->thresh);
1230 hatm_init_tpdrq(struct hatm_softc *sc)
1235 tq->tpdrq = tq->mem.base;
1236 tq->tail = tq->head = 0;
1238 DBG(sc, ATTACH, ("TPDRQ=0x%lx", (u_long)tq->mem.paddr));
1240 WRITE4(sc, HE_REGO_TPDRQ_H, tq->mem.paddr);
1241 WRITE4(sc, HE_REGO_TPDRQ_T, 0);
1242 WRITE4(sc, HE_REGO_TPDRQ_S, tq->size - 1);
1246 * Function can be called by the infrastructure to start the card.
1251 struct hatm_softc *sc = p;
1255 hatm_initialize(sc);
1256 mtx_unlock(&sc->mtx);
1267 hatm_sysctl(SYSCTL_HANDLER_ARGS)
1269 struct hatm_softc *sc = arg1;
1277 len = sizeof(sc->istats);
1281 panic("bad control code");
1284 ret = malloc(len, M_TEMP, M_WAITOK);
1290 sc->istats.mcc += READ4(sc, HE_REGO_MCC);
1291 sc->istats.oec += READ4(sc, HE_REGO_OEC);
1292 sc->istats.dcc += READ4(sc, HE_REGO_DCC);
1293 sc->istats.cec += READ4(sc, HE_REGO_CEC);
1294 bcopy(&sc->istats, ret, sizeof(sc->istats));
1297 mtx_unlock(&sc->mtx);
1299 error = SYSCTL_OUT(req, ret, len);
1306 kenv_getuint(struct hatm_softc *sc, const char *var,
1307 u_int *ptr, u_int def, int rw)
1309 char full[IFNAMSIZ + 3 + 20];
1315 if (SYSCTL_ADD_UINT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1316 OID_AUTO, var, rw ? CTLFLAG_RW : CTLFLAG_RD, ptr, 0, "") == NULL)
1319 snprintf(full, sizeof(full), "hw.%s.%s",
1320 device_get_nameunit(sc->dev), var);
1322 if ((val = getenv(full)) == NULL)
1324 u = strtoul(val, &end, 0);
1325 if (end == val || *end != '\0') {
1331 if_printf(sc->ifp, "%s=%u\n", full, u);
1337 * Set configurable parameters. Many of these are configurable via
1341 hatm_configure(struct hatm_softc *sc)
1343 /* Receive buffer pool 0 small */
1344 kenv_getuint(sc, "rbps0_size", &sc->rbp_s0.size,
1345 HE_CONFIG_RBPS0_SIZE, 0);
1346 kenv_getuint(sc, "rbps0_thresh", &sc->rbp_s0.thresh,
1347 HE_CONFIG_RBPS0_THRESH, 0);
1348 sc->rbp_s0.bsize = MBUF0_SIZE;
1350 /* Receive buffer pool 0 large */
1351 kenv_getuint(sc, "rbpl0_size", &sc->rbp_l0.size,
1352 HE_CONFIG_RBPL0_SIZE, 0);
1353 kenv_getuint(sc, "rbpl0_thresh", &sc->rbp_l0.thresh,
1354 HE_CONFIG_RBPL0_THRESH, 0);
1355 sc->rbp_l0.bsize = MCLBYTES - MBUFL_OFFSET;
1357 /* Receive buffer return queue 0 */
1358 kenv_getuint(sc, "rbrq0_size", &sc->rbrq_0.size,
1359 HE_CONFIG_RBRQ0_SIZE, 0);
1360 kenv_getuint(sc, "rbrq0_thresh", &sc->rbrq_0.thresh,
1361 HE_CONFIG_RBRQ0_THRESH, 0);
1362 kenv_getuint(sc, "rbrq0_tout", &sc->rbrq_0.tout,
1363 HE_CONFIG_RBRQ0_TOUT, 0);
1364 kenv_getuint(sc, "rbrq0_pcnt", &sc->rbrq_0.pcnt,
1365 HE_CONFIG_RBRQ0_PCNT, 0);
1367 /* Receive buffer pool 1 small */
1368 kenv_getuint(sc, "rbps1_size", &sc->rbp_s1.size,
1369 HE_CONFIG_RBPS1_SIZE, 0);
1370 kenv_getuint(sc, "rbps1_thresh", &sc->rbp_s1.thresh,
1371 HE_CONFIG_RBPS1_THRESH, 0);
1372 sc->rbp_s1.bsize = MBUF1_SIZE;
1374 /* Receive buffer return queue 1 */
1375 kenv_getuint(sc, "rbrq1_size", &sc->rbrq_1.size,
1376 HE_CONFIG_RBRQ1_SIZE, 0);
1377 kenv_getuint(sc, "rbrq1_thresh", &sc->rbrq_1.thresh,
1378 HE_CONFIG_RBRQ1_THRESH, 0);
1379 kenv_getuint(sc, "rbrq1_tout", &sc->rbrq_1.tout,
1380 HE_CONFIG_RBRQ1_TOUT, 0);
1381 kenv_getuint(sc, "rbrq1_pcnt", &sc->rbrq_1.pcnt,
1382 HE_CONFIG_RBRQ1_PCNT, 0);
1384 /* Interrupt queue 0 */
1385 kenv_getuint(sc, "irq0_size", &sc->irq_0.size,
1386 HE_CONFIG_IRQ0_SIZE, 0);
1387 kenv_getuint(sc, "irq0_thresh", &sc->irq_0.thresh,
1388 HE_CONFIG_IRQ0_THRESH, 0);
1389 sc->irq_0.line = HE_CONFIG_IRQ0_LINE;
1391 /* Transmit buffer return queue 0 */
1392 kenv_getuint(sc, "tbrq0_size", &sc->tbrq.size,
1393 HE_CONFIG_TBRQ_SIZE, 0);
1394 kenv_getuint(sc, "tbrq0_thresh", &sc->tbrq.thresh,
1395 HE_CONFIG_TBRQ_THRESH, 0);
1397 /* Transmit buffer ready queue */
1398 kenv_getuint(sc, "tpdrq_size", &sc->tpdrq.size,
1399 HE_CONFIG_TPDRQ_SIZE, 0);
1400 /* Max TPDs per VCC */
1401 kenv_getuint(sc, "tpdmax", &sc->max_tpd,
1402 HE_CONFIG_TPD_MAXCC, 0);
1404 /* external mbuf pages */
1405 kenv_getuint(sc, "max_mbuf_pages", &sc->mbuf_max_pages,
1406 HE_CONFIG_MAX_MBUF_PAGES, 0);
1409 kenv_getuint(sc, "mpsafe", &sc->mpsafe, 0, 0);
1410 if (sc->mpsafe != 0)
1411 sc->mpsafe = INTR_MPSAFE;
1419 * Get TSRs from connection memory
1422 hatm_sysctl_tsr(SYSCTL_HANDLER_ARGS)
1424 struct hatm_softc *sc = arg1;
1428 val = malloc(sizeof(uint32_t) * HE_MAX_VCCS * 15, M_TEMP, M_WAITOK);
1431 for (i = 0; i < HE_MAX_VCCS; i++)
1432 for (j = 0; j <= 14; j++)
1433 val[15 * i + j] = READ_TSR(sc, i, j);
1434 mtx_unlock(&sc->mtx);
1436 error = SYSCTL_OUT(req, val, sizeof(uint32_t) * HE_MAX_VCCS * 15);
1438 if (error != 0 || req->newptr == NULL)
1445 * Get TPDs from connection memory
1448 hatm_sysctl_tpd(SYSCTL_HANDLER_ARGS)
1450 struct hatm_softc *sc = arg1;
1454 val = malloc(sizeof(uint32_t) * HE_MAX_VCCS * 16, M_TEMP, M_WAITOK);
1457 for (i = 0; i < HE_MAX_VCCS; i++)
1458 for (j = 0; j < 16; j++)
1459 val[16 * i + j] = READ_TCM4(sc, 16 * i + j);
1460 mtx_unlock(&sc->mtx);
1462 error = SYSCTL_OUT(req, val, sizeof(uint32_t) * HE_MAX_VCCS * 16);
1464 if (error != 0 || req->newptr == NULL)
1471 * Get mbox registers
1474 hatm_sysctl_mbox(SYSCTL_HANDLER_ARGS)
1476 struct hatm_softc *sc = arg1;
1480 val = malloc(sizeof(uint32_t) * HE_REGO_CS_END, M_TEMP, M_WAITOK);
1483 for (i = 0; i < HE_REGO_CS_END; i++)
1484 val[i] = READ_MBOX4(sc, i);
1485 mtx_unlock(&sc->mtx);
1487 error = SYSCTL_OUT(req, val, sizeof(uint32_t) * HE_REGO_CS_END);
1489 if (error != 0 || req->newptr == NULL)
1496 * Get connection memory
1499 hatm_sysctl_cm(SYSCTL_HANDLER_ARGS)
1501 struct hatm_softc *sc = arg1;
1505 val = malloc(sizeof(uint32_t) * (HE_CONFIG_RXMEM + 1), M_TEMP, M_WAITOK);
1508 val[0] = READ4(sc, HE_REGO_RCMABR_BA);
1509 for (i = 0; i < HE_CONFIG_RXMEM; i++)
1510 val[i + 1] = READ_RCM4(sc, i);
1511 mtx_unlock(&sc->mtx);
1513 error = SYSCTL_OUT(req, val, sizeof(uint32_t) * (HE_CONFIG_RXMEM + 1));
1515 if (error != 0 || req->newptr == NULL)
1522 * Get local buffer memory
1525 hatm_sysctl_lbmem(SYSCTL_HANDLER_ARGS)
1527 struct hatm_softc *sc = arg1;
1530 u_int bytes = (1 << 21);
1532 val = malloc(bytes, M_TEMP, M_WAITOK);
1535 for (i = 0; i < bytes / 4; i++)
1536 val[i] = READ_LB4(sc, i);
1537 mtx_unlock(&sc->mtx);
1539 error = SYSCTL_OUT(req, val, bytes);
1541 if (error != 0 || req->newptr == NULL)
1548 * Get all card registers
1551 hatm_sysctl_heregs(SYSCTL_HANDLER_ARGS)
1553 struct hatm_softc *sc = arg1;
1557 val = malloc(HE_REGO_END, M_TEMP, M_WAITOK);
1560 for (i = 0; i < HE_REGO_END; i += 4)
1561 val[i / 4] = READ4(sc, i);
1562 mtx_unlock(&sc->mtx);
1564 error = SYSCTL_OUT(req, val, HE_REGO_END);
1566 if (error != 0 || req->newptr == NULL)
1574 * Suni register access
1577 * read at most n SUNI registers starting at reg into val
1580 hatm_utopia_readregs(struct ifatm *ifatm, u_int reg, uint8_t *val, u_int *n)
1583 struct hatm_softc *sc = ifatm->ifp->if_softc;
1585 if (reg >= (HE_REGO_SUNI_END - HE_REGO_SUNI) / 4)
1587 if (reg + *n > (HE_REGO_SUNI_END - HE_REGO_SUNI) / 4)
1588 *n = reg - (HE_REGO_SUNI_END - HE_REGO_SUNI) / 4;
1590 mtx_assert(&sc->mtx, MA_OWNED);
1591 for (i = 0; i < *n; i++)
1592 val[i] = READ4(sc, HE_REGO_SUNI + 4 * (reg + i));
1598 * change the bits given by mask to them in val in register reg
1601 hatm_utopia_writereg(struct ifatm *ifatm, u_int reg, u_int mask, u_int val)
1604 struct hatm_softc *sc = ifatm->ifp->if_softc;
1606 if (reg >= (HE_REGO_SUNI_END - HE_REGO_SUNI) / 4)
1609 mtx_assert(&sc->mtx, MA_OWNED);
1610 regval = READ4(sc, HE_REGO_SUNI + 4 * reg);
1611 regval = (regval & ~mask) | (val & mask);
1612 WRITE4(sc, HE_REGO_SUNI + 4 * reg, regval);
1617 static struct utopia_methods hatm_utopia_methods = {
1618 hatm_utopia_readregs,
1619 hatm_utopia_writereg,
1623 * Detach - if it is running, stop. Destroy.
1626 hatm_detach(device_t dev)
1628 struct hatm_softc *sc = device_get_softc(dev);
1632 if (sc->utopia.state & UTP_ST_ATTACHED) {
1633 utopia_stop(&sc->utopia);
1634 utopia_detach(&sc->utopia);
1636 mtx_unlock(&sc->mtx);
1638 atm_ifdetach(sc->ifp);
1646 * Attach to the device. Assume that no locking is needed here.
1647 * All resource we allocate here are freed by calling hatm_destroy.
1650 hatm_attach(device_t dev)
1652 struct hatm_softc *sc;
1657 sc = device_get_softc(dev);
1659 ifp = sc->ifp = if_alloc(IFT_ATM);
1661 device_printf(dev, "could not if_alloc()\n");
1666 IFP2IFATM(sc->ifp)->mib.device = ATM_DEVICE_HE155;
1667 IFP2IFATM(sc->ifp)->mib.serial = 0;
1668 IFP2IFATM(sc->ifp)->mib.hw_version = 0;
1669 IFP2IFATM(sc->ifp)->mib.sw_version = 0;
1670 IFP2IFATM(sc->ifp)->mib.vpi_bits = HE_CONFIG_VPI_BITS;
1671 IFP2IFATM(sc->ifp)->mib.vci_bits = HE_CONFIG_VCI_BITS;
1672 IFP2IFATM(sc->ifp)->mib.max_vpcs = 0;
1673 IFP2IFATM(sc->ifp)->mib.max_vccs = HE_MAX_VCCS;
1674 IFP2IFATM(sc->ifp)->mib.media = IFM_ATM_UNKNOWN;
1676 IFP2IFATM(sc->ifp)->phy = &sc->utopia;
1678 SLIST_INIT(&sc->tpd_free);
1680 mtx_init(&sc->mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, MTX_DEF);
1681 cv_init(&sc->vcc_cv, "HEVCCcv");
1682 cv_init(&sc->cv_rcclose, "RCClose");
1684 sysctl_ctx_init(&sc->sysctl_ctx);
1687 * 4.2 BIOS Configuration
1689 v = pci_read_config(dev, PCIR_COMMAND, 2);
1690 v |= PCIM_CMD_BUSMASTEREN | PCIM_CMD_MWRICEN;
1691 pci_write_config(dev, PCIR_COMMAND, v, 2);
1694 * 4.3 PCI Bus Controller-Specific Initialisation
1696 v = pci_read_config(dev, HE_PCIR_GEN_CNTL_0, 4);
1697 v |= HE_PCIM_CTL0_MRL | HE_PCIM_CTL0_MRM | HE_PCIM_CTL0_IGNORE_TIMEOUT;
1698 #if BYTE_ORDER == BIG_ENDIAN && 0
1699 v |= HE_PCIM_CTL0_BIGENDIAN;
1701 pci_write_config(dev, HE_PCIR_GEN_CNTL_0, v, 4);
1706 sc->memid = PCIR_BAR(0);
1707 sc->memres = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->memid,
1709 if (sc->memres == NULL) {
1710 device_printf(dev, "could not map memory\n");
1714 sc->memh = rman_get_bushandle(sc->memres);
1715 sc->memt = rman_get_bustag(sc->memres);
1718 * ALlocate a DMA tag for subsequent allocations
1720 if (bus_dma_tag_create(bus_get_dma_tag(sc->dev), 1, 0,
1721 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
1723 BUS_SPACE_MAXSIZE_32BIT, 1,
1724 BUS_SPACE_MAXSIZE_32BIT, 0,
1725 NULL, NULL, &sc->parent_tag)) {
1726 device_printf(dev, "could not allocate DMA tag\n");
1731 if (bus_dma_tag_create(sc->parent_tag, 1, 0,
1732 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
1736 NULL, NULL, &sc->mbuf_tag)) {
1737 device_printf(dev, "could not allocate mbuf DMA tag\n");
1743 * Allocate a DMA tag for packets to send. Here we have a problem with
1744 * the specification of the maximum number of segments. Theoretically
1745 * this would be the size of the transmit ring - 1 multiplied by 3,
1746 * but this would not work. So make the maximum number of TPDs
1747 * occupied by one packet a configuration parameter.
1749 if (bus_dma_tag_create(bus_get_dma_tag(sc->dev), 1, 0,
1750 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
1751 HE_MAX_PDU, 3 * HE_CONFIG_MAX_TPD_PER_PACKET, HE_MAX_PDU, 0,
1752 NULL, NULL, &sc->tx_tag)) {
1753 device_printf(dev, "could not allocate TX tag\n");
1759 * Setup the interrupt
1762 sc->irqres = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irqid,
1763 RF_SHAREABLE | RF_ACTIVE);
1764 if (sc->irqres == 0) {
1765 device_printf(dev, "could not allocate irq\n");
1771 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1774 * Make the sysctl tree
1777 if ((sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx,
1778 SYSCTL_STATIC_CHILDREN(_hw_atm), OID_AUTO,
1779 device_get_nameunit(dev), CTLFLAG_RD, 0, "")) == NULL)
1782 if (SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1783 OID_AUTO, "istats", CTLFLAG_RD | CTLTYPE_OPAQUE, sc, CTL_ISTATS,
1784 hatm_sysctl, "LU", "internal statistics") == NULL)
1788 if (SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1789 OID_AUTO, "tsr", CTLFLAG_RD | CTLTYPE_OPAQUE, sc, 0,
1790 hatm_sysctl_tsr, "S", "transmission status registers") == NULL)
1793 if (SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1794 OID_AUTO, "tpd", CTLFLAG_RD | CTLTYPE_OPAQUE, sc, 0,
1795 hatm_sysctl_tpd, "S", "transmission packet descriptors") == NULL)
1798 if (SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1799 OID_AUTO, "mbox", CTLFLAG_RD | CTLTYPE_OPAQUE, sc, 0,
1800 hatm_sysctl_mbox, "S", "mbox registers") == NULL)
1803 if (SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1804 OID_AUTO, "cm", CTLFLAG_RD | CTLTYPE_OPAQUE, sc, 0,
1805 hatm_sysctl_cm, "S", "connection memory") == NULL)
1808 if (SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1809 OID_AUTO, "heregs", CTLFLAG_RD | CTLTYPE_OPAQUE, sc, 0,
1810 hatm_sysctl_heregs, "S", "card registers") == NULL)
1813 if (SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1814 OID_AUTO, "lbmem", CTLFLAG_RD | CTLTYPE_OPAQUE, sc, 0,
1815 hatm_sysctl_lbmem, "S", "local memory") == NULL)
1818 kenv_getuint(sc, "debug", &sc->debug, HATM_DEBUG, 1);
1824 if ((error = hatm_configure(sc)) != 0)
1828 * Compute memory parameters
1830 if (sc->rbp_s0.size != 0) {
1831 sc->rbp_s0.mask = (sc->rbp_s0.size - 1) << 3;
1832 sc->rbp_s0.mem.size = sc->rbp_s0.size * 8;
1833 sc->rbp_s0.mem.align = sc->rbp_s0.mem.size;
1835 if (sc->rbp_l0.size != 0) {
1836 sc->rbp_l0.mask = (sc->rbp_l0.size - 1) << 3;
1837 sc->rbp_l0.mem.size = sc->rbp_l0.size * 8;
1838 sc->rbp_l0.mem.align = sc->rbp_l0.mem.size;
1840 if (sc->rbp_s1.size != 0) {
1841 sc->rbp_s1.mask = (sc->rbp_s1.size - 1) << 3;
1842 sc->rbp_s1.mem.size = sc->rbp_s1.size * 8;
1843 sc->rbp_s1.mem.align = sc->rbp_s1.mem.size;
1845 if (sc->rbrq_0.size != 0) {
1846 sc->rbrq_0.mem.size = sc->rbrq_0.size * 8;
1847 sc->rbrq_0.mem.align = sc->rbrq_0.mem.size;
1849 if (sc->rbrq_1.size != 0) {
1850 sc->rbrq_1.mem.size = sc->rbrq_1.size * 8;
1851 sc->rbrq_1.mem.align = sc->rbrq_1.mem.size;
1854 sc->irq_0.mem.size = sc->irq_0.size * sizeof(uint32_t);
1855 sc->irq_0.mem.align = 4 * 1024;
1857 sc->tbrq.mem.size = sc->tbrq.size * 4;
1858 sc->tbrq.mem.align = 2 * sc->tbrq.mem.size; /* ZZZ */
1860 sc->tpdrq.mem.size = sc->tpdrq.size * 8;
1861 sc->tpdrq.mem.align = sc->tpdrq.mem.size;
1863 sc->hsp_mem.size = sizeof(struct he_hsp);
1864 sc->hsp_mem.align = 1024;
1866 sc->lbufs_size = sc->rbp_l0.size + sc->rbrq_0.size;
1867 sc->tpd_total = sc->tbrq.size + sc->tpdrq.size;
1868 sc->tpds.align = 64;
1869 sc->tpds.size = sc->tpd_total * HE_TPD_SIZE;
1871 hatm_init_rmaps(sc);
1872 hatm_init_smbufs(sc);
1873 if ((error = hatm_init_tpds(sc)) != 0)
1879 if ((error = hatm_alloc_dmamem(sc, "IRQ", &sc->irq_0.mem)) != 0 ||
1880 (error = hatm_alloc_dmamem(sc, "TBRQ0", &sc->tbrq.mem)) != 0 ||
1881 (error = hatm_alloc_dmamem(sc, "TPDRQ", &sc->tpdrq.mem)) != 0 ||
1882 (error = hatm_alloc_dmamem(sc, "HSP", &sc->hsp_mem)) != 0)
1885 if (sc->rbp_s0.mem.size != 0 &&
1886 (error = hatm_alloc_dmamem(sc, "RBPS0", &sc->rbp_s0.mem)))
1888 if (sc->rbp_l0.mem.size != 0 &&
1889 (error = hatm_alloc_dmamem(sc, "RBPL0", &sc->rbp_l0.mem)))
1891 if (sc->rbp_s1.mem.size != 0 &&
1892 (error = hatm_alloc_dmamem(sc, "RBPS1", &sc->rbp_s1.mem)))
1895 if (sc->rbrq_0.mem.size != 0 &&
1896 (error = hatm_alloc_dmamem(sc, "RBRQ0", &sc->rbrq_0.mem)))
1898 if (sc->rbrq_1.mem.size != 0 &&
1899 (error = hatm_alloc_dmamem(sc, "RBRQ1", &sc->rbrq_1.mem)))
1902 if ((sc->vcc_zone = uma_zcreate("HE vccs", sizeof(struct hevcc),
1903 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 0)) == NULL) {
1904 device_printf(dev, "cannot allocate zone for vccs\n");
1909 * 4.4 Reset the card.
1911 if ((error = hatm_reset(sc)) != 0)
1917 hatm_init_bus_width(sc);
1918 hatm_init_read_eeprom(sc);
1919 hatm_init_endianess(sc);
1922 * Initialize interface
1924 ifp->if_flags = IFF_SIMPLEX;
1925 ifp->if_ioctl = hatm_ioctl;
1926 ifp->if_start = hatm_start;
1927 ifp->if_init = hatm_init;
1929 utopia_attach(&sc->utopia, IFP2IFATM(sc->ifp), &sc->media, &sc->mtx,
1930 &sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1931 &hatm_utopia_methods);
1932 utopia_init_media(&sc->utopia);
1934 /* these two SUNI routines need the lock */
1936 /* poll while we are not running */
1937 sc->utopia.flags |= UTP_FL_POLL_CARRIER;
1938 utopia_start(&sc->utopia);
1939 utopia_reset(&sc->utopia);
1940 mtx_unlock(&sc->mtx);
1945 bpfattach(ifp, DLT_ATM_RFC1483, sizeof(struct atmllc));
1948 error = bus_setup_intr(dev, sc->irqres, sc->mpsafe | INTR_TYPE_NET,
1949 NULL, hatm_intr, &sc->irq_0, &sc->ih);
1951 device_printf(dev, "could not setup interrupt\n");
1964 * Start the interface. Assume a state as from attach().
1967 hatm_initialize(struct hatm_softc *sc)
1971 static const u_int layout[2][7] = HE_CONFIG_MEM_LAYOUT;
1973 if (sc->ifp->if_drv_flags & IFF_DRV_RUNNING)
1976 hatm_init_bus_width(sc);
1977 hatm_init_endianess(sc);
1979 if_printf(sc->ifp, "%s, Rev. %s, S/N %u, "
1980 "MAC=%02x:%02x:%02x:%02x:%02x:%02x (%ubit PCI)\n",
1981 sc->prod_id, sc->rev, IFP2IFATM(sc->ifp)->mib.serial,
1982 IFP2IFATM(sc->ifp)->mib.esi[0], IFP2IFATM(sc->ifp)->mib.esi[1], IFP2IFATM(sc->ifp)->mib.esi[2],
1983 IFP2IFATM(sc->ifp)->mib.esi[3], IFP2IFATM(sc->ifp)->mib.esi[4], IFP2IFATM(sc->ifp)->mib.esi[5],
1984 sc->pci64 ? 64 : 32);
1987 * 4.8 SDRAM Controller Initialisation
1988 * 4.9 Initialize RNUM value
1991 WRITE4(sc, HE_REGO_SDRAM_CNTL, HE_REGM_SDRAM_64BIT);
1993 WRITE4(sc, HE_REGO_SDRAM_CNTL, 0);
1996 v = READ4(sc, HE_REGO_LB_SWAP);
1998 v |= 0xf << HE_REGS_LBSWAP_RNUM;
1999 WRITE4(sc, HE_REGO_LB_SWAP, v);
2002 hatm_init_irq(sc, &sc->irq_0, 0);
2003 hatm_clear_irq(sc, 1);
2004 hatm_clear_irq(sc, 2);
2005 hatm_clear_irq(sc, 3);
2007 WRITE4(sc, HE_REGO_GRP_1_0_MAP, 0);
2008 WRITE4(sc, HE_REGO_GRP_3_2_MAP, 0);
2009 WRITE4(sc, HE_REGO_GRP_5_4_MAP, 0);
2010 WRITE4(sc, HE_REGO_GRP_7_6_MAP, 0);
2014 * 4.11 Enable PCI Bus Controller State Machine
2016 v = READ4(sc, HE_REGO_HOST_CNTL);
2018 v |= HE_REGM_HOST_OUTFF_ENB | HE_REGM_HOST_CMDFF_ENB |
2019 HE_REGM_HOST_QUICK_RD | HE_REGM_HOST_QUICK_WR;
2020 WRITE4(sc, HE_REGO_HOST_CNTL, v);
2024 * 5.1.1 Generic configuration state
2026 sc->cells_per_row = layout[sc->he622][0];
2027 sc->bytes_per_row = layout[sc->he622][1];
2028 sc->r0_numrows = layout[sc->he622][2];
2029 sc->tx_numrows = layout[sc->he622][3];
2030 sc->r1_numrows = layout[sc->he622][4];
2031 sc->r0_startrow = layout[sc->he622][5];
2032 sc->tx_startrow = sc->r0_startrow + sc->r0_numrows;
2033 sc->r1_startrow = sc->tx_startrow + sc->tx_numrows;
2034 sc->cells_per_lbuf = layout[sc->he622][6];
2036 sc->r0_numbuffs = sc->r0_numrows * (sc->cells_per_row /
2037 sc->cells_per_lbuf);
2038 sc->r1_numbuffs = sc->r1_numrows * (sc->cells_per_row /
2039 sc->cells_per_lbuf);
2040 sc->tx_numbuffs = sc->tx_numrows * (sc->cells_per_row /
2041 sc->cells_per_lbuf);
2043 if (sc->r0_numbuffs > 2560)
2044 sc->r0_numbuffs = 2560;
2045 if (sc->r1_numbuffs > 2560)
2046 sc->r1_numbuffs = 2560;
2047 if (sc->tx_numbuffs > 5120)
2048 sc->tx_numbuffs = 5120;
2050 DBG(sc, ATTACH, ("cells_per_row=%u bytes_per_row=%u r0_numrows=%u "
2051 "tx_numrows=%u r1_numrows=%u r0_startrow=%u tx_startrow=%u "
2052 "r1_startrow=%u cells_per_lbuf=%u\nr0_numbuffs=%u r1_numbuffs=%u "
2053 "tx_numbuffs=%u\n", sc->cells_per_row, sc->bytes_per_row,
2054 sc->r0_numrows, sc->tx_numrows, sc->r1_numrows, sc->r0_startrow,
2055 sc->tx_startrow, sc->r1_startrow, sc->cells_per_lbuf,
2056 sc->r0_numbuffs, sc->r1_numbuffs, sc->tx_numbuffs));
2059 * 5.1.2 Configure Hardware dependend registers
2062 WRITE4(sc, HE_REGO_LBARB,
2063 (0x2 << HE_REGS_LBARB_SLICE) |
2064 (0xf << HE_REGS_LBARB_RNUM) |
2065 (0x3 << HE_REGS_LBARB_THPRI) |
2066 (0x3 << HE_REGS_LBARB_RHPRI) |
2067 (0x2 << HE_REGS_LBARB_TLPRI) |
2068 (0x1 << HE_REGS_LBARB_RLPRI) |
2069 (0x28 << HE_REGS_LBARB_BUS_MULT) |
2070 (0x50 << HE_REGS_LBARB_NET_PREF));
2072 WRITE4(sc, HE_REGO_SDRAMCON,
2073 /* HW bug: don't use banking */
2074 /* HE_REGM_SDRAMCON_BANK | */
2075 HE_REGM_SDRAMCON_WIDE |
2076 (0x384 << HE_REGS_SDRAMCON_REF));
2078 WRITE4(sc, HE_REGO_RCMCONFIG,
2079 (0x1 << HE_REGS_RCMCONFIG_BANK_WAIT) |
2080 (0x1 << HE_REGS_RCMCONFIG_RW_WAIT) |
2081 (0x0 << HE_REGS_RCMCONFIG_TYPE));
2082 WRITE4(sc, HE_REGO_TCMCONFIG,
2083 (0x2 << HE_REGS_TCMCONFIG_BANK_WAIT) |
2084 (0x1 << HE_REGS_TCMCONFIG_RW_WAIT) |
2085 (0x0 << HE_REGS_TCMCONFIG_TYPE));
2087 WRITE4(sc, HE_REGO_LBARB,
2088 (0x2 << HE_REGS_LBARB_SLICE) |
2089 (0xf << HE_REGS_LBARB_RNUM) |
2090 (0x3 << HE_REGS_LBARB_THPRI) |
2091 (0x3 << HE_REGS_LBARB_RHPRI) |
2092 (0x2 << HE_REGS_LBARB_TLPRI) |
2093 (0x1 << HE_REGS_LBARB_RLPRI) |
2094 (0x46 << HE_REGS_LBARB_BUS_MULT) |
2095 (0x8C << HE_REGS_LBARB_NET_PREF));
2097 WRITE4(sc, HE_REGO_SDRAMCON,
2098 /* HW bug: don't use banking */
2099 /* HE_REGM_SDRAMCON_BANK | */
2100 (0x150 << HE_REGS_SDRAMCON_REF));
2102 WRITE4(sc, HE_REGO_RCMCONFIG,
2103 (0x0 << HE_REGS_RCMCONFIG_BANK_WAIT) |
2104 (0x1 << HE_REGS_RCMCONFIG_RW_WAIT) |
2105 (0x0 << HE_REGS_RCMCONFIG_TYPE));
2106 WRITE4(sc, HE_REGO_TCMCONFIG,
2107 (0x1 << HE_REGS_TCMCONFIG_BANK_WAIT) |
2108 (0x1 << HE_REGS_TCMCONFIG_RW_WAIT) |
2109 (0x0 << HE_REGS_TCMCONFIG_TYPE));
2111 WRITE4(sc, HE_REGO_LBCONFIG, (sc->cells_per_lbuf * 48));
2113 WRITE4(sc, HE_REGO_RLBC_H, 0);
2114 WRITE4(sc, HE_REGO_RLBC_T, 0);
2115 WRITE4(sc, HE_REGO_RLBC_H2, 0);
2117 WRITE4(sc, HE_REGO_RXTHRSH, 512);
2118 WRITE4(sc, HE_REGO_LITHRSH, 256);
2120 WRITE4(sc, HE_REGO_RLBF0_C, sc->r0_numbuffs);
2121 WRITE4(sc, HE_REGO_RLBF1_C, sc->r1_numbuffs);
2124 WRITE4(sc, HE_REGO_RCCONFIG,
2125 (8 << HE_REGS_RCCONFIG_UTDELAY) |
2126 (IFP2IFATM(sc->ifp)->mib.vpi_bits << HE_REGS_RCCONFIG_VP) |
2127 (IFP2IFATM(sc->ifp)->mib.vci_bits << HE_REGS_RCCONFIG_VC));
2128 WRITE4(sc, HE_REGO_TXCONFIG,
2129 (32 << HE_REGS_TXCONFIG_THRESH) |
2130 (IFP2IFATM(sc->ifp)->mib.vci_bits << HE_REGS_TXCONFIG_VCI_MASK) |
2131 (sc->tx_numbuffs << HE_REGS_TXCONFIG_LBFREE));
2133 WRITE4(sc, HE_REGO_RCCONFIG,
2134 (0 << HE_REGS_RCCONFIG_UTDELAY) |
2135 HE_REGM_RCCONFIG_UT_MODE |
2136 (IFP2IFATM(sc->ifp)->mib.vpi_bits << HE_REGS_RCCONFIG_VP) |
2137 (IFP2IFATM(sc->ifp)->mib.vci_bits << HE_REGS_RCCONFIG_VC));
2138 WRITE4(sc, HE_REGO_TXCONFIG,
2139 (32 << HE_REGS_TXCONFIG_THRESH) |
2140 HE_REGM_TXCONFIG_UTMODE |
2141 (IFP2IFATM(sc->ifp)->mib.vci_bits << HE_REGS_TXCONFIG_VCI_MASK) |
2142 (sc->tx_numbuffs << HE_REGS_TXCONFIG_LBFREE));
2145 WRITE4(sc, HE_REGO_TXAAL5_PROTO, 0);
2147 if (sc->rbp_s1.size != 0) {
2148 WRITE4(sc, HE_REGO_RHCONFIG,
2149 HE_REGM_RHCONFIG_PHYENB |
2150 ((sc->he622 ? 0x41 : 0x31) << HE_REGS_RHCONFIG_PTMR_PRE) |
2151 (1 << HE_REGS_RHCONFIG_OAM_GID));
2153 WRITE4(sc, HE_REGO_RHCONFIG,
2154 HE_REGM_RHCONFIG_PHYENB |
2155 ((sc->he622 ? 0x41 : 0x31) << HE_REGS_RHCONFIG_PTMR_PRE) |
2156 (0 << HE_REGS_RHCONFIG_OAM_GID));
2162 hatm_init_rx_buffer_pool(sc, 0, sc->r0_startrow, sc->r0_numbuffs);
2163 hatm_init_rx_buffer_pool(sc, 1, sc->r1_startrow, sc->r1_numbuffs);
2164 hatm_init_tx_buffer_pool(sc, sc->tx_startrow, sc->tx_numbuffs);
2166 hatm_init_imed_queues(sc);
2169 * 5.1.6 Application tunable Parameters
2171 WRITE4(sc, HE_REGO_MCC, 0);
2172 WRITE4(sc, HE_REGO_OEC, 0);
2173 WRITE4(sc, HE_REGO_DCC, 0);
2174 WRITE4(sc, HE_REGO_CEC, 0);
2176 hatm_init_cs_block(sc);
2177 hatm_init_cs_block_cm(sc);
2179 hatm_init_rpool(sc, &sc->rbp_s0, 0, 0);
2180 hatm_init_rpool(sc, &sc->rbp_l0, 0, 1);
2181 hatm_init_rpool(sc, &sc->rbp_s1, 1, 0);
2182 hatm_clear_rpool(sc, 1, 1);
2183 hatm_clear_rpool(sc, 2, 0);
2184 hatm_clear_rpool(sc, 2, 1);
2185 hatm_clear_rpool(sc, 3, 0);
2186 hatm_clear_rpool(sc, 3, 1);
2187 hatm_clear_rpool(sc, 4, 0);
2188 hatm_clear_rpool(sc, 4, 1);
2189 hatm_clear_rpool(sc, 5, 0);
2190 hatm_clear_rpool(sc, 5, 1);
2191 hatm_clear_rpool(sc, 6, 0);
2192 hatm_clear_rpool(sc, 6, 1);
2193 hatm_clear_rpool(sc, 7, 0);
2194 hatm_clear_rpool(sc, 7, 1);
2195 hatm_init_rbrq(sc, &sc->rbrq_0, 0);
2196 hatm_init_rbrq(sc, &sc->rbrq_1, 1);
2197 hatm_clear_rbrq(sc, 2);
2198 hatm_clear_rbrq(sc, 3);
2199 hatm_clear_rbrq(sc, 4);
2200 hatm_clear_rbrq(sc, 5);
2201 hatm_clear_rbrq(sc, 6);
2202 hatm_clear_rbrq(sc, 7);
2205 bzero(sc->lbufs, sizeof(sc->lbufs[0]) * sc->lbufs_size);
2207 hatm_init_tbrq(sc, &sc->tbrq, 0);
2208 hatm_clear_tbrq(sc, 1);
2209 hatm_clear_tbrq(sc, 2);
2210 hatm_clear_tbrq(sc, 3);
2211 hatm_clear_tbrq(sc, 4);
2212 hatm_clear_tbrq(sc, 5);
2213 hatm_clear_tbrq(sc, 6);
2214 hatm_clear_tbrq(sc, 7);
2216 hatm_init_tpdrq(sc);
2218 WRITE4(sc, HE_REGO_UBUFF_BA, (sc->he622 ? 0x104780 : 0x800));
2223 bzero(sc->hsp_mem.base, sc->hsp_mem.size);
2224 sc->hsp = sc->hsp_mem.base;
2225 WRITE4(sc, HE_REGO_HSP_BA, sc->hsp_mem.paddr);
2228 * 5.1.12 Enable transmit and receive
2229 * Enable bus master and interrupts
2231 v = READ_MBOX4(sc, HE_REGO_CS_ERCTL0);
2233 WRITE_MBOX4(sc, HE_REGO_CS_ERCTL0, v);
2235 v = READ4(sc, HE_REGO_RCCONFIG);
2236 v |= HE_REGM_RCCONFIG_RXENB;
2237 WRITE4(sc, HE_REGO_RCCONFIG, v);
2239 v = pci_read_config(sc->dev, HE_PCIR_GEN_CNTL_0, 4);
2240 v |= HE_PCIM_CTL0_INIT_ENB | HE_PCIM_CTL0_INT_PROC_ENB;
2241 pci_write_config(sc->dev, HE_PCIR_GEN_CNTL_0, v, 4);
2243 sc->ifp->if_drv_flags |= IFF_DRV_RUNNING;
2244 sc->ifp->if_baudrate = 53 * 8 * IFP2IFATM(sc->ifp)->mib.pcr;
2246 sc->utopia.flags &= ~UTP_FL_POLL_CARRIER;
2249 for (cid = 0; cid < HE_MAX_VCCS; cid++)
2250 if (sc->vccs[cid] != NULL)
2251 hatm_load_vc(sc, cid, 1);
2253 ATMEV_SEND_IFSTATE_CHANGED(IFP2IFATM(sc->ifp),
2254 sc->utopia.carrier == UTP_CARR_OK);
2258 * This functions stops the card and frees all resources allocated after
2259 * the attach. Must have the global lock.
2262 hatm_stop(struct hatm_softc *sc)
2266 struct mbuf_chunk_hdr *ch;
2267 struct mbuf_page *pg;
2269 mtx_assert(&sc->mtx, MA_OWNED);
2271 if (!(sc->ifp->if_drv_flags & IFF_DRV_RUNNING))
2273 sc->ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2275 ATMEV_SEND_IFSTATE_CHANGED(IFP2IFATM(sc->ifp),
2276 sc->utopia.carrier == UTP_CARR_OK);
2278 sc->utopia.flags |= UTP_FL_POLL_CARRIER;
2281 * Stop and reset the hardware so that everything remains
2284 v = READ_MBOX4(sc, HE_REGO_CS_ERCTL0);
2286 WRITE_MBOX4(sc, HE_REGO_CS_ERCTL0, v);
2288 v = READ4(sc, HE_REGO_RCCONFIG);
2289 v &= ~HE_REGM_RCCONFIG_RXENB;
2290 WRITE4(sc, HE_REGO_RCCONFIG, v);
2292 WRITE4(sc, HE_REGO_RHCONFIG, (0x2 << HE_REGS_RHCONFIG_PTMR_PRE));
2295 v = READ4(sc, HE_REGO_HOST_CNTL);
2297 v &= ~(HE_REGM_HOST_OUTFF_ENB | HE_REGM_HOST_CMDFF_ENB);
2298 WRITE4(sc, HE_REGO_HOST_CNTL, v);
2302 * Disable bust master and interrupts
2304 v = pci_read_config(sc->dev, HE_PCIR_GEN_CNTL_0, 4);
2305 v &= ~(HE_PCIM_CTL0_INIT_ENB | HE_PCIM_CTL0_INT_PROC_ENB);
2306 pci_write_config(sc->dev, HE_PCIR_GEN_CNTL_0, v, 4);
2308 (void)hatm_reset(sc);
2311 * Card resets the SUNI when resetted, so re-initialize it
2313 utopia_reset(&sc->utopia);
2316 * Give any waiters on closing a VCC a chance. They will stop
2317 * to wait if they see that IFF_DRV_RUNNING disappeared.
2319 cv_broadcast(&sc->vcc_cv);
2320 cv_broadcast(&sc->cv_rcclose);
2323 * Now free all resources.
2327 * Free the large mbufs that are given to the card.
2329 for (i = 0 ; i < sc->lbufs_size; i++) {
2330 if (sc->lbufs[i] != NULL) {
2331 bus_dmamap_unload(sc->mbuf_tag, sc->rmaps[i]);
2332 m_freem(sc->lbufs[i]);
2333 sc->lbufs[i] = NULL;
2338 * Free small buffers
2340 for (p = 0; p < sc->mbuf_npages; p++) {
2341 pg = sc->mbuf_pages[p];
2342 for (i = 0; i < pg->hdr.nchunks; i++) {
2343 ch = (struct mbuf_chunk_hdr *) ((char *)pg +
2344 i * pg->hdr.chunksize + pg->hdr.hdroff);
2345 if (ch->flags & MBUF_CARD) {
2346 ch->flags &= ~MBUF_CARD;
2347 ch->flags |= MBUF_USED;
2348 hatm_ext_free(&sc->mbuf_list[pg->hdr.pool],
2349 (struct mbufx_free *)((u_char *)ch -
2358 * Free all partial reassembled PDUs on any VCC.
2360 for (cid = 0; cid < HE_MAX_VCCS; cid++) {
2361 if (sc->vccs[cid] != NULL) {
2362 if (sc->vccs[cid]->chain != NULL) {
2363 m_freem(sc->vccs[cid]->chain);
2364 sc->vccs[cid]->chain = NULL;
2365 sc->vccs[cid]->last = NULL;
2367 if (!(sc->vccs[cid]->vflags & (HE_VCC_RX_OPEN |
2369 hatm_tx_vcc_closed(sc, cid);
2370 uma_zfree(sc->vcc_zone, sc->vccs[cid]);
2371 sc->vccs[cid] = NULL;
2374 sc->vccs[cid]->vflags = 0;
2375 sc->vccs[cid]->ntpds = 0;
2380 if (sc->rbp_s0.size != 0)
2381 bzero(sc->rbp_s0.mem.base, sc->rbp_s0.mem.size);
2382 if (sc->rbp_l0.size != 0)
2383 bzero(sc->rbp_l0.mem.base, sc->rbp_l0.mem.size);
2384 if (sc->rbp_s1.size != 0)
2385 bzero(sc->rbp_s1.mem.base, sc->rbp_s1.mem.size);
2386 if (sc->rbrq_0.size != 0)
2387 bzero(sc->rbrq_0.mem.base, sc->rbrq_0.mem.size);
2388 if (sc->rbrq_1.size != 0)
2389 bzero(sc->rbrq_1.mem.base, sc->rbrq_1.mem.size);
2391 bzero(sc->tbrq.mem.base, sc->tbrq.mem.size);
2392 bzero(sc->tpdrq.mem.base, sc->tpdrq.mem.size);
2393 bzero(sc->hsp_mem.base, sc->hsp_mem.size);
2396 /************************************************************
2398 * Driver infrastructure
2400 devclass_t hatm_devclass;
2402 static device_method_t hatm_methods[] = {
2403 DEVMETHOD(device_probe, hatm_probe),
2404 DEVMETHOD(device_attach, hatm_attach),
2405 DEVMETHOD(device_detach, hatm_detach),
2408 static driver_t hatm_driver = {
2411 sizeof(struct hatm_softc),
2413 DRIVER_MODULE(hatm, pci, hatm_driver, hatm_devclass, NULL, 0);