3 * ===================================
4 * HARP | Host ATM Research Platform
5 * ===================================
8 * This Host ATM Research Platform ("HARP") file (the "Software") is
9 * made available by Network Computing Services, Inc. ("NetworkCS")
10 * "AS IS". NetworkCS does not provide maintenance, improvements or
11 * support of any kind.
13 * NETWORKCS MAKES NO WARRANTIES OR REPRESENTATIONS, EXPRESS OR IMPLIED,
14 * INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY
15 * AND FITNESS FOR A PARTICULAR PURPOSE, AS TO ANY ELEMENT OF THE
16 * SOFTWARE OR ANY SUPPORT PROVIDED IN CONNECTION WITH THIS SOFTWARE.
17 * In no event shall NetworkCS be responsible for any damages, including
18 * but not limited to consequential damages, arising from or relating to
19 * any use of the Software or related support.
21 * Copyright 1994-1998 Network Computing Services, Inc.
23 * Copies of this Software may be made, however, the above copyright
24 * notice must be reproduced on all copies.
31 * FORE Systems 200-Series Adapter Support
32 * ---------------------------------------
34 * Host protocol control blocks
44 * Contains the common and Fore-specific information for each VCC
45 * which is opened through a Fore device.
48 struct cmn_vcc fv_cmn; /* Common VCC stuff */
49 Fore_aal fv_aal; /* CP version of AAL */
50 uint32_t rate; /* Rate control (data/idle cell ratio) */
52 typedef struct fore_vcc Fore_vcc;
54 #define fv_next fv_cmn.cv_next
55 #define fv_toku fv_cmn.cv_toku
56 #define fv_upper fv_cmn.cv_upper
57 #define fv_connvc fv_cmn.cv_connvc
58 #define fv_state fv_cmn.cv_state
59 #define fv_flags fv_cmn.cv_flags
64 #define FVF_ACTCMD 0x01 /* Activate command issued */
68 * Host Transmit Queue Element
70 * Defines the host's view of the CP PDU Transmit Queue
73 struct h_xmit_queue *hxq_next; /* Next element in queue */
74 Xmit_queue *hxq_cpelem; /* CP queue element */
75 Q_status *hxq_status; /* Element status word */
76 Xmit_descr *hxq_descr; /* Element's transmit descriptor */
77 vm_paddr_t hxq_descr_dma; /* Element's transmit descriptor */
78 Fore_vcc *hxq_vcc; /* Data's VCC */
79 KBuffer *hxq_buf; /* Data's buffer chain head */
80 H_dma hxq_dma[XMIT_MAX_SEGS]; /* DMA addresses for segments */
82 typedef struct h_xmit_queue H_xmit_queue;
87 * Host Receive Queue Element
89 * Defines the host's view of the CP PDU Receive Queue
92 struct h_recv_queue *hrq_next; /* Next element in queue */
93 Recv_queue *hrq_cpelem; /* CP queue element */
94 Q_status *hrq_status; /* Element status word */
95 Recv_descr *hrq_descr; /* Element's receive descriptor */
96 vm_paddr_t hrq_descr_dma; /* Element's receive descriptor */
98 typedef struct h_recv_queue H_recv_queue;
103 * Host Buffer Supply Queue Element
105 * Defines the host's view of the CP Buffer Supply Queue
108 struct h_buf_queue *hbq_next; /* Next element in queue */
109 Buf_queue *hbq_cpelem; /* CP queue element */
110 Q_status *hbq_status; /* Element status word */
111 Buf_descr *hbq_descr; /* Element's buffer descriptor array */
112 vm_paddr_t hbq_descr_dma; /* Element's buffer descriptor array */
114 typedef struct h_buf_queue H_buf_queue;
119 * Host Command Queue Element
121 * Defines the host's view of the CP Command Queue
124 struct h_cmd_queue *hcq_next; /* Next element in queue */
125 Cmd_queue *hcq_cpelem; /* CP queue element */
126 Q_status *hcq_status; /* Element status word */
127 Cmd_code hcq_code; /* Command code */
128 void *hcq_arg; /* Command-specific argument */
130 typedef struct h_cmd_queue H_cmd_queue;
137 * For each buffer supplied to the CP, there will be one of these structures
138 * embedded into the non-data portion of the buffer. This will allow us to
139 * track which buffers are currently "controlled" by the CP. The address of
140 * this structure will supplied to/returned from the CP as the buffer handle.
143 Qelem_t bh_qelem; /* Queuing element */
144 u_int bh_type; /* Buffer type (see below) */
145 H_dma bh_dma; /* Buffer DMA address */
147 typedef struct buf_handle Buf_handle;
148 #define SIZEOF_Buf_handle 16
153 #define BHT_S1_SMALL 1 /* Buffer strategy 1, small */
154 #define BHT_S1_LARGE 2 /* Buffer strategy 1, large */
155 #define BHT_S2_SMALL 3 /* Buffer strategy 2, small */
156 #define BHT_S2_LARGE 4 /* Buffer strategy 2, large */
161 * Device Unit Structure
163 * Contains all the information for a single device (adapter).
166 Cmn_unit fu_cmn; /* Common unit stuff */
167 Fore_reg *fu_ctlreg; /* Device control register */
168 Fore_reg *fu_imask; /* Interrupt mask register */
169 Fore_reg *fu_psr; /* PCI specific register */
171 pcici_t fu_pcitag; /* PCI tag */
173 Fore_mem *fu_ram; /* Device RAM */
174 u_int fu_ramsize; /* Size of device RAM */
175 Mon960 *fu_mon; /* Monitor program interface */
176 Aali *fu_aali; /* Microcode program interface */
177 u_int fu_timer; /* Watchdog timer value */
180 H_xmit_queue fu_xmit_q[XMIT_QUELEN]; /* Host queue */
181 H_xmit_queue *fu_xmit_head; /* Queue head */
182 H_xmit_queue *fu_xmit_tail; /* Queue tail */
183 Q_status *fu_xmit_stat; /* Status array (host) */
184 vm_paddr_t fu_xmit_statd; /* Status array (DMA) */
187 H_recv_queue fu_recv_q[RECV_QUELEN]; /* Host queue */
188 H_recv_queue *fu_recv_head; /* Queue head */
189 Q_status *fu_recv_stat; /* Status array (host) */
190 vm_paddr_t fu_recv_statd; /* Status array (DMA) */
191 Recv_descr *fu_recv_desc; /* Descriptor array (host) */
192 vm_paddr_t fu_recv_descd; /* Descriptor array (DMA) */
194 /* Buffer Supply Queue - Strategy 1 Small */
195 H_buf_queue fu_buf1s_q[BUF1_SM_QUELEN]; /* Host queue */
196 H_buf_queue *fu_buf1s_head; /* Queue head */
197 H_buf_queue *fu_buf1s_tail; /* Queue tail */
198 Q_status *fu_buf1s_stat; /* Status array (host) */
199 vm_paddr_t fu_buf1s_statd;/* Status array (DMA) */
200 Buf_descr *fu_buf1s_desc; /* Descriptor array (host) */
201 vm_paddr_t fu_buf1s_descd;/* Descriptor array (DMA) */
202 Queue_t fu_buf1s_bq; /* Queue of supplied buffers */
203 u_int fu_buf1s_cnt; /* Count of supplied buffers */
205 /* Buffer Supply Queue - Strategy 1 Large */
206 H_buf_queue fu_buf1l_q[BUF1_LG_QUELEN]; /* Host queue */
207 H_buf_queue *fu_buf1l_head; /* Queue head */
208 H_buf_queue *fu_buf1l_tail; /* Queue tail */
209 Q_status *fu_buf1l_stat; /* Status array (host) */
210 vm_paddr_t fu_buf1l_statd;/* Status array (DMA) */
211 Buf_descr *fu_buf1l_desc; /* Descriptor array (host) */
212 vm_paddr_t fu_buf1l_descd;/* Descriptor array (DMA) */
213 Queue_t fu_buf1l_bq; /* Queue of supplied buffers */
214 u_int fu_buf1l_cnt; /* Count of supplied buffers */
217 H_cmd_queue fu_cmd_q[CMD_QUELEN]; /* Host queue */
218 H_cmd_queue *fu_cmd_head; /* Queue head */
219 H_cmd_queue *fu_cmd_tail; /* Queue tail */
220 Q_status *fu_cmd_stat; /* Status array (host) */
221 vm_paddr_t fu_cmd_statd; /* Status array (DMA) */
223 Fore_stats *fu_stats; /* Device statistics buffer */
224 vm_paddr_t fu_statsd; /* Device statistics buffer (DMA) */
225 time_t fu_stats_time; /* Last stats request timestamp */
226 int fu_stats_ret; /* Stats request return code */
227 Fore_prom *fu_prom; /* Device PROM buffer */
228 vm_paddr_t fu_promd; /* Device PROM buffer (DMA) */
229 struct callout_handle fu_thandle; /* Timer handle */
230 int fu_ft4; /* Running ForeThought 4 firmware */
234 u_int fu_num_shaped; /* number of shaped VCCs */
236 typedef struct fore_unit Fore_unit;
238 #define fu_pif fu_cmn.cu_pif
239 #define fu_unit fu_cmn.cu_unit
240 #define fu_flags fu_cmn.cu_flags
241 #define fu_mtu fu_cmn.cu_mtu
242 #define fu_open_vcc fu_cmn.cu_open_vcc
243 #define fu_vcc fu_cmn.cu_vcc
244 #define fu_intrpri fu_cmn.cu_intrpri
245 #define fu_savepri fu_cmn.cu_savepri
246 #define fu_vcc_zone fu_cmn.cu_vcc_zone
247 #define fu_nif_zone fu_cmn.cu_nif_zone
248 #define fu_ioctl fu_cmn.cu_ioctl
249 #define fu_instvcc fu_cmn.cu_instvcc
250 #define fu_openvcc fu_cmn.cu_openvcc
251 #define fu_closevcc fu_cmn.cu_closevcc
252 #define fu_output fu_cmn.cu_output
253 #define fu_config fu_cmn.cu_config
254 #define fu_softc fu_cmn.cu_softc
257 * Device flags (in addition to CUF_* flags)
259 #define FUF_STATCMD 0x80 /* Statistics request in progress */
264 #define FUS_NO_SHAPING 0
265 #define FUS_SHAPE_ONE 1
266 #define FUS_SHAPE_ALL 2
269 * Macros to access CP memory
271 #define CP_READ(x) ntohl((u_long)(x))
272 #define CP_WRITE(x) htonl((u_long)(x))
274 #endif /* _FORE_VAR_H */