sys/dev/hifn/hifn7751.c

   1 /*      $OpenBSD: hifn7751.c,v 1.120 2002/05/17 00:33:34 deraadt Exp $  */
   2
   3 /*-
   4  * Invertex AEON / Hifn 7751 driver
   5  * Copyright (c) 1999 Invertex Inc. All rights reserved.
   6  * Copyright (c) 1999 Theo de Raadt
   7  * Copyright (c) 2000-2001 Network Security Technologies, Inc.
   8  *                      http://www.netsec.net
   9  * Copyright (c) 2003 Hifn Inc.
  10  *
  11  * This driver is based on a previous driver by Invertex, for which they
  12  * requested:  Please send any comments, feedback, bug-fixes, or feature
  13  * requests to software@invertex.com.
  14  *
  15  * Redistribution and use in source and binary forms, with or without
  16  * modification, are permitted provided that the following conditions
  17  * are met:
  18  *
  19  * 1. Redistributions of source code must retain the above copyright
  20  *   notice, this list of conditions and the following disclaimer.
  21  * 2. Redistributions in binary form must reproduce the above copyright
  22  *   notice, this list of conditions and the following disclaimer in the
  23  *   documentation and/or other materials provided with the distribution.
  24  * 3. The name of the author may not be used to endorse or promote products
  25  *   derived from this software without specific prior written permission.
  26  *
  27  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  28  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  29  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  30  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  31  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  32  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  33  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  34  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  35  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  36  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  37  *
  38  * Effort sponsored in part by the Defense Advanced Research Projects
  39  * Agency (DARPA) and Air Force Research Laboratory, Air Force
  40  * Materiel Command, USAF, under agreement number F30602-01-2-0537.
  41  */
  42
  43 #include <sys/cdefs.h>
  44 __FBSDID("$FreeBSD$");
  45
  46 /*
  47  * Driver for various Hifn encryption processors.
  48  */
  49 #include "opt_hifn.h"
  50
  51 #include <sys/param.h>
  52 #include <sys/systm.h>
  53 #include <sys/proc.h>
  54 #include <sys/errno.h>
  55 #include <sys/malloc.h>
  56 #include <sys/kernel.h>
  57 #include <sys/module.h>
  58 #include <sys/mbuf.h>
  59 #include <sys/lock.h>
  60 #include <sys/mutex.h>
  61 #include <sys/sysctl.h>
  62
  63 #include <vm/vm.h>
  64 #include <vm/pmap.h>
  65
  66 #include <machine/bus.h>
  67 #include <machine/resource.h>
  68 #include <sys/bus.h>
  69 #include <sys/rman.h>
  70
  71 #include <opencrypto/cryptodev.h>
  72 #include <sys/random.h>
  73
  74 #include <dev/pci/pcivar.h>
  75 #include <dev/pci/pcireg.h>
  76
  77 #ifdef HIFN_RNDTEST
  78 #include <dev/rndtest/rndtest.h>
  79 #endif
  80 #include <dev/hifn/hifn7751reg.h>
  81 #include <dev/hifn/hifn7751var.h>
  82
  83 /*
  84  * Prototypes and count for the pci_device structure
  85  */
  86 static  int hifn_probe(device_t);
  87 static  int hifn_attach(device_t);
  88 static  int hifn_detach(device_t);
  89 static  int hifn_suspend(device_t);
  90 static  int hifn_resume(device_t);
  91 static  void hifn_shutdown(device_t);
  92
  93 static device_method_t hifn_methods[] = {
  94         /* Device interface */
  95         DEVMETHOD(device_probe,         hifn_probe),
  96         DEVMETHOD(device_attach,        hifn_attach),
  97         DEVMETHOD(device_detach,        hifn_detach),
  98         DEVMETHOD(device_suspend,       hifn_suspend),
  99         DEVMETHOD(device_resume,        hifn_resume),
 100         DEVMETHOD(device_shutdown,      hifn_shutdown),
 101
 102         /* bus interface */
 103         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 104         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
 105
 106         { 0, 0 }
 107 };
 108 static driver_t hifn_driver = {
 109         "hifn",
 110         hifn_methods,
 111         sizeof (struct hifn_softc)
 112 };
 113 static devclass_t hifn_devclass;
 114
 115 DRIVER_MODULE(hifn, pci, hifn_driver, hifn_devclass, 0, 0);
 116 MODULE_DEPEND(hifn, crypto, 1, 1, 1);
 117 #ifdef HIFN_RNDTEST
 118 MODULE_DEPEND(hifn, rndtest, 1, 1, 1);
 119 #endif
 120
 121 static  void hifn_reset_board(struct hifn_softc *, int);
 122 static  void hifn_reset_puc(struct hifn_softc *);
 123 static  void hifn_puc_wait(struct hifn_softc *);
 124 static  int hifn_enable_crypto(struct hifn_softc *);
 125 static  void hifn_set_retry(struct hifn_softc *sc);
 126 static  void hifn_init_dma(struct hifn_softc *);
 127 static  void hifn_init_pci_registers(struct hifn_softc *);
 128 static  int hifn_sramsize(struct hifn_softc *);
 129 static  int hifn_dramsize(struct hifn_softc *);
 130 static  int hifn_ramtype(struct hifn_softc *);
 131 static  void hifn_sessions(struct hifn_softc *);
 132 static  void hifn_intr(void *);
 133 static  u_int hifn_write_command(struct hifn_command *, u_int8_t *);
 134 static  u_int32_t hifn_next_signature(u_int32_t a, u_int cnt);
 135 static  int hifn_newsession(void *, u_int32_t *, struct cryptoini *);
 136 static  int hifn_freesession(void *, u_int64_t);
 137 static  int hifn_process(void *, struct cryptop *, int);
 138 static  void hifn_callback(struct hifn_softc *, struct hifn_command *, u_int8_t *);
 139 static  int hifn_crypto(struct hifn_softc *, struct hifn_command *, struct cryptop *, int);
 140 static  int hifn_readramaddr(struct hifn_softc *, int, u_int8_t *);
 141 static  int hifn_writeramaddr(struct hifn_softc *, int, u_int8_t *);
 142 static  int hifn_dmamap_load_src(struct hifn_softc *, struct hifn_command *);
 143 static  int hifn_dmamap_load_dst(struct hifn_softc *, struct hifn_command *);
 144 static  int hifn_init_pubrng(struct hifn_softc *);
 145 static  void hifn_rng(void *);
 146 static  void hifn_tick(void *);
 147 static  void hifn_abort(struct hifn_softc *);
 148 static  void hifn_alloc_slot(struct hifn_softc *, int *, int *, int *, int *);
 149
 150 static  void hifn_write_reg_0(struct hifn_softc *, bus_size_t, u_int32_t);
 151 static  void hifn_write_reg_1(struct hifn_softc *, bus_size_t, u_int32_t);
 152
 153 static __inline u_int32_t
 154 READ_REG_0(struct hifn_softc *sc, bus_size_t reg)
 155 {
 156     u_int32_t v = bus_space_read_4(sc->sc_st0, sc->sc_sh0, reg);
 157     sc->sc_bar0_lastreg = (bus_size_t) -1;
 158     return (v);
 159 }
 160 #define WRITE_REG_0(sc, reg, val)       hifn_write_reg_0(sc, reg, val)
 161
 162 static __inline u_int32_t
 163 READ_REG_1(struct hifn_softc *sc, bus_size_t reg)
 164 {
 165     u_int32_t v = bus_space_read_4(sc->sc_st1, sc->sc_sh1, reg);
 166     sc->sc_bar1_lastreg = (bus_size_t) -1;
 167     return (v);
 168 }
 169 #define WRITE_REG_1(sc, reg, val)       hifn_write_reg_1(sc, reg, val)
 170
 171 SYSCTL_NODE(_hw, OID_AUTO, hifn, CTLFLAG_RD, 0, "Hifn driver parameters");
 172
 173 #ifdef HIFN_DEBUG
 174 static  int hifn_debug = 0;
 175 SYSCTL_INT(_hw_hifn, OID_AUTO, debug, CTLFLAG_RW, &hifn_debug,
 176             0, "control debugging msgs");
 177 #endif
 178
 179 static  struct hifn_stats hifnstats;
 180 SYSCTL_STRUCT(_hw_hifn, OID_AUTO, stats, CTLFLAG_RD, &hifnstats,
 181             hifn_stats, "driver statistics");
 182 static  int hifn_maxbatch = 1;
 183 SYSCTL_INT(_hw_hifn, OID_AUTO, maxbatch, CTLFLAG_RW, &hifn_maxbatch,
 184             0, "max ops to batch w/o interrupt");
 185
 186 /*
 187  * Probe for a supported device.  The PCI vendor and device
 188  * IDs are used to detect devices we know how to handle.
 189  */
 190 static int
 191 hifn_probe(device_t dev)
 192 {
 193         if (pci_get_vendor(dev) == PCI_VENDOR_INVERTEX &&
 194             pci_get_device(dev) == PCI_PRODUCT_INVERTEX_AEON)
 195                 return (BUS_PROBE_DEFAULT);
 196         if (pci_get_vendor(dev) == PCI_VENDOR_HIFN &&
 197             (pci_get_device(dev) == PCI_PRODUCT_HIFN_7751 ||
 198              pci_get_device(dev) == PCI_PRODUCT_HIFN_7951 ||
 199              pci_get_device(dev) == PCI_PRODUCT_HIFN_7955 ||
 200              pci_get_device(dev) == PCI_PRODUCT_HIFN_7956 ||
 201              pci_get_device(dev) == PCI_PRODUCT_HIFN_7811))
 202                 return (BUS_PROBE_DEFAULT);
 203         if (pci_get_vendor(dev) == PCI_VENDOR_NETSEC &&
 204             pci_get_device(dev) == PCI_PRODUCT_NETSEC_7751)
 205                 return (BUS_PROBE_DEFAULT);
 206         return (ENXIO);
 207 }
 208
 209 static void
 210 hifn_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
 211 {
 212         bus_addr_t *paddr = (bus_addr_t*) arg;
 213         *paddr = segs->ds_addr;
 214 }
 215
 216 static const char*
 217 hifn_partname(struct hifn_softc *sc)
 218 {
 219         /* XXX sprintf numbers when not decoded */
 220         switch (pci_get_vendor(sc->sc_dev)) {
 221         case PCI_VENDOR_HIFN:
 222                 switch (pci_get_device(sc->sc_dev)) {
 223                 case PCI_PRODUCT_HIFN_6500:     return "Hifn 6500";
 224                 case PCI_PRODUCT_HIFN_7751:     return "Hifn 7751";
 225                 case PCI_PRODUCT_HIFN_7811:     return "Hifn 7811";
 226                 case PCI_PRODUCT_HIFN_7951:     return "Hifn 7951";
 227                 case PCI_PRODUCT_HIFN_7955:     return "Hifn 7955";
 228                 case PCI_PRODUCT_HIFN_7956:     return "Hifn 7956";
 229                 }
 230                 return "Hifn unknown-part";
 231         case PCI_VENDOR_INVERTEX:
 232                 switch (pci_get_device(sc->sc_dev)) {
 233                 case PCI_PRODUCT_INVERTEX_AEON: return "Invertex AEON";
 234                 }
 235                 return "Invertex unknown-part";
 236         case PCI_VENDOR_NETSEC:
 237                 switch (pci_get_device(sc->sc_dev)) {
 238                 case PCI_PRODUCT_NETSEC_7751:   return "NetSec 7751";
 239                 }
 240                 return "NetSec unknown-part";
 241         }
 242         return "Unknown-vendor unknown-part";
 243 }
 244
 245 static void
 246 default_harvest(struct rndtest_state *rsp, void *buf, u_int count)
 247 {
 248         random_harvest(buf, count, count*NBBY, 0, RANDOM_PURE);
 249 }
 250
 251 static u_int
 252 checkmaxmin(device_t dev, const char *what, u_int v, u_int min, u_int max)
 253 {
 254         if (v > max) {
 255                 device_printf(dev, "Warning, %s %u out of range, "
 256                         "using max %u\n", what, v, max);
 257                 v = max;
 258         } else if (v < min) {
 259                 device_printf(dev, "Warning, %s %u out of range, "
 260                         "using min %u\n", what, v, min);
 261                 v = min;
 262         }
 263         return v;
 264 }
 265
 266 /*
 267  * Select PLL configuration for 795x parts.  This is complicated in
 268  * that we cannot determine the optimal parameters without user input.
 269  * The reference clock is derived from an external clock through a
 270  * multiplier.  The external clock is either the host bus (i.e. PCI)
 271  * or an external clock generator.  When using the PCI bus we assume
 272  * the clock is either 33 or 66 MHz; for an external source we cannot
 273  * tell the speed.
 274  *
 275  * PLL configuration is done with a string: "pci" for PCI bus, or "ext"
 276  * for an external source, followed by the frequency.  We calculate
 277  * the appropriate multiplier and PLL register contents accordingly.
 278  * When no configuration is given we default to "pci66" since that
 279  * always will allow the card to work.  If a card is using the PCI
 280  * bus clock and in a 33MHz slot then it will be operating at half
 281  * speed until the correct information is provided.
 282  */
 283 static void
 284 hifn_getpllconfig(device_t dev, u_int *pll)
 285 {
 286         const char *pllspec;
 287         u_int freq, mul, fl, fh;
 288         u_int32_t pllconfig;
 289         char *nxt;
 290
 291         if (resource_string_value("hifn", device_get_unit(dev),
 292             "pllconfig", &pllspec))
 293                 pllspec = "pci66";
 294         fl = 33, fh = 66;
 295         pllconfig = 0;
 296         if (strncmp(pllspec, "ext", 3) == 0) {
 297                 pllspec += 3;
 298                 pllconfig |= HIFN_PLL_REF_SEL;
 299                 switch (pci_get_device(dev)) {
 300                 case PCI_PRODUCT_HIFN_7955:
 301                 case PCI_PRODUCT_HIFN_7956:
 302                         fl = 20, fh = 100;
 303                         break;
 304 #ifdef notyet
 305                 case PCI_PRODUCT_HIFN_7954:
 306                         fl = 20, fh = 66;
 307                         break;
 308 #endif
 309                 }
 310         } else if (strncmp(pllspec, "pci", 3) == 0)
 311                 pllspec += 3;
 312         freq = strtoul(pllspec, &nxt, 10);
 313         if (nxt == pllspec)
 314                 freq = 66;
 315         else
 316                 freq = checkmaxmin(dev, "frequency", freq, fl, fh);
 317         /*
 318          * Calculate multiplier.  We target a Fck of 266 MHz,
 319          * allowing only even values, possibly rounded down.
 320          * Multipliers > 8 must set the charge pump current.
 321          */
 322         mul = checkmaxmin(dev, "PLL divisor", (266 / freq) &~ 1, 2, 12);
 323         pllconfig |= (mul / 2 - 1) << HIFN_PLL_ND_SHIFT;
 324         if (mul > 8)
 325                 pllconfig |= HIFN_PLL_IS;
 326         *pll = pllconfig;
 327 }
 328
 329 /*
 330  * Attach an interface that successfully probed.
 331  */
 332 static int
 333 hifn_attach(device_t dev)
 334 {
 335         struct hifn_softc *sc = device_get_softc(dev);
 336         u_int32_t cmd;
 337         caddr_t kva;
 338         int rseg, rid;
 339         char rbase;
 340         u_int16_t ena, rev;
 341
 342         KASSERT(sc != NULL, ("hifn_attach: null software carrier!"));
 343         bzero(sc, sizeof (*sc));
 344         sc->sc_dev = dev;
 345
 346         mtx_init(&sc->sc_mtx, device_get_nameunit(dev), "hifn driver", MTX_DEF);
 347
 348         /* XXX handle power management */
 349
 350         /*
 351          * The 7951 and 795x have a random number generator and
 352          * public key support; note this.
 353          */
 354         if (pci_get_vendor(dev) == PCI_VENDOR_HIFN &&
 355             (pci_get_device(dev) == PCI_PRODUCT_HIFN_7951 ||
 356              pci_get_device(dev) == PCI_PRODUCT_HIFN_7955 ||
 357              pci_get_device(dev) == PCI_PRODUCT_HIFN_7956))
 358                 sc->sc_flags = HIFN_HAS_RNG | HIFN_HAS_PUBLIC;
 359         /*
 360          * The 7811 has a random number generator and
 361          * we also note it's identity 'cuz of some quirks.
 362          */
 363         if (pci_get_vendor(dev) == PCI_VENDOR_HIFN &&
 364             pci_get_device(dev) == PCI_PRODUCT_HIFN_7811)
 365                 sc->sc_flags |= HIFN_IS_7811 | HIFN_HAS_RNG;
 366
 367         /*
 368          * The 795x parts support AES.
 369          */
 370         if (pci_get_vendor(dev) == PCI_VENDOR_HIFN &&
 371             (pci_get_device(dev) == PCI_PRODUCT_HIFN_7955 ||
 372              pci_get_device(dev) == PCI_PRODUCT_HIFN_7956)) {
 373                 sc->sc_flags |= HIFN_IS_7956 | HIFN_HAS_AES;
 374                 /*
 375                  * Select PLL configuration.  This depends on the
 376                  * bus and board design and must be manually configured
 377                  * if the default setting is unacceptable.
 378                  */
 379                 hifn_getpllconfig(dev, &sc->sc_pllconfig);
 380         }
 381
 382         /*
 383          * Configure support for memory-mapped access to
 384          * registers and for DMA operations.
 385          */
 386 #define PCIM_ENA        (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN)
 387         cmd = pci_read_config(dev, PCIR_COMMAND, 4);
 388         cmd |= PCIM_ENA;
 389         pci_write_config(dev, PCIR_COMMAND, cmd, 4);
 390         cmd = pci_read_config(dev, PCIR_COMMAND, 4);
 391         if ((cmd & PCIM_ENA) != PCIM_ENA) {
 392                 device_printf(dev, "failed to enable %s\n",
 393                         (cmd & PCIM_ENA) == 0 ?
 394                                 "memory mapping & bus mastering" :
 395                         (cmd & PCIM_CMD_MEMEN) == 0 ?
 396                                 "memory mapping" : "bus mastering");
 397                 goto fail_pci;
 398         }
 399 #undef PCIM_ENA
 400
 401         /*
 402          * Setup PCI resources. Note that we record the bus
 403          * tag and handle for each register mapping, this is
 404          * used by the READ_REG_0, WRITE_REG_0, READ_REG_1,
 405          * and WRITE_REG_1 macros throughout the driver.
 406          */
 407         rid = HIFN_BAR0;
 408         sc->sc_bar0res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
 409                                                 RF_ACTIVE);
 410         if (sc->sc_bar0res == NULL) {
 411                 device_printf(dev, "cannot map bar%d register space\n", 0);
 412                 goto fail_pci;
 413         }
 414         sc->sc_st0 = rman_get_bustag(sc->sc_bar0res);
 415         sc->sc_sh0 = rman_get_bushandle(sc->sc_bar0res);
 416         sc->sc_bar0_lastreg = (bus_size_t) -1;
 417
 418         rid = HIFN_BAR1;
 419         sc->sc_bar1res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
 420                                                 RF_ACTIVE);
 421         if (sc->sc_bar1res == NULL) {
 422                 device_printf(dev, "cannot map bar%d register space\n", 1);
 423                 goto fail_io0;
 424         }
 425         sc->sc_st1 = rman_get_bustag(sc->sc_bar1res);
 426         sc->sc_sh1 = rman_get_bushandle(sc->sc_bar1res);
 427         sc->sc_bar1_lastreg = (bus_size_t) -1;
 428
 429         hifn_set_retry(sc);
 430
 431         /*
 432          * Setup the area where the Hifn DMA's descriptors
 433          * and associated data structures.
 434          */
 435         if (bus_dma_tag_create(NULL,                    /* parent */
 436                                1, 0,                    /* alignment,boundary */
 437                                BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
 438                                BUS_SPACE_MAXADDR,       /* highaddr */
 439                                NULL, NULL,              /* filter, filterarg */
 440                                HIFN_MAX_DMALEN,         /* maxsize */
 441                                MAX_SCATTER,             /* nsegments */
 442                                HIFN_MAX_SEGLEN,         /* maxsegsize */
 443                                BUS_DMA_ALLOCNOW,        /* flags */
 444                                NULL,                    /* lockfunc */
 445                                NULL,                    /* lockarg */
 446                                &sc->sc_dmat)) {
 447                 device_printf(dev, "cannot allocate DMA tag\n");
 448                 goto fail_io1;
 449         }
 450         if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, &sc->sc_dmamap)) {
 451                 device_printf(dev, "cannot create dma map\n");
 452                 bus_dma_tag_destroy(sc->sc_dmat);
 453                 goto fail_io1;
 454         }
 455         if (bus_dmamem_alloc(sc->sc_dmat, (void**) &kva, BUS_DMA_NOWAIT, &sc->sc_dmamap)) {
 456                 device_printf(dev, "cannot alloc dma buffer\n");
 457                 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap);
 458                 bus_dma_tag_destroy(sc->sc_dmat);
 459                 goto fail_io1;
 460         }
 461         if (bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, kva,
 462                              sizeof (*sc->sc_dma),
 463                              hifn_dmamap_cb, &sc->sc_dma_physaddr,
 464                              BUS_DMA_NOWAIT)) {
 465                 device_printf(dev, "cannot load dma map\n");
 466                 bus_dmamem_free(sc->sc_dmat, kva, sc->sc_dmamap);
 467                 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap);
 468                 bus_dma_tag_destroy(sc->sc_dmat);
 469                 goto fail_io1;
 470         }
 471         sc->sc_dma = (struct hifn_dma *)kva;
 472         bzero(sc->sc_dma, sizeof(*sc->sc_dma));
 473
 474         KASSERT(sc->sc_st0 != 0, ("hifn_attach: null bar0 tag!"));
 475         KASSERT(sc->sc_sh0 != 0, ("hifn_attach: null bar0 handle!"));
 476         KASSERT(sc->sc_st1 != 0, ("hifn_attach: null bar1 tag!"));
 477         KASSERT(sc->sc_sh1 != 0, ("hifn_attach: null bar1 handle!"));
 478
 479         /*
 480          * Reset the board and do the ``secret handshake''
 481          * to enable the crypto support.  Then complete the
 482          * initialization procedure by setting up the interrupt
 483          * and hooking in to the system crypto support so we'll
 484          * get used for system services like the crypto device,
 485          * IPsec, RNG device, etc.
 486          */
 487         hifn_reset_board(sc, 0);
 488
 489         if (hifn_enable_crypto(sc) != 0) {
 490                 device_printf(dev, "crypto enabling failed\n");
 491                 goto fail_mem;
 492         }
 493         hifn_reset_puc(sc);
 494
 495         hifn_init_dma(sc);
 496         hifn_init_pci_registers(sc);
 497
 498         /* XXX can't dynamically determine ram type for 795x; force dram */
 499         if (sc->sc_flags & HIFN_IS_7956)
 500                 sc->sc_drammodel = 1;
 501         else if (hifn_ramtype(sc))
 502                 goto fail_mem;
 503
 504         if (sc->sc_drammodel == 0)
 505                 hifn_sramsize(sc);
 506         else
 507                 hifn_dramsize(sc);
 508
 509         /*
 510          * Workaround for NetSec 7751 rev A: half ram size because two
 511          * of the address lines were left floating
 512          */
 513         if (pci_get_vendor(dev) == PCI_VENDOR_NETSEC &&
 514             pci_get_device(dev) == PCI_PRODUCT_NETSEC_7751 &&
 515             pci_get_revid(dev) == 0x61) /*XXX???*/
 516                 sc->sc_ramsize >>= 1;
 517
 518         /*
 519          * Arrange the interrupt line.
 520          */
 521         rid = 0;
 522         sc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
 523                                             RF_SHAREABLE|RF_ACTIVE);
 524         if (sc->sc_irq == NULL) {
 525                 device_printf(dev, "could not map interrupt\n");
 526                 goto fail_mem;
 527         }
 528         /*
 529          * NB: Network code assumes we are blocked with splimp()
 530          *     so make sure the IRQ is marked appropriately.
 531          */
 532         if (bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_NET | INTR_MPSAFE,
 533                            hifn_intr, sc, &sc->sc_intrhand)) {
 534                 device_printf(dev, "could not setup interrupt\n");
 535                 goto fail_intr2;
 536         }
 537
 538         hifn_sessions(sc);
 539
 540         /*
 541          * NB: Keep only the low 16 bits; this masks the chip id
 542          *     from the 7951.
 543          */
 544         rev = READ_REG_1(sc, HIFN_1_REVID) & 0xffff;
 545
 546         rseg = sc->sc_ramsize / 1024;
 547         rbase = 'K';
 548         if (sc->sc_ramsize >= (1024 * 1024)) {
 549                 rbase = 'M';
 550                 rseg /= 1024;
 551         }
 552         device_printf(sc->sc_dev, "%s, rev %u, %d%cB %cram",
 553                 hifn_partname(sc), rev,
 554                 rseg, rbase, sc->sc_drammodel ? 'd' : 's');
 555         if (sc->sc_flags & HIFN_IS_7956)
 556                 printf(", pll=0x%x<%s clk, %ux mult>",
 557                         sc->sc_pllconfig,
 558                         sc->sc_pllconfig & HIFN_PLL_REF_SEL ? "ext" : "pci",
 559                         2 + 2*((sc->sc_pllconfig & HIFN_PLL_ND) >> 11));
 560         printf("\n");
 561
 562         sc->sc_cid = crypto_get_driverid(0);
 563         if (sc->sc_cid < 0) {
 564                 device_printf(dev, "could not get crypto driver id\n");
 565                 goto fail_intr;
 566         }
 567
 568         WRITE_REG_0(sc, HIFN_0_PUCNFG,
 569             READ_REG_0(sc, HIFN_0_PUCNFG) | HIFN_PUCNFG_CHIPID);
 570         ena = READ_REG_0(sc, HIFN_0_PUSTAT) & HIFN_PUSTAT_CHIPENA;
 571
 572         switch (ena) {
 573         case HIFN_PUSTAT_ENA_2:
 574                 crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0,
 575                     hifn_newsession, hifn_freesession, hifn_process, sc);
 576                 crypto_register(sc->sc_cid, CRYPTO_ARC4, 0, 0,
 577                     hifn_newsession, hifn_freesession, hifn_process, sc);
 578                 if (sc->sc_flags & HIFN_HAS_AES)
 579                         crypto_register(sc->sc_cid, CRYPTO_AES_CBC,  0, 0,
 580                                 hifn_newsession, hifn_freesession,
 581                                 hifn_process, sc);
 582                 /*FALLTHROUGH*/
 583         case HIFN_PUSTAT_ENA_1:
 584                 crypto_register(sc->sc_cid, CRYPTO_MD5, 0, 0,
 585                     hifn_newsession, hifn_freesession, hifn_process, sc);
 586                 crypto_register(sc->sc_cid, CRYPTO_SHA1, 0, 0,
 587                     hifn_newsession, hifn_freesession, hifn_process, sc);
 588                 crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0,
 589                     hifn_newsession, hifn_freesession, hifn_process, sc);
 590                 crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0,
 591                     hifn_newsession, hifn_freesession, hifn_process, sc);
 592                 crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0,
 593                     hifn_newsession, hifn_freesession, hifn_process, sc);
 594                 break;
 595         }
 596
 597         bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap,
 598             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
 599
 600         if (sc->sc_flags & (HIFN_HAS_PUBLIC | HIFN_HAS_RNG))
 601                 hifn_init_pubrng(sc);
 602
 603         callout_init(&sc->sc_tickto, CALLOUT_MPSAFE);
 604         callout_reset(&sc->sc_tickto, hz, hifn_tick, sc);
 605
 606         return (0);
 607
 608 fail_intr:
 609         bus_teardown_intr(dev, sc->sc_irq, sc->sc_intrhand);
 610 fail_intr2:
 611         /* XXX don't store rid */
 612         bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq);
 613 fail_mem:
 614         bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap);
 615         bus_dmamem_free(sc->sc_dmat, sc->sc_dma, sc->sc_dmamap);
 616         bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap);
 617         bus_dma_tag_destroy(sc->sc_dmat);
 618
 619         /* Turn off DMA polling */
 620         WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET |
 621             HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE);
 622 fail_io1:
 623         bus_release_resource(dev, SYS_RES_MEMORY, HIFN_BAR1, sc->sc_bar1res);
 624 fail_io0:
 625         bus_release_resource(dev, SYS_RES_MEMORY, HIFN_BAR0, sc->sc_bar0res);
 626 fail_pci:
 627         mtx_destroy(&sc->sc_mtx);
 628         return (ENXIO);
 629 }
 630
 631 /*
 632  * Detach an interface that successfully probed.
 633  */
 634 static int
 635 hifn_detach(device_t dev)
 636 {
 637         struct hifn_softc *sc = device_get_softc(dev);
 638
 639         KASSERT(sc != NULL, ("hifn_detach: null software carrier!"));
 640
 641         /* disable interrupts */
 642         WRITE_REG_1(sc, HIFN_1_DMA_IER, 0);
 643
 644         /*XXX other resources */
 645         callout_stop(&sc->sc_tickto);
 646         callout_stop(&sc->sc_rngto);
 647 #ifdef HIFN_RNDTEST
 648         if (sc->sc_rndtest)
 649                 rndtest_detach(sc->sc_rndtest);
 650 #endif
 651
 652         /* Turn off DMA polling */
 653         WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET |
 654             HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE);
 655
 656         crypto_unregister_all(sc->sc_cid);
 657
 658         bus_generic_detach(dev);        /*XXX should be no children, right? */
 659
 660         bus_teardown_intr(dev, sc->sc_irq, sc->sc_intrhand);
 661         /* XXX don't store rid */
 662         bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq);
 663
 664         bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap);
 665         bus_dmamem_free(sc->sc_dmat, sc->sc_dma, sc->sc_dmamap);
 666         bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap);
 667         bus_dma_tag_destroy(sc->sc_dmat);
 668
 669         bus_release_resource(dev, SYS_RES_MEMORY, HIFN_BAR1, sc->sc_bar1res);
 670         bus_release_resource(dev, SYS_RES_MEMORY, HIFN_BAR0, sc->sc_bar0res);
 671
 672         mtx_destroy(&sc->sc_mtx);
 673
 674         return (0);
 675 }
 676
 677 /*
 678  * Stop all chip I/O so that the kernel's probe routines don't
 679  * get confused by errant DMAs when rebooting.
 680  */
 681 static void
 682 hifn_shutdown(device_t dev)
 683 {
 684 #ifdef notyet
 685         hifn_stop(device_get_softc(dev));
 686 #endif
 687 }
 688
 689 /*
 690  * Device suspend routine.  Stop the interface and save some PCI
 691  * settings in case the BIOS doesn't restore them properly on
 692  * resume.
 693  */
 694 static int
 695 hifn_suspend(device_t dev)
 696 {
 697         struct hifn_softc *sc = device_get_softc(dev);
 698 #ifdef notyet
 699         hifn_stop(sc);
 700 #endif
 701         sc->sc_suspended = 1;
 702
 703         return (0);
 704 }
 705
 706 /*
 707  * Device resume routine.  Restore some PCI settings in case the BIOS
 708  * doesn't, re-enable busmastering, and restart the interface if
 709  * appropriate.
 710  */
 711 static int
 712 hifn_resume(device_t dev)
 713 {
 714         struct hifn_softc *sc = device_get_softc(dev);
 715 #ifdef notyet
 716         /* reenable busmastering */
 717         pci_enable_busmaster(dev);
 718         pci_enable_io(dev, HIFN_RES);
 719
 720         /* reinitialize interface if necessary */
 721         if (ifp->if_flags & IFF_UP)
 722                 rl_init(sc);
 723 #endif
 724         sc->sc_suspended = 0;
 725
 726         return (0);
 727 }
 728
 729 static int
 730 hifn_init_pubrng(struct hifn_softc *sc)
 731 {
 732         u_int32_t r;
 733         int i;
 734
 735 #ifdef HIFN_RNDTEST
 736         sc->sc_rndtest = rndtest_attach(sc->sc_dev);
 737         if (sc->sc_rndtest)
 738                 sc->sc_harvest = rndtest_harvest;
 739         else
 740                 sc->sc_harvest = default_harvest;
 741 #else
 742         sc->sc_harvest = default_harvest;
 743 #endif
 744         if ((sc->sc_flags & HIFN_IS_7811) == 0) {
 745                 /* Reset 7951 public key/rng engine */
 746                 WRITE_REG_1(sc, HIFN_1_PUB_RESET,
 747                     READ_REG_1(sc, HIFN_1_PUB_RESET) | HIFN_PUBRST_RESET);
 748
 749                 for (i = 0; i < 100; i++) {
 750                         DELAY(1000);
 751                         if ((READ_REG_1(sc, HIFN_1_PUB_RESET) &
 752                             HIFN_PUBRST_RESET) == 0)
 753                                 break;
 754                 }
 755
 756                 if (i == 100) {
 757                         device_printf(sc->sc_dev, "public key init failed\n");
 758                         return (1);
 759                 }
 760         }
 761
 762         /* Enable the rng, if available */
 763         if (sc->sc_flags & HIFN_HAS_RNG) {
 764                 if (sc->sc_flags & HIFN_IS_7811) {
 765                         r = READ_REG_1(sc, HIFN_1_7811_RNGENA);
 766                         if (r & HIFN_7811_RNGENA_ENA) {
 767                                 r &= ~HIFN_7811_RNGENA_ENA;
 768                                 WRITE_REG_1(sc, HIFN_1_7811_RNGENA, r);
 769                         }
 770                         WRITE_REG_1(sc, HIFN_1_7811_RNGCFG,
 771                             HIFN_7811_RNGCFG_DEFL);
 772                         r |= HIFN_7811_RNGENA_ENA;
 773                         WRITE_REG_1(sc, HIFN_1_7811_RNGENA, r);
 774                 } else
 775                         WRITE_REG_1(sc, HIFN_1_RNG_CONFIG,
 776                             READ_REG_1(sc, HIFN_1_RNG_CONFIG) |
 777                             HIFN_RNGCFG_ENA);
 778
 779                 sc->sc_rngfirst = 1;
 780                 if (hz >= 100)
 781                         sc->sc_rnghz = hz / 100;
 782                 else
 783                         sc->sc_rnghz = 1;
 784                 callout_init(&sc->sc_rngto, CALLOUT_MPSAFE);
 785                 callout_reset(&sc->sc_rngto, sc->sc_rnghz, hifn_rng, sc);
 786         }
 787
 788         /* Enable public key engine, if available */
 789         if (sc->sc_flags & HIFN_HAS_PUBLIC) {
 790                 WRITE_REG_1(sc, HIFN_1_PUB_IEN, HIFN_PUBIEN_DONE);
 791                 sc->sc_dmaier |= HIFN_DMAIER_PUBDONE;
 792                 WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier);
 793         }
 794
 795         return (0);
 796 }
 797
 798 static void
 799 hifn_rng(void *vsc)
 800 {
 801 #define RANDOM_BITS(n)  (n)*sizeof (u_int32_t), (n)*sizeof (u_int32_t)*NBBY, 0
 802         struct hifn_softc *sc = vsc;
 803         u_int32_t sts, num[2];
 804         int i;
 805
 806         if (sc->sc_flags & HIFN_IS_7811) {
 807                 for (i = 0; i < 5; i++) {
 808                         sts = READ_REG_1(sc, HIFN_1_7811_RNGSTS);
 809                         if (sts & HIFN_7811_RNGSTS_UFL) {
 810                                 device_printf(sc->sc_dev,
 811                                               "RNG underflow: disabling\n");
 812                                 return;
 813                         }
 814                         if ((sts & HIFN_7811_RNGSTS_RDY) == 0)
 815                                 break;
 816
 817                         /*
 818                          * There are at least two words in the RNG FIFO
 819                          * at this point.
 820                          */
 821                         num[0] = READ_REG_1(sc, HIFN_1_7811_RNGDAT);
 822                         num[1] = READ_REG_1(sc, HIFN_1_7811_RNGDAT);
 823                         /* NB: discard first data read */
 824                         if (sc->sc_rngfirst)
 825                                 sc->sc_rngfirst = 0;
 826                         else
 827                                 (*sc->sc_harvest)(sc->sc_rndtest,
 828                                         num, sizeof (num));
 829                 }
 830         } else {
 831                 num[0] = READ_REG_1(sc, HIFN_1_RNG_DATA);
 832
 833                 /* NB: discard first data read */
 834                 if (sc->sc_rngfirst)
 835                         sc->sc_rngfirst = 0;
 836                 else
 837                         (*sc->sc_harvest)(sc->sc_rndtest,
 838                                 num, sizeof (num[0]));
 839         }
 840
 841         callout_reset(&sc->sc_rngto, sc->sc_rnghz, hifn_rng, sc);
 842 #undef RANDOM_BITS
 843 }
 844
 845 static void
 846 hifn_puc_wait(struct hifn_softc *sc)
 847 {
 848         int i;
 849
 850         for (i = 5000; i > 0; i--) {
 851                 DELAY(1);
 852                 if (!(READ_REG_0(sc, HIFN_0_PUCTRL) & HIFN_PUCTRL_RESET))
 853                         break;
 854         }
 855         if (!i)
 856                 device_printf(sc->sc_dev, "proc unit did not reset\n");
 857 }
 858
 859 /*
 860  * Reset the processing unit.
 861  */
 862 static void
 863 hifn_reset_puc(struct hifn_softc *sc)
 864 {
 865         /* Reset processing unit */
 866         WRITE_REG_0(sc, HIFN_0_PUCTRL, HIFN_PUCTRL_DMAENA);
 867         hifn_puc_wait(sc);
 868 }
 869
 870 /*
 871  * Set the Retry and TRDY registers; note that we set them to
 872  * zero because the 7811 locks up when forced to retry (section
 873  * 3.6 of "Specification Update SU-0014-04".  Not clear if we
 874  * should do this for all Hifn parts, but it doesn't seem to hurt.
 875  */
 876 static void
 877 hifn_set_retry(struct hifn_softc *sc)
 878 {
 879         /* NB: RETRY only responds to 8-bit reads/writes */
 880         pci_write_config(sc->sc_dev, HIFN_RETRY_TIMEOUT, 0, 1);
 881         pci_write_config(sc->sc_dev, HIFN_TRDY_TIMEOUT, 0, 4);
 882 }
 883
 884 /*
 885  * Resets the board.  Values in the regesters are left as is
 886  * from the reset (i.e. initial values are assigned elsewhere).
 887  */
 888 static void
 889 hifn_reset_board(struct hifn_softc *sc, int full)
 890 {
 891         u_int32_t reg;
 892
 893         /*
 894          * Set polling in the DMA configuration register to zero.  0x7 avoids
 895          * resetting the board and zeros out the other fields.
 896          */
 897         WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET |
 898             HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE);
 899
 900         /*
 901          * Now that polling has been disabled, we have to wait 1 ms
 902          * before resetting the board.
 903          */
 904         DELAY(1000);
 905
 906         /* Reset the DMA unit */
 907         if (full) {
 908                 WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MODE);
 909                 DELAY(1000);
 910         } else {
 911                 WRITE_REG_1(sc, HIFN_1_DMA_CNFG,
 912                     HIFN_DMACNFG_MODE | HIFN_DMACNFG_MSTRESET);
 913                 hifn_reset_puc(sc);
 914         }
 915
 916         KASSERT(sc->sc_dma != NULL, ("hifn_reset_board: null DMA tag!"));
 917         bzero(sc->sc_dma, sizeof(*sc->sc_dma));
 918
 919         /* Bring dma unit out of reset */
 920         WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET |
 921             HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE);
 922
 923         hifn_puc_wait(sc);
 924         hifn_set_retry(sc);
 925
 926         if (sc->sc_flags & HIFN_IS_7811) {
 927                 for (reg = 0; reg < 1000; reg++) {
 928                         if (READ_REG_1(sc, HIFN_1_7811_MIPSRST) &
 929                             HIFN_MIPSRST_CRAMINIT)
 930                                 break;
 931                         DELAY(1000);
 932                 }
 933                 if (reg == 1000)
 934                         printf(": cram init timeout\n");
 935         }
 936 }
 937
 938 static u_int32_t
 939 hifn_next_signature(u_int32_t a, u_int cnt)
 940 {
 941         int i;
 942         u_int32_t v;
 943
 944         for (i = 0; i < cnt; i++) {
 945
 946                 /* get the parity */
 947                 v = a & 0x80080125;
 948                 v ^= v >> 16;
 949                 v ^= v >> 8;
 950                 v ^= v >> 4;
 951                 v ^= v >> 2;
 952                 v ^= v >> 1;
 953
 954                 a = (v & 1) ^ (a << 1);
 955         }
 956
 957         return a;
 958 }
 959
 960 struct pci2id {
 961         u_short         pci_vendor;
 962         u_short         pci_prod;
 963         char            card_id[13];
 964 };
 965 static struct pci2id pci2id[] = {
 966         {
 967                 PCI_VENDOR_HIFN,
 968                 PCI_PRODUCT_HIFN_7951,
 969                 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 970                   0x00, 0x00, 0x00, 0x00, 0x00 }
 971         }, {
 972                 PCI_VENDOR_HIFN,
 973                 PCI_PRODUCT_HIFN_7955,
 974                 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 975                   0x00, 0x00, 0x00, 0x00, 0x00 }
 976         }, {
 977                 PCI_VENDOR_HIFN,
 978                 PCI_PRODUCT_HIFN_7956,
 979                 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 980                   0x00, 0x00, 0x00, 0x00, 0x00 }
 981         }, {
 982                 PCI_VENDOR_NETSEC,
 983                 PCI_PRODUCT_NETSEC_7751,
 984                 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 985                   0x00, 0x00, 0x00, 0x00, 0x00 }
 986         }, {
 987                 PCI_VENDOR_INVERTEX,
 988                 PCI_PRODUCT_INVERTEX_AEON,
 989                 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 990                   0x00, 0x00, 0x00, 0x00, 0x00 }
 991         }, {
 992                 PCI_VENDOR_HIFN,
 993                 PCI_PRODUCT_HIFN_7811,
 994                 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 995                   0x00, 0x00, 0x00, 0x00, 0x00 }
 996         }, {
 997                 /*
 998                  * Other vendors share this PCI ID as well, such as
 999                  * http://www.powercrypt.com, and obviously they also
1000                  * use the same key.
1001                  */
1002                 PCI_VENDOR_HIFN,
1003                 PCI_PRODUCT_HIFN_7751,
1004                 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1005                   0x00, 0x00, 0x00, 0x00, 0x00 }
1006         },
1007 };
1008
1009 /*
1010  * Checks to see if crypto is already enabled.  If crypto isn't enable,
1011  * "hifn_enable_crypto" is called to enable it.  The check is important,
1012  * as enabling crypto twice will lock the board.
1013  */
1014 static int
1015 hifn_enable_crypto(struct hifn_softc *sc)
1016 {
1017         u_int32_t dmacfg, ramcfg, encl, addr, i;
1018         char *offtbl = NULL;
1019
1020         for (i = 0; i < sizeof(pci2id)/sizeof(pci2id[0]); i++) {
1021                 if (pci2id[i].pci_vendor == pci_get_vendor(sc->sc_dev) &&
1022                     pci2id[i].pci_prod == pci_get_device(sc->sc_dev)) {
1023                         offtbl = pci2id[i].card_id;
1024                         break;
1025                 }
1026         }
1027         if (offtbl == NULL) {
1028                 device_printf(sc->sc_dev, "Unknown card!\n");
1029                 return (1);
1030         }
1031
1032         ramcfg = READ_REG_0(sc, HIFN_0_PUCNFG);
1033         dmacfg = READ_REG_1(sc, HIFN_1_DMA_CNFG);
1034
1035         /*
1036          * The RAM config register's encrypt level bit needs to be set before
1037          * every read performed on the encryption level register.
1038          */
1039         WRITE_REG_0(sc, HIFN_0_PUCNFG, ramcfg | HIFN_PUCNFG_CHIPID);
1040
1041         encl = READ_REG_0(sc, HIFN_0_PUSTAT) & HIFN_PUSTAT_CHIPENA;
1042
1043         /*
1044          * Make sure we don't re-unlock.  Two unlocks kills chip until the
1045          * next reboot.
1046          */
1047         if (encl == HIFN_PUSTAT_ENA_1 || encl == HIFN_PUSTAT_ENA_2) {
1048 #ifdef HIFN_DEBUG
1049                 if (hifn_debug)
1050                         device_printf(sc->sc_dev,
1051                             "Strong crypto already enabled!\n");
1052 #endif
1053                 goto report;
1054         }
1055
1056         if (encl != 0 && encl != HIFN_PUSTAT_ENA_0) {
1057 #ifdef HIFN_DEBUG
1058                 if (hifn_debug)
1059                         device_printf(sc->sc_dev,
1060                               "Unknown encryption level 0x%x\n", encl);
1061 #endif
1062                 return 1;
1063         }
1064
1065         WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_UNLOCK |
1066             HIFN_DMACNFG_MSTRESET | HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE);
1067         DELAY(1000);
1068         addr = READ_REG_1(sc, HIFN_UNLOCK_SECRET1);
1069         DELAY(1000);
1070         WRITE_REG_1(sc, HIFN_UNLOCK_SECRET2, 0);
1071         DELAY(1000);
1072
1073         for (i = 0; i <= 12; i++) {
1074                 addr = hifn_next_signature(addr, offtbl[i] + 0x101);
1075                 WRITE_REG_1(sc, HIFN_UNLOCK_SECRET2, addr);
1076
1077                 DELAY(1000);
1078         }
1079
1080         WRITE_REG_0(sc, HIFN_0_PUCNFG, ramcfg | HIFN_PUCNFG_CHIPID);
1081         encl = READ_REG_0(sc, HIFN_0_PUSTAT) & HIFN_PUSTAT_CHIPENA;
1082
1083 #ifdef HIFN_DEBUG
1084         if (hifn_debug) {
1085                 if (encl != HIFN_PUSTAT_ENA_1 && encl != HIFN_PUSTAT_ENA_2)
1086                         device_printf(sc->sc_dev, "Engine is permanently "
1087                                 "locked until next system reset!\n");
1088                 else
1089                         device_printf(sc->sc_dev, "Engine enabled "
1090                                 "successfully!\n");
1091         }
1092 #endif
1093
1094 report:
1095         WRITE_REG_0(sc, HIFN_0_PUCNFG, ramcfg);
1096         WRITE_REG_1(sc, HIFN_1_DMA_CNFG, dmacfg);
1097
1098         switch (encl) {
1099         case HIFN_PUSTAT_ENA_1:
1100         case HIFN_PUSTAT_ENA_2:
1101                 break;
1102         case HIFN_PUSTAT_ENA_0:
1103         default:
1104                 device_printf(sc->sc_dev, "disabled");
1105                 break;
1106         }
1107
1108         return 0;
1109 }
1110
1111 /*
1112  * Give initial values to the registers listed in the "Register Space"
1113  * section of the HIFN Software Development reference manual.
1114  */
1115 static void
1116 hifn_init_pci_registers(struct hifn_softc *sc)
1117 {
1118         /* write fixed values needed by the Initialization registers */
1119         WRITE_REG_0(sc, HIFN_0_PUCTRL, HIFN_PUCTRL_DMAENA);
1120         WRITE_REG_0(sc, HIFN_0_FIFOCNFG, HIFN_FIFOCNFG_THRESHOLD);
1121         WRITE_REG_0(sc, HIFN_0_PUIER, HIFN_PUIER_DSTOVER);
1122
1123         /* write all 4 ring address registers */
1124         WRITE_REG_1(sc, HIFN_1_DMA_CRAR, sc->sc_dma_physaddr +
1125             offsetof(struct hifn_dma, cmdr[0]));
1126         WRITE_REG_1(sc, HIFN_1_DMA_SRAR, sc->sc_dma_physaddr +
1127             offsetof(struct hifn_dma, srcr[0]));
1128         WRITE_REG_1(sc, HIFN_1_DMA_DRAR, sc->sc_dma_physaddr +
1129             offsetof(struct hifn_dma, dstr[0]));
1130         WRITE_REG_1(sc, HIFN_1_DMA_RRAR, sc->sc_dma_physaddr +
1131             offsetof(struct hifn_dma, resr[0]));
1132
1133         DELAY(2000);
1134
1135         /* write status register */
1136         WRITE_REG_1(sc, HIFN_1_DMA_CSR,
1137             HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS |
1138             HIFN_DMACSR_S_CTRL_DIS | HIFN_DMACSR_C_CTRL_DIS |
1139             HIFN_DMACSR_D_ABORT | HIFN_DMACSR_D_DONE | HIFN_DMACSR_D_LAST |
1140             HIFN_DMACSR_D_WAIT | HIFN_DMACSR_D_OVER |
1141             HIFN_DMACSR_R_ABORT | HIFN_DMACSR_R_DONE | HIFN_DMACSR_R_LAST |
1142             HIFN_DMACSR_R_WAIT | HIFN_DMACSR_R_OVER |
1143             HIFN_DMACSR_S_ABORT | HIFN_DMACSR_S_DONE | HIFN_DMACSR_S_LAST |
1144             HIFN_DMACSR_S_WAIT |
1145             HIFN_DMACSR_C_ABORT | HIFN_DMACSR_C_DONE | HIFN_DMACSR_C_LAST |
1146             HIFN_DMACSR_C_WAIT |
1147             HIFN_DMACSR_ENGINE |
1148             ((sc->sc_flags & HIFN_HAS_PUBLIC) ?
1149                 HIFN_DMACSR_PUBDONE : 0) |
1150             ((sc->sc_flags & HIFN_IS_7811) ?
1151                 HIFN_DMACSR_ILLW | HIFN_DMACSR_ILLR : 0));
1152
1153         sc->sc_d_busy = sc->sc_r_busy = sc->sc_s_busy = sc->sc_c_busy = 0;
1154         sc->sc_dmaier |= HIFN_DMAIER_R_DONE | HIFN_DMAIER_C_ABORT |
1155             HIFN_DMAIER_D_OVER | HIFN_DMAIER_R_OVER |
1156             HIFN_DMAIER_S_ABORT | HIFN_DMAIER_D_ABORT | HIFN_DMAIER_R_ABORT |
1157             ((sc->sc_flags & HIFN_IS_7811) ?
1158                 HIFN_DMAIER_ILLW | HIFN_DMAIER_ILLR : 0);
1159         sc->sc_dmaier &= ~HIFN_DMAIER_C_WAIT;
1160         WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier);
1161
1162
1163         if (sc->sc_flags & HIFN_IS_7956) {
1164                 u_int32_t pll;
1165
1166                 WRITE_REG_0(sc, HIFN_0_PUCNFG, HIFN_PUCNFG_COMPSING |
1167                     HIFN_PUCNFG_TCALLPHASES |
1168                     HIFN_PUCNFG_TCDRVTOTEM | HIFN_PUCNFG_BUS32);
1169
1170                 /* turn off the clocks and insure bypass is set */
1171                 pll = READ_REG_1(sc, HIFN_1_PLL);
1172                 pll = (pll &~ (HIFN_PLL_PK_CLK_SEL | HIFN_PLL_PE_CLK_SEL))
1173                     | HIFN_PLL_BP;
1174                 WRITE_REG_1(sc, HIFN_1_PLL, pll);
1175                 DELAY(10*1000);         /* 10ms */
1176                 /* change configuration */
1177                 pll = (pll &~ HIFN_PLL_CONFIG) | sc->sc_pllconfig;
1178                 WRITE_REG_1(sc, HIFN_1_PLL, pll);
1179                 DELAY(10*1000);         /* 10ms */
1180                 /* disable bypass */
1181                 pll &= ~HIFN_PLL_BP;
1182                 WRITE_REG_1(sc, HIFN_1_PLL, pll);
1183                 /* enable clocks with new configuration */
1184                 pll |= HIFN_PLL_PK_CLK_SEL | HIFN_PLL_PE_CLK_SEL;
1185                 WRITE_REG_1(sc, HIFN_1_PLL, pll);
1186         } else {
1187                 WRITE_REG_0(sc, HIFN_0_PUCNFG, HIFN_PUCNFG_COMPSING |
1188                     HIFN_PUCNFG_DRFR_128 | HIFN_PUCNFG_TCALLPHASES |
1189                     HIFN_PUCNFG_TCDRVTOTEM | HIFN_PUCNFG_BUS32 |
1190                     (sc->sc_drammodel ? HIFN_PUCNFG_DRAM : HIFN_PUCNFG_SRAM));
1191         }
1192
1193         WRITE_REG_0(sc, HIFN_0_PUISR, HIFN_PUISR_DSTOVER);
1194         WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET |
1195             HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE | HIFN_DMACNFG_LAST |
1196             ((HIFN_POLL_FREQUENCY << 16 ) & HIFN_DMACNFG_POLLFREQ) |
1197             ((HIFN_POLL_SCALAR << 8) & HIFN_DMACNFG_POLLINVAL));
1198 }
1199
1200 /*
1201  * The maximum number of sessions supported by the card
1202  * is dependent on the amount of context ram, which
1203  * encryption algorithms are enabled, and how compression
1204  * is configured.  This should be configured before this
1205  * routine is called.
1206  */
1207 static void
1208 hifn_sessions(struct hifn_softc *sc)
1209 {
1210         u_int32_t pucnfg;
1211         int ctxsize;
1212
1213         pucnfg = READ_REG_0(sc, HIFN_0_PUCNFG);
1214
1215         if (pucnfg & HIFN_PUCNFG_COMPSING) {
1216                 if (pucnfg & HIFN_PUCNFG_ENCCNFG)
1217                         ctxsize = 128;
1218                 else
1219                         ctxsize = 512;
1220                 /*
1221                  * 7955/7956 has internal context memory of 32K
1222                  */
1223                 if (sc->sc_flags & HIFN_IS_7956)
1224                         sc->sc_maxses = 32768 / ctxsize;
1225                 else
1226                         sc->sc_maxses = 1 +
1227                             ((sc->sc_ramsize - 32768) / ctxsize);
1228         } else
1229                 sc->sc_maxses = sc->sc_ramsize / 16384;
1230
1231         if (sc->sc_maxses > 2048)
1232                 sc->sc_maxses = 2048;
1233 }
1234
1235 /*
1236  * Determine ram type (sram or dram).  Board should be just out of a reset
1237  * state when this is called.
1238  */
1239 static int
1240 hifn_ramtype(struct hifn_softc *sc)
1241 {
1242         u_int8_t data[8], dataexpect[8];
1243         int i;
1244
1245         for (i = 0; i < sizeof(data); i++)
1246                 data[i] = dataexpect[i] = 0x55;
1247         if (hifn_writeramaddr(sc, 0, data))
1248                 return (-1);
1249         if (hifn_readramaddr(sc, 0, data))
1250                 return (-1);
1251         if (bcmp(data, dataexpect, sizeof(data)) != 0) {
1252                 sc->sc_drammodel = 1;
1253                 return (0);
1254         }
1255
1256         for (i = 0; i < sizeof(data); i++)
1257                 data[i] = dataexpect[i] = 0xaa;
1258         if (hifn_writeramaddr(sc, 0, data))
1259                 return (-1);
1260         if (hifn_readramaddr(sc, 0, data))
1261                 return (-1);
1262         if (bcmp(data, dataexpect, sizeof(data)) != 0) {
1263                 sc->sc_drammodel = 1;
1264                 return (0);
1265         }
1266
1267         return (0);
1268 }
1269
1270 #define HIFN_SRAM_MAX           (32 << 20)
1271 #define HIFN_SRAM_STEP_SIZE     16384
1272 #define HIFN_SRAM_GRANULARITY   (HIFN_SRAM_MAX / HIFN_SRAM_STEP_SIZE)
1273
1274 static int
1275 hifn_sramsize(struct hifn_softc *sc)
1276 {
1277         u_int32_t a;
1278         u_int8_t data[8];
1279         u_int8_t dataexpect[sizeof(data)];
1280         int32_t i;
1281
1282         for (i = 0; i < sizeof(data); i++)
1283                 data[i] = dataexpect[i] = i ^ 0x5a;
1284
1285         for (i = HIFN_SRAM_GRANULARITY - 1; i >= 0; i--) {
1286                 a = i * HIFN_SRAM_STEP_SIZE;
1287                 bcopy(&i, data, sizeof(i));
1288                 hifn_writeramaddr(sc, a, data);
1289         }
1290
1291         for (i = 0; i < HIFN_SRAM_GRANULARITY; i++) {
1292                 a = i * HIFN_SRAM_STEP_SIZE;
1293                 bcopy(&i, dataexpect, sizeof(i));
1294                 if (hifn_readramaddr(sc, a, data) < 0)
1295                         return (0);
1296                 if (bcmp(data, dataexpect, sizeof(data)) != 0)
1297                         return (0);
1298                 sc->sc_ramsize = a + HIFN_SRAM_STEP_SIZE;
1299         }
1300
1301         return (0);
1302 }
1303
1304 /*
1305  * XXX For dram boards, one should really try all of the
1306  * HIFN_PUCNFG_DSZ_*'s.  This just assumes that PUCNFG
1307  * is already set up correctly.
1308  */
1309 static int
1310 hifn_dramsize(struct hifn_softc *sc)
1311 {
1312         u_int32_t cnfg;
1313
1314         if (sc->sc_flags & HIFN_IS_7956) {
1315                 /*
1316                  * 7955/7956 have a fixed internal ram of only 32K.
1317                  */
1318                 sc->sc_ramsize = 32768;
1319         } else {
1320                 cnfg = READ_REG_0(sc, HIFN_0_PUCNFG) &
1321                     HIFN_PUCNFG_DRAMMASK;
1322                 sc->sc_ramsize = 1 << ((cnfg >> 13) + 18);
1323         }
1324         return (0);
1325 }
1326
1327 static void
1328 hifn_alloc_slot(struct hifn_softc *sc, int *cmdp, int *srcp, int *dstp, int *resp)
1329 {
1330         struct hifn_dma *dma = sc->sc_dma;
1331
1332         if (dma->cmdi == HIFN_D_CMD_RSIZE) {
1333                 dma->cmdi = 0;
1334                 dma->cmdr[HIFN_D_CMD_RSIZE].l = htole32(HIFN_D_VALID |
1335                     HIFN_D_JUMP | HIFN_D_MASKDONEIRQ);
1336                 HIFN_CMDR_SYNC(sc, HIFN_D_CMD_RSIZE,
1337                     BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1338         }
1339         *cmdp = dma->cmdi++;
1340         dma->cmdk = dma->cmdi;
1341
1342         if (dma->srci == HIFN_D_SRC_RSIZE) {
1343                 dma->srci = 0;
1344                 dma->srcr[HIFN_D_SRC_RSIZE].l = htole32(HIFN_D_VALID |
1345                     HIFN_D_JUMP | HIFN_D_MASKDONEIRQ);
1346                 HIFN_SRCR_SYNC(sc, HIFN_D_SRC_RSIZE,
1347                     BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1348         }
1349         *srcp = dma->srci++;
1350         dma->srck = dma->srci;
1351
1352         if (dma->dsti == HIFN_D_DST_RSIZE) {
1353                 dma->dsti = 0;
1354                 dma->dstr[HIFN_D_DST_RSIZE].l = htole32(HIFN_D_VALID |
1355                     HIFN_D_JUMP | HIFN_D_MASKDONEIRQ);
1356                 HIFN_DSTR_SYNC(sc, HIFN_D_DST_RSIZE,
1357                     BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1358         }
1359         *dstp = dma->dsti++;
1360         dma->dstk = dma->dsti;
1361
1362         if (dma->resi == HIFN_D_RES_RSIZE) {
1363                 dma->resi = 0;
1364                 dma->resr[HIFN_D_RES_RSIZE].l = htole32(HIFN_D_VALID |
1365                     HIFN_D_JUMP | HIFN_D_MASKDONEIRQ);
1366                 HIFN_RESR_SYNC(sc, HIFN_D_RES_RSIZE,
1367                     BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1368         }
1369         *resp = dma->resi++;
1370         dma->resk = dma->resi;
1371 }
1372
1373 static int
1374 hifn_writeramaddr(struct hifn_softc *sc, int addr, u_int8_t *data)
1375 {
1376         struct hifn_dma *dma = sc->sc_dma;
1377         hifn_base_command_t wc;
1378         const u_int32_t masks = HIFN_D_VALID | HIFN_D_LAST | HIFN_D_MASKDONEIRQ;
1379         int r, cmdi, resi, srci, dsti;
1380
1381         wc.masks = htole16(3 << 13);
1382         wc.session_num = htole16(addr >> 14);
1383         wc.total_source_count = htole16(8);
1384         wc.total_dest_count = htole16(addr & 0x3fff);
1385
1386         hifn_alloc_slot(sc, &cmdi, &srci, &dsti, &resi);
1387
1388         WRITE_REG_1(sc, HIFN_1_DMA_CSR,
1389             HIFN_DMACSR_C_CTRL_ENA | HIFN_DMACSR_S_CTRL_ENA |
1390             HIFN_DMACSR_D_CTRL_ENA | HIFN_DMACSR_R_CTRL_ENA);
1391
1392         /* build write command */
1393         bzero(dma->command_bufs[cmdi], HIFN_MAX_COMMAND);
1394         *(hifn_base_command_t *)dma->command_bufs[cmdi] = wc;
1395         bcopy(data, &dma->test_src, sizeof(dma->test_src));
1396
1397         dma->srcr[srci].p = htole32(sc->sc_dma_physaddr
1398             + offsetof(struct hifn_dma, test_src));
1399         dma->dstr[dsti].p = htole32(sc->sc_dma_physaddr
1400             + offsetof(struct hifn_dma, test_dst));
1401
1402         dma->cmdr[cmdi].l = htole32(16 | masks);
1403         dma->srcr[srci].l = htole32(8 | masks);
1404         dma->dstr[dsti].l = htole32(4 | masks);
1405         dma->resr[resi].l = htole32(4 | masks);
1406
1407         bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap,
1408             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1409
1410         for (r = 10000; r >= 0; r--) {
1411                 DELAY(10);
1412                 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap,
1413                     BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1414                 if ((dma->resr[resi].l & htole32(HIFN_D_VALID)) == 0)
1415                         break;
1416                 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap,
1417                     BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1418         }
1419         if (r == 0) {
1420                 device_printf(sc->sc_dev, "writeramaddr -- "
1421                     "result[%d](addr %d) still valid\n", resi, addr);
1422                 r = -1;
1423                 return (-1);
1424         } else
1425                 r = 0;
1426
1427         WRITE_REG_1(sc, HIFN_1_DMA_CSR,
1428             HIFN_DMACSR_C_CTRL_DIS | HIFN_DMACSR_S_CTRL_DIS |
1429             HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS);
1430
1431         return (r);
1432 }
1433
1434 static int
1435 hifn_readramaddr(struct hifn_softc *sc, int addr, u_int8_t *data)
1436 {
1437         struct hifn_dma *dma = sc->sc_dma;
1438         hifn_base_command_t rc;
1439         const u_int32_t masks = HIFN_D_VALID | HIFN_D_LAST | HIFN_D_MASKDONEIRQ;
1440         int r, cmdi, srci, dsti, resi;
1441
1442         rc.masks = htole16(2 << 13);
1443         rc.session_num = htole16(addr >> 14);
1444         rc.total_source_count = htole16(addr & 0x3fff);
1445         rc.total_dest_count = htole16(8);
1446
1447         hifn_alloc_slot(sc, &cmdi, &srci, &dsti, &resi);
1448
1449         WRITE_REG_1(sc, HIFN_1_DMA_CSR,
1450             HIFN_DMACSR_C_CTRL_ENA | HIFN_DMACSR_S_CTRL_ENA |
1451             HIFN_DMACSR_D_CTRL_ENA | HIFN_DMACSR_R_CTRL_ENA);
1452
1453         bzero(dma->command_bufs[cmdi], HIFN_MAX_COMMAND);
1454         *(hifn_base_command_t *)dma->command_bufs[cmdi] = rc;
1455
1456         dma->srcr[srci].p = htole32(sc->sc_dma_physaddr +
1457             offsetof(struct hifn_dma, test_src));
1458         dma->test_src = 0;
1459         dma->dstr[dsti].p =  htole32(sc->sc_dma_physaddr +
1460             offsetof(struct hifn_dma, test_dst));
1461         dma->test_dst = 0;
1462         dma->cmdr[cmdi].l = htole32(8 | masks);
1463         dma->srcr[srci].l = htole32(8 | masks);
1464         dma->dstr[dsti].l = htole32(8 | masks);
1465         dma->resr[resi].l = htole32(HIFN_MAX_RESULT | masks);
1466
1467         bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap,
1468             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1469
1470         for (r = 10000; r >= 0; r--) {
1471                 DELAY(10);
1472                 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap,
1473                     BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1474                 if ((dma->resr[resi].l & htole32(HIFN_D_VALID)) == 0)
1475                         break;
1476                 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap,
1477                     BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1478         }
1479         if (r == 0) {
1480                 device_printf(sc->sc_dev, "readramaddr -- "
1481                     "result[%d](addr %d) still valid\n", resi, addr);
1482                 r = -1;
1483         } else {
1484                 r = 0;
1485                 bcopy(&dma->test_dst, data, sizeof(dma->test_dst));
1486         }
1487
1488         WRITE_REG_1(sc, HIFN_1_DMA_CSR,
1489             HIFN_DMACSR_C_CTRL_DIS | HIFN_DMACSR_S_CTRL_DIS |
1490             HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS);
1491
1492         return (r);
1493 }
1494
1495 /*
1496  * Initialize the descriptor rings.
1497  */
1498 static void
1499 hifn_init_dma(struct hifn_softc *sc)
1500 {
1501         struct hifn_dma *dma = sc->sc_dma;
1502         int i;
1503
1504         hifn_set_retry(sc);
1505
1506         /* initialize static pointer values */
1507         for (i = 0; i < HIFN_D_CMD_RSIZE; i++)
1508                 dma->cmdr[i].p = htole32(sc->sc_dma_physaddr +
1509                     offsetof(struct hifn_dma, command_bufs[i][0]));
1510         for (i = 0; i < HIFN_D_RES_RSIZE; i++)
1511                 dma->resr[i].p = htole32(sc->sc_dma_physaddr +
1512                     offsetof(struct hifn_dma, result_bufs[i][0]));
1513
1514         dma->cmdr[HIFN_D_CMD_RSIZE].p =
1515             htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, cmdr[0]));
1516         dma->srcr[HIFN_D_SRC_RSIZE].p =
1517             htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, srcr[0]));
1518         dma->dstr[HIFN_D_DST_RSIZE].p =
1519             htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, dstr[0]));
1520         dma->resr[HIFN_D_RES_RSIZE].p =
1521             htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, resr[0]));
1522
1523         dma->cmdu = dma->srcu = dma->dstu = dma->resu = 0;
1524         dma->cmdi = dma->srci = dma->dsti = dma->resi = 0;
1525         dma->cmdk = dma->srck = dma->dstk = dma->resk = 0;
1526 }
1527
1528 /*
1529  * Writes out the raw command buffer space.  Returns the
1530  * command buffer size.
1531  */
1532 static u_int
1533 hifn_write_command(struct hifn_command *cmd, u_int8_t *buf)
1534 {
1535         u_int8_t *buf_pos;
1536         hifn_base_command_t *base_cmd;
1537         hifn_mac_command_t *mac_cmd;
1538         hifn_crypt_command_t *cry_cmd;
1539         int using_mac, using_crypt, len, ivlen;
1540         u_int32_t dlen, slen;
1541
1542         buf_pos = buf;
1543         using_mac = cmd->base_masks & HIFN_BASE_CMD_MAC;
1544         using_crypt = cmd->base_masks & HIFN_BASE_CMD_CRYPT;
1545
1546         base_cmd = (hifn_base_command_t *)buf_pos;
1547         base_cmd->masks = htole16(cmd->base_masks);
1548         slen = cmd->src_mapsize;
1549         if (cmd->sloplen)
1550                 dlen = cmd->dst_mapsize - cmd->sloplen + sizeof(u_int32_t);
1551         else
1552                 dlen = cmd->dst_mapsize;
1553         base_cmd->total_source_count = htole16(slen & HIFN_BASE_CMD_LENMASK_LO);
1554         base_cmd->total_dest_count = htole16(dlen & HIFN_BASE_CMD_LENMASK_LO);
1555         dlen >>= 16;
1556         slen >>= 16;
1557         base_cmd->session_num = htole16(
1558             ((slen << HIFN_BASE_CMD_SRCLEN_S) & HIFN_BASE_CMD_SRCLEN_M) |
1559             ((dlen << HIFN_BASE_CMD_DSTLEN_S) & HIFN_BASE_CMD_DSTLEN_M));
1560         buf_pos += sizeof(hifn_base_command_t);
1561
1562         if (using_mac) {
1563                 mac_cmd = (hifn_mac_command_t *)buf_pos;
1564                 dlen = cmd->maccrd->crd_len;
1565                 mac_cmd->source_count = htole16(dlen & 0xffff);
1566                 dlen >>= 16;
1567                 mac_cmd->masks = htole16(cmd->mac_masks |
1568                     ((dlen << HIFN_MAC_CMD_SRCLEN_S) & HIFN_MAC_CMD_SRCLEN_M));
1569                 mac_cmd->header_skip = htole16(cmd->maccrd->crd_skip);
1570                 mac_cmd->reserved = 0;
1571                 buf_pos += sizeof(hifn_mac_command_t);
1572         }
1573
1574         if (using_crypt) {
1575                 cry_cmd = (hifn_crypt_command_t *)buf_pos;
1576                 dlen = cmd->enccrd->crd_len;
1577                 cry_cmd->source_count = htole16(dlen & 0xffff);
1578                 dlen >>= 16;
1579                 cry_cmd->masks = htole16(cmd->cry_masks |
1580                     ((dlen << HIFN_CRYPT_CMD_SRCLEN_S) & HIFN_CRYPT_CMD_SRCLEN_M));
1581                 cry_cmd->header_skip = htole16(cmd->enccrd->crd_skip);
1582                 cry_cmd->reserved = 0;
1583                 buf_pos += sizeof(hifn_crypt_command_t);
1584         }
1585
1586         if (using_mac && cmd->mac_masks & HIFN_MAC_CMD_NEW_KEY) {
1587                 bcopy(cmd->mac, buf_pos, HIFN_MAC_KEY_LENGTH);
1588                 buf_pos += HIFN_MAC_KEY_LENGTH;
1589         }
1590
1591         if (using_crypt && cmd->cry_masks & HIFN_CRYPT_CMD_NEW_KEY) {
1592                 switch (cmd->cry_masks & HIFN_CRYPT_CMD_ALG_MASK) {
1593                 case HIFN_CRYPT_CMD_ALG_3DES:
1594                         bcopy(cmd->ck, buf_pos, HIFN_3DES_KEY_LENGTH);
1595                         buf_pos += HIFN_3DES_KEY_LENGTH;
1596                         break;
1597                 case HIFN_CRYPT_CMD_ALG_DES:
1598                         bcopy(cmd->ck, buf_pos, HIFN_DES_KEY_LENGTH);
1599                         buf_pos += HIFN_DES_KEY_LENGTH;
1600                         break;
1601                 case HIFN_CRYPT_CMD_ALG_RC4:
1602                         len = 256;
1603                         do {
1604                                 int clen;
1605
1606                                 clen = MIN(cmd->cklen, len);
1607                                 bcopy(cmd->ck, buf_pos, clen);
1608                                 len -= clen;
1609                                 buf_pos += clen;
1610                         } while (len > 0);
1611                         bzero(buf_pos, 4);
1612                         buf_pos += 4;
1613                         break;
1614                 case HIFN_CRYPT_CMD_ALG_AES:
1615                         /*
1616                          * AES keys are variable 128, 192 and
1617                          * 256 bits (16, 24 and 32 bytes).
1618                          */
1619                         bcopy(cmd->ck, buf_pos, cmd->cklen);
1620                         buf_pos += cmd->cklen;
1621                         break;
1622                 }
1623         }
1624
1625         if (using_crypt && cmd->cry_masks & HIFN_CRYPT_CMD_NEW_IV) {
1626                 switch (cmd->cry_masks & HIFN_CRYPT_CMD_ALG_MASK) {
1627                 case HIFN_CRYPT_CMD_ALG_AES:
1628                         ivlen = HIFN_AES_IV_LENGTH;
1629                         break;
1630                 default:
1631                         ivlen = HIFN_IV_LENGTH;
1632                         break;
1633                 }
1634                 bcopy(cmd->iv, buf_pos, ivlen);
1635                 buf_pos += ivlen;
1636         }
1637
1638         if ((cmd->base_masks & (HIFN_BASE_CMD_MAC|HIFN_BASE_CMD_CRYPT)) == 0) {
1639                 bzero(buf_pos, 8);
1640                 buf_pos += 8;
1641         }
1642
1643         return (buf_pos - buf);
1644 }
1645
1646 static int
1647 hifn_dmamap_aligned(struct hifn_operand *op)
1648 {
1649         int i;
1650
1651         for (i = 0; i < op->nsegs; i++) {
1652                 if (op->segs[i].ds_addr & 3)
1653                         return (0);
1654                 if ((i != (op->nsegs - 1)) && (op->segs[i].ds_len & 3))
1655                         return (0);
1656         }
1657         return (1);
1658 }
1659
1660 static int
1661 hifn_dmamap_load_dst(struct hifn_softc *sc, struct hifn_command *cmd)
1662 {
1663         struct hifn_dma *dma = sc->sc_dma;
1664         struct hifn_operand *dst = &cmd->dst;
1665         u_int32_t p, l;
1666         int idx, used = 0, i;
1667
1668         idx = dma->dsti;
1669         for (i = 0; i < dst->nsegs - 1; i++) {
1670                 dma->dstr[idx].p = htole32(dst->segs[i].ds_addr);
1671                 dma->dstr[idx].l = htole32(HIFN_D_VALID |
1672                     HIFN_D_MASKDONEIRQ | dst->segs[i].ds_len);
1673                 HIFN_DSTR_SYNC(sc, idx,
1674                     BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1675                 used++;
1676
1677                 if (++idx == HIFN_D_DST_RSIZE) {
1678                         dma->dstr[idx].l = htole32(HIFN_D_VALID |
1679                             HIFN_D_JUMP | HIFN_D_MASKDONEIRQ);
1680                         HIFN_DSTR_SYNC(sc, idx,
1681                             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1682                         idx = 0;
1683                 }
1684         }
1685
1686         if (cmd->sloplen == 0) {
1687                 p = dst->segs[i].ds_addr;
1688                 l = HIFN_D_VALID | HIFN_D_MASKDONEIRQ | HIFN_D_LAST |
1689                     dst->segs[i].ds_len;
1690         } else {
1691                 p = sc->sc_dma_physaddr +
1692                     offsetof(struct hifn_dma, slop[cmd->slopidx]);
1693                 l = HIFN_D_VALID | HIFN_D_MASKDONEIRQ | HIFN_D_LAST |
1694                     sizeof(u_int32_t);
1695
1696                 if ((dst->segs[i].ds_len - cmd->sloplen) != 0) {
1697                         dma->dstr[idx].p = htole32(dst->segs[i].ds_addr);
1698                         dma->dstr[idx].l = htole32(HIFN_D_VALID |
1699                             HIFN_D_MASKDONEIRQ |
1700                             (dst->segs[i].ds_len - cmd->sloplen));
1701                         HIFN_DSTR_SYNC(sc, idx,
1702                             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1703                         used++;
1704
1705                         if (++idx == HIFN_D_DST_RSIZE) {
1706                                 dma->dstr[idx].l = htole32(HIFN_D_VALID |
1707                                     HIFN_D_JUMP | HIFN_D_MASKDONEIRQ);
1708                                 HIFN_DSTR_SYNC(sc, idx,
1709                                     BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1710                                 idx = 0;
1711                         }
1712                 }
1713         }
1714         dma->dstr[idx].p = htole32(p);
1715         dma->dstr[idx].l = htole32(l);
1716         HIFN_DSTR_SYNC(sc, idx, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1717         used++;
1718
1719         if (++idx == HIFN_D_DST_RSIZE) {
1720                 dma->dstr[idx].l = htole32(HIFN_D_VALID | HIFN_D_JUMP |
1721                     HIFN_D_MASKDONEIRQ);
1722                 HIFN_DSTR_SYNC(sc, idx,
1723                     BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1724                 idx = 0;
1725         }
1726
1727         dma->dsti = idx;
1728         dma->dstu += used;
1729         return (idx);
1730 }
1731
1732 static int
1733 hifn_dmamap_load_src(struct hifn_softc *sc, struct hifn_command *cmd)
1734 {
1735         struct hifn_dma *dma = sc->sc_dma;
1736         struct hifn_operand *src = &cmd->src;
1737         int idx, i;
1738         u_int32_t last = 0;
1739
1740         idx = dma->srci;
1741         for (i = 0; i < src->nsegs; i++) {
1742                 if (i == src->nsegs - 1)
1743                         last = HIFN_D_LAST;
1744
1745                 dma->srcr[idx].p = htole32(src->segs[i].ds_addr);
1746                 dma->srcr[idx].l = htole32(src->segs[i].ds_len |
1747                     HIFN_D_VALID | HIFN_D_MASKDONEIRQ | last);
1748                 HIFN_SRCR_SYNC(sc, idx,
1749                     BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1750
1751                 if (++idx == HIFN_D_SRC_RSIZE) {
1752                         dma->srcr[idx].l = htole32(HIFN_D_VALID |
1753                             HIFN_D_JUMP | HIFN_D_MASKDONEIRQ);
1754                         HIFN_SRCR_SYNC(sc, HIFN_D_SRC_RSIZE,
1755                             BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1756                         idx = 0;
1757                 }
1758         }
1759         dma->srci = idx;
1760         dma->srcu += src->nsegs;
1761         return (idx);
1762 }
1763
1764 static void
1765 hifn_op_cb(void* arg, bus_dma_segment_t *seg, int nsegs, bus_size_t mapsize, int error)
1766 {
1767         struct hifn_operand *op = arg;
1768
1769         KASSERT(nsegs <= MAX_SCATTER,
1770                 ("hifn_op_cb: too many DMA segments (%u > %u) "
1771                  "returned when mapping operand", nsegs, MAX_SCATTER));
1772         op->mapsize = mapsize;
1773         op->nsegs = nsegs;
1774         bcopy(seg, op->segs, nsegs * sizeof (seg[0]));
1775 }
1776
1777 static int
1778 hifn_crypto(
1779         struct hifn_softc *sc,
1780         struct hifn_command *cmd,
1781         struct cryptop *crp,
1782         int hint)
1783 {
1784         struct  hifn_dma *dma = sc->sc_dma;
1785         u_int32_t cmdlen;
1786         int cmdi, resi, err = 0;
1787
1788         /*
1789          * need 1 cmd, and 1 res
1790          *
1791          * NB: check this first since it's easy.
1792          */
1793         HIFN_LOCK(sc);
1794         if ((dma->cmdu + 1) > HIFN_D_CMD_RSIZE ||
1795             (dma->resu + 1) > HIFN_D_RES_RSIZE) {
1796 #ifdef HIFN_DEBUG
1797                 if (hifn_debug) {
1798                         device_printf(sc->sc_dev,
1799                                 "cmd/result exhaustion, cmdu %u resu %u\n",
1800                                 dma->cmdu, dma->resu);
1801                 }
1802 #endif
1803                 hifnstats.hst_nomem_cr++;
1804                 HIFN_UNLOCK(sc);
1805                 return (ERESTART);
1806         }
1807
1808         if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, &cmd->src_map)) {
1809                 hifnstats.hst_nomem_map++;
1810                 HIFN_UNLOCK(sc);
1811                 return (ENOMEM);
1812         }
1813
1814         if (crp->crp_flags & CRYPTO_F_IMBUF) {
1815                 if (bus_dmamap_load_mbuf(sc->sc_dmat, cmd->src_map,
1816                     cmd->src_m, hifn_op_cb, &cmd->src, BUS_DMA_NOWAIT)) {
1817                         hifnstats.hst_nomem_load++;
1818                         err = ENOMEM;
1819                         goto err_srcmap1;
1820                 }
1821         } else if (crp->crp_flags & CRYPTO_F_IOV) {
1822                 if (bus_dmamap_load_uio(sc->sc_dmat, cmd->src_map,
1823                     cmd->src_io, hifn_op_cb, &cmd->src, BUS_DMA_NOWAIT)) {
1824                         hifnstats.hst_nomem_load++;
1825                         err = ENOMEM;
1826                         goto err_srcmap1;
1827                 }
1828         } else {
1829                 err = EINVAL;
1830                 goto err_srcmap1;
1831         }
1832
1833         if (hifn_dmamap_aligned(&cmd->src)) {
1834                 cmd->sloplen = cmd->src_mapsize & 3;
1835                 cmd->dst = cmd->src;
1836         } else {
1837                 if (crp->crp_flags & CRYPTO_F_IOV) {
1838                         err = EINVAL;
1839                         goto err_srcmap;
1840                 } else if (crp->crp_flags & CRYPTO_F_IMBUF) {
1841                         int totlen, len;
1842                         struct mbuf *m, *m0, *mlast;
1843
1844                         KASSERT(cmd->dst_m == cmd->src_m,
1845                                 ("hifn_crypto: dst_m initialized improperly"));
1846                         hifnstats.hst_unaligned++;
1847                         /*
1848                          * Source is not aligned on a longword boundary.
1849                          * Copy the data to insure alignment.  If we fail
1850                          * to allocate mbufs or clusters while doing this
1851                          * we return ERESTART so the operation is requeued
1852                          * at the crypto later, but only if there are
1853                          * ops already posted to the hardware; otherwise we
1854                          * have no guarantee that we'll be re-entered.
1855                          */
1856                         totlen = cmd->src_mapsize;
1857                         if (cmd->src_m->m_flags & M_PKTHDR) {
1858                                 len = MHLEN;
1859                                 MGETHDR(m0, M_DONTWAIT, MT_DATA);
1860                                 if (m0 && !m_dup_pkthdr(m0, cmd->src_m, M_DONTWAIT)) {
1861                                         m_free(m0);
1862                                         m0 = NULL;
1863                                 }
1864                         } else {
1865                                 len = MLEN;
1866                                 MGET(m0, M_DONTWAIT, MT_DATA);
1867                         }
1868                         if (m0 == NULL) {
1869                                 hifnstats.hst_nomem_mbuf++;
1870                                 err = dma->cmdu ? ERESTART : ENOMEM;
1871                                 goto err_srcmap;
1872                         }
1873                         if (totlen >= MINCLSIZE) {
1874                                 MCLGET(m0, M_DONTWAIT);
1875                                 if ((m0->m_flags & M_EXT) == 0) {
1876                                         hifnstats.hst_nomem_mcl++;
1877                                         err = dma->cmdu ? ERESTART : ENOMEM;
1878                                         m_freem(m0);
1879                                         goto err_srcmap;
1880                                 }
1881                                 len = MCLBYTES;
1882                         }
1883                         totlen -= len;
1884                         m0->m_pkthdr.len = m0->m_len = len;
1885                         mlast = m0;
1886
1887                         while (totlen > 0) {
1888                                 MGET(m, M_DONTWAIT, MT_DATA);
1889                                 if (m == NULL) {
1890                                         hifnstats.hst_nomem_mbuf++;
1891                                         err = dma->cmdu ? ERESTART : ENOMEM;
1892                                         m_freem(m0);
1893                                         goto err_srcmap;
1894                                 }
1895                                 len = MLEN;
1896                                 if (totlen >= MINCLSIZE) {
1897                                         MCLGET(m, M_DONTWAIT);
1898                                         if ((m->m_flags & M_EXT) == 0) {
1899                                                 hifnstats.hst_nomem_mcl++;
1900                                                 err = dma->cmdu ? ERESTART : ENOMEM;
1901                                                 mlast->m_next = m;
1902                                                 m_freem(m0);
1903                                                 goto err_srcmap;
1904                                         }
1905                                         len = MCLBYTES;
1906                                 }
1907
1908                                 m->m_len = len;
1909                                 m0->m_pkthdr.len += len;
1910                                 totlen -= len;
1911
1912                                 mlast->m_next = m;
1913                                 mlast = m;
1914                         }
1915                         cmd->dst_m = m0;
1916                 }
1917         }
1918
1919         if (cmd->dst_map == NULL) {
1920                 if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, &cmd->dst_map)) {
1921                         hifnstats.hst_nomem_map++;
1922                         err = ENOMEM;
1923                         goto err_srcmap;
1924                 }
1925                 if (crp->crp_flags & CRYPTO_F_IMBUF) {
1926                         if (bus_dmamap_load_mbuf(sc->sc_dmat, cmd->dst_map,
1927                             cmd->dst_m, hifn_op_cb, &cmd->dst, BUS_DMA_NOWAIT)) {
1928                                 hifnstats.hst_nomem_map++;
1929                                 err = ENOMEM;
1930                                 goto err_dstmap1;
1931                         }
1932                 } else if (crp->crp_flags & CRYPTO_F_IOV) {
1933                         if (bus_dmamap_load_uio(sc->sc_dmat, cmd->dst_map,
1934                             cmd->dst_io, hifn_op_cb, &cmd->dst, BUS_DMA_NOWAIT)) {
1935                                 hifnstats.hst_nomem_load++;
1936                                 err = ENOMEM;
1937                                 goto err_dstmap1;
1938                         }
1939                 }
1940         }
1941
1942 #ifdef HIFN_DEBUG
1943         if (hifn_debug) {
1944                 device_printf(sc->sc_dev,
1945                     "Entering cmd: stat %8x ien %8x u %d/%d/%d/%d n %d/%d\n",
1946                     READ_REG_1(sc, HIFN_1_DMA_CSR),
1947                     READ_REG_1(sc, HIFN_1_DMA_IER),
1948                     dma->cmdu, dma->srcu, dma->dstu, dma->resu,
1949                     cmd->src_nsegs, cmd->dst_nsegs);
1950         }
1951 #endif
1952
1953         if (cmd->src_map == cmd->dst_map) {
1954                 bus_dmamap_sync(sc->sc_dmat, cmd->src_map,
1955                     BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
1956         } else {
1957                 bus_dmamap_sync(sc->sc_dmat, cmd->src_map,
1958                     BUS_DMASYNC_PREWRITE);
1959                 bus_dmamap_sync(sc->sc_dmat, cmd->dst_map,
1960                     BUS_DMASYNC_PREREAD);
1961         }
1962
1963         /*
1964          * need N src, and N dst
1965          */
1966         if ((dma->srcu + cmd->src_nsegs) > HIFN_D_SRC_RSIZE ||
1967             (dma->dstu + cmd->dst_nsegs + 1) > HIFN_D_DST_RSIZE) {
1968 #ifdef HIFN_DEBUG
1969                 if (hifn_debug) {
1970                         device_printf(sc->sc_dev,
1971                                 "src/dst exhaustion, srcu %u+%u dstu %u+%u\n",
1972                                 dma->srcu, cmd->src_nsegs,
1973                                 dma->dstu, cmd->dst_nsegs);
1974                 }
1975 #endif
1976                 hifnstats.hst_nomem_sd++;
1977                 err = ERESTART;
1978                 goto err_dstmap;
1979         }
1980
1981         if (dma->cmdi == HIFN_D_CMD_RSIZE) {
1982                 dma->cmdi = 0;
1983                 dma->cmdr[HIFN_D_CMD_RSIZE].l = htole32(HIFN_D_VALID |
1984                     HIFN_D_JUMP | HIFN_D_MASKDONEIRQ);
1985                 HIFN_CMDR_SYNC(sc, HIFN_D_CMD_RSIZE,
1986                     BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1987         }
1988         cmdi = dma->cmdi++;
1989         cmdlen = hifn_write_command(cmd, dma->command_bufs[cmdi]);
1990         HIFN_CMD_SYNC(sc, cmdi, BUS_DMASYNC_PREWRITE);
1991
1992         /* .p for command/result already set */
1993         dma->cmdr[cmdi].l = htole32(cmdlen | HIFN_D_VALID | HIFN_D_LAST |
1994             HIFN_D_MASKDONEIRQ);
1995         HIFN_CMDR_SYNC(sc, cmdi,
1996             BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1997         dma->cmdu++;
1998         if (sc->sc_c_busy == 0) {
1999                 WRITE_REG_1(sc, HIFN_1_DMA_CSR, HIFN_DMACSR_C_CTRL_ENA);
2000                 sc->sc_c_busy = 1;
2001         }
2002
2003         /*
2004          * We don't worry about missing an interrupt (which a "command wait"
2005          * interrupt salvages us from), unless there is more than one command
2006          * in the queue.
2007          */
2008         if (dma->cmdu > 1) {
2009                 sc->sc_dmaier |= HIFN_DMAIER_C_WAIT;
2010                 WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier);
2011         }
2012
2013         hifnstats.hst_ipackets++;
2014         hifnstats.hst_ibytes += cmd->src_mapsize;
2015
2016         hifn_dmamap_load_src(sc, cmd);
2017         if (sc->sc_s_busy == 0) {
2018                 WRITE_REG_1(sc, HIFN_1_DMA_CSR, HIFN_DMACSR_S_CTRL_ENA);
2019                 sc->sc_s_busy = 1;
2020         }
2021
2022         /*
2023          * Unlike other descriptors, we don't mask done interrupt from
2024          * result descriptor.
2025          */
2026 #ifdef HIFN_DEBUG
2027         if (hifn_debug)
2028                 printf("load res\n");
2029 #endif
2030         if (dma->resi == HIFN_D_RES_RSIZE) {
2031                 dma->resi = 0;
2032                 dma->resr[HIFN_D_RES_RSIZE].l = htole32(HIFN_D_VALID |
2033                     HIFN_D_JUMP | HIFN_D_MASKDONEIRQ);
2034                 HIFN_RESR_SYNC(sc, HIFN_D_RES_RSIZE,
2035                     BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2036         }
2037         resi = dma->resi++;
2038         KASSERT(dma->hifn_commands[resi] == NULL,
2039                 ("hifn_crypto: command slot %u busy", resi));
2040         dma->hifn_commands[resi] = cmd;
2041         HIFN_RES_SYNC(sc, resi, BUS_DMASYNC_PREREAD);
2042         if ((hint & CRYPTO_HINT_MORE) && sc->sc_curbatch < hifn_maxbatch) {
2043                 dma->resr[resi].l = htole32(HIFN_MAX_RESULT |
2044                     HIFN_D_VALID | HIFN_D_LAST | HIFN_D_MASKDONEIRQ);
2045                 sc->sc_curbatch++;
2046                 if (sc->sc_curbatch > hifnstats.hst_maxbatch)
2047                         hifnstats.hst_maxbatch = sc->sc_curbatch;
2048                 hifnstats.hst_totbatch++;
2049         } else {
2050                 dma->resr[resi].l = htole32(HIFN_MAX_RESULT |
2051                     HIFN_D_VALID | HIFN_D_LAST);
2052                 sc->sc_curbatch = 0;
2053         }
2054         HIFN_RESR_SYNC(sc, resi,
2055             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2056         dma->resu++;
2057         if (sc->sc_r_busy == 0) {
2058                 WRITE_REG_1(sc, HIFN_1_DMA_CSR, HIFN_DMACSR_R_CTRL_ENA);
2059                 sc->sc_r_busy = 1;
2060         }
2061
2062         if (cmd->sloplen)
2063                 cmd->slopidx = resi;
2064
2065         hifn_dmamap_load_dst(sc, cmd);
2066
2067         if (sc->sc_d_busy == 0) {
2068                 WRITE_REG_1(sc, HIFN_1_DMA_CSR, HIFN_DMACSR_D_CTRL_ENA);
2069                 sc->sc_d_busy = 1;
2070         }
2071
2072 #ifdef HIFN_DEBUG
2073         if (hifn_debug) {
2074                 device_printf(sc->sc_dev, "command: stat %8x ier %8x\n",
2075                     READ_REG_1(sc, HIFN_1_DMA_CSR),
2076                     READ_REG_1(sc, HIFN_1_DMA_IER));
2077         }
2078 #endif
2079
2080         sc->sc_active = 5;
2081         HIFN_UNLOCK(sc);
2082         KASSERT(err == 0, ("hifn_crypto: success with error %u", err));
2083         return (err);           /* success */
2084
2085 err_dstmap:
2086         if (cmd->src_map != cmd->dst_map)
2087                 bus_dmamap_unload(sc->sc_dmat, cmd->dst_map);
2088 err_dstmap1:
2089         if (cmd->src_map != cmd->dst_map)
2090                 bus_dmamap_destroy(sc->sc_dmat, cmd->dst_map);
2091 err_srcmap:
2092         if (crp->crp_flags & CRYPTO_F_IMBUF) {
2093                 if (cmd->src_m != cmd->dst_m)
2094                         m_freem(cmd->dst_m);
2095         }
2096         bus_dmamap_unload(sc->sc_dmat, cmd->src_map);
2097 err_srcmap1:
2098         bus_dmamap_destroy(sc->sc_dmat, cmd->src_map);
2099         HIFN_UNLOCK(sc);
2100         return (err);
2101 }
2102
2103 static void
2104 hifn_tick(void* vsc)
2105 {
2106         struct hifn_softc *sc = vsc;
2107
2108         HIFN_LOCK(sc);
2109         if (sc->sc_active == 0) {
2110                 struct hifn_dma *dma = sc->sc_dma;
2111                 u_int32_t r = 0;
2112
2113                 if (dma->cmdu == 0 && sc->sc_c_busy) {
2114                         sc->sc_c_busy = 0;
2115                         r |= HIFN_DMACSR_C_CTRL_DIS;
2116                 }
2117                 if (dma->srcu == 0 && sc->sc_s_busy) {
2118                         sc->sc_s_busy = 0;
2119                         r |= HIFN_DMACSR_S_CTRL_DIS;
2120                 }
2121                 if (dma->dstu == 0 && sc->sc_d_busy) {
2122                         sc->sc_d_busy = 0;
2123                         r |= HIFN_DMACSR_D_CTRL_DIS;
2124                 }
2125                 if (dma->resu == 0 && sc->sc_r_busy) {
2126                         sc->sc_r_busy = 0;
2127                         r |= HIFN_DMACSR_R_CTRL_DIS;
2128                 }
2129                 if (r)
2130                         WRITE_REG_1(sc, HIFN_1_DMA_CSR, r);
2131         } else
2132                 sc->sc_active--;
2133         HIFN_UNLOCK(sc);
2134         callout_reset(&sc->sc_tickto, hz, hifn_tick, sc);
2135 }
2136
2137 static void
2138 hifn_intr(void *arg)
2139 {
2140         struct hifn_softc *sc = arg;
2141         struct hifn_dma *dma;
2142         u_int32_t dmacsr, restart;
2143         int i, u;
2144
2145         dmacsr = READ_REG_1(sc, HIFN_1_DMA_CSR);
2146
2147         /* Nothing in the DMA unit interrupted */
2148         if ((dmacsr & sc->sc_dmaier) == 0)
2149                 return;
2150
2151         HIFN_LOCK(sc);
2152
2153         dma = sc->sc_dma;
2154
2155 #ifdef HIFN_DEBUG
2156         if (hifn_debug) {
2157                 device_printf(sc->sc_dev,
2158                     "irq: stat %08x ien %08x damier %08x i %d/%d/%d/%d k %d/%d/%d/%d u %d/%d/%d/%d\n",
2159                     dmacsr, READ_REG_1(sc, HIFN_1_DMA_IER), sc->sc_dmaier,
2160                     dma->cmdi, dma->srci, dma->dsti, dma->resi,
2161                     dma->cmdk, dma->srck, dma->dstk, dma->resk,
2162                     dma->cmdu, dma->srcu, dma->dstu, dma->resu);
2163         }
2164 #endif
2165
2166         WRITE_REG_1(sc, HIFN_1_DMA_CSR, dmacsr & sc->sc_dmaier);
2167
2168         if ((sc->sc_flags & HIFN_HAS_PUBLIC) &&
2169             (dmacsr & HIFN_DMACSR_PUBDONE))
2170                 WRITE_REG_1(sc, HIFN_1_PUB_STATUS,
2171                     READ_REG_1(sc, HIFN_1_PUB_STATUS) | HIFN_PUBSTS_DONE);
2172
2173         restart = dmacsr & (HIFN_DMACSR_D_OVER | HIFN_DMACSR_R_OVER);
2174         if (restart)
2175                 device_printf(sc->sc_dev, "overrun %x\n", dmacsr);
2176
2177         if (sc->sc_flags & HIFN_IS_7811) {
2178                 if (dmacsr & HIFN_DMACSR_ILLR)
2179                         device_printf(sc->sc_dev, "illegal read\n");
2180                 if (dmacsr & HIFN_DMACSR_ILLW)
2181                         device_printf(sc->sc_dev, "illegal write\n");
2182         }
2183
2184         restart = dmacsr & (HIFN_DMACSR_C_ABORT | HIFN_DMACSR_S_ABORT |
2185             HIFN_DMACSR_D_ABORT | HIFN_DMACSR_R_ABORT);
2186         if (restart) {
2187                 device_printf(sc->sc_dev, "abort, resetting.\n");
2188                 hifnstats.hst_abort++;
2189                 hifn_abort(sc);
2190                 HIFN_UNLOCK(sc);
2191                 return;
2192         }
2193
2194         if ((dmacsr & HIFN_DMACSR_C_WAIT) && (dma->cmdu == 0)) {
2195                 /*
2196                  * If no slots to process and we receive a "waiting on
2197                  * command" interrupt, we disable the "waiting on command"
2198                  * (by clearing it).
2199                  */
2200                 sc->sc_dmaier &= ~HIFN_DMAIER_C_WAIT;
2201                 WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier);
2202         }
2203
2204         /* clear the rings */
2205         i = dma->resk; u = dma->resu;
2206         while (u != 0) {
2207                 HIFN_RESR_SYNC(sc, i,
2208                     BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2209                 if (dma->resr[i].l & htole32(HIFN_D_VALID)) {
2210                         HIFN_RESR_SYNC(sc, i,
2211                             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2212                         break;
2213                 }
2214
2215                 if (i != HIFN_D_RES_RSIZE) {
2216                         struct hifn_command *cmd;
2217                         u_int8_t *macbuf = NULL;
2218
2219                         HIFN_RES_SYNC(sc, i, BUS_DMASYNC_POSTREAD);
2220                         cmd = dma->hifn_commands[i];
2221                         KASSERT(cmd != NULL,
2222                                 ("hifn_intr: null command slot %u", i));
2223                         dma->hifn_commands[i] = NULL;
2224
2225                         if (cmd->base_masks & HIFN_BASE_CMD_MAC) {
2226                                 macbuf = dma->result_bufs[i];
2227                                 macbuf += 12;
2228                         }
2229
2230                         hifn_callback(sc, cmd, macbuf);
2231                         hifnstats.hst_opackets++;
2232                         u--;
2233                 }
2234
2235                 if (++i == (HIFN_D_RES_RSIZE + 1))
2236                         i = 0;
2237         }
2238         dma->resk = i; dma->resu = u;
2239
2240         i = dma->srck; u = dma->srcu;
2241         while (u != 0) {
2242                 if (i == HIFN_D_SRC_RSIZE)
2243                         i = 0;
2244                 HIFN_SRCR_SYNC(sc, i,
2245                     BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2246                 if (dma->srcr[i].l & htole32(HIFN_D_VALID)) {
2247                         HIFN_SRCR_SYNC(sc, i,
2248                             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2249                         break;
2250                 }
2251                 i++, u--;
2252         }
2253         dma->srck = i; dma->srcu = u;
2254
2255         i = dma->cmdk; u = dma->cmdu;
2256         while (u != 0) {
2257                 HIFN_CMDR_SYNC(sc, i,
2258                     BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2259                 if (dma->cmdr[i].l & htole32(HIFN_D_VALID)) {
2260                         HIFN_CMDR_SYNC(sc, i,
2261                             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2262                         break;
2263                 }
2264                 if (i != HIFN_D_CMD_RSIZE) {
2265                         u--;
2266                         HIFN_CMD_SYNC(sc, i, BUS_DMASYNC_POSTWRITE);
2267                 }
2268                 if (++i == (HIFN_D_CMD_RSIZE + 1))
2269                         i = 0;
2270         }
2271         dma->cmdk = i; dma->cmdu = u;
2272
2273         HIFN_UNLOCK(sc);
2274
2275         if (sc->sc_needwakeup) {                /* XXX check high watermark */
2276                 int wakeup = sc->sc_needwakeup & (CRYPTO_SYMQ|CRYPTO_ASYMQ);
2277 #ifdef HIFN_DEBUG
2278                 if (hifn_debug)
2279                         device_printf(sc->sc_dev,
2280                                 "wakeup crypto (%x) u %d/%d/%d/%d\n",
2281                                 sc->sc_needwakeup,
2282                                 dma->cmdu, dma->srcu, dma->dstu, dma->resu);
2283 #endif
2284                 sc->sc_needwakeup &= ~wakeup;
2285                 crypto_unblock(sc->sc_cid, wakeup);
2286         }
2287 }
2288
2289 /*
2290  * Allocate a new 'session' and return an encoded session id.  'sidp'
2291  * contains our registration id, and should contain an encoded session
2292  * id on successful allocation.
2293  */
2294 static int
2295 hifn_newsession(void *arg, u_int32_t *sidp, struct cryptoini *cri)
2296 {
2297         struct cryptoini *c;
2298         struct hifn_softc *sc = arg;
2299         int mac = 0, cry = 0, sesn;
2300         struct hifn_session *ses = NULL;
2301
2302         KASSERT(sc != NULL, ("hifn_newsession: null softc"));
2303         if (sidp == NULL || cri == NULL || sc == NULL)
2304                 return (EINVAL);
2305
2306         if (sc->sc_sessions == NULL) {
2307                 ses = sc->sc_sessions = (struct hifn_session *)malloc(
2308                     sizeof(*ses), M_DEVBUF, M_NOWAIT);
2309                 if (ses == NULL)
2310                         return (ENOMEM);
2311                 sesn = 0;
2312                 sc->sc_nsessions = 1;
2313         } else {
2314                 for (sesn = 0; sesn < sc->sc_nsessions; sesn++) {
2315                         if (!sc->sc_sessions[sesn].hs_used) {
2316                                 ses = &sc->sc_sessions[sesn];
2317                                 break;
2318                         }
2319                 }
2320
2321                 if (ses == NULL) {
2322                         sesn = sc->sc_nsessions;
2323                         ses = (struct hifn_session *)malloc((sesn + 1) *
2324                             sizeof(*ses), M_DEVBUF, M_NOWAIT);
2325                         if (ses == NULL)
2326                                 return (ENOMEM);
2327                         bcopy(sc->sc_sessions, ses, sesn * sizeof(*ses));
2328                         bzero(sc->sc_sessions, sesn * sizeof(*ses));
2329                         free(sc->sc_sessions, M_DEVBUF);
2330                         sc->sc_sessions = ses;
2331                         ses = &sc->sc_sessions[sesn];
2332                         sc->sc_nsessions++;
2333                 }
2334         }
2335         bzero(ses, sizeof(*ses));
2336         ses->hs_used = 1;
2337
2338         for (c = cri; c != NULL; c = c->cri_next) {
2339                 switch (c->cri_alg) {
2340                 case CRYPTO_MD5:
2341                 case CRYPTO_SHA1:
2342                 case CRYPTO_MD5_HMAC:
2343                 case CRYPTO_SHA1_HMAC:
2344                         if (mac)
2345                                 return (EINVAL);
2346                         mac = 1;
2347                         ses->hs_mlen = c->cri_mlen;
2348                         if (ses->hs_mlen == 0) {
2349                                 switch (c->cri_alg) {
2350                                 case CRYPTO_MD5:
2351                                 case CRYPTO_MD5_HMAC:
2352                                         ses->hs_mlen = 16;
2353                                         break;
2354                                 case CRYPTO_SHA1:
2355                                 case CRYPTO_SHA1_HMAC:
2356                                         ses->hs_mlen = 20;
2357                                         break;
2358                                 }
2359                         }
2360                         break;
2361                 case CRYPTO_DES_CBC:
2362                 case CRYPTO_3DES_CBC:
2363                 case CRYPTO_AES_CBC:
2364                         /* XXX this may read fewer, does it matter? */
2365                         read_random(ses->hs_iv,
2366                                 c->cri_alg == CRYPTO_AES_CBC ?
2367                                         HIFN_AES_IV_LENGTH : HIFN_IV_LENGTH);
2368                         /*FALLTHROUGH*/
2369                 case CRYPTO_ARC4:
2370                         if (cry)
2371                                 return (EINVAL);
2372                         cry = 1;
2373                         break;
2374                 default:
2375                         return (EINVAL);
2376                 }
2377         }
2378         if (mac == 0 && cry == 0)
2379                 return (EINVAL);
2380
2381         *sidp = HIFN_SID(device_get_unit(sc->sc_dev), sesn);
2382
2383         return (0);
2384 }
2385
2386 /*
2387  * Deallocate a session.
2388  * XXX this routine should run a zero'd mac/encrypt key into context ram.
2389  * XXX to blow away any keys already stored there.
2390  */
2391 static int
2392 hifn_freesession(void *arg, u_int64_t tid)
2393 {
2394         struct hifn_softc *sc = arg;
2395         int session;
2396         u_int32_t sid = CRYPTO_SESID2LID(tid);
2397
2398         KASSERT(sc != NULL, ("hifn_freesession: null softc"));
2399         if (sc == NULL)
2400                 return (EINVAL);
2401
2402         session = HIFN_SESSION(sid);
2403         if (session >= sc->sc_nsessions)
2404                 return (EINVAL);
2405
2406         bzero(&sc->sc_sessions[session], sizeof(sc->sc_sessions[session]));
2407         return (0);
2408 }
2409
2410 static int
2411 hifn_process(void *arg, struct cryptop *crp, int hint)
2412 {
2413         struct hifn_softc *sc = arg;
2414         struct hifn_command *cmd = NULL;
2415         int session, err, ivlen;
2416         struct cryptodesc *crd1, *crd2, *maccrd, *enccrd;
2417
2418         if (crp == NULL || crp->crp_callback == NULL) {
2419                 hifnstats.hst_invalid++;
2420                 return (EINVAL);
2421         }
2422         session = HIFN_SESSION(crp->crp_sid);
2423
2424         if (sc == NULL || session >= sc->sc_nsessions) {
2425                 err = EINVAL;
2426                 goto errout;
2427         }
2428
2429         cmd = malloc(sizeof(struct hifn_command), M_DEVBUF, M_NOWAIT | M_ZERO);
2430         if (cmd == NULL) {
2431                 hifnstats.hst_nomem++;
2432                 err = ENOMEM;
2433                 goto errout;
2434         }
2435
2436         if (crp->crp_flags & CRYPTO_F_IMBUF) {
2437                 cmd->src_m = (struct mbuf *)crp->crp_buf;
2438                 cmd->dst_m = (struct mbuf *)crp->crp_buf;
2439         } else if (crp->crp_flags & CRYPTO_F_IOV) {
2440                 cmd->src_io = (struct uio *)crp->crp_buf;
2441                 cmd->dst_io = (struct uio *)crp->crp_buf;
2442         } else {
2443                 err = EINVAL;
2444                 goto errout;    /* XXX we don't handle contiguous buffers! */
2445         }
2446
2447         crd1 = crp->crp_desc;
2448         if (crd1 == NULL) {
2449                 err = EINVAL;
2450                 goto errout;
2451         }
2452         crd2 = crd1->crd_next;
2453
2454         if (crd2 == NULL) {
2455                 if (crd1->crd_alg == CRYPTO_MD5_HMAC ||
2456                     crd1->crd_alg == CRYPTO_SHA1_HMAC ||
2457                     crd1->crd_alg == CRYPTO_SHA1 ||
2458                     crd1->crd_alg == CRYPTO_MD5) {
2459                         maccrd = crd1;
2460                         enccrd = NULL;
2461                 } else if (crd1->crd_alg == CRYPTO_DES_CBC ||
2462                     crd1->crd_alg == CRYPTO_3DES_CBC ||
2463                     crd1->crd_alg == CRYPTO_AES_CBC ||
2464                     crd1->crd_alg == CRYPTO_ARC4) {
2465                         if ((crd1->crd_flags & CRD_F_ENCRYPT) == 0)
2466                                 cmd->base_masks |= HIFN_BASE_CMD_DECODE;
2467                         maccrd = NULL;
2468                         enccrd = crd1;
2469                 } else {
2470                         err = EINVAL;
2471                         goto errout;
2472                 }
2473         } else {
2474                 if ((crd1->crd_alg == CRYPTO_MD5_HMAC ||
2475                      crd1->crd_alg == CRYPTO_SHA1_HMAC ||
2476                      crd1->crd_alg == CRYPTO_MD5 ||
2477                      crd1->crd_alg == CRYPTO_SHA1) &&
2478                     (crd2->crd_alg == CRYPTO_DES_CBC ||
2479                      crd2->crd_alg == CRYPTO_3DES_CBC ||
2480                      crd2->crd_alg == CRYPTO_AES_CBC ||
2481                      crd2->crd_alg == CRYPTO_ARC4) &&
2482                     ((crd2->crd_flags & CRD_F_ENCRYPT) == 0)) {
2483                         cmd->base_masks = HIFN_BASE_CMD_DECODE;
2484                         maccrd = crd1;
2485                         enccrd = crd2;
2486                 } else if ((crd1->crd_alg == CRYPTO_DES_CBC ||
2487                      crd1->crd_alg == CRYPTO_ARC4 ||
2488                      crd1->crd_alg == CRYPTO_3DES_CBC ||
2489                      crd1->crd_alg == CRYPTO_AES_CBC) &&
2490                     (crd2->crd_alg == CRYPTO_MD5_HMAC ||
2491                      crd2->crd_alg == CRYPTO_SHA1_HMAC ||
2492                      crd2->crd_alg == CRYPTO_MD5 ||
2493                      crd2->crd_alg == CRYPTO_SHA1) &&
2494                     (crd1->crd_flags & CRD_F_ENCRYPT)) {
2495                         enccrd = crd1;
2496                         maccrd = crd2;
2497                 } else {
2498                         /*
2499                          * We cannot order the 7751 as requested
2500                          */
2501                         err = EINVAL;
2502                         goto errout;
2503                 }
2504         }
2505
2506         if (enccrd) {
2507                 cmd->enccrd = enccrd;
2508                 cmd->base_masks |= HIFN_BASE_CMD_CRYPT;
2509                 switch (enccrd->crd_alg) {
2510                 case CRYPTO_ARC4:
2511                         cmd->cry_masks |= HIFN_CRYPT_CMD_ALG_RC4;
2512                         break;
2513                 case CRYPTO_DES_CBC:
2514                         cmd->cry_masks |= HIFN_CRYPT_CMD_ALG_DES |
2515                             HIFN_CRYPT_CMD_MODE_CBC |
2516                             HIFN_CRYPT_CMD_NEW_IV;
2517                         break;
2518                 case CRYPTO_3DES_CBC:
2519                         cmd->cry_masks |= HIFN_CRYPT_CMD_ALG_3DES |
2520                             HIFN_CRYPT_CMD_MODE_CBC |
2521                             HIFN_CRYPT_CMD_NEW_IV;
2522                         break;
2523                 case CRYPTO_AES_CBC:
2524                         cmd->cry_masks |= HIFN_CRYPT_CMD_ALG_AES |
2525                             HIFN_CRYPT_CMD_MODE_CBC |
2526                             HIFN_CRYPT_CMD_NEW_IV;
2527                         break;
2528                 default:
2529                         err = EINVAL;
2530                         goto errout;
2531                 }
2532                 if (enccrd->crd_alg != CRYPTO_ARC4) {
2533                         ivlen = ((enccrd->crd_alg == CRYPTO_AES_CBC) ?
2534                                 HIFN_AES_IV_LENGTH : HIFN_IV_LENGTH);
2535                         if (enccrd->crd_flags & CRD_F_ENCRYPT) {
2536                                 if (enccrd->crd_flags & CRD_F_IV_EXPLICIT)
2537                                         bcopy(enccrd->crd_iv, cmd->iv, ivlen);
2538                                 else
2539                                         bcopy(sc->sc_sessions[session].hs_iv,
2540                                             cmd->iv, ivlen);
2541
2542                                 if ((enccrd->crd_flags & CRD_F_IV_PRESENT)
2543                                     == 0) {
2544                                         if (crp->crp_flags & CRYPTO_F_IMBUF)
2545                                                 m_copyback(cmd->src_m,
2546                                                     enccrd->crd_inject,
2547                                                     ivlen, cmd->iv);
2548                                         else if (crp->crp_flags & CRYPTO_F_IOV)
2549                                                 cuio_copyback(cmd->src_io,
2550                                                     enccrd->crd_inject,
2551                                                     ivlen, cmd->iv);
2552                                 }
2553                         } else {
2554                                 if (enccrd->crd_flags & CRD_F_IV_EXPLICIT)
2555                                         bcopy(enccrd->crd_iv, cmd->iv, ivlen);
2556                                 else if (crp->crp_flags & CRYPTO_F_IMBUF)
2557                                         m_copydata(cmd->src_m,
2558                                             enccrd->crd_inject, ivlen, cmd->iv);
2559                                 else if (crp->crp_flags & CRYPTO_F_IOV)
2560                                         cuio_copydata(cmd->src_io,
2561                                             enccrd->crd_inject, ivlen, cmd->iv);
2562                         }
2563                 }
2564
2565                 if (enccrd->crd_flags & CRD_F_KEY_EXPLICIT)
2566                         cmd->cry_masks |= HIFN_CRYPT_CMD_NEW_KEY;
2567                 cmd->ck = enccrd->crd_key;
2568                 cmd->cklen = enccrd->crd_klen >> 3;
2569                 cmd->cry_masks |= HIFN_CRYPT_CMD_NEW_KEY;
2570
2571                 /*
2572                  * Need to specify the size for the AES key in the masks.
2573                  */
2574                 if ((cmd->cry_masks & HIFN_CRYPT_CMD_ALG_MASK) ==
2575                     HIFN_CRYPT_CMD_ALG_AES) {
2576                         switch (cmd->cklen) {
2577                         case 16:
2578                                 cmd->cry_masks |= HIFN_CRYPT_CMD_KSZ_128;
2579                                 break;
2580                         case 24:
2581                                 cmd->cry_masks |= HIFN_CRYPT_CMD_KSZ_192;
2582                                 break;
2583                         case 32:
2584                                 cmd->cry_masks |= HIFN_CRYPT_CMD_KSZ_256;
2585                                 break;
2586                         default:
2587                                 err = EINVAL;
2588                                 goto errout;
2589                         }
2590                 }
2591         }
2592
2593         if (maccrd) {
2594                 cmd->maccrd = maccrd;
2595                 cmd->base_masks |= HIFN_BASE_CMD_MAC;
2596
2597                 switch (maccrd->crd_alg) {
2598                 case CRYPTO_MD5:
2599                         cmd->mac_masks |= HIFN_MAC_CMD_ALG_MD5 |
2600                             HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HASH |
2601                             HIFN_MAC_CMD_POS_IPSEC;
2602                        break;
2603                 case CRYPTO_MD5_HMAC:
2604                         cmd->mac_masks |= HIFN_MAC_CMD_ALG_MD5 |
2605                             HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HMAC |
2606                             HIFN_MAC_CMD_POS_IPSEC | HIFN_MAC_CMD_TRUNC;
2607                         break;
2608                 case CRYPTO_SHA1:
2609                         cmd->mac_masks |= HIFN_MAC_CMD_ALG_SHA1 |
2610                             HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HASH |
2611                             HIFN_MAC_CMD_POS_IPSEC;
2612                         break;
2613                 case CRYPTO_SHA1_HMAC:
2614                         cmd->mac_masks |= HIFN_MAC_CMD_ALG_SHA1 |
2615                             HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HMAC |
2616                             HIFN_MAC_CMD_POS_IPSEC | HIFN_MAC_CMD_TRUNC;
2617                         break;
2618                 }
2619
2620                 if (maccrd->crd_alg == CRYPTO_SHA1_HMAC ||
2621                      maccrd->crd_alg == CRYPTO_MD5_HMAC) {
2622                         cmd->mac_masks |= HIFN_MAC_CMD_NEW_KEY;
2623                         bcopy(maccrd->crd_key, cmd->mac, maccrd->crd_klen >> 3);
2624                         bzero(cmd->mac + (maccrd->crd_klen >> 3),
2625                             HIFN_MAC_KEY_LENGTH - (maccrd->crd_klen >> 3));
2626                 }
2627         }
2628
2629         cmd->crp = crp;
2630         cmd->session_num = session;
2631         cmd->softc = sc;
2632
2633         err = hifn_crypto(sc, cmd, crp, hint);
2634         if (!err) {
2635                 return 0;
2636         } else if (err == ERESTART) {
2637                 /*
2638                  * There weren't enough resources to dispatch the request
2639                  * to the part.  Notify the caller so they'll requeue this
2640                  * request and resubmit it again soon.
2641                  */
2642 #ifdef HIFN_DEBUG
2643                 if (hifn_debug)
2644                         device_printf(sc->sc_dev, "requeue request\n");
2645 #endif
2646                 free(cmd, M_DEVBUF);
2647                 sc->sc_needwakeup |= CRYPTO_SYMQ;
2648                 return (err);
2649         }
2650
2651 errout:
2652         if (cmd != NULL)
2653                 free(cmd, M_DEVBUF);
2654         if (err == EINVAL)
2655                 hifnstats.hst_invalid++;
2656         else
2657                 hifnstats.hst_nomem++;
2658         crp->crp_etype = err;
2659         crypto_done(crp);
2660         return (err);
2661 }
2662
2663 static void
2664 hifn_abort(struct hifn_softc *sc)
2665 {
2666         struct hifn_dma *dma = sc->sc_dma;
2667         struct hifn_command *cmd;
2668         struct cryptop *crp;
2669         int i, u;
2670
2671         i = dma->resk; u = dma->resu;
2672         while (u != 0) {
2673                 cmd = dma->hifn_commands[i];
2674                 KASSERT(cmd != NULL, ("hifn_abort: null command slot %u", i));
2675                 dma->hifn_commands[i] = NULL;
2676                 crp = cmd->crp;
2677
2678                 if ((dma->resr[i].l & htole32(HIFN_D_VALID)) == 0) {
2679                         /* Salvage what we can. */
2680                         u_int8_t *macbuf;
2681
2682                         if (cmd->base_masks & HIFN_BASE_CMD_MAC) {
2683                                 macbuf = dma->result_bufs[i];
2684                                 macbuf += 12;
2685                         } else
2686                                 macbuf = NULL;
2687                         hifnstats.hst_opackets++;
2688                         hifn_callback(sc, cmd, macbuf);
2689                 } else {
2690                         if (cmd->src_map == cmd->dst_map) {
2691                                 bus_dmamap_sync(sc->sc_dmat, cmd->src_map,
2692                                     BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
2693                         } else {
2694                                 bus_dmamap_sync(sc->sc_dmat, cmd->src_map,
2695                                     BUS_DMASYNC_POSTWRITE);
2696                                 bus_dmamap_sync(sc->sc_dmat, cmd->dst_map,
2697                                     BUS_DMASYNC_POSTREAD);
2698                         }
2699
2700                         if (cmd->src_m != cmd->dst_m) {
2701                                 m_freem(cmd->src_m);
2702                                 crp->crp_buf = (caddr_t)cmd->dst_m;
2703                         }
2704
2705                         /* non-shared buffers cannot be restarted */
2706                         if (cmd->src_map != cmd->dst_map) {
2707                                 /*
2708                                  * XXX should be EAGAIN, delayed until
2709                                  * after the reset.
2710                                  */
2711                                 crp->crp_etype = ENOMEM;
2712                                 bus_dmamap_unload(sc->sc_dmat, cmd->dst_map);
2713                                 bus_dmamap_destroy(sc->sc_dmat, cmd->dst_map);
2714                         } else
2715                                 crp->crp_etype = ENOMEM;
2716
2717                         bus_dmamap_unload(sc->sc_dmat, cmd->src_map);
2718                         bus_dmamap_destroy(sc->sc_dmat, cmd->src_map);
2719
2720                         free(cmd, M_DEVBUF);
2721                         if (crp->crp_etype != EAGAIN)
2722                                 crypto_done(crp);
2723                 }
2724
2725                 if (++i == HIFN_D_RES_RSIZE)
2726                         i = 0;
2727                 u--;
2728         }
2729         dma->resk = i; dma->resu = u;
2730
2731         hifn_reset_board(sc, 1);
2732         hifn_init_dma(sc);
2733         hifn_init_pci_registers(sc);
2734 }
2735
2736 static void
2737 hifn_callback(struct hifn_softc *sc, struct hifn_command *cmd, u_int8_t *macbuf)
2738 {
2739         struct hifn_dma *dma = sc->sc_dma;
2740         struct cryptop *crp = cmd->crp;
2741         struct cryptodesc *crd;
2742         struct mbuf *m;
2743         int totlen, i, u, ivlen;
2744
2745         if (cmd->src_map == cmd->dst_map) {
2746                 bus_dmamap_sync(sc->sc_dmat, cmd->src_map,
2747                     BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
2748         } else {
2749                 bus_dmamap_sync(sc->sc_dmat, cmd->src_map,
2750                     BUS_DMASYNC_POSTWRITE);
2751                 bus_dmamap_sync(sc->sc_dmat, cmd->dst_map,
2752                     BUS_DMASYNC_POSTREAD);
2753         }
2754
2755         if (crp->crp_flags & CRYPTO_F_IMBUF) {
2756                 if (cmd->src_m != cmd->dst_m) {
2757                         crp->crp_buf = (caddr_t)cmd->dst_m;
2758                         totlen = cmd->src_mapsize;
2759                         for (m = cmd->dst_m; m != NULL; m = m->m_next) {
2760                                 if (totlen < m->m_len) {
2761                                         m->m_len = totlen;
2762                                         totlen = 0;
2763                                 } else
2764                                         totlen -= m->m_len;
2765                         }
2766                         cmd->dst_m->m_pkthdr.len = cmd->src_m->m_pkthdr.len;
2767                         m_freem(cmd->src_m);
2768                 }
2769         }
2770
2771         if (cmd->sloplen != 0) {
2772                 if (crp->crp_flags & CRYPTO_F_IMBUF)
2773                         m_copyback((struct mbuf *)crp->crp_buf,
2774                             cmd->src_mapsize - cmd->sloplen,
2775                             cmd->sloplen, (caddr_t)&dma->slop[cmd->slopidx]);
2776                 else if (crp->crp_flags & CRYPTO_F_IOV)
2777                         cuio_copyback((struct uio *)crp->crp_buf,
2778                             cmd->src_mapsize - cmd->sloplen,
2779                             cmd->sloplen, (caddr_t)&dma->slop[cmd->slopidx]);
2780         }
2781
2782         i = dma->dstk; u = dma->dstu;
2783         while (u != 0) {
2784                 if (i == HIFN_D_DST_RSIZE)
2785                         i = 0;
2786                 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap,
2787                     BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2788                 if (dma->dstr[i].l & htole32(HIFN_D_VALID)) {
2789                         bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap,
2790                             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2791                         break;
2792                 }
2793                 i++, u--;
2794         }
2795         dma->dstk = i; dma->dstu = u;
2796
2797         hifnstats.hst_obytes += cmd->dst_mapsize;
2798
2799         if ((cmd->base_masks & (HIFN_BASE_CMD_CRYPT | HIFN_BASE_CMD_DECODE)) ==
2800             HIFN_BASE_CMD_CRYPT) {
2801                 for (crd = crp->crp_desc; crd; crd = crd->crd_next) {
2802                         if (crd->crd_alg != CRYPTO_DES_CBC &&
2803                             crd->crd_alg != CRYPTO_3DES_CBC &&
2804                             crd->crd_alg != CRYPTO_AES_CBC)
2805                                 continue;
2806                         ivlen = ((crd->crd_alg == CRYPTO_AES_CBC) ?
2807                                 HIFN_AES_IV_LENGTH : HIFN_IV_LENGTH);
2808                         if (crp->crp_flags & CRYPTO_F_IMBUF)
2809                                 m_copydata((struct mbuf *)crp->crp_buf,
2810                                     crd->crd_skip + crd->crd_len - ivlen, ivlen,
2811                                     cmd->softc->sc_sessions[cmd->session_num].hs_iv);
2812                         else if (crp->crp_flags & CRYPTO_F_IOV) {
2813                                 cuio_copydata((struct uio *)crp->crp_buf,
2814                                     crd->crd_skip + crd->crd_len - ivlen, ivlen,
2815                                     cmd->softc->sc_sessions[cmd->session_num].hs_iv);
2816                         }
2817                         break;
2818                 }
2819         }
2820
2821         if (macbuf != NULL) {
2822                 for (crd = crp->crp_desc; crd; crd = crd->crd_next) {
2823                         int len;
2824
2825                         if (crd->crd_alg != CRYPTO_MD5 &&
2826                             crd->crd_alg != CRYPTO_SHA1 &&
2827                             crd->crd_alg != CRYPTO_MD5_HMAC &&
2828                             crd->crd_alg != CRYPTO_SHA1_HMAC) {
2829                                 continue;
2830                         }
2831                         len = cmd->softc->sc_sessions[cmd->session_num].hs_mlen;
2832                         if (crp->crp_flags & CRYPTO_F_IMBUF)
2833                                 m_copyback((struct mbuf *)crp->crp_buf,
2834                                    crd->crd_inject, len, macbuf);
2835                         else if ((crp->crp_flags & CRYPTO_F_IOV) && crp->crp_mac)
2836                                 bcopy((caddr_t)macbuf, crp->crp_mac, len);
2837                         break;
2838                 }
2839         }
2840
2841         if (cmd->src_map != cmd->dst_map) {
2842                 bus_dmamap_unload(sc->sc_dmat, cmd->dst_map);
2843                 bus_dmamap_destroy(sc->sc_dmat, cmd->dst_map);
2844         }
2845         bus_dmamap_unload(sc->sc_dmat, cmd->src_map);
2846         bus_dmamap_destroy(sc->sc_dmat, cmd->src_map);
2847         free(cmd, M_DEVBUF);
2848         crypto_done(crp);
2849 }
2850
2851 /*
2852  * 7811 PB3 rev/2 parts lock-up on burst writes to Group 0
2853  * and Group 1 registers; avoid conditions that could create
2854  * burst writes by doing a read in between the writes.
2855  *
2856  * NB: The read we interpose is always to the same register;
2857  *     we do this because reading from an arbitrary (e.g. last)
2858  *     register may not always work.
2859  */
2860 static void
2861 hifn_write_reg_0(struct hifn_softc *sc, bus_size_t reg, u_int32_t val)
2862 {
2863         if (sc->sc_flags & HIFN_IS_7811) {
2864                 if (sc->sc_bar0_lastreg == reg - 4)
2865                         bus_space_read_4(sc->sc_st0, sc->sc_sh0, HIFN_0_PUCNFG);
2866                 sc->sc_bar0_lastreg = reg;
2867         }
2868         bus_space_write_4(sc->sc_st0, sc->sc_sh0, reg, val);
2869 }
2870
2871 static void
2872 hifn_write_reg_1(struct hifn_softc *sc, bus_size_t reg, u_int32_t val)
2873 {
2874         if (sc->sc_flags & HIFN_IS_7811) {
2875                 if (sc->sc_bar1_lastreg == reg - 4)
2876                         bus_space_read_4(sc->sc_st1, sc->sc_sh1, HIFN_1_REVID);
2877                 sc->sc_bar1_lastreg = reg;
2878         }
2879         bus_space_write_4(sc->sc_st1, sc->sc_sh1, reg, val);
2880 }