sys/dev/hifn/hifn7751.c

   1 /*      $OpenBSD: hifn7751.c,v 1.120 2002/05/17 00:33:34 deraadt Exp $  */
   2
   3 /*-
   4  * Invertex AEON / Hifn 7751 driver
   5  * Copyright (c) 1999 Invertex Inc. All rights reserved.
   6  * Copyright (c) 1999 Theo de Raadt
   7  * Copyright (c) 2000-2001 Network Security Technologies, Inc.
   8  *                      http://www.netsec.net
   9  * Copyright (c) 2003 Hifn Inc.
  10  *
  11  * This driver is based on a previous driver by Invertex, for which they
  12  * requested:  Please send any comments, feedback, bug-fixes, or feature
  13  * requests to software@invertex.com.
  14  *
  15  * Redistribution and use in source and binary forms, with or without
  16  * modification, are permitted provided that the following conditions
  17  * are met:
  18  *
  19  * 1. Redistributions of source code must retain the above copyright
  20  *   notice, this list of conditions and the following disclaimer.
  21  * 2. Redistributions in binary form must reproduce the above copyright
  22  *   notice, this list of conditions and the following disclaimer in the
  23  *   documentation and/or other materials provided with the distribution.
  24  * 3. The name of the author may not be used to endorse or promote products
  25  *   derived from this software without specific prior written permission.
  26  *
  27  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  28  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  29  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  30  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  31  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  32  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  33  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  34  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  35  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  36  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  37  *
  38  * Effort sponsored in part by the Defense Advanced Research Projects
  39  * Agency (DARPA) and Air Force Research Laboratory, Air Force
  40  * Materiel Command, USAF, under agreement number F30602-01-2-0537.
  41  */
  42
  43 #include <sys/cdefs.h>
  44 __FBSDID("$FreeBSD$");
  45
  46 /*
  47  * Driver for various Hifn encryption processors.
  48  */
  49 #include "opt_hifn.h"
  50
  51 #include <sys/param.h>
  52 #include <sys/systm.h>
  53 #include <sys/proc.h>
  54 #include <sys/errno.h>
  55 #include <sys/malloc.h>
  56 #include <sys/kernel.h>
  57 #include <sys/module.h>
  58 #include <sys/mbuf.h>
  59 #include <sys/lock.h>
  60 #include <sys/mutex.h>
  61 #include <sys/sysctl.h>
  62
  63 #include <vm/vm.h>
  64 #include <vm/pmap.h>
  65
  66 #include <machine/bus.h>
  67 #include <machine/resource.h>
  68 #include <sys/bus.h>
  69 #include <sys/rman.h>
  70
  71 #include <opencrypto/cryptodev.h>
  72 #include <sys/random.h>
  73 #include <sys/kobj.h>
  74
  75 #include "cryptodev_if.h"
  76
  77 #include <dev/pci/pcivar.h>
  78 #include <dev/pci/pcireg.h>
  79
  80 #ifdef HIFN_RNDTEST
  81 #include <dev/rndtest/rndtest.h>
  82 #endif
  83 #include <dev/hifn/hifn7751reg.h>
  84 #include <dev/hifn/hifn7751var.h>
  85
  86 #ifdef HIFN_VULCANDEV
  87 #include <sys/conf.h>
  88 #include <sys/uio.h>
  89
  90 static struct cdevsw vulcanpk_cdevsw; /* forward declaration */
  91 #endif
  92
  93 /*
  94  * Prototypes and count for the pci_device structure
  95  */
  96 static  int hifn_probe(device_t);
  97 static  int hifn_attach(device_t);
  98 static  int hifn_detach(device_t);
  99 static  int hifn_suspend(device_t);
 100 static  int hifn_resume(device_t);
 101 static  int hifn_shutdown(device_t);
 102
 103 static  int hifn_newsession(device_t, u_int32_t *, struct cryptoini *);
 104 static  int hifn_freesession(device_t, u_int64_t);
 105 static  int hifn_process(device_t, struct cryptop *, int);
 106
 107 static device_method_t hifn_methods[] = {
 108         /* Device interface */
 109         DEVMETHOD(device_probe,         hifn_probe),
 110         DEVMETHOD(device_attach,        hifn_attach),
 111         DEVMETHOD(device_detach,        hifn_detach),
 112         DEVMETHOD(device_suspend,       hifn_suspend),
 113         DEVMETHOD(device_resume,        hifn_resume),
 114         DEVMETHOD(device_shutdown,      hifn_shutdown),
 115
 116         /* crypto device methods */
 117         DEVMETHOD(cryptodev_newsession, hifn_newsession),
 118         DEVMETHOD(cryptodev_freesession,hifn_freesession),
 119         DEVMETHOD(cryptodev_process,    hifn_process),
 120
 121         DEVMETHOD_END
 122 };
 123 static driver_t hifn_driver = {
 124         "hifn",
 125         hifn_methods,
 126         sizeof (struct hifn_softc)
 127 };
 128 static devclass_t hifn_devclass;
 129
 130 DRIVER_MODULE(hifn, pci, hifn_driver, hifn_devclass, 0, 0);
 131 MODULE_DEPEND(hifn, crypto, 1, 1, 1);
 132 #ifdef HIFN_RNDTEST
 133 MODULE_DEPEND(hifn, rndtest, 1, 1, 1);
 134 #endif
 135
 136 static  void hifn_reset_board(struct hifn_softc *, int);
 137 static  void hifn_reset_puc(struct hifn_softc *);
 138 static  void hifn_puc_wait(struct hifn_softc *);
 139 static  int hifn_enable_crypto(struct hifn_softc *);
 140 static  void hifn_set_retry(struct hifn_softc *sc);
 141 static  void hifn_init_dma(struct hifn_softc *);
 142 static  void hifn_init_pci_registers(struct hifn_softc *);
 143 static  int hifn_sramsize(struct hifn_softc *);
 144 static  int hifn_dramsize(struct hifn_softc *);
 145 static  int hifn_ramtype(struct hifn_softc *);
 146 static  void hifn_sessions(struct hifn_softc *);
 147 static  void hifn_intr(void *);
 148 static  u_int hifn_write_command(struct hifn_command *, u_int8_t *);
 149 static  u_int32_t hifn_next_signature(u_int32_t a, u_int cnt);
 150 static  void hifn_callback(struct hifn_softc *, struct hifn_command *, u_int8_t *);
 151 static  int hifn_crypto(struct hifn_softc *, struct hifn_command *, struct cryptop *, int);
 152 static  int hifn_readramaddr(struct hifn_softc *, int, u_int8_t *);
 153 static  int hifn_writeramaddr(struct hifn_softc *, int, u_int8_t *);
 154 static  int hifn_dmamap_load_src(struct hifn_softc *, struct hifn_command *);
 155 static  int hifn_dmamap_load_dst(struct hifn_softc *, struct hifn_command *);
 156 static  int hifn_init_pubrng(struct hifn_softc *);
 157 static  void hifn_rng(void *);
 158 static  void hifn_tick(void *);
 159 static  void hifn_abort(struct hifn_softc *);
 160 static  void hifn_alloc_slot(struct hifn_softc *, int *, int *, int *, int *);
 161
 162 static  void hifn_write_reg_0(struct hifn_softc *, bus_size_t, u_int32_t);
 163 static  void hifn_write_reg_1(struct hifn_softc *, bus_size_t, u_int32_t);
 164
 165 static __inline u_int32_t
 166 READ_REG_0(struct hifn_softc *sc, bus_size_t reg)
 167 {
 168     u_int32_t v = bus_space_read_4(sc->sc_st0, sc->sc_sh0, reg);
 169     sc->sc_bar0_lastreg = (bus_size_t) -1;
 170     return (v);
 171 }
 172 #define WRITE_REG_0(sc, reg, val)       hifn_write_reg_0(sc, reg, val)
 173
 174 static __inline u_int32_t
 175 READ_REG_1(struct hifn_softc *sc, bus_size_t reg)
 176 {
 177     u_int32_t v = bus_space_read_4(sc->sc_st1, sc->sc_sh1, reg);
 178     sc->sc_bar1_lastreg = (bus_size_t) -1;
 179     return (v);
 180 }
 181 #define WRITE_REG_1(sc, reg, val)       hifn_write_reg_1(sc, reg, val)
 182
 183 static SYSCTL_NODE(_hw, OID_AUTO, hifn, CTLFLAG_RD, 0,
 184             "Hifn driver parameters");
 185
 186 #ifdef HIFN_DEBUG
 187 static  int hifn_debug = 0;
 188 SYSCTL_INT(_hw_hifn, OID_AUTO, debug, CTLFLAG_RW, &hifn_debug,
 189             0, "control debugging msgs");
 190 #endif
 191
 192 static  struct hifn_stats hifnstats;
 193 SYSCTL_STRUCT(_hw_hifn, OID_AUTO, stats, CTLFLAG_RD, &hifnstats,
 194             hifn_stats, "driver statistics");
 195 static  int hifn_maxbatch = 1;
 196 SYSCTL_INT(_hw_hifn, OID_AUTO, maxbatch, CTLFLAG_RW, &hifn_maxbatch,
 197             0, "max ops to batch w/o interrupt");
 198
 199 /*
 200  * Probe for a supported device.  The PCI vendor and device
 201  * IDs are used to detect devices we know how to handle.
 202  */
 203 static int
 204 hifn_probe(device_t dev)
 205 {
 206         if (pci_get_vendor(dev) == PCI_VENDOR_INVERTEX &&
 207             pci_get_device(dev) == PCI_PRODUCT_INVERTEX_AEON)
 208                 return (BUS_PROBE_DEFAULT);
 209         if (pci_get_vendor(dev) == PCI_VENDOR_HIFN &&
 210             (pci_get_device(dev) == PCI_PRODUCT_HIFN_7751 ||
 211              pci_get_device(dev) == PCI_PRODUCT_HIFN_7951 ||
 212              pci_get_device(dev) == PCI_PRODUCT_HIFN_7955 ||
 213              pci_get_device(dev) == PCI_PRODUCT_HIFN_7956 ||
 214              pci_get_device(dev) == PCI_PRODUCT_HIFN_7811))
 215                 return (BUS_PROBE_DEFAULT);
 216         if (pci_get_vendor(dev) == PCI_VENDOR_NETSEC &&
 217             pci_get_device(dev) == PCI_PRODUCT_NETSEC_7751)
 218                 return (BUS_PROBE_DEFAULT);
 219         return (ENXIO);
 220 }
 221
 222 static void
 223 hifn_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
 224 {
 225         bus_addr_t *paddr = (bus_addr_t*) arg;
 226         *paddr = segs->ds_addr;
 227 }
 228
 229 static const char*
 230 hifn_partname(struct hifn_softc *sc)
 231 {
 232         /* XXX sprintf numbers when not decoded */
 233         switch (pci_get_vendor(sc->sc_dev)) {
 234         case PCI_VENDOR_HIFN:
 235                 switch (pci_get_device(sc->sc_dev)) {
 236                 case PCI_PRODUCT_HIFN_6500:     return "Hifn 6500";
 237                 case PCI_PRODUCT_HIFN_7751:     return "Hifn 7751";
 238                 case PCI_PRODUCT_HIFN_7811:     return "Hifn 7811";
 239                 case PCI_PRODUCT_HIFN_7951:     return "Hifn 7951";
 240                 case PCI_PRODUCT_HIFN_7955:     return "Hifn 7955";
 241                 case PCI_PRODUCT_HIFN_7956:     return "Hifn 7956";
 242                 }
 243                 return "Hifn unknown-part";
 244         case PCI_VENDOR_INVERTEX:
 245                 switch (pci_get_device(sc->sc_dev)) {
 246                 case PCI_PRODUCT_INVERTEX_AEON: return "Invertex AEON";
 247                 }
 248                 return "Invertex unknown-part";
 249         case PCI_VENDOR_NETSEC:
 250                 switch (pci_get_device(sc->sc_dev)) {
 251                 case PCI_PRODUCT_NETSEC_7751:   return "NetSec 7751";
 252                 }
 253                 return "NetSec unknown-part";
 254         }
 255         return "Unknown-vendor unknown-part";
 256 }
 257
 258 static void
 259 default_harvest(struct rndtest_state *rsp, void *buf, u_int count)
 260 {
 261         random_harvest(buf, count, count*NBBY/2, RANDOM_PURE_HIFN);
 262 }
 263
 264 static u_int
 265 checkmaxmin(device_t dev, const char *what, u_int v, u_int min, u_int max)
 266 {
 267         if (v > max) {
 268                 device_printf(dev, "Warning, %s %u out of range, "
 269                         "using max %u\n", what, v, max);
 270                 v = max;
 271         } else if (v < min) {
 272                 device_printf(dev, "Warning, %s %u out of range, "
 273                         "using min %u\n", what, v, min);
 274                 v = min;
 275         }
 276         return v;
 277 }
 278
 279 /*
 280  * Select PLL configuration for 795x parts.  This is complicated in
 281  * that we cannot determine the optimal parameters without user input.
 282  * The reference clock is derived from an external clock through a
 283  * multiplier.  The external clock is either the host bus (i.e. PCI)
 284  * or an external clock generator.  When using the PCI bus we assume
 285  * the clock is either 33 or 66 MHz; for an external source we cannot
 286  * tell the speed.
 287  *
 288  * PLL configuration is done with a string: "pci" for PCI bus, or "ext"
 289  * for an external source, followed by the frequency.  We calculate
 290  * the appropriate multiplier and PLL register contents accordingly.
 291  * When no configuration is given we default to "pci66" since that
 292  * always will allow the card to work.  If a card is using the PCI
 293  * bus clock and in a 33MHz slot then it will be operating at half
 294  * speed until the correct information is provided.
 295  *
 296  * We use a default setting of "ext66" because according to Mike Ham
 297  * of HiFn, almost every board in existence has an external crystal
 298  * populated at 66Mhz. Using PCI can be a problem on modern motherboards,
 299  * because PCI33 can have clocks from 0 to 33Mhz, and some have
 300  * non-PCI-compliant spread-spectrum clocks, which can confuse the pll.
 301  */
 302 static void
 303 hifn_getpllconfig(device_t dev, u_int *pll)
 304 {
 305         const char *pllspec;
 306         u_int freq, mul, fl, fh;
 307         u_int32_t pllconfig;
 308         char *nxt;
 309
 310         if (resource_string_value("hifn", device_get_unit(dev),
 311             "pllconfig", &pllspec))
 312                 pllspec = "ext66";
 313         fl = 33, fh = 66;
 314         pllconfig = 0;
 315         if (strncmp(pllspec, "ext", 3) == 0) {
 316                 pllspec += 3;
 317                 pllconfig |= HIFN_PLL_REF_SEL;
 318                 switch (pci_get_device(dev)) {
 319                 case PCI_PRODUCT_HIFN_7955:
 320                 case PCI_PRODUCT_HIFN_7956:
 321                         fl = 20, fh = 100;
 322                         break;
 323 #ifdef notyet
 324                 case PCI_PRODUCT_HIFN_7954:
 325                         fl = 20, fh = 66;
 326                         break;
 327 #endif
 328                 }
 329         } else if (strncmp(pllspec, "pci", 3) == 0)
 330                 pllspec += 3;
 331         freq = strtoul(pllspec, &nxt, 10);
 332         if (nxt == pllspec)
 333                 freq = 66;
 334         else
 335                 freq = checkmaxmin(dev, "frequency", freq, fl, fh);
 336         /*
 337          * Calculate multiplier.  We target a Fck of 266 MHz,
 338          * allowing only even values, possibly rounded down.
 339          * Multipliers > 8 must set the charge pump current.
 340          */
 341         mul = checkmaxmin(dev, "PLL divisor", (266 / freq) &~ 1, 2, 12);
 342         pllconfig |= (mul / 2 - 1) << HIFN_PLL_ND_SHIFT;
 343         if (mul > 8)
 344                 pllconfig |= HIFN_PLL_IS;
 345         *pll = pllconfig;
 346 }
 347
 348 /*
 349  * Attach an interface that successfully probed.
 350  */
 351 static int
 352 hifn_attach(device_t dev)
 353 {
 354         struct hifn_softc *sc = device_get_softc(dev);
 355         caddr_t kva;
 356         int rseg, rid;
 357         char rbase;
 358         u_int16_t ena, rev;
 359
 360         sc->sc_dev = dev;
 361
 362         mtx_init(&sc->sc_mtx, device_get_nameunit(dev), "hifn driver", MTX_DEF);
 363
 364         /* XXX handle power management */
 365
 366         /*
 367          * The 7951 and 795x have a random number generator and
 368          * public key support; note this.
 369          */
 370         if (pci_get_vendor(dev) == PCI_VENDOR_HIFN &&
 371             (pci_get_device(dev) == PCI_PRODUCT_HIFN_7951 ||
 372              pci_get_device(dev) == PCI_PRODUCT_HIFN_7955 ||
 373              pci_get_device(dev) == PCI_PRODUCT_HIFN_7956))
 374                 sc->sc_flags = HIFN_HAS_RNG | HIFN_HAS_PUBLIC;
 375         /*
 376          * The 7811 has a random number generator and
 377          * we also note it's identity 'cuz of some quirks.
 378          */
 379         if (pci_get_vendor(dev) == PCI_VENDOR_HIFN &&
 380             pci_get_device(dev) == PCI_PRODUCT_HIFN_7811)
 381                 sc->sc_flags |= HIFN_IS_7811 | HIFN_HAS_RNG;
 382
 383         /*
 384          * The 795x parts support AES.
 385          */
 386         if (pci_get_vendor(dev) == PCI_VENDOR_HIFN &&
 387             (pci_get_device(dev) == PCI_PRODUCT_HIFN_7955 ||
 388              pci_get_device(dev) == PCI_PRODUCT_HIFN_7956)) {
 389                 sc->sc_flags |= HIFN_IS_7956 | HIFN_HAS_AES;
 390                 /*
 391                  * Select PLL configuration.  This depends on the
 392                  * bus and board design and must be manually configured
 393                  * if the default setting is unacceptable.
 394                  */
 395                 hifn_getpllconfig(dev, &sc->sc_pllconfig);
 396         }
 397
 398         /*
 399          * Setup PCI resources. Note that we record the bus
 400          * tag and handle for each register mapping, this is
 401          * used by the READ_REG_0, WRITE_REG_0, READ_REG_1,
 402          * and WRITE_REG_1 macros throughout the driver.
 403          */
 404         pci_enable_busmaster(dev);
 405
 406         rid = HIFN_BAR0;
 407         sc->sc_bar0res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
 408                                                 RF_ACTIVE);
 409         if (sc->sc_bar0res == NULL) {
 410                 device_printf(dev, "cannot map bar%d register space\n", 0);
 411                 goto fail_pci;
 412         }
 413         sc->sc_st0 = rman_get_bustag(sc->sc_bar0res);
 414         sc->sc_sh0 = rman_get_bushandle(sc->sc_bar0res);
 415         sc->sc_bar0_lastreg = (bus_size_t) -1;
 416
 417         rid = HIFN_BAR1;
 418         sc->sc_bar1res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
 419                                                 RF_ACTIVE);
 420         if (sc->sc_bar1res == NULL) {
 421                 device_printf(dev, "cannot map bar%d register space\n", 1);
 422                 goto fail_io0;
 423         }
 424         sc->sc_st1 = rman_get_bustag(sc->sc_bar1res);
 425         sc->sc_sh1 = rman_get_bushandle(sc->sc_bar1res);
 426         sc->sc_bar1_lastreg = (bus_size_t) -1;
 427
 428         hifn_set_retry(sc);
 429
 430         /*
 431          * Setup the area where the Hifn DMA's descriptors
 432          * and associated data structures.
 433          */
 434         if (bus_dma_tag_create(bus_get_dma_tag(dev),    /* PCI parent */
 435                                1, 0,                    /* alignment,boundary */
 436                                BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
 437                                BUS_SPACE_MAXADDR,       /* highaddr */
 438                                NULL, NULL,              /* filter, filterarg */
 439                                HIFN_MAX_DMALEN,         /* maxsize */
 440                                MAX_SCATTER,             /* nsegments */
 441                                HIFN_MAX_SEGLEN,         /* maxsegsize */
 442                                BUS_DMA_ALLOCNOW,        /* flags */
 443                                NULL,                    /* lockfunc */
 444                                NULL,                    /* lockarg */
 445                                &sc->sc_dmat)) {
 446                 device_printf(dev, "cannot allocate DMA tag\n");
 447                 goto fail_io1;
 448         }
 449         if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, &sc->sc_dmamap)) {
 450                 device_printf(dev, "cannot create dma map\n");
 451                 bus_dma_tag_destroy(sc->sc_dmat);
 452                 goto fail_io1;
 453         }
 454         if (bus_dmamem_alloc(sc->sc_dmat, (void**) &kva, BUS_DMA_NOWAIT, &sc->sc_dmamap)) {
 455                 device_printf(dev, "cannot alloc dma buffer\n");
 456                 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap);
 457                 bus_dma_tag_destroy(sc->sc_dmat);
 458                 goto fail_io1;
 459         }
 460         if (bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, kva,
 461                              sizeof (*sc->sc_dma),
 462                              hifn_dmamap_cb, &sc->sc_dma_physaddr,
 463                              BUS_DMA_NOWAIT)) {
 464                 device_printf(dev, "cannot load dma map\n");
 465                 bus_dmamem_free(sc->sc_dmat, kva, sc->sc_dmamap);
 466                 bus_dma_tag_destroy(sc->sc_dmat);
 467                 goto fail_io1;
 468         }
 469         sc->sc_dma = (struct hifn_dma *)kva;
 470         bzero(sc->sc_dma, sizeof(*sc->sc_dma));
 471
 472         KASSERT(sc->sc_st0 != 0, ("hifn_attach: null bar0 tag!"));
 473         KASSERT(sc->sc_sh0 != 0, ("hifn_attach: null bar0 handle!"));
 474         KASSERT(sc->sc_st1 != 0, ("hifn_attach: null bar1 tag!"));
 475         KASSERT(sc->sc_sh1 != 0, ("hifn_attach: null bar1 handle!"));
 476
 477         /*
 478          * Reset the board and do the ``secret handshake''
 479          * to enable the crypto support.  Then complete the
 480          * initialization procedure by setting up the interrupt
 481          * and hooking in to the system crypto support so we'll
 482          * get used for system services like the crypto device,
 483          * IPsec, RNG device, etc.
 484          */
 485         hifn_reset_board(sc, 0);
 486
 487         if (hifn_enable_crypto(sc) != 0) {
 488                 device_printf(dev, "crypto enabling failed\n");
 489                 goto fail_mem;
 490         }
 491         hifn_reset_puc(sc);
 492
 493         hifn_init_dma(sc);
 494         hifn_init_pci_registers(sc);
 495
 496         /* XXX can't dynamically determine ram type for 795x; force dram */
 497         if (sc->sc_flags & HIFN_IS_7956)
 498                 sc->sc_drammodel = 1;
 499         else if (hifn_ramtype(sc))
 500                 goto fail_mem;
 501
 502         if (sc->sc_drammodel == 0)
 503                 hifn_sramsize(sc);
 504         else
 505                 hifn_dramsize(sc);
 506
 507         /*
 508          * Workaround for NetSec 7751 rev A: half ram size because two
 509          * of the address lines were left floating
 510          */
 511         if (pci_get_vendor(dev) == PCI_VENDOR_NETSEC &&
 512             pci_get_device(dev) == PCI_PRODUCT_NETSEC_7751 &&
 513             pci_get_revid(dev) == 0x61) /*XXX???*/
 514                 sc->sc_ramsize >>= 1;
 515
 516         /*
 517          * Arrange the interrupt line.
 518          */
 519         rid = 0;
 520         sc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
 521                                             RF_SHAREABLE|RF_ACTIVE);
 522         if (sc->sc_irq == NULL) {
 523                 device_printf(dev, "could not map interrupt\n");
 524                 goto fail_mem;
 525         }
 526         /*
 527          * NB: Network code assumes we are blocked with splimp()
 528          *     so make sure the IRQ is marked appropriately.
 529          */
 530         if (bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_NET | INTR_MPSAFE,
 531                            NULL, hifn_intr, sc, &sc->sc_intrhand)) {
 532                 device_printf(dev, "could not setup interrupt\n");
 533                 goto fail_intr2;
 534         }
 535
 536         hifn_sessions(sc);
 537
 538         /*
 539          * NB: Keep only the low 16 bits; this masks the chip id
 540          *     from the 7951.
 541          */
 542         rev = READ_REG_1(sc, HIFN_1_REVID) & 0xffff;
 543
 544         rseg = sc->sc_ramsize / 1024;
 545         rbase = 'K';
 546         if (sc->sc_ramsize >= (1024 * 1024)) {
 547                 rbase = 'M';
 548                 rseg /= 1024;
 549         }
 550         device_printf(sc->sc_dev, "%s, rev %u, %d%cB %cram",
 551                 hifn_partname(sc), rev,
 552                 rseg, rbase, sc->sc_drammodel ? 'd' : 's');
 553         if (sc->sc_flags & HIFN_IS_7956)
 554                 printf(", pll=0x%x<%s clk, %ux mult>",
 555                         sc->sc_pllconfig,
 556                         sc->sc_pllconfig & HIFN_PLL_REF_SEL ? "ext" : "pci",
 557                         2 + 2*((sc->sc_pllconfig & HIFN_PLL_ND) >> 11));
 558         printf("\n");
 559
 560         sc->sc_cid = crypto_get_driverid(dev, CRYPTOCAP_F_HARDWARE);
 561         if (sc->sc_cid < 0) {
 562                 device_printf(dev, "could not get crypto driver id\n");
 563                 goto fail_intr;
 564         }
 565
 566         WRITE_REG_0(sc, HIFN_0_PUCNFG,
 567             READ_REG_0(sc, HIFN_0_PUCNFG) | HIFN_PUCNFG_CHIPID);
 568         ena = READ_REG_0(sc, HIFN_0_PUSTAT) & HIFN_PUSTAT_CHIPENA;
 569
 570         switch (ena) {
 571         case HIFN_PUSTAT_ENA_2:
 572                 crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0);
 573                 crypto_register(sc->sc_cid, CRYPTO_ARC4, 0, 0);
 574                 if (sc->sc_flags & HIFN_HAS_AES)
 575                         crypto_register(sc->sc_cid, CRYPTO_AES_CBC, 0, 0);
 576                 /*FALLTHROUGH*/
 577         case HIFN_PUSTAT_ENA_1:
 578                 crypto_register(sc->sc_cid, CRYPTO_MD5, 0, 0);
 579                 crypto_register(sc->sc_cid, CRYPTO_SHA1, 0, 0);
 580                 crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0);
 581                 crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0);
 582                 crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0);
 583                 break;
 584         }
 585
 586         bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap,
 587             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
 588
 589         if (sc->sc_flags & (HIFN_HAS_PUBLIC | HIFN_HAS_RNG))
 590                 hifn_init_pubrng(sc);
 591
 592         callout_init(&sc->sc_tickto, CALLOUT_MPSAFE);
 593         callout_reset(&sc->sc_tickto, hz, hifn_tick, sc);
 594
 595         return (0);
 596
 597 fail_intr:
 598         bus_teardown_intr(dev, sc->sc_irq, sc->sc_intrhand);
 599 fail_intr2:
 600         /* XXX don't store rid */
 601         bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq);
 602 fail_mem:
 603         bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap);
 604         bus_dmamem_free(sc->sc_dmat, sc->sc_dma, sc->sc_dmamap);
 605         bus_dma_tag_destroy(sc->sc_dmat);
 606
 607         /* Turn off DMA polling */
 608         WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET |
 609             HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE);
 610 fail_io1:
 611         bus_release_resource(dev, SYS_RES_MEMORY, HIFN_BAR1, sc->sc_bar1res);
 612 fail_io0:
 613         bus_release_resource(dev, SYS_RES_MEMORY, HIFN_BAR0, sc->sc_bar0res);
 614 fail_pci:
 615         mtx_destroy(&sc->sc_mtx);
 616         return (ENXIO);
 617 }
 618
 619 /*
 620  * Detach an interface that successfully probed.
 621  */
 622 static int
 623 hifn_detach(device_t dev)
 624 {
 625         struct hifn_softc *sc = device_get_softc(dev);
 626
 627         KASSERT(sc != NULL, ("hifn_detach: null software carrier!"));
 628
 629         /* disable interrupts */
 630         WRITE_REG_1(sc, HIFN_1_DMA_IER, 0);
 631
 632         /*XXX other resources */
 633         callout_stop(&sc->sc_tickto);
 634         callout_stop(&sc->sc_rngto);
 635 #ifdef HIFN_RNDTEST
 636         if (sc->sc_rndtest)
 637                 rndtest_detach(sc->sc_rndtest);
 638 #endif
 639
 640         /* Turn off DMA polling */
 641         WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET |
 642             HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE);
 643
 644         crypto_unregister_all(sc->sc_cid);
 645
 646         bus_generic_detach(dev);        /*XXX should be no children, right? */
 647
 648         bus_teardown_intr(dev, sc->sc_irq, sc->sc_intrhand);
 649         /* XXX don't store rid */
 650         bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq);
 651
 652         bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap);
 653         bus_dmamem_free(sc->sc_dmat, sc->sc_dma, sc->sc_dmamap);
 654         bus_dma_tag_destroy(sc->sc_dmat);
 655
 656         bus_release_resource(dev, SYS_RES_MEMORY, HIFN_BAR1, sc->sc_bar1res);
 657         bus_release_resource(dev, SYS_RES_MEMORY, HIFN_BAR0, sc->sc_bar0res);
 658
 659         mtx_destroy(&sc->sc_mtx);
 660
 661         return (0);
 662 }
 663
 664 /*
 665  * Stop all chip I/O so that the kernel's probe routines don't
 666  * get confused by errant DMAs when rebooting.
 667  */
 668 static int
 669 hifn_shutdown(device_t dev)
 670 {
 671 #ifdef notyet
 672         hifn_stop(device_get_softc(dev));
 673 #endif
 674         return (0);
 675 }
 676
 677 /*
 678  * Device suspend routine.  Stop the interface and save some PCI
 679  * settings in case the BIOS doesn't restore them properly on
 680  * resume.
 681  */
 682 static int
 683 hifn_suspend(device_t dev)
 684 {
 685         struct hifn_softc *sc = device_get_softc(dev);
 686 #ifdef notyet
 687         hifn_stop(sc);
 688 #endif
 689         sc->sc_suspended = 1;
 690
 691         return (0);
 692 }
 693
 694 /*
 695  * Device resume routine.  Restore some PCI settings in case the BIOS
 696  * doesn't, re-enable busmastering, and restart the interface if
 697  * appropriate.
 698  */
 699 static int
 700 hifn_resume(device_t dev)
 701 {
 702         struct hifn_softc *sc = device_get_softc(dev);
 703 #ifdef notyet
 704         /* reinitialize interface if necessary */
 705         if (ifp->if_flags & IFF_UP)
 706                 rl_init(sc);
 707 #endif
 708         sc->sc_suspended = 0;
 709
 710         return (0);
 711 }
 712
 713 static int
 714 hifn_init_pubrng(struct hifn_softc *sc)
 715 {
 716         u_int32_t r;
 717         int i;
 718
 719 #ifdef HIFN_RNDTEST
 720         sc->sc_rndtest = rndtest_attach(sc->sc_dev);
 721         if (sc->sc_rndtest)
 722                 sc->sc_harvest = rndtest_harvest;
 723         else
 724                 sc->sc_harvest = default_harvest;
 725 #else
 726         sc->sc_harvest = default_harvest;
 727 #endif
 728         if ((sc->sc_flags & HIFN_IS_7811) == 0) {
 729                 /* Reset 7951 public key/rng engine */
 730                 WRITE_REG_1(sc, HIFN_1_PUB_RESET,
 731                     READ_REG_1(sc, HIFN_1_PUB_RESET) | HIFN_PUBRST_RESET);
 732
 733                 for (i = 0; i < 100; i++) {
 734                         DELAY(1000);
 735                         if ((READ_REG_1(sc, HIFN_1_PUB_RESET) &
 736                             HIFN_PUBRST_RESET) == 0)
 737                                 break;
 738                 }
 739
 740                 if (i == 100) {
 741                         device_printf(sc->sc_dev, "public key init failed\n");
 742                         return (1);
 743                 }
 744         }
 745
 746         /* Enable the rng, if available */
 747         if (sc->sc_flags & HIFN_HAS_RNG) {
 748                 if (sc->sc_flags & HIFN_IS_7811) {
 749                         r = READ_REG_1(sc, HIFN_1_7811_RNGENA);
 750                         if (r & HIFN_7811_RNGENA_ENA) {
 751                                 r &= ~HIFN_7811_RNGENA_ENA;
 752                                 WRITE_REG_1(sc, HIFN_1_7811_RNGENA, r);
 753                         }
 754                         WRITE_REG_1(sc, HIFN_1_7811_RNGCFG,
 755                             HIFN_7811_RNGCFG_DEFL);
 756                         r |= HIFN_7811_RNGENA_ENA;
 757                         WRITE_REG_1(sc, HIFN_1_7811_RNGENA, r);
 758                 } else
 759                         WRITE_REG_1(sc, HIFN_1_RNG_CONFIG,
 760                             READ_REG_1(sc, HIFN_1_RNG_CONFIG) |
 761                             HIFN_RNGCFG_ENA);
 762
 763                 sc->sc_rngfirst = 1;
 764                 if (hz >= 100)
 765                         sc->sc_rnghz = hz / 100;
 766                 else
 767                         sc->sc_rnghz = 1;
 768                 callout_init(&sc->sc_rngto, CALLOUT_MPSAFE);
 769                 callout_reset(&sc->sc_rngto, sc->sc_rnghz, hifn_rng, sc);
 770         }
 771
 772         /* Enable public key engine, if available */
 773         if (sc->sc_flags & HIFN_HAS_PUBLIC) {
 774                 WRITE_REG_1(sc, HIFN_1_PUB_IEN, HIFN_PUBIEN_DONE);
 775                 sc->sc_dmaier |= HIFN_DMAIER_PUBDONE;
 776                 WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier);
 777 #ifdef HIFN_VULCANDEV
 778                 sc->sc_pkdev = make_dev(&vulcanpk_cdevsw, 0,
 779                                         UID_ROOT, GID_WHEEL, 0666,
 780                                         "vulcanpk");
 781                 sc->sc_pkdev->si_drv1 = sc;
 782 #endif
 783         }
 784
 785         return (0);
 786 }
 787
 788 static void
 789 hifn_rng(void *vsc)
 790 {
 791 #define RANDOM_BITS(n)  (n)*sizeof (u_int32_t), (n)*sizeof (u_int32_t)*NBBY, 0
 792         struct hifn_softc *sc = vsc;
 793         u_int32_t sts, num[2];
 794         int i;
 795
 796         if (sc->sc_flags & HIFN_IS_7811) {
 797                 /* ONLY VALID ON 7811!!!! */
 798                 for (i = 0; i < 5; i++) {
 799                         sts = READ_REG_1(sc, HIFN_1_7811_RNGSTS);
 800                         if (sts & HIFN_7811_RNGSTS_UFL) {
 801                                 device_printf(sc->sc_dev,
 802                                               "RNG underflow: disabling\n");
 803                                 return;
 804                         }
 805                         if ((sts & HIFN_7811_RNGSTS_RDY) == 0)
 806                                 break;
 807
 808                         /*
 809                          * There are at least two words in the RNG FIFO
 810                          * at this point.
 811                          */
 812                         num[0] = READ_REG_1(sc, HIFN_1_7811_RNGDAT);
 813                         num[1] = READ_REG_1(sc, HIFN_1_7811_RNGDAT);
 814                         /* NB: discard first data read */
 815                         if (sc->sc_rngfirst)
 816                                 sc->sc_rngfirst = 0;
 817                         else
 818                                 (*sc->sc_harvest)(sc->sc_rndtest,
 819                                         num, sizeof (num));
 820                 }
 821         } else {
 822                 num[0] = READ_REG_1(sc, HIFN_1_RNG_DATA);
 823
 824                 /* NB: discard first data read */
 825                 if (sc->sc_rngfirst)
 826                         sc->sc_rngfirst = 0;
 827                 else
 828                         (*sc->sc_harvest)(sc->sc_rndtest,
 829                                 num, sizeof (num[0]));
 830         }
 831
 832         callout_reset(&sc->sc_rngto, sc->sc_rnghz, hifn_rng, sc);
 833 #undef RANDOM_BITS
 834 }
 835
 836 static void
 837 hifn_puc_wait(struct hifn_softc *sc)
 838 {
 839         int i;
 840         int reg = HIFN_0_PUCTRL;
 841
 842         if (sc->sc_flags & HIFN_IS_7956) {
 843                 reg = HIFN_0_PUCTRL2;
 844         }
 845
 846         for (i = 5000; i > 0; i--) {
 847                 DELAY(1);
 848                 if (!(READ_REG_0(sc, reg) & HIFN_PUCTRL_RESET))
 849                         break;
 850         }
 851         if (!i)
 852                 device_printf(sc->sc_dev, "proc unit did not reset\n");
 853 }
 854
 855 /*
 856  * Reset the processing unit.
 857  */
 858 static void
 859 hifn_reset_puc(struct hifn_softc *sc)
 860 {
 861         /* Reset processing unit */
 862         int reg = HIFN_0_PUCTRL;
 863
 864         if (sc->sc_flags & HIFN_IS_7956) {
 865                 reg = HIFN_0_PUCTRL2;
 866         }
 867         WRITE_REG_0(sc, reg, HIFN_PUCTRL_DMAENA);
 868
 869         hifn_puc_wait(sc);
 870 }
 871
 872 /*
 873  * Set the Retry and TRDY registers; note that we set them to
 874  * zero because the 7811 locks up when forced to retry (section
 875  * 3.6 of "Specification Update SU-0014-04".  Not clear if we
 876  * should do this for all Hifn parts, but it doesn't seem to hurt.
 877  */
 878 static void
 879 hifn_set_retry(struct hifn_softc *sc)
 880 {
 881         /* NB: RETRY only responds to 8-bit reads/writes */
 882         pci_write_config(sc->sc_dev, HIFN_RETRY_TIMEOUT, 0, 1);
 883         pci_write_config(sc->sc_dev, HIFN_TRDY_TIMEOUT, 0, 1);
 884 }
 885
 886 /*
 887  * Resets the board.  Values in the regesters are left as is
 888  * from the reset (i.e. initial values are assigned elsewhere).
 889  */
 890 static void
 891 hifn_reset_board(struct hifn_softc *sc, int full)
 892 {
 893         u_int32_t reg;
 894
 895         /*
 896          * Set polling in the DMA configuration register to zero.  0x7 avoids
 897          * resetting the board and zeros out the other fields.
 898          */
 899         WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET |
 900             HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE);
 901
 902         /*
 903          * Now that polling has been disabled, we have to wait 1 ms
 904          * before resetting the board.
 905          */
 906         DELAY(1000);
 907
 908         /* Reset the DMA unit */
 909         if (full) {
 910                 WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MODE);
 911                 DELAY(1000);
 912         } else {
 913                 WRITE_REG_1(sc, HIFN_1_DMA_CNFG,
 914                     HIFN_DMACNFG_MODE | HIFN_DMACNFG_MSTRESET);
 915                 hifn_reset_puc(sc);
 916         }
 917
 918         KASSERT(sc->sc_dma != NULL, ("hifn_reset_board: null DMA tag!"));
 919         bzero(sc->sc_dma, sizeof(*sc->sc_dma));
 920
 921         /* Bring dma unit out of reset */
 922         WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET |
 923             HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE);
 924
 925         hifn_puc_wait(sc);
 926         hifn_set_retry(sc);
 927
 928         if (sc->sc_flags & HIFN_IS_7811) {
 929                 for (reg = 0; reg < 1000; reg++) {
 930                         if (READ_REG_1(sc, HIFN_1_7811_MIPSRST) &
 931                             HIFN_MIPSRST_CRAMINIT)
 932                                 break;
 933                         DELAY(1000);
 934                 }
 935                 if (reg == 1000)
 936                         printf(": cram init timeout\n");
 937         } else {
 938           /* set up DMA configuration register #2 */
 939           /* turn off all PK and BAR0 swaps */
 940           WRITE_REG_1(sc, HIFN_1_DMA_CNFG2,
 941                       (3 << HIFN_DMACNFG2_INIT_WRITE_BURST_SHIFT)|
 942                       (3 << HIFN_DMACNFG2_INIT_READ_BURST_SHIFT)|
 943                       (2 << HIFN_DMACNFG2_TGT_WRITE_BURST_SHIFT)|
 944                       (2 << HIFN_DMACNFG2_TGT_READ_BURST_SHIFT));
 945         }
 946
 947 }
 948
 949 static u_int32_t
 950 hifn_next_signature(u_int32_t a, u_int cnt)
 951 {
 952         int i;
 953         u_int32_t v;
 954
 955         for (i = 0; i < cnt; i++) {
 956
 957                 /* get the parity */
 958                 v = a & 0x80080125;
 959                 v ^= v >> 16;
 960                 v ^= v >> 8;
 961                 v ^= v >> 4;
 962                 v ^= v >> 2;
 963                 v ^= v >> 1;
 964
 965                 a = (v & 1) ^ (a << 1);
 966         }
 967
 968         return a;
 969 }
 970
 971 struct pci2id {
 972         u_short         pci_vendor;
 973         u_short         pci_prod;
 974         char            card_id[13];
 975 };
 976 static struct pci2id pci2id[] = {
 977         {
 978                 PCI_VENDOR_HIFN,
 979                 PCI_PRODUCT_HIFN_7951,
 980                 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 981                   0x00, 0x00, 0x00, 0x00, 0x00 }
 982         }, {
 983                 PCI_VENDOR_HIFN,
 984                 PCI_PRODUCT_HIFN_7955,
 985                 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 986                   0x00, 0x00, 0x00, 0x00, 0x00 }
 987         }, {
 988                 PCI_VENDOR_HIFN,
 989                 PCI_PRODUCT_HIFN_7956,
 990                 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 991                   0x00, 0x00, 0x00, 0x00, 0x00 }
 992         }, {
 993                 PCI_VENDOR_NETSEC,
 994                 PCI_PRODUCT_NETSEC_7751,
 995                 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 996                   0x00, 0x00, 0x00, 0x00, 0x00 }
 997         }, {
 998                 PCI_VENDOR_INVERTEX,
 999                 PCI_PRODUCT_INVERTEX_AEON,
1000                 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1001                   0x00, 0x00, 0x00, 0x00, 0x00 }
1002         }, {
1003                 PCI_VENDOR_HIFN,
1004                 PCI_PRODUCT_HIFN_7811,
1005                 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1006                   0x00, 0x00, 0x00, 0x00, 0x00 }
1007         }, {
1008                 /*
1009                  * Other vendors share this PCI ID as well, such as
1010                  * http://www.powercrypt.com, and obviously they also
1011                  * use the same key.
1012                  */
1013                 PCI_VENDOR_HIFN,
1014                 PCI_PRODUCT_HIFN_7751,
1015                 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1016                   0x00, 0x00, 0x00, 0x00, 0x00 }
1017         },
1018 };
1019
1020 /*
1021  * Checks to see if crypto is already enabled.  If crypto isn't enable,
1022  * "hifn_enable_crypto" is called to enable it.  The check is important,
1023  * as enabling crypto twice will lock the board.
1024  */
1025 static int
1026 hifn_enable_crypto(struct hifn_softc *sc)
1027 {
1028         u_int32_t dmacfg, ramcfg, encl, addr, i;
1029         char *offtbl = NULL;
1030
1031         for (i = 0; i < sizeof(pci2id)/sizeof(pci2id[0]); i++) {
1032                 if (pci2id[i].pci_vendor == pci_get_vendor(sc->sc_dev) &&
1033                     pci2id[i].pci_prod == pci_get_device(sc->sc_dev)) {
1034                         offtbl = pci2id[i].card_id;
1035                         break;
1036                 }
1037         }
1038         if (offtbl == NULL) {
1039                 device_printf(sc->sc_dev, "Unknown card!\n");
1040                 return (1);
1041         }
1042
1043         ramcfg = READ_REG_0(sc, HIFN_0_PUCNFG);
1044         dmacfg = READ_REG_1(sc, HIFN_1_DMA_CNFG);
1045
1046         /*
1047          * The RAM config register's encrypt level bit needs to be set before
1048          * every read performed on the encryption level register.
1049          */
1050         WRITE_REG_0(sc, HIFN_0_PUCNFG, ramcfg | HIFN_PUCNFG_CHIPID);
1051
1052         encl = READ_REG_0(sc, HIFN_0_PUSTAT) & HIFN_PUSTAT_CHIPENA;
1053
1054         /*
1055          * Make sure we don't re-unlock.  Two unlocks kills chip until the
1056          * next reboot.
1057          */
1058         if (encl == HIFN_PUSTAT_ENA_1 || encl == HIFN_PUSTAT_ENA_2) {
1059 #ifdef HIFN_DEBUG
1060                 if (hifn_debug)
1061                         device_printf(sc->sc_dev,
1062                             "Strong crypto already enabled!\n");
1063 #endif
1064                 goto report;
1065         }
1066
1067         if (encl != 0 && encl != HIFN_PUSTAT_ENA_0) {
1068 #ifdef HIFN_DEBUG
1069                 if (hifn_debug)
1070                         device_printf(sc->sc_dev,
1071                               "Unknown encryption level 0x%x\n", encl);
1072 #endif
1073                 return 1;
1074         }
1075
1076         WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_UNLOCK |
1077             HIFN_DMACNFG_MSTRESET | HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE);
1078         DELAY(1000);
1079         addr = READ_REG_1(sc, HIFN_UNLOCK_SECRET1);
1080         DELAY(1000);
1081         WRITE_REG_1(sc, HIFN_UNLOCK_SECRET2, 0);
1082         DELAY(1000);
1083
1084         for (i = 0; i <= 12; i++) {
1085                 addr = hifn_next_signature(addr, offtbl[i] + 0x101);
1086                 WRITE_REG_1(sc, HIFN_UNLOCK_SECRET2, addr);
1087
1088                 DELAY(1000);
1089         }
1090
1091         WRITE_REG_0(sc, HIFN_0_PUCNFG, ramcfg | HIFN_PUCNFG_CHIPID);
1092         encl = READ_REG_0(sc, HIFN_0_PUSTAT) & HIFN_PUSTAT_CHIPENA;
1093
1094 #ifdef HIFN_DEBUG
1095         if (hifn_debug) {
1096                 if (encl != HIFN_PUSTAT_ENA_1 && encl != HIFN_PUSTAT_ENA_2)
1097                         device_printf(sc->sc_dev, "Engine is permanently "
1098                                 "locked until next system reset!\n");
1099                 else
1100                         device_printf(sc->sc_dev, "Engine enabled "
1101                                 "successfully!\n");
1102         }
1103 #endif
1104
1105 report:
1106         WRITE_REG_0(sc, HIFN_0_PUCNFG, ramcfg);
1107         WRITE_REG_1(sc, HIFN_1_DMA_CNFG, dmacfg);
1108
1109         switch (encl) {
1110         case HIFN_PUSTAT_ENA_1:
1111         case HIFN_PUSTAT_ENA_2:
1112                 break;
1113         case HIFN_PUSTAT_ENA_0:
1114         default:
1115                 device_printf(sc->sc_dev, "disabled");
1116                 break;
1117         }
1118
1119         return 0;
1120 }
1121
1122 /*
1123  * Give initial values to the registers listed in the "Register Space"
1124  * section of the HIFN Software Development reference manual.
1125  */
1126 static void
1127 hifn_init_pci_registers(struct hifn_softc *sc)
1128 {
1129         /* write fixed values needed by the Initialization registers */
1130         WRITE_REG_0(sc, HIFN_0_PUCTRL, HIFN_PUCTRL_DMAENA);
1131         WRITE_REG_0(sc, HIFN_0_FIFOCNFG, HIFN_FIFOCNFG_THRESHOLD);
1132         WRITE_REG_0(sc, HIFN_0_PUIER, HIFN_PUIER_DSTOVER);
1133
1134         /* write all 4 ring address registers */
1135         WRITE_REG_1(sc, HIFN_1_DMA_CRAR, sc->sc_dma_physaddr +
1136             offsetof(struct hifn_dma, cmdr[0]));
1137         WRITE_REG_1(sc, HIFN_1_DMA_SRAR, sc->sc_dma_physaddr +
1138             offsetof(struct hifn_dma, srcr[0]));
1139         WRITE_REG_1(sc, HIFN_1_DMA_DRAR, sc->sc_dma_physaddr +
1140             offsetof(struct hifn_dma, dstr[0]));
1141         WRITE_REG_1(sc, HIFN_1_DMA_RRAR, sc->sc_dma_physaddr +
1142             offsetof(struct hifn_dma, resr[0]));
1143
1144         DELAY(2000);
1145
1146         /* write status register */
1147         WRITE_REG_1(sc, HIFN_1_DMA_CSR,
1148             HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS |
1149             HIFN_DMACSR_S_CTRL_DIS | HIFN_DMACSR_C_CTRL_DIS |
1150             HIFN_DMACSR_D_ABORT | HIFN_DMACSR_D_DONE | HIFN_DMACSR_D_LAST |
1151             HIFN_DMACSR_D_WAIT | HIFN_DMACSR_D_OVER |
1152             HIFN_DMACSR_R_ABORT | HIFN_DMACSR_R_DONE | HIFN_DMACSR_R_LAST |
1153             HIFN_DMACSR_R_WAIT | HIFN_DMACSR_R_OVER |
1154             HIFN_DMACSR_S_ABORT | HIFN_DMACSR_S_DONE | HIFN_DMACSR_S_LAST |
1155             HIFN_DMACSR_S_WAIT |
1156             HIFN_DMACSR_C_ABORT | HIFN_DMACSR_C_DONE | HIFN_DMACSR_C_LAST |
1157             HIFN_DMACSR_C_WAIT |
1158             HIFN_DMACSR_ENGINE |
1159             ((sc->sc_flags & HIFN_HAS_PUBLIC) ?
1160                 HIFN_DMACSR_PUBDONE : 0) |
1161             ((sc->sc_flags & HIFN_IS_7811) ?
1162                 HIFN_DMACSR_ILLW | HIFN_DMACSR_ILLR : 0));
1163
1164         sc->sc_d_busy = sc->sc_r_busy = sc->sc_s_busy = sc->sc_c_busy = 0;
1165         sc->sc_dmaier |= HIFN_DMAIER_R_DONE | HIFN_DMAIER_C_ABORT |
1166             HIFN_DMAIER_D_OVER | HIFN_DMAIER_R_OVER |
1167             HIFN_DMAIER_S_ABORT | HIFN_DMAIER_D_ABORT | HIFN_DMAIER_R_ABORT |
1168             ((sc->sc_flags & HIFN_IS_7811) ?
1169                 HIFN_DMAIER_ILLW | HIFN_DMAIER_ILLR : 0);
1170         sc->sc_dmaier &= ~HIFN_DMAIER_C_WAIT;
1171         WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier);
1172
1173
1174         if (sc->sc_flags & HIFN_IS_7956) {
1175                 u_int32_t pll;
1176
1177                 WRITE_REG_0(sc, HIFN_0_PUCNFG, HIFN_PUCNFG_COMPSING |
1178                     HIFN_PUCNFG_TCALLPHASES |
1179                     HIFN_PUCNFG_TCDRVTOTEM | HIFN_PUCNFG_BUS32);
1180
1181                 /* turn off the clocks and insure bypass is set */
1182                 pll = READ_REG_1(sc, HIFN_1_PLL);
1183                 pll = (pll &~ (HIFN_PLL_PK_CLK_SEL | HIFN_PLL_PE_CLK_SEL))
1184                   | HIFN_PLL_BP | HIFN_PLL_MBSET;
1185                 WRITE_REG_1(sc, HIFN_1_PLL, pll);
1186                 DELAY(10*1000);         /* 10ms */
1187
1188                 /* change configuration */
1189                 pll = (pll &~ HIFN_PLL_CONFIG) | sc->sc_pllconfig;
1190                 WRITE_REG_1(sc, HIFN_1_PLL, pll);
1191                 DELAY(10*1000);         /* 10ms */
1192
1193                 /* disable bypass */
1194                 pll &= ~HIFN_PLL_BP;
1195                 WRITE_REG_1(sc, HIFN_1_PLL, pll);
1196                 /* enable clocks with new configuration */
1197                 pll |= HIFN_PLL_PK_CLK_SEL | HIFN_PLL_PE_CLK_SEL;
1198                 WRITE_REG_1(sc, HIFN_1_PLL, pll);
1199         } else {
1200                 WRITE_REG_0(sc, HIFN_0_PUCNFG, HIFN_PUCNFG_COMPSING |
1201                     HIFN_PUCNFG_DRFR_128 | HIFN_PUCNFG_TCALLPHASES |
1202                     HIFN_PUCNFG_TCDRVTOTEM | HIFN_PUCNFG_BUS32 |
1203                     (sc->sc_drammodel ? HIFN_PUCNFG_DRAM : HIFN_PUCNFG_SRAM));
1204         }
1205
1206         WRITE_REG_0(sc, HIFN_0_PUISR, HIFN_PUISR_DSTOVER);
1207         WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET |
1208             HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE | HIFN_DMACNFG_LAST |
1209             ((HIFN_POLL_FREQUENCY << 16 ) & HIFN_DMACNFG_POLLFREQ) |
1210             ((HIFN_POLL_SCALAR << 8) & HIFN_DMACNFG_POLLINVAL));
1211 }
1212
1213 /*
1214  * The maximum number of sessions supported by the card
1215  * is dependent on the amount of context ram, which
1216  * encryption algorithms are enabled, and how compression
1217  * is configured.  This should be configured before this
1218  * routine is called.
1219  */
1220 static void
1221 hifn_sessions(struct hifn_softc *sc)
1222 {
1223         u_int32_t pucnfg;
1224         int ctxsize;
1225
1226         pucnfg = READ_REG_0(sc, HIFN_0_PUCNFG);
1227
1228         if (pucnfg & HIFN_PUCNFG_COMPSING) {
1229                 if (pucnfg & HIFN_PUCNFG_ENCCNFG)
1230                         ctxsize = 128;
1231                 else
1232                         ctxsize = 512;
1233                 /*
1234                  * 7955/7956 has internal context memory of 32K
1235                  */
1236                 if (sc->sc_flags & HIFN_IS_7956)
1237                         sc->sc_maxses = 32768 / ctxsize;
1238                 else
1239                         sc->sc_maxses = 1 +
1240                             ((sc->sc_ramsize - 32768) / ctxsize);
1241         } else
1242                 sc->sc_maxses = sc->sc_ramsize / 16384;
1243
1244         if (sc->sc_maxses > 2048)
1245                 sc->sc_maxses = 2048;
1246 }
1247
1248 /*
1249  * Determine ram type (sram or dram).  Board should be just out of a reset
1250  * state when this is called.
1251  */
1252 static int
1253 hifn_ramtype(struct hifn_softc *sc)
1254 {
1255         u_int8_t data[8], dataexpect[8];
1256         int i;
1257
1258         for (i = 0; i < sizeof(data); i++)
1259                 data[i] = dataexpect[i] = 0x55;
1260         if (hifn_writeramaddr(sc, 0, data))
1261                 return (-1);
1262         if (hifn_readramaddr(sc, 0, data))
1263                 return (-1);
1264         if (bcmp(data, dataexpect, sizeof(data)) != 0) {
1265                 sc->sc_drammodel = 1;
1266                 return (0);
1267         }
1268
1269         for (i = 0; i < sizeof(data); i++)
1270                 data[i] = dataexpect[i] = 0xaa;
1271         if (hifn_writeramaddr(sc, 0, data))
1272                 return (-1);
1273         if (hifn_readramaddr(sc, 0, data))
1274                 return (-1);
1275         if (bcmp(data, dataexpect, sizeof(data)) != 0) {
1276                 sc->sc_drammodel = 1;
1277                 return (0);
1278         }
1279
1280         return (0);
1281 }
1282
1283 #define HIFN_SRAM_MAX           (32 << 20)
1284 #define HIFN_SRAM_STEP_SIZE     16384
1285 #define HIFN_SRAM_GRANULARITY   (HIFN_SRAM_MAX / HIFN_SRAM_STEP_SIZE)
1286
1287 static int
1288 hifn_sramsize(struct hifn_softc *sc)
1289 {
1290         u_int32_t a;
1291         u_int8_t data[8];
1292         u_int8_t dataexpect[sizeof(data)];
1293         int32_t i;
1294
1295         for (i = 0; i < sizeof(data); i++)
1296                 data[i] = dataexpect[i] = i ^ 0x5a;
1297
1298         for (i = HIFN_SRAM_GRANULARITY - 1; i >= 0; i--) {
1299                 a = i * HIFN_SRAM_STEP_SIZE;
1300                 bcopy(&i, data, sizeof(i));
1301                 hifn_writeramaddr(sc, a, data);
1302         }
1303
1304         for (i = 0; i < HIFN_SRAM_GRANULARITY; i++) {
1305                 a = i * HIFN_SRAM_STEP_SIZE;
1306                 bcopy(&i, dataexpect, sizeof(i));
1307                 if (hifn_readramaddr(sc, a, data) < 0)
1308                         return (0);
1309                 if (bcmp(data, dataexpect, sizeof(data)) != 0)
1310                         return (0);
1311                 sc->sc_ramsize = a + HIFN_SRAM_STEP_SIZE;
1312         }
1313
1314         return (0);
1315 }
1316
1317 /*
1318  * XXX For dram boards, one should really try all of the
1319  * HIFN_PUCNFG_DSZ_*'s.  This just assumes that PUCNFG
1320  * is already set up correctly.
1321  */
1322 static int
1323 hifn_dramsize(struct hifn_softc *sc)
1324 {
1325         u_int32_t cnfg;
1326
1327         if (sc->sc_flags & HIFN_IS_7956) {
1328                 /*
1329                  * 7955/7956 have a fixed internal ram of only 32K.
1330                  */
1331                 sc->sc_ramsize = 32768;
1332         } else {
1333                 cnfg = READ_REG_0(sc, HIFN_0_PUCNFG) &
1334                     HIFN_PUCNFG_DRAMMASK;
1335                 sc->sc_ramsize = 1 << ((cnfg >> 13) + 18);
1336         }
1337         return (0);
1338 }
1339
1340 static void
1341 hifn_alloc_slot(struct hifn_softc *sc, int *cmdp, int *srcp, int *dstp, int *resp)
1342 {
1343         struct hifn_dma *dma = sc->sc_dma;
1344
1345         if (sc->sc_cmdi == HIFN_D_CMD_RSIZE) {
1346                 sc->sc_cmdi = 0;
1347                 dma->cmdr[HIFN_D_CMD_RSIZE].l = htole32(HIFN_D_VALID |
1348                     HIFN_D_JUMP | HIFN_D_MASKDONEIRQ);
1349                 HIFN_CMDR_SYNC(sc, HIFN_D_CMD_RSIZE,
1350                     BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1351         }
1352         *cmdp = sc->sc_cmdi++;
1353         sc->sc_cmdk = sc->sc_cmdi;
1354
1355         if (sc->sc_srci == HIFN_D_SRC_RSIZE) {
1356                 sc->sc_srci = 0;
1357                 dma->srcr[HIFN_D_SRC_RSIZE].l = htole32(HIFN_D_VALID |
1358                     HIFN_D_JUMP | HIFN_D_MASKDONEIRQ);
1359                 HIFN_SRCR_SYNC(sc, HIFN_D_SRC_RSIZE,
1360                     BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1361         }
1362         *srcp = sc->sc_srci++;
1363         sc->sc_srck = sc->sc_srci;
1364
1365         if (sc->sc_dsti == HIFN_D_DST_RSIZE) {
1366                 sc->sc_dsti = 0;
1367                 dma->dstr[HIFN_D_DST_RSIZE].l = htole32(HIFN_D_VALID |
1368                     HIFN_D_JUMP | HIFN_D_MASKDONEIRQ);
1369                 HIFN_DSTR_SYNC(sc, HIFN_D_DST_RSIZE,
1370                     BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1371         }
1372         *dstp = sc->sc_dsti++;
1373         sc->sc_dstk = sc->sc_dsti;
1374
1375         if (sc->sc_resi == HIFN_D_RES_RSIZE) {
1376                 sc->sc_resi = 0;
1377                 dma->resr[HIFN_D_RES_RSIZE].l = htole32(HIFN_D_VALID |
1378                     HIFN_D_JUMP | HIFN_D_MASKDONEIRQ);
1379                 HIFN_RESR_SYNC(sc, HIFN_D_RES_RSIZE,
1380                     BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1381         }
1382         *resp = sc->sc_resi++;
1383         sc->sc_resk = sc->sc_resi;
1384 }
1385
1386 static int
1387 hifn_writeramaddr(struct hifn_softc *sc, int addr, u_int8_t *data)
1388 {
1389         struct hifn_dma *dma = sc->sc_dma;
1390         hifn_base_command_t wc;
1391         const u_int32_t masks = HIFN_D_VALID | HIFN_D_LAST | HIFN_D_MASKDONEIRQ;
1392         int r, cmdi, resi, srci, dsti;
1393
1394         wc.masks = htole16(3 << 13);
1395         wc.session_num = htole16(addr >> 14);
1396         wc.total_source_count = htole16(8);
1397         wc.total_dest_count = htole16(addr & 0x3fff);
1398
1399         hifn_alloc_slot(sc, &cmdi, &srci, &dsti, &resi);
1400
1401         WRITE_REG_1(sc, HIFN_1_DMA_CSR,
1402             HIFN_DMACSR_C_CTRL_ENA | HIFN_DMACSR_S_CTRL_ENA |
1403             HIFN_DMACSR_D_CTRL_ENA | HIFN_DMACSR_R_CTRL_ENA);
1404
1405         /* build write command */
1406         bzero(dma->command_bufs[cmdi], HIFN_MAX_COMMAND);
1407         *(hifn_base_command_t *)dma->command_bufs[cmdi] = wc;
1408         bcopy(data, &dma->test_src, sizeof(dma->test_src));
1409
1410         dma->srcr[srci].p = htole32(sc->sc_dma_physaddr
1411             + offsetof(struct hifn_dma, test_src));
1412         dma->dstr[dsti].p = htole32(sc->sc_dma_physaddr
1413             + offsetof(struct hifn_dma, test_dst));
1414
1415         dma->cmdr[cmdi].l = htole32(16 | masks);
1416         dma->srcr[srci].l = htole32(8 | masks);
1417         dma->dstr[dsti].l = htole32(4 | masks);
1418         dma->resr[resi].l = htole32(4 | masks);
1419
1420         bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap,
1421             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1422
1423         for (r = 10000; r >= 0; r--) {
1424                 DELAY(10);
1425                 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap,
1426                     BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1427                 if ((dma->resr[resi].l & htole32(HIFN_D_VALID)) == 0)
1428                         break;
1429                 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap,
1430                     BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1431         }
1432         if (r == 0) {
1433                 device_printf(sc->sc_dev, "writeramaddr -- "
1434                     "result[%d](addr %d) still valid\n", resi, addr);
1435                 r = -1;
1436                 return (-1);
1437         } else
1438                 r = 0;
1439
1440         WRITE_REG_1(sc, HIFN_1_DMA_CSR,
1441             HIFN_DMACSR_C_CTRL_DIS | HIFN_DMACSR_S_CTRL_DIS |
1442             HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS);
1443
1444         return (r);
1445 }
1446
1447 static int
1448 hifn_readramaddr(struct hifn_softc *sc, int addr, u_int8_t *data)
1449 {
1450         struct hifn_dma *dma = sc->sc_dma;
1451         hifn_base_command_t rc;
1452         const u_int32_t masks = HIFN_D_VALID | HIFN_D_LAST | HIFN_D_MASKDONEIRQ;
1453         int r, cmdi, srci, dsti, resi;
1454
1455         rc.masks = htole16(2 << 13);
1456         rc.session_num = htole16(addr >> 14);
1457         rc.total_source_count = htole16(addr & 0x3fff);
1458         rc.total_dest_count = htole16(8);
1459
1460         hifn_alloc_slot(sc, &cmdi, &srci, &dsti, &resi);
1461
1462         WRITE_REG_1(sc, HIFN_1_DMA_CSR,
1463             HIFN_DMACSR_C_CTRL_ENA | HIFN_DMACSR_S_CTRL_ENA |
1464             HIFN_DMACSR_D_CTRL_ENA | HIFN_DMACSR_R_CTRL_ENA);
1465
1466         bzero(dma->command_bufs[cmdi], HIFN_MAX_COMMAND);
1467         *(hifn_base_command_t *)dma->command_bufs[cmdi] = rc;
1468
1469         dma->srcr[srci].p = htole32(sc->sc_dma_physaddr +
1470             offsetof(struct hifn_dma, test_src));
1471         dma->test_src = 0;
1472         dma->dstr[dsti].p =  htole32(sc->sc_dma_physaddr +
1473             offsetof(struct hifn_dma, test_dst));
1474         dma->test_dst = 0;
1475         dma->cmdr[cmdi].l = htole32(8 | masks);
1476         dma->srcr[srci].l = htole32(8 | masks);
1477         dma->dstr[dsti].l = htole32(8 | masks);
1478         dma->resr[resi].l = htole32(HIFN_MAX_RESULT | masks);
1479
1480         bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap,
1481             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1482
1483         for (r = 10000; r >= 0; r--) {
1484                 DELAY(10);
1485                 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap,
1486                     BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1487                 if ((dma->resr[resi].l & htole32(HIFN_D_VALID)) == 0)
1488                         break;
1489                 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap,
1490                     BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1491         }
1492         if (r == 0) {
1493                 device_printf(sc->sc_dev, "readramaddr -- "
1494                     "result[%d](addr %d) still valid\n", resi, addr);
1495                 r = -1;
1496         } else {
1497                 r = 0;
1498                 bcopy(&dma->test_dst, data, sizeof(dma->test_dst));
1499         }
1500
1501         WRITE_REG_1(sc, HIFN_1_DMA_CSR,
1502             HIFN_DMACSR_C_CTRL_DIS | HIFN_DMACSR_S_CTRL_DIS |
1503             HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS);
1504
1505         return (r);
1506 }
1507
1508 /*
1509  * Initialize the descriptor rings.
1510  */
1511 static void
1512 hifn_init_dma(struct hifn_softc *sc)
1513 {
1514         struct hifn_dma *dma = sc->sc_dma;
1515         int i;
1516
1517         hifn_set_retry(sc);
1518
1519         /* initialize static pointer values */
1520         for (i = 0; i < HIFN_D_CMD_RSIZE; i++)
1521                 dma->cmdr[i].p = htole32(sc->sc_dma_physaddr +
1522                     offsetof(struct hifn_dma, command_bufs[i][0]));
1523         for (i = 0; i < HIFN_D_RES_RSIZE; i++)
1524                 dma->resr[i].p = htole32(sc->sc_dma_physaddr +
1525                     offsetof(struct hifn_dma, result_bufs[i][0]));
1526
1527         dma->cmdr[HIFN_D_CMD_RSIZE].p =
1528             htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, cmdr[0]));
1529         dma->srcr[HIFN_D_SRC_RSIZE].p =
1530             htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, srcr[0]));
1531         dma->dstr[HIFN_D_DST_RSIZE].p =
1532             htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, dstr[0]));
1533         dma->resr[HIFN_D_RES_RSIZE].p =
1534             htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, resr[0]));
1535
1536         sc->sc_cmdu = sc->sc_srcu = sc->sc_dstu = sc->sc_resu = 0;
1537         sc->sc_cmdi = sc->sc_srci = sc->sc_dsti = sc->sc_resi = 0;
1538         sc->sc_cmdk = sc->sc_srck = sc->sc_dstk = sc->sc_resk = 0;
1539 }
1540
1541 /*
1542  * Writes out the raw command buffer space.  Returns the
1543  * command buffer size.
1544  */
1545 static u_int
1546 hifn_write_command(struct hifn_command *cmd, u_int8_t *buf)
1547 {
1548         u_int8_t *buf_pos;
1549         hifn_base_command_t *base_cmd;
1550         hifn_mac_command_t *mac_cmd;
1551         hifn_crypt_command_t *cry_cmd;
1552         int using_mac, using_crypt, len, ivlen;
1553         u_int32_t dlen, slen;
1554
1555         buf_pos = buf;
1556         using_mac = cmd->base_masks & HIFN_BASE_CMD_MAC;
1557         using_crypt = cmd->base_masks & HIFN_BASE_CMD_CRYPT;
1558
1559         base_cmd = (hifn_base_command_t *)buf_pos;
1560         base_cmd->masks = htole16(cmd->base_masks);
1561         slen = cmd->src_mapsize;
1562         if (cmd->sloplen)
1563                 dlen = cmd->dst_mapsize - cmd->sloplen + sizeof(u_int32_t);
1564         else
1565                 dlen = cmd->dst_mapsize;
1566         base_cmd->total_source_count = htole16(slen & HIFN_BASE_CMD_LENMASK_LO);
1567         base_cmd->total_dest_count = htole16(dlen & HIFN_BASE_CMD_LENMASK_LO);
1568         dlen >>= 16;
1569         slen >>= 16;
1570         base_cmd->session_num = htole16(
1571             ((slen << HIFN_BASE_CMD_SRCLEN_S) & HIFN_BASE_CMD_SRCLEN_M) |
1572             ((dlen << HIFN_BASE_CMD_DSTLEN_S) & HIFN_BASE_CMD_DSTLEN_M));
1573         buf_pos += sizeof(hifn_base_command_t);
1574
1575         if (using_mac) {
1576                 mac_cmd = (hifn_mac_command_t *)buf_pos;
1577                 dlen = cmd->maccrd->crd_len;
1578                 mac_cmd->source_count = htole16(dlen & 0xffff);
1579                 dlen >>= 16;
1580                 mac_cmd->masks = htole16(cmd->mac_masks |
1581                     ((dlen << HIFN_MAC_CMD_SRCLEN_S) & HIFN_MAC_CMD_SRCLEN_M));
1582                 mac_cmd->header_skip = htole16(cmd->maccrd->crd_skip);
1583                 mac_cmd->reserved = 0;
1584                 buf_pos += sizeof(hifn_mac_command_t);
1585         }
1586
1587         if (using_crypt) {
1588                 cry_cmd = (hifn_crypt_command_t *)buf_pos;
1589                 dlen = cmd->enccrd->crd_len;
1590                 cry_cmd->source_count = htole16(dlen & 0xffff);
1591                 dlen >>= 16;
1592                 cry_cmd->masks = htole16(cmd->cry_masks |
1593                     ((dlen << HIFN_CRYPT_CMD_SRCLEN_S) & HIFN_CRYPT_CMD_SRCLEN_M));
1594                 cry_cmd->header_skip = htole16(cmd->enccrd->crd_skip);
1595                 cry_cmd->reserved = 0;
1596                 buf_pos += sizeof(hifn_crypt_command_t);
1597         }
1598
1599         if (using_mac && cmd->mac_masks & HIFN_MAC_CMD_NEW_KEY) {
1600                 bcopy(cmd->mac, buf_pos, HIFN_MAC_KEY_LENGTH);
1601                 buf_pos += HIFN_MAC_KEY_LENGTH;
1602         }
1603
1604         if (using_crypt && cmd->cry_masks & HIFN_CRYPT_CMD_NEW_KEY) {
1605                 switch (cmd->cry_masks & HIFN_CRYPT_CMD_ALG_MASK) {
1606                 case HIFN_CRYPT_CMD_ALG_3DES:
1607                         bcopy(cmd->ck, buf_pos, HIFN_3DES_KEY_LENGTH);
1608                         buf_pos += HIFN_3DES_KEY_LENGTH;
1609                         break;
1610                 case HIFN_CRYPT_CMD_ALG_DES:
1611                         bcopy(cmd->ck, buf_pos, HIFN_DES_KEY_LENGTH);
1612                         buf_pos += HIFN_DES_KEY_LENGTH;
1613                         break;
1614                 case HIFN_CRYPT_CMD_ALG_RC4:
1615                         len = 256;
1616                         do {
1617                                 int clen;
1618
1619                                 clen = MIN(cmd->cklen, len);
1620                                 bcopy(cmd->ck, buf_pos, clen);
1621                                 len -= clen;
1622                                 buf_pos += clen;
1623                         } while (len > 0);
1624                         bzero(buf_pos, 4);
1625                         buf_pos += 4;
1626                         break;
1627                 case HIFN_CRYPT_CMD_ALG_AES:
1628                         /*
1629                          * AES keys are variable 128, 192 and
1630                          * 256 bits (16, 24 and 32 bytes).
1631                          */
1632                         bcopy(cmd->ck, buf_pos, cmd->cklen);
1633                         buf_pos += cmd->cklen;
1634                         break;
1635                 }
1636         }
1637
1638         if (using_crypt && cmd->cry_masks & HIFN_CRYPT_CMD_NEW_IV) {
1639                 switch (cmd->cry_masks & HIFN_CRYPT_CMD_ALG_MASK) {
1640                 case HIFN_CRYPT_CMD_ALG_AES:
1641                         ivlen = HIFN_AES_IV_LENGTH;
1642                         break;
1643                 default:
1644                         ivlen = HIFN_IV_LENGTH;
1645                         break;
1646                 }
1647                 bcopy(cmd->iv, buf_pos, ivlen);
1648                 buf_pos += ivlen;
1649         }
1650
1651         if ((cmd->base_masks & (HIFN_BASE_CMD_MAC|HIFN_BASE_CMD_CRYPT)) == 0) {
1652                 bzero(buf_pos, 8);
1653                 buf_pos += 8;
1654         }
1655
1656         return (buf_pos - buf);
1657 }
1658
1659 static int
1660 hifn_dmamap_aligned(struct hifn_operand *op)
1661 {
1662         int i;
1663
1664         for (i = 0; i < op->nsegs; i++) {
1665                 if (op->segs[i].ds_addr & 3)
1666                         return (0);
1667                 if ((i != (op->nsegs - 1)) && (op->segs[i].ds_len & 3))
1668                         return (0);
1669         }
1670         return (1);
1671 }
1672
1673 static __inline int
1674 hifn_dmamap_dstwrap(struct hifn_softc *sc, int idx)
1675 {
1676         struct hifn_dma *dma = sc->sc_dma;
1677
1678         if (++idx == HIFN_D_DST_RSIZE) {
1679                 dma->dstr[idx].l = htole32(HIFN_D_VALID | HIFN_D_JUMP |
1680                     HIFN_D_MASKDONEIRQ);
1681                 HIFN_DSTR_SYNC(sc, idx,
1682                     BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1683                 idx = 0;
1684         }
1685         return (idx);
1686 }
1687
1688 static int
1689 hifn_dmamap_load_dst(struct hifn_softc *sc, struct hifn_command *cmd)
1690 {
1691         struct hifn_dma *dma = sc->sc_dma;
1692         struct hifn_operand *dst = &cmd->dst;
1693         u_int32_t p, l;
1694         int idx, used = 0, i;
1695
1696         idx = sc->sc_dsti;
1697         for (i = 0; i < dst->nsegs - 1; i++) {
1698                 dma->dstr[idx].p = htole32(dst->segs[i].ds_addr);
1699                 dma->dstr[idx].l = htole32(HIFN_D_VALID |
1700                     HIFN_D_MASKDONEIRQ | dst->segs[i].ds_len);
1701                 HIFN_DSTR_SYNC(sc, idx,
1702                     BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1703                 used++;
1704
1705                 idx = hifn_dmamap_dstwrap(sc, idx);
1706         }
1707
1708         if (cmd->sloplen == 0) {
1709                 p = dst->segs[i].ds_addr;
1710                 l = HIFN_D_VALID | HIFN_D_MASKDONEIRQ | HIFN_D_LAST |
1711                     dst->segs[i].ds_len;
1712         } else {
1713                 p = sc->sc_dma_physaddr +
1714                     offsetof(struct hifn_dma, slop[cmd->slopidx]);
1715                 l = HIFN_D_VALID | HIFN_D_MASKDONEIRQ | HIFN_D_LAST |
1716                     sizeof(u_int32_t);
1717
1718                 if ((dst->segs[i].ds_len - cmd->sloplen) != 0) {
1719                         dma->dstr[idx].p = htole32(dst->segs[i].ds_addr);
1720                         dma->dstr[idx].l = htole32(HIFN_D_VALID |
1721                             HIFN_D_MASKDONEIRQ |
1722                             (dst->segs[i].ds_len - cmd->sloplen));
1723                         HIFN_DSTR_SYNC(sc, idx,
1724                             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1725                         used++;
1726
1727                         idx = hifn_dmamap_dstwrap(sc, idx);
1728                 }
1729         }
1730         dma->dstr[idx].p = htole32(p);
1731         dma->dstr[idx].l = htole32(l);
1732         HIFN_DSTR_SYNC(sc, idx, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1733         used++;
1734
1735         idx = hifn_dmamap_dstwrap(sc, idx);
1736
1737         sc->sc_dsti = idx;
1738         sc->sc_dstu += used;
1739         return (idx);
1740 }
1741
1742 static __inline int
1743 hifn_dmamap_srcwrap(struct hifn_softc *sc, int idx)
1744 {
1745         struct hifn_dma *dma = sc->sc_dma;
1746
1747         if (++idx == HIFN_D_SRC_RSIZE) {
1748                 dma->srcr[idx].l = htole32(HIFN_D_VALID |
1749                     HIFN_D_JUMP | HIFN_D_MASKDONEIRQ);
1750                 HIFN_SRCR_SYNC(sc, HIFN_D_SRC_RSIZE,
1751                     BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1752                 idx = 0;
1753         }
1754         return (idx);
1755 }
1756
1757 static int
1758 hifn_dmamap_load_src(struct hifn_softc *sc, struct hifn_command *cmd)
1759 {
1760         struct hifn_dma *dma = sc->sc_dma;
1761         struct hifn_operand *src = &cmd->src;
1762         int idx, i;
1763         u_int32_t last = 0;
1764
1765         idx = sc->sc_srci;
1766         for (i = 0; i < src->nsegs; i++) {
1767                 if (i == src->nsegs - 1)
1768                         last = HIFN_D_LAST;
1769
1770                 dma->srcr[idx].p = htole32(src->segs[i].ds_addr);
1771                 dma->srcr[idx].l = htole32(src->segs[i].ds_len |
1772                     HIFN_D_VALID | HIFN_D_MASKDONEIRQ | last);
1773                 HIFN_SRCR_SYNC(sc, idx,
1774                     BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1775
1776                 idx = hifn_dmamap_srcwrap(sc, idx);
1777         }
1778         sc->sc_srci = idx;
1779         sc->sc_srcu += src->nsegs;
1780         return (idx);
1781 }
1782
1783 static void
1784 hifn_op_cb(void* arg, bus_dma_segment_t *seg, int nsegs, bus_size_t mapsize, int error)
1785 {
1786         struct hifn_operand *op = arg;
1787
1788         KASSERT(nsegs <= MAX_SCATTER,
1789                 ("hifn_op_cb: too many DMA segments (%u > %u) "
1790                  "returned when mapping operand", nsegs, MAX_SCATTER));
1791         op->mapsize = mapsize;
1792         op->nsegs = nsegs;
1793         bcopy(seg, op->segs, nsegs * sizeof (seg[0]));
1794 }
1795
1796 static int
1797 hifn_crypto(
1798         struct hifn_softc *sc,
1799         struct hifn_command *cmd,
1800         struct cryptop *crp,
1801         int hint)
1802 {
1803         struct  hifn_dma *dma = sc->sc_dma;
1804         u_int32_t cmdlen, csr;
1805         int cmdi, resi, err = 0;
1806
1807         /*
1808          * need 1 cmd, and 1 res
1809          *
1810          * NB: check this first since it's easy.
1811          */
1812         HIFN_LOCK(sc);
1813         if ((sc->sc_cmdu + 1) > HIFN_D_CMD_RSIZE ||
1814             (sc->sc_resu + 1) > HIFN_D_RES_RSIZE) {
1815 #ifdef HIFN_DEBUG
1816                 if (hifn_debug) {
1817                         device_printf(sc->sc_dev,
1818                                 "cmd/result exhaustion, cmdu %u resu %u\n",
1819                                 sc->sc_cmdu, sc->sc_resu);
1820                 }
1821 #endif
1822                 hifnstats.hst_nomem_cr++;
1823                 HIFN_UNLOCK(sc);
1824                 return (ERESTART);
1825         }
1826
1827         if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, &cmd->src_map)) {
1828                 hifnstats.hst_nomem_map++;
1829                 HIFN_UNLOCK(sc);
1830                 return (ENOMEM);
1831         }
1832
1833         if (crp->crp_flags & CRYPTO_F_IMBUF) {
1834                 if (bus_dmamap_load_mbuf(sc->sc_dmat, cmd->src_map,
1835                     cmd->src_m, hifn_op_cb, &cmd->src, BUS_DMA_NOWAIT)) {
1836                         hifnstats.hst_nomem_load++;
1837                         err = ENOMEM;
1838                         goto err_srcmap1;
1839                 }
1840         } else if (crp->crp_flags & CRYPTO_F_IOV) {
1841                 if (bus_dmamap_load_uio(sc->sc_dmat, cmd->src_map,
1842                     cmd->src_io, hifn_op_cb, &cmd->src, BUS_DMA_NOWAIT)) {
1843                         hifnstats.hst_nomem_load++;
1844                         err = ENOMEM;
1845                         goto err_srcmap1;
1846                 }
1847         } else {
1848                 err = EINVAL;
1849                 goto err_srcmap1;
1850         }
1851
1852         if (hifn_dmamap_aligned(&cmd->src)) {
1853                 cmd->sloplen = cmd->src_mapsize & 3;
1854                 cmd->dst = cmd->src;
1855         } else {
1856                 if (crp->crp_flags & CRYPTO_F_IOV) {
1857                         err = EINVAL;
1858                         goto err_srcmap;
1859                 } else if (crp->crp_flags & CRYPTO_F_IMBUF) {
1860                         int totlen, len;
1861                         struct mbuf *m, *m0, *mlast;
1862
1863                         KASSERT(cmd->dst_m == cmd->src_m,
1864                                 ("hifn_crypto: dst_m initialized improperly"));
1865                         hifnstats.hst_unaligned++;
1866                         /*
1867                          * Source is not aligned on a longword boundary.
1868                          * Copy the data to insure alignment.  If we fail
1869                          * to allocate mbufs or clusters while doing this
1870                          * we return ERESTART so the operation is requeued
1871                          * at the crypto later, but only if there are
1872                          * ops already posted to the hardware; otherwise we
1873                          * have no guarantee that we'll be re-entered.
1874                          */
1875                         totlen = cmd->src_mapsize;
1876                         if (cmd->src_m->m_flags & M_PKTHDR) {
1877                                 len = MHLEN;
1878                                 MGETHDR(m0, M_NOWAIT, MT_DATA);
1879                                 if (m0 && !m_dup_pkthdr(m0, cmd->src_m, M_NOWAIT)) {
1880                                         m_free(m0);
1881                                         m0 = NULL;
1882                                 }
1883                         } else {
1884                                 len = MLEN;
1885                                 MGET(m0, M_NOWAIT, MT_DATA);
1886                         }
1887                         if (m0 == NULL) {
1888                                 hifnstats.hst_nomem_mbuf++;
1889                                 err = sc->sc_cmdu ? ERESTART : ENOMEM;
1890                                 goto err_srcmap;
1891                         }
1892                         if (totlen >= MINCLSIZE) {
1893                                 if (!(MCLGET(m0, M_NOWAIT))) {
1894                                         hifnstats.hst_nomem_mcl++;
1895                                         err = sc->sc_cmdu ? ERESTART : ENOMEM;
1896                                         m_freem(m0);
1897                                         goto err_srcmap;
1898                                 }
1899                                 len = MCLBYTES;
1900                         }
1901                         totlen -= len;
1902                         m0->m_pkthdr.len = m0->m_len = len;
1903                         mlast = m0;
1904
1905                         while (totlen > 0) {
1906                                 MGET(m, M_NOWAIT, MT_DATA);
1907                                 if (m == NULL) {
1908                                         hifnstats.hst_nomem_mbuf++;
1909                                         err = sc->sc_cmdu ? ERESTART : ENOMEM;
1910                                         m_freem(m0);
1911                                         goto err_srcmap;
1912                                 }
1913                                 len = MLEN;
1914                                 if (totlen >= MINCLSIZE) {
1915                                         if (!(MCLGET(m, M_NOWAIT))) {
1916                                                 hifnstats.hst_nomem_mcl++;
1917                                                 err = sc->sc_cmdu ? ERESTART : ENOMEM;
1918                                                 mlast->m_next = m;
1919                                                 m_freem(m0);
1920                                                 goto err_srcmap;
1921                                         }
1922                                         len = MCLBYTES;
1923                                 }
1924
1925                                 m->m_len = len;
1926                                 m0->m_pkthdr.len += len;
1927                                 totlen -= len;
1928
1929                                 mlast->m_next = m;
1930                                 mlast = m;
1931                         }
1932                         cmd->dst_m = m0;
1933                 }
1934         }
1935
1936         if (cmd->dst_map == NULL) {
1937                 if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, &cmd->dst_map)) {
1938                         hifnstats.hst_nomem_map++;
1939                         err = ENOMEM;
1940                         goto err_srcmap;
1941                 }
1942                 if (crp->crp_flags & CRYPTO_F_IMBUF) {
1943                         if (bus_dmamap_load_mbuf(sc->sc_dmat, cmd->dst_map,
1944                             cmd->dst_m, hifn_op_cb, &cmd->dst, BUS_DMA_NOWAIT)) {
1945                                 hifnstats.hst_nomem_map++;
1946                                 err = ENOMEM;
1947                                 goto err_dstmap1;
1948                         }
1949                 } else if (crp->crp_flags & CRYPTO_F_IOV) {
1950                         if (bus_dmamap_load_uio(sc->sc_dmat, cmd->dst_map,
1951                             cmd->dst_io, hifn_op_cb, &cmd->dst, BUS_DMA_NOWAIT)) {
1952                                 hifnstats.hst_nomem_load++;
1953                                 err = ENOMEM;
1954                                 goto err_dstmap1;
1955                         }
1956                 }
1957         }
1958
1959 #ifdef HIFN_DEBUG
1960         if (hifn_debug) {
1961                 device_printf(sc->sc_dev,
1962                     "Entering cmd: stat %8x ien %8x u %d/%d/%d/%d n %d/%d\n",
1963                     READ_REG_1(sc, HIFN_1_DMA_CSR),
1964                     READ_REG_1(sc, HIFN_1_DMA_IER),
1965                     sc->sc_cmdu, sc->sc_srcu, sc->sc_dstu, sc->sc_resu,
1966                     cmd->src_nsegs, cmd->dst_nsegs);
1967         }
1968 #endif
1969
1970         if (cmd->src_map == cmd->dst_map) {
1971                 bus_dmamap_sync(sc->sc_dmat, cmd->src_map,
1972                     BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
1973         } else {
1974                 bus_dmamap_sync(sc->sc_dmat, cmd->src_map,
1975                     BUS_DMASYNC_PREWRITE);
1976                 bus_dmamap_sync(sc->sc_dmat, cmd->dst_map,
1977                     BUS_DMASYNC_PREREAD);
1978         }
1979
1980         /*
1981          * need N src, and N dst
1982          */
1983         if ((sc->sc_srcu + cmd->src_nsegs) > HIFN_D_SRC_RSIZE ||
1984             (sc->sc_dstu + cmd->dst_nsegs + 1) > HIFN_D_DST_RSIZE) {
1985 #ifdef HIFN_DEBUG
1986                 if (hifn_debug) {
1987                         device_printf(sc->sc_dev,
1988                                 "src/dst exhaustion, srcu %u+%u dstu %u+%u\n",
1989                                 sc->sc_srcu, cmd->src_nsegs,
1990                                 sc->sc_dstu, cmd->dst_nsegs);
1991                 }
1992 #endif
1993                 hifnstats.hst_nomem_sd++;
1994                 err = ERESTART;
1995                 goto err_dstmap;
1996         }
1997
1998         if (sc->sc_cmdi == HIFN_D_CMD_RSIZE) {
1999                 sc->sc_cmdi = 0;
2000                 dma->cmdr[HIFN_D_CMD_RSIZE].l = htole32(HIFN_D_VALID |
2001                     HIFN_D_JUMP | HIFN_D_MASKDONEIRQ);
2002                 HIFN_CMDR_SYNC(sc, HIFN_D_CMD_RSIZE,
2003                     BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2004         }
2005         cmdi = sc->sc_cmdi++;
2006         cmdlen = hifn_write_command(cmd, dma->command_bufs[cmdi]);
2007         HIFN_CMD_SYNC(sc, cmdi, BUS_DMASYNC_PREWRITE);
2008
2009         /* .p for command/result already set */
2010         dma->cmdr[cmdi].l = htole32(cmdlen | HIFN_D_VALID | HIFN_D_LAST |
2011             HIFN_D_MASKDONEIRQ);
2012         HIFN_CMDR_SYNC(sc, cmdi,
2013             BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2014         sc->sc_cmdu++;
2015
2016         /*
2017          * We don't worry about missing an interrupt (which a "command wait"
2018          * interrupt salvages us from), unless there is more than one command
2019          * in the queue.
2020          */
2021         if (sc->sc_cmdu > 1) {
2022                 sc->sc_dmaier |= HIFN_DMAIER_C_WAIT;
2023                 WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier);
2024         }
2025
2026         hifnstats.hst_ipackets++;
2027         hifnstats.hst_ibytes += cmd->src_mapsize;
2028
2029         hifn_dmamap_load_src(sc, cmd);
2030
2031         /*
2032          * Unlike other descriptors, we don't mask done interrupt from
2033          * result descriptor.
2034          */
2035 #ifdef HIFN_DEBUG
2036         if (hifn_debug)
2037                 printf("load res\n");
2038 #endif
2039         if (sc->sc_resi == HIFN_D_RES_RSIZE) {
2040                 sc->sc_resi = 0;
2041                 dma->resr[HIFN_D_RES_RSIZE].l = htole32(HIFN_D_VALID |
2042                     HIFN_D_JUMP | HIFN_D_MASKDONEIRQ);
2043                 HIFN_RESR_SYNC(sc, HIFN_D_RES_RSIZE,
2044                     BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2045         }
2046         resi = sc->sc_resi++;
2047         KASSERT(sc->sc_hifn_commands[resi] == NULL,
2048                 ("hifn_crypto: command slot %u busy", resi));
2049         sc->sc_hifn_commands[resi] = cmd;
2050         HIFN_RES_SYNC(sc, resi, BUS_DMASYNC_PREREAD);
2051         if ((hint & CRYPTO_HINT_MORE) && sc->sc_curbatch < hifn_maxbatch) {
2052                 dma->resr[resi].l = htole32(HIFN_MAX_RESULT |
2053                     HIFN_D_VALID | HIFN_D_LAST | HIFN_D_MASKDONEIRQ);
2054                 sc->sc_curbatch++;
2055                 if (sc->sc_curbatch > hifnstats.hst_maxbatch)
2056                         hifnstats.hst_maxbatch = sc->sc_curbatch;
2057                 hifnstats.hst_totbatch++;
2058         } else {
2059                 dma->resr[resi].l = htole32(HIFN_MAX_RESULT |
2060                     HIFN_D_VALID | HIFN_D_LAST);
2061                 sc->sc_curbatch = 0;
2062         }
2063         HIFN_RESR_SYNC(sc, resi,
2064             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2065         sc->sc_resu++;
2066
2067         if (cmd->sloplen)
2068                 cmd->slopidx = resi;
2069
2070         hifn_dmamap_load_dst(sc, cmd);
2071
2072         csr = 0;
2073         if (sc->sc_c_busy == 0) {
2074                 csr |= HIFN_DMACSR_C_CTRL_ENA;
2075                 sc->sc_c_busy = 1;
2076         }
2077         if (sc->sc_s_busy == 0) {
2078                 csr |= HIFN_DMACSR_S_CTRL_ENA;
2079                 sc->sc_s_busy = 1;
2080         }
2081         if (sc->sc_r_busy == 0) {
2082                 csr |= HIFN_DMACSR_R_CTRL_ENA;
2083                 sc->sc_r_busy = 1;
2084         }
2085         if (sc->sc_d_busy == 0) {
2086                 csr |= HIFN_DMACSR_D_CTRL_ENA;
2087                 sc->sc_d_busy = 1;
2088         }
2089         if (csr)
2090                 WRITE_REG_1(sc, HIFN_1_DMA_CSR, csr);
2091
2092 #ifdef HIFN_DEBUG
2093         if (hifn_debug) {
2094                 device_printf(sc->sc_dev, "command: stat %8x ier %8x\n",
2095                     READ_REG_1(sc, HIFN_1_DMA_CSR),
2096                     READ_REG_1(sc, HIFN_1_DMA_IER));
2097         }
2098 #endif
2099
2100         sc->sc_active = 5;
2101         HIFN_UNLOCK(sc);
2102         KASSERT(err == 0, ("hifn_crypto: success with error %u", err));
2103         return (err);           /* success */
2104
2105 err_dstmap:
2106         if (cmd->src_map != cmd->dst_map)
2107                 bus_dmamap_unload(sc->sc_dmat, cmd->dst_map);
2108 err_dstmap1:
2109         if (cmd->src_map != cmd->dst_map)
2110                 bus_dmamap_destroy(sc->sc_dmat, cmd->dst_map);
2111 err_srcmap:
2112         if (crp->crp_flags & CRYPTO_F_IMBUF) {
2113                 if (cmd->src_m != cmd->dst_m)
2114                         m_freem(cmd->dst_m);
2115         }
2116         bus_dmamap_unload(sc->sc_dmat, cmd->src_map);
2117 err_srcmap1:
2118         bus_dmamap_destroy(sc->sc_dmat, cmd->src_map);
2119         HIFN_UNLOCK(sc);
2120         return (err);
2121 }
2122
2123 static void
2124 hifn_tick(void* vsc)
2125 {
2126         struct hifn_softc *sc = vsc;
2127
2128         HIFN_LOCK(sc);
2129         if (sc->sc_active == 0) {
2130                 u_int32_t r = 0;
2131
2132                 if (sc->sc_cmdu == 0 && sc->sc_c_busy) {
2133                         sc->sc_c_busy = 0;
2134                         r |= HIFN_DMACSR_C_CTRL_DIS;
2135                 }
2136                 if (sc->sc_srcu == 0 && sc->sc_s_busy) {
2137                         sc->sc_s_busy = 0;
2138                         r |= HIFN_DMACSR_S_CTRL_DIS;
2139                 }
2140                 if (sc->sc_dstu == 0 && sc->sc_d_busy) {
2141                         sc->sc_d_busy = 0;
2142                         r |= HIFN_DMACSR_D_CTRL_DIS;
2143                 }
2144                 if (sc->sc_resu == 0 && sc->sc_r_busy) {
2145                         sc->sc_r_busy = 0;
2146                         r |= HIFN_DMACSR_R_CTRL_DIS;
2147                 }
2148                 if (r)
2149                         WRITE_REG_1(sc, HIFN_1_DMA_CSR, r);
2150         } else
2151                 sc->sc_active--;
2152         HIFN_UNLOCK(sc);
2153         callout_reset(&sc->sc_tickto, hz, hifn_tick, sc);
2154 }
2155
2156 static void
2157 hifn_intr(void *arg)
2158 {
2159         struct hifn_softc *sc = arg;
2160         struct hifn_dma *dma;
2161         u_int32_t dmacsr, restart;
2162         int i, u;
2163
2164         dmacsr = READ_REG_1(sc, HIFN_1_DMA_CSR);
2165
2166         /* Nothing in the DMA unit interrupted */
2167         if ((dmacsr & sc->sc_dmaier) == 0)
2168                 return;
2169
2170         HIFN_LOCK(sc);
2171
2172         dma = sc->sc_dma;
2173
2174 #ifdef HIFN_DEBUG
2175         if (hifn_debug) {
2176                 device_printf(sc->sc_dev,
2177                     "irq: stat %08x ien %08x damier %08x i %d/%d/%d/%d k %d/%d/%d/%d u %d/%d/%d/%d\n",
2178                     dmacsr, READ_REG_1(sc, HIFN_1_DMA_IER), sc->sc_dmaier,
2179                     sc->sc_cmdi, sc->sc_srci, sc->sc_dsti, sc->sc_resi,
2180                     sc->sc_cmdk, sc->sc_srck, sc->sc_dstk, sc->sc_resk,
2181                     sc->sc_cmdu, sc->sc_srcu, sc->sc_dstu, sc->sc_resu);
2182         }
2183 #endif
2184
2185         WRITE_REG_1(sc, HIFN_1_DMA_CSR, dmacsr & sc->sc_dmaier);
2186
2187         if ((sc->sc_flags & HIFN_HAS_PUBLIC) &&
2188             (dmacsr & HIFN_DMACSR_PUBDONE))
2189                 WRITE_REG_1(sc, HIFN_1_PUB_STATUS,
2190                     READ_REG_1(sc, HIFN_1_PUB_STATUS) | HIFN_PUBSTS_DONE);
2191
2192         restart = dmacsr & (HIFN_DMACSR_D_OVER | HIFN_DMACSR_R_OVER);
2193         if (restart)
2194                 device_printf(sc->sc_dev, "overrun %x\n", dmacsr);
2195
2196         if (sc->sc_flags & HIFN_IS_7811) {
2197                 if (dmacsr & HIFN_DMACSR_ILLR)
2198                         device_printf(sc->sc_dev, "illegal read\n");
2199                 if (dmacsr & HIFN_DMACSR_ILLW)
2200                         device_printf(sc->sc_dev, "illegal write\n");
2201         }
2202
2203         restart = dmacsr & (HIFN_DMACSR_C_ABORT | HIFN_DMACSR_S_ABORT |
2204             HIFN_DMACSR_D_ABORT | HIFN_DMACSR_R_ABORT);
2205         if (restart) {
2206                 device_printf(sc->sc_dev, "abort, resetting.\n");
2207                 hifnstats.hst_abort++;
2208                 hifn_abort(sc);
2209                 HIFN_UNLOCK(sc);
2210                 return;
2211         }
2212
2213         if ((dmacsr & HIFN_DMACSR_C_WAIT) && (sc->sc_cmdu == 0)) {
2214                 /*
2215                  * If no slots to process and we receive a "waiting on
2216                  * command" interrupt, we disable the "waiting on command"
2217                  * (by clearing it).
2218                  */
2219                 sc->sc_dmaier &= ~HIFN_DMAIER_C_WAIT;
2220                 WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier);
2221         }
2222
2223         /* clear the rings */
2224         i = sc->sc_resk; u = sc->sc_resu;
2225         while (u != 0) {
2226                 HIFN_RESR_SYNC(sc, i,
2227                     BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2228                 if (dma->resr[i].l & htole32(HIFN_D_VALID)) {
2229                         HIFN_RESR_SYNC(sc, i,
2230                             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2231                         break;
2232                 }
2233
2234                 if (i != HIFN_D_RES_RSIZE) {
2235                         struct hifn_command *cmd;
2236                         u_int8_t *macbuf = NULL;
2237
2238                         HIFN_RES_SYNC(sc, i, BUS_DMASYNC_POSTREAD);
2239                         cmd = sc->sc_hifn_commands[i];
2240                         KASSERT(cmd != NULL,
2241                                 ("hifn_intr: null command slot %u", i));
2242                         sc->sc_hifn_commands[i] = NULL;
2243
2244                         if (cmd->base_masks & HIFN_BASE_CMD_MAC) {
2245                                 macbuf = dma->result_bufs[i];
2246                                 macbuf += 12;
2247                         }
2248
2249                         hifn_callback(sc, cmd, macbuf);
2250                         hifnstats.hst_opackets++;
2251                         u--;
2252                 }
2253
2254                 if (++i == (HIFN_D_RES_RSIZE + 1))
2255                         i = 0;
2256         }
2257         sc->sc_resk = i; sc->sc_resu = u;
2258
2259         i = sc->sc_srck; u = sc->sc_srcu;
2260         while (u != 0) {
2261                 if (i == HIFN_D_SRC_RSIZE)
2262                         i = 0;
2263                 HIFN_SRCR_SYNC(sc, i,
2264                     BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2265                 if (dma->srcr[i].l & htole32(HIFN_D_VALID)) {
2266                         HIFN_SRCR_SYNC(sc, i,
2267                             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2268                         break;
2269                 }
2270                 i++, u--;
2271         }
2272         sc->sc_srck = i; sc->sc_srcu = u;
2273
2274         i = sc->sc_cmdk; u = sc->sc_cmdu;
2275         while (u != 0) {
2276                 HIFN_CMDR_SYNC(sc, i,
2277                     BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2278                 if (dma->cmdr[i].l & htole32(HIFN_D_VALID)) {
2279                         HIFN_CMDR_SYNC(sc, i,
2280                             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2281                         break;
2282                 }
2283                 if (i != HIFN_D_CMD_RSIZE) {
2284                         u--;
2285                         HIFN_CMD_SYNC(sc, i, BUS_DMASYNC_POSTWRITE);
2286                 }
2287                 if (++i == (HIFN_D_CMD_RSIZE + 1))
2288                         i = 0;
2289         }
2290         sc->sc_cmdk = i; sc->sc_cmdu = u;
2291
2292         HIFN_UNLOCK(sc);
2293
2294         if (sc->sc_needwakeup) {                /* XXX check high watermark */
2295                 int wakeup = sc->sc_needwakeup & (CRYPTO_SYMQ|CRYPTO_ASYMQ);
2296 #ifdef HIFN_DEBUG
2297                 if (hifn_debug)
2298                         device_printf(sc->sc_dev,
2299                                 "wakeup crypto (%x) u %d/%d/%d/%d\n",
2300                                 sc->sc_needwakeup,
2301                                 sc->sc_cmdu, sc->sc_srcu, sc->sc_dstu, sc->sc_resu);
2302 #endif
2303                 sc->sc_needwakeup &= ~wakeup;
2304                 crypto_unblock(sc->sc_cid, wakeup);
2305         }
2306 }
2307
2308 /*
2309  * Allocate a new 'session' and return an encoded session id.  'sidp'
2310  * contains our registration id, and should contain an encoded session
2311  * id on successful allocation.
2312  */
2313 static int
2314 hifn_newsession(device_t dev, u_int32_t *sidp, struct cryptoini *cri)
2315 {
2316         struct hifn_softc *sc = device_get_softc(dev);
2317         struct cryptoini *c;
2318         int mac = 0, cry = 0, sesn;
2319         struct hifn_session *ses = NULL;
2320
2321         KASSERT(sc != NULL, ("hifn_newsession: null softc"));
2322         if (sidp == NULL || cri == NULL || sc == NULL)
2323                 return (EINVAL);
2324
2325         HIFN_LOCK(sc);
2326         if (sc->sc_sessions == NULL) {
2327                 ses = sc->sc_sessions = (struct hifn_session *)malloc(
2328                     sizeof(*ses), M_DEVBUF, M_NOWAIT);
2329                 if (ses == NULL) {
2330                         HIFN_UNLOCK(sc);
2331                         return (ENOMEM);
2332                 }
2333                 sesn = 0;
2334                 sc->sc_nsessions = 1;
2335         } else {
2336                 for (sesn = 0; sesn < sc->sc_nsessions; sesn++) {
2337                         if (!sc->sc_sessions[sesn].hs_used) {
2338                                 ses = &sc->sc_sessions[sesn];
2339                                 break;
2340                         }
2341                 }
2342
2343                 if (ses == NULL) {
2344                         sesn = sc->sc_nsessions;
2345                         ses = (struct hifn_session *)malloc((sesn + 1) *
2346                             sizeof(*ses), M_DEVBUF, M_NOWAIT);
2347                         if (ses == NULL) {
2348                                 HIFN_UNLOCK(sc);
2349                                 return (ENOMEM);
2350                         }
2351                         bcopy(sc->sc_sessions, ses, sesn * sizeof(*ses));
2352                         bzero(sc->sc_sessions, sesn * sizeof(*ses));
2353                         free(sc->sc_sessions, M_DEVBUF);
2354                         sc->sc_sessions = ses;
2355                         ses = &sc->sc_sessions[sesn];
2356                         sc->sc_nsessions++;
2357                 }
2358         }
2359         HIFN_UNLOCK(sc);
2360
2361         bzero(ses, sizeof(*ses));
2362         ses->hs_used = 1;
2363
2364         for (c = cri; c != NULL; c = c->cri_next) {
2365                 switch (c->cri_alg) {
2366                 case CRYPTO_MD5:
2367                 case CRYPTO_SHA1:
2368                 case CRYPTO_MD5_HMAC:
2369                 case CRYPTO_SHA1_HMAC:
2370                         if (mac)
2371                                 return (EINVAL);
2372                         mac = 1;
2373                         ses->hs_mlen = c->cri_mlen;
2374                         if (ses->hs_mlen == 0) {
2375                                 switch (c->cri_alg) {
2376                                 case CRYPTO_MD5:
2377                                 case CRYPTO_MD5_HMAC:
2378                                         ses->hs_mlen = 16;
2379                                         break;
2380                                 case CRYPTO_SHA1:
2381                                 case CRYPTO_SHA1_HMAC:
2382                                         ses->hs_mlen = 20;
2383                                         break;
2384                                 }
2385                         }
2386                         break;
2387                 case CRYPTO_DES_CBC:
2388                 case CRYPTO_3DES_CBC:
2389                 case CRYPTO_AES_CBC:
2390                         /* XXX this may read fewer, does it matter? */
2391                         read_random(ses->hs_iv,
2392                                 c->cri_alg == CRYPTO_AES_CBC ?
2393                                         HIFN_AES_IV_LENGTH : HIFN_IV_LENGTH);
2394                         /*FALLTHROUGH*/
2395                 case CRYPTO_ARC4:
2396                         if (cry)
2397                                 return (EINVAL);
2398                         cry = 1;
2399                         break;
2400                 default:
2401                         return (EINVAL);
2402                 }
2403         }
2404         if (mac == 0 && cry == 0)
2405                 return (EINVAL);
2406
2407         *sidp = HIFN_SID(device_get_unit(sc->sc_dev), sesn);
2408
2409         return (0);
2410 }
2411
2412 /*
2413  * Deallocate a session.
2414  * XXX this routine should run a zero'd mac/encrypt key into context ram.
2415  * XXX to blow away any keys already stored there.
2416  */
2417 static int
2418 hifn_freesession(device_t dev, u_int64_t tid)
2419 {
2420         struct hifn_softc *sc = device_get_softc(dev);
2421         int session, error;
2422         u_int32_t sid = CRYPTO_SESID2LID(tid);
2423
2424         KASSERT(sc != NULL, ("hifn_freesession: null softc"));
2425         if (sc == NULL)
2426                 return (EINVAL);
2427
2428         HIFN_LOCK(sc);
2429         session = HIFN_SESSION(sid);
2430         if (session < sc->sc_nsessions) {
2431                 bzero(&sc->sc_sessions[session], sizeof(struct hifn_session));
2432                 error = 0;
2433         } else
2434                 error = EINVAL;
2435         HIFN_UNLOCK(sc);
2436
2437         return (error);
2438 }
2439
2440 static int
2441 hifn_process(device_t dev, struct cryptop *crp, int hint)
2442 {
2443         struct hifn_softc *sc = device_get_softc(dev);
2444         struct hifn_command *cmd = NULL;
2445         int session, err, ivlen;
2446         struct cryptodesc *crd1, *crd2, *maccrd, *enccrd;
2447
2448         if (crp == NULL || crp->crp_callback == NULL) {
2449                 hifnstats.hst_invalid++;
2450                 return (EINVAL);
2451         }
2452         session = HIFN_SESSION(crp->crp_sid);
2453
2454         if (sc == NULL || session >= sc->sc_nsessions) {
2455                 err = EINVAL;
2456                 goto errout;
2457         }
2458
2459         cmd = malloc(sizeof(struct hifn_command), M_DEVBUF, M_NOWAIT | M_ZERO);
2460         if (cmd == NULL) {
2461                 hifnstats.hst_nomem++;
2462                 err = ENOMEM;
2463                 goto errout;
2464         }
2465
2466         if (crp->crp_flags & CRYPTO_F_IMBUF) {
2467                 cmd->src_m = (struct mbuf *)crp->crp_buf;
2468                 cmd->dst_m = (struct mbuf *)crp->crp_buf;
2469         } else if (crp->crp_flags & CRYPTO_F_IOV) {
2470                 cmd->src_io = (struct uio *)crp->crp_buf;
2471                 cmd->dst_io = (struct uio *)crp->crp_buf;
2472         } else {
2473                 err = EINVAL;
2474                 goto errout;    /* XXX we don't handle contiguous buffers! */
2475         }
2476
2477         crd1 = crp->crp_desc;
2478         if (crd1 == NULL) {
2479                 err = EINVAL;
2480                 goto errout;
2481         }
2482         crd2 = crd1->crd_next;
2483
2484         if (crd2 == NULL) {
2485                 if (crd1->crd_alg == CRYPTO_MD5_HMAC ||
2486                     crd1->crd_alg == CRYPTO_SHA1_HMAC ||
2487                     crd1->crd_alg == CRYPTO_SHA1 ||
2488                     crd1->crd_alg == CRYPTO_MD5) {
2489                         maccrd = crd1;
2490                         enccrd = NULL;
2491                 } else if (crd1->crd_alg == CRYPTO_DES_CBC ||
2492                     crd1->crd_alg == CRYPTO_3DES_CBC ||
2493                     crd1->crd_alg == CRYPTO_AES_CBC ||
2494                     crd1->crd_alg == CRYPTO_ARC4) {
2495                         if ((crd1->crd_flags & CRD_F_ENCRYPT) == 0)
2496                                 cmd->base_masks |= HIFN_BASE_CMD_DECODE;
2497                         maccrd = NULL;
2498                         enccrd = crd1;
2499                 } else {
2500                         err = EINVAL;
2501                         goto errout;
2502                 }
2503         } else {
2504                 if ((crd1->crd_alg == CRYPTO_MD5_HMAC ||
2505                      crd1->crd_alg == CRYPTO_SHA1_HMAC ||
2506                      crd1->crd_alg == CRYPTO_MD5 ||
2507                      crd1->crd_alg == CRYPTO_SHA1) &&
2508                     (crd2->crd_alg == CRYPTO_DES_CBC ||
2509                      crd2->crd_alg == CRYPTO_3DES_CBC ||
2510                      crd2->crd_alg == CRYPTO_AES_CBC ||
2511                      crd2->crd_alg == CRYPTO_ARC4) &&
2512                     ((crd2->crd_flags & CRD_F_ENCRYPT) == 0)) {
2513                         cmd->base_masks = HIFN_BASE_CMD_DECODE;
2514                         maccrd = crd1;
2515                         enccrd = crd2;
2516                 } else if ((crd1->crd_alg == CRYPTO_DES_CBC ||
2517                      crd1->crd_alg == CRYPTO_ARC4 ||
2518                      crd1->crd_alg == CRYPTO_3DES_CBC ||
2519                      crd1->crd_alg == CRYPTO_AES_CBC) &&
2520                     (crd2->crd_alg == CRYPTO_MD5_HMAC ||
2521                      crd2->crd_alg == CRYPTO_SHA1_HMAC ||
2522                      crd2->crd_alg == CRYPTO_MD5 ||
2523                      crd2->crd_alg == CRYPTO_SHA1) &&
2524                     (crd1->crd_flags & CRD_F_ENCRYPT)) {
2525                         enccrd = crd1;
2526                         maccrd = crd2;
2527                 } else {
2528                         /*
2529                          * We cannot order the 7751 as requested
2530                          */
2531                         err = EINVAL;
2532                         goto errout;
2533                 }
2534         }
2535
2536         if (enccrd) {
2537                 cmd->enccrd = enccrd;
2538                 cmd->base_masks |= HIFN_BASE_CMD_CRYPT;
2539                 switch (enccrd->crd_alg) {
2540                 case CRYPTO_ARC4:
2541                         cmd->cry_masks |= HIFN_CRYPT_CMD_ALG_RC4;
2542                         break;
2543                 case CRYPTO_DES_CBC:
2544                         cmd->cry_masks |= HIFN_CRYPT_CMD_ALG_DES |
2545                             HIFN_CRYPT_CMD_MODE_CBC |
2546                             HIFN_CRYPT_CMD_NEW_IV;
2547                         break;
2548                 case CRYPTO_3DES_CBC:
2549                         cmd->cry_masks |= HIFN_CRYPT_CMD_ALG_3DES |
2550                             HIFN_CRYPT_CMD_MODE_CBC |
2551                             HIFN_CRYPT_CMD_NEW_IV;
2552                         break;
2553                 case CRYPTO_AES_CBC:
2554                         cmd->cry_masks |= HIFN_CRYPT_CMD_ALG_AES |
2555                             HIFN_CRYPT_CMD_MODE_CBC |
2556                             HIFN_CRYPT_CMD_NEW_IV;
2557                         break;
2558                 default:
2559                         err = EINVAL;
2560                         goto errout;
2561                 }
2562                 if (enccrd->crd_alg != CRYPTO_ARC4) {
2563                         ivlen = ((enccrd->crd_alg == CRYPTO_AES_CBC) ?
2564                                 HIFN_AES_IV_LENGTH : HIFN_IV_LENGTH);
2565                         if (enccrd->crd_flags & CRD_F_ENCRYPT) {
2566                                 if (enccrd->crd_flags & CRD_F_IV_EXPLICIT)
2567                                         bcopy(enccrd->crd_iv, cmd->iv, ivlen);
2568                                 else
2569                                         bcopy(sc->sc_sessions[session].hs_iv,
2570                                             cmd->iv, ivlen);
2571
2572                                 if ((enccrd->crd_flags & CRD_F_IV_PRESENT)
2573                                     == 0) {
2574                                         crypto_copyback(crp->crp_flags,
2575                                             crp->crp_buf, enccrd->crd_inject,
2576                                             ivlen, cmd->iv);
2577                                 }
2578                         } else {
2579                                 if (enccrd->crd_flags & CRD_F_IV_EXPLICIT)
2580                                         bcopy(enccrd->crd_iv, cmd->iv, ivlen);
2581                                 else {
2582                                         crypto_copydata(crp->crp_flags,
2583                                             crp->crp_buf, enccrd->crd_inject,
2584                                             ivlen, cmd->iv);
2585                                 }
2586                         }
2587                 }
2588
2589                 if (enccrd->crd_flags & CRD_F_KEY_EXPLICIT)
2590                         cmd->cry_masks |= HIFN_CRYPT_CMD_NEW_KEY;
2591                 cmd->ck = enccrd->crd_key;
2592                 cmd->cklen = enccrd->crd_klen >> 3;
2593                 cmd->cry_masks |= HIFN_CRYPT_CMD_NEW_KEY;
2594
2595                 /*
2596                  * Need to specify the size for the AES key in the masks.
2597                  */
2598                 if ((cmd->cry_masks & HIFN_CRYPT_CMD_ALG_MASK) ==
2599                     HIFN_CRYPT_CMD_ALG_AES) {
2600                         switch (cmd->cklen) {
2601                         case 16:
2602                                 cmd->cry_masks |= HIFN_CRYPT_CMD_KSZ_128;
2603                                 break;
2604                         case 24:
2605                                 cmd->cry_masks |= HIFN_CRYPT_CMD_KSZ_192;
2606                                 break;
2607                         case 32:
2608                                 cmd->cry_masks |= HIFN_CRYPT_CMD_KSZ_256;
2609                                 break;
2610                         default:
2611                                 err = EINVAL;
2612                                 goto errout;
2613                         }
2614                 }
2615         }
2616
2617         if (maccrd) {
2618                 cmd->maccrd = maccrd;
2619                 cmd->base_masks |= HIFN_BASE_CMD_MAC;
2620
2621                 switch (maccrd->crd_alg) {
2622                 case CRYPTO_MD5:
2623                         cmd->mac_masks |= HIFN_MAC_CMD_ALG_MD5 |
2624                             HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HASH |
2625                             HIFN_MAC_CMD_POS_IPSEC;
2626                        break;
2627                 case CRYPTO_MD5_HMAC:
2628                         cmd->mac_masks |= HIFN_MAC_CMD_ALG_MD5 |
2629                             HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HMAC |
2630                             HIFN_MAC_CMD_POS_IPSEC | HIFN_MAC_CMD_TRUNC;
2631                         break;
2632                 case CRYPTO_SHA1:
2633                         cmd->mac_masks |= HIFN_MAC_CMD_ALG_SHA1 |
2634                             HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HASH |
2635                             HIFN_MAC_CMD_POS_IPSEC;
2636                         break;
2637                 case CRYPTO_SHA1_HMAC:
2638                         cmd->mac_masks |= HIFN_MAC_CMD_ALG_SHA1 |
2639                             HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HMAC |
2640                             HIFN_MAC_CMD_POS_IPSEC | HIFN_MAC_CMD_TRUNC;
2641                         break;
2642                 }
2643
2644                 if (maccrd->crd_alg == CRYPTO_SHA1_HMAC ||
2645                      maccrd->crd_alg == CRYPTO_MD5_HMAC) {
2646                         cmd->mac_masks |= HIFN_MAC_CMD_NEW_KEY;
2647                         bcopy(maccrd->crd_key, cmd->mac, maccrd->crd_klen >> 3);
2648                         bzero(cmd->mac + (maccrd->crd_klen >> 3),
2649                             HIFN_MAC_KEY_LENGTH - (maccrd->crd_klen >> 3));
2650                 }
2651         }
2652
2653         cmd->crp = crp;
2654         cmd->session_num = session;
2655         cmd->softc = sc;
2656
2657         err = hifn_crypto(sc, cmd, crp, hint);
2658         if (!err) {
2659                 return 0;
2660         } else if (err == ERESTART) {
2661                 /*
2662                  * There weren't enough resources to dispatch the request
2663                  * to the part.  Notify the caller so they'll requeue this
2664                  * request and resubmit it again soon.
2665                  */
2666 #ifdef HIFN_DEBUG
2667                 if (hifn_debug)
2668                         device_printf(sc->sc_dev, "requeue request\n");
2669 #endif
2670                 free(cmd, M_DEVBUF);
2671                 sc->sc_needwakeup |= CRYPTO_SYMQ;
2672                 return (err);
2673         }
2674
2675 errout:
2676         if (cmd != NULL)
2677                 free(cmd, M_DEVBUF);
2678         if (err == EINVAL)
2679                 hifnstats.hst_invalid++;
2680         else
2681                 hifnstats.hst_nomem++;
2682         crp->crp_etype = err;
2683         crypto_done(crp);
2684         return (err);
2685 }
2686
2687 static void
2688 hifn_abort(struct hifn_softc *sc)
2689 {
2690         struct hifn_dma *dma = sc->sc_dma;
2691         struct hifn_command *cmd;
2692         struct cryptop *crp;
2693         int i, u;
2694
2695         i = sc->sc_resk; u = sc->sc_resu;
2696         while (u != 0) {
2697                 cmd = sc->sc_hifn_commands[i];
2698                 KASSERT(cmd != NULL, ("hifn_abort: null command slot %u", i));
2699                 sc->sc_hifn_commands[i] = NULL;
2700                 crp = cmd->crp;
2701
2702                 if ((dma->resr[i].l & htole32(HIFN_D_VALID)) == 0) {
2703                         /* Salvage what we can. */
2704                         u_int8_t *macbuf;
2705
2706                         if (cmd->base_masks & HIFN_BASE_CMD_MAC) {
2707                                 macbuf = dma->result_bufs[i];
2708                                 macbuf += 12;
2709                         } else
2710                                 macbuf = NULL;
2711                         hifnstats.hst_opackets++;
2712                         hifn_callback(sc, cmd, macbuf);
2713                 } else {
2714                         if (cmd->src_map == cmd->dst_map) {
2715                                 bus_dmamap_sync(sc->sc_dmat, cmd->src_map,
2716                                     BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
2717                         } else {
2718                                 bus_dmamap_sync(sc->sc_dmat, cmd->src_map,
2719                                     BUS_DMASYNC_POSTWRITE);
2720                                 bus_dmamap_sync(sc->sc_dmat, cmd->dst_map,
2721                                     BUS_DMASYNC_POSTREAD);
2722                         }
2723
2724                         if (cmd->src_m != cmd->dst_m) {
2725                                 m_freem(cmd->src_m);
2726                                 crp->crp_buf = (caddr_t)cmd->dst_m;
2727                         }
2728
2729                         /* non-shared buffers cannot be restarted */
2730                         if (cmd->src_map != cmd->dst_map) {
2731                                 /*
2732                                  * XXX should be EAGAIN, delayed until
2733                                  * after the reset.
2734                                  */
2735                                 crp->crp_etype = ENOMEM;
2736                                 bus_dmamap_unload(sc->sc_dmat, cmd->dst_map);
2737                                 bus_dmamap_destroy(sc->sc_dmat, cmd->dst_map);
2738                         } else
2739                                 crp->crp_etype = ENOMEM;
2740
2741                         bus_dmamap_unload(sc->sc_dmat, cmd->src_map);
2742                         bus_dmamap_destroy(sc->sc_dmat, cmd->src_map);
2743
2744                         free(cmd, M_DEVBUF);
2745                         if (crp->crp_etype != EAGAIN)
2746                                 crypto_done(crp);
2747                 }
2748
2749                 if (++i == HIFN_D_RES_RSIZE)
2750                         i = 0;
2751                 u--;
2752         }
2753         sc->sc_resk = i; sc->sc_resu = u;
2754
2755         hifn_reset_board(sc, 1);
2756         hifn_init_dma(sc);
2757         hifn_init_pci_registers(sc);
2758 }
2759
2760 static void
2761 hifn_callback(struct hifn_softc *sc, struct hifn_command *cmd, u_int8_t *macbuf)
2762 {
2763         struct hifn_dma *dma = sc->sc_dma;
2764         struct cryptop *crp = cmd->crp;
2765         struct cryptodesc *crd;
2766         struct mbuf *m;
2767         int totlen, i, u, ivlen;
2768
2769         if (cmd->src_map == cmd->dst_map) {
2770                 bus_dmamap_sync(sc->sc_dmat, cmd->src_map,
2771                     BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
2772         } else {
2773                 bus_dmamap_sync(sc->sc_dmat, cmd->src_map,
2774                     BUS_DMASYNC_POSTWRITE);
2775                 bus_dmamap_sync(sc->sc_dmat, cmd->dst_map,
2776                     BUS_DMASYNC_POSTREAD);
2777         }
2778
2779         if (crp->crp_flags & CRYPTO_F_IMBUF) {
2780                 if (cmd->src_m != cmd->dst_m) {
2781                         crp->crp_buf = (caddr_t)cmd->dst_m;
2782                         totlen = cmd->src_mapsize;
2783                         for (m = cmd->dst_m; m != NULL; m = m->m_next) {
2784                                 if (totlen < m->m_len) {
2785                                         m->m_len = totlen;
2786                                         totlen = 0;
2787                                 } else
2788                                         totlen -= m->m_len;
2789                         }
2790                         cmd->dst_m->m_pkthdr.len = cmd->src_m->m_pkthdr.len;
2791                         m_freem(cmd->src_m);
2792                 }
2793         }
2794
2795         if (cmd->sloplen != 0) {
2796                 crypto_copyback(crp->crp_flags, crp->crp_buf,
2797                     cmd->src_mapsize - cmd->sloplen, cmd->sloplen,
2798                     (caddr_t)&dma->slop[cmd->slopidx]);
2799         }
2800
2801         i = sc->sc_dstk; u = sc->sc_dstu;
2802         while (u != 0) {
2803                 if (i == HIFN_D_DST_RSIZE)
2804                         i = 0;
2805                 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap,
2806                     BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2807                 if (dma->dstr[i].l & htole32(HIFN_D_VALID)) {
2808                         bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap,
2809                             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2810                         break;
2811                 }
2812                 i++, u--;
2813         }
2814         sc->sc_dstk = i; sc->sc_dstu = u;
2815
2816         hifnstats.hst_obytes += cmd->dst_mapsize;
2817
2818         if ((cmd->base_masks & (HIFN_BASE_CMD_CRYPT | HIFN_BASE_CMD_DECODE)) ==
2819             HIFN_BASE_CMD_CRYPT) {
2820                 for (crd = crp->crp_desc; crd; crd = crd->crd_next) {
2821                         if (crd->crd_alg != CRYPTO_DES_CBC &&
2822                             crd->crd_alg != CRYPTO_3DES_CBC &&
2823                             crd->crd_alg != CRYPTO_AES_CBC)
2824                                 continue;
2825                         ivlen = ((crd->crd_alg == CRYPTO_AES_CBC) ?
2826                                 HIFN_AES_IV_LENGTH : HIFN_IV_LENGTH);
2827                         crypto_copydata(crp->crp_flags, crp->crp_buf,
2828                             crd->crd_skip + crd->crd_len - ivlen, ivlen,
2829                             cmd->softc->sc_sessions[cmd->session_num].hs_iv);
2830                         break;
2831                 }
2832         }
2833
2834         if (macbuf != NULL) {
2835                 for (crd = crp->crp_desc; crd; crd = crd->crd_next) {
2836                         int len;
2837
2838                         if (crd->crd_alg != CRYPTO_MD5 &&
2839                             crd->crd_alg != CRYPTO_SHA1 &&
2840                             crd->crd_alg != CRYPTO_MD5_HMAC &&
2841                             crd->crd_alg != CRYPTO_SHA1_HMAC) {
2842                                 continue;
2843                         }
2844                         len = cmd->softc->sc_sessions[cmd->session_num].hs_mlen;
2845                         crypto_copyback(crp->crp_flags, crp->crp_buf,
2846                             crd->crd_inject, len, macbuf);
2847                         break;
2848                 }
2849         }
2850
2851         if (cmd->src_map != cmd->dst_map) {
2852                 bus_dmamap_unload(sc->sc_dmat, cmd->dst_map);
2853                 bus_dmamap_destroy(sc->sc_dmat, cmd->dst_map);
2854         }
2855         bus_dmamap_unload(sc->sc_dmat, cmd->src_map);
2856         bus_dmamap_destroy(sc->sc_dmat, cmd->src_map);
2857         free(cmd, M_DEVBUF);
2858         crypto_done(crp);
2859 }
2860
2861 /*
2862  * 7811 PB3 rev/2 parts lock-up on burst writes to Group 0
2863  * and Group 1 registers; avoid conditions that could create
2864  * burst writes by doing a read in between the writes.
2865  *
2866  * NB: The read we interpose is always to the same register;
2867  *     we do this because reading from an arbitrary (e.g. last)
2868  *     register may not always work.
2869  */
2870 static void
2871 hifn_write_reg_0(struct hifn_softc *sc, bus_size_t reg, u_int32_t val)
2872 {
2873         if (sc->sc_flags & HIFN_IS_7811) {
2874                 if (sc->sc_bar0_lastreg == reg - 4)
2875                         bus_space_read_4(sc->sc_st0, sc->sc_sh0, HIFN_0_PUCNFG);
2876                 sc->sc_bar0_lastreg = reg;
2877         }
2878         bus_space_write_4(sc->sc_st0, sc->sc_sh0, reg, val);
2879 }
2880
2881 static void
2882 hifn_write_reg_1(struct hifn_softc *sc, bus_size_t reg, u_int32_t val)
2883 {
2884         if (sc->sc_flags & HIFN_IS_7811) {
2885                 if (sc->sc_bar1_lastreg == reg - 4)
2886                         bus_space_read_4(sc->sc_st1, sc->sc_sh1, HIFN_1_REVID);
2887                 sc->sc_bar1_lastreg = reg;
2888         }
2889         bus_space_write_4(sc->sc_st1, sc->sc_sh1, reg, val);
2890 }
2891
2892 #ifdef HIFN_VULCANDEV
2893 /*
2894  * this code provides support for mapping the PK engine's register
2895  * into a userspace program.
2896  *
2897  */
2898 static int
2899 vulcanpk_mmap(struct cdev *dev, vm_ooffset_t offset,
2900               vm_paddr_t *paddr, int nprot, vm_memattr_t *memattr)
2901 {
2902         struct hifn_softc *sc;
2903         vm_paddr_t pd;
2904         void *b;
2905
2906         sc = dev->si_drv1;
2907
2908         pd = rman_get_start(sc->sc_bar1res);
2909         b = rman_get_virtual(sc->sc_bar1res);
2910
2911 #if 0
2912         printf("vpk mmap: %p(%016llx) offset=%lld\n", b,
2913             (unsigned long long)pd, offset);
2914         hexdump(b, HIFN_1_PUB_MEMEND, "vpk", 0);
2915 #endif
2916
2917         if (offset == 0) {
2918                 *paddr = pd;
2919                 return (0);
2920         }
2921         return (-1);
2922 }
2923
2924 static struct cdevsw vulcanpk_cdevsw = {
2925         .d_version =    D_VERSION,
2926         .d_mmap =       vulcanpk_mmap,
2927         .d_name =       "vulcanpk",
2928 };
2929 #endif /* HIFN_VULCANDEV */