1 /* $OpenBSD: hifn7751.c,v 1.120 2002/05/17 00:33:34 deraadt Exp $ */
4 * Invertex AEON / Hifn 7751 driver
5 * Copyright (c) 1999 Invertex Inc. All rights reserved.
6 * Copyright (c) 1999 Theo de Raadt
7 * Copyright (c) 2000-2001 Network Security Technologies, Inc.
8 * http://www.netsec.net
9 * Copyright (c) 2003 Hifn Inc.
11 * This driver is based on a previous driver by Invertex, for which they
12 * requested: Please send any comments, feedback, bug-fixes, or feature
13 * requests to software@invertex.com.
15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions
19 * 1. Redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer.
21 * 2. Redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution.
24 * 3. The name of the author may not be used to endorse or promote products
25 * derived from this software without specific prior written permission.
27 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
28 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
29 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
30 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
31 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
32 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
33 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
34 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
35 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
36 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 * Effort sponsored in part by the Defense Advanced Research Projects
39 * Agency (DARPA) and Air Force Research Laboratory, Air Force
40 * Materiel Command, USAF, under agreement number F30602-01-2-0537.
43 #include <sys/cdefs.h>
44 __FBSDID("$FreeBSD$");
47 * Driver for various Hifn encryption processors.
51 #include <sys/param.h>
52 #include <sys/systm.h>
54 #include <sys/errno.h>
55 #include <sys/malloc.h>
56 #include <sys/kernel.h>
57 #include <sys/module.h>
60 #include <sys/mutex.h>
61 #include <sys/sysctl.h>
66 #include <machine/bus.h>
67 #include <machine/resource.h>
71 #include <opencrypto/cryptodev.h>
72 #include <sys/random.h>
75 #include "cryptodev_if.h"
77 #include <dev/pci/pcivar.h>
78 #include <dev/pci/pcireg.h>
81 #include <dev/rndtest/rndtest.h>
83 #include <dev/hifn/hifn7751reg.h>
84 #include <dev/hifn/hifn7751var.h>
90 static struct cdevsw vulcanpk_cdevsw; /* forward declaration */
94 * Prototypes and count for the pci_device structure
96 static int hifn_probe(device_t);
97 static int hifn_attach(device_t);
98 static int hifn_detach(device_t);
99 static int hifn_suspend(device_t);
100 static int hifn_resume(device_t);
101 static int hifn_shutdown(device_t);
103 static int hifn_newsession(device_t, u_int32_t *, struct cryptoini *);
104 static int hifn_freesession(device_t, u_int64_t);
105 static int hifn_process(device_t, struct cryptop *, int);
107 static device_method_t hifn_methods[] = {
108 /* Device interface */
109 DEVMETHOD(device_probe, hifn_probe),
110 DEVMETHOD(device_attach, hifn_attach),
111 DEVMETHOD(device_detach, hifn_detach),
112 DEVMETHOD(device_suspend, hifn_suspend),
113 DEVMETHOD(device_resume, hifn_resume),
114 DEVMETHOD(device_shutdown, hifn_shutdown),
116 /* crypto device methods */
117 DEVMETHOD(cryptodev_newsession, hifn_newsession),
118 DEVMETHOD(cryptodev_freesession,hifn_freesession),
119 DEVMETHOD(cryptodev_process, hifn_process),
123 static driver_t hifn_driver = {
126 sizeof (struct hifn_softc)
128 static devclass_t hifn_devclass;
130 DRIVER_MODULE(hifn, pci, hifn_driver, hifn_devclass, 0, 0);
131 MODULE_DEPEND(hifn, crypto, 1, 1, 1);
133 MODULE_DEPEND(hifn, rndtest, 1, 1, 1);
136 static void hifn_reset_board(struct hifn_softc *, int);
137 static void hifn_reset_puc(struct hifn_softc *);
138 static void hifn_puc_wait(struct hifn_softc *);
139 static int hifn_enable_crypto(struct hifn_softc *);
140 static void hifn_set_retry(struct hifn_softc *sc);
141 static void hifn_init_dma(struct hifn_softc *);
142 static void hifn_init_pci_registers(struct hifn_softc *);
143 static int hifn_sramsize(struct hifn_softc *);
144 static int hifn_dramsize(struct hifn_softc *);
145 static int hifn_ramtype(struct hifn_softc *);
146 static void hifn_sessions(struct hifn_softc *);
147 static void hifn_intr(void *);
148 static u_int hifn_write_command(struct hifn_command *, u_int8_t *);
149 static u_int32_t hifn_next_signature(u_int32_t a, u_int cnt);
150 static void hifn_callback(struct hifn_softc *, struct hifn_command *, u_int8_t *);
151 static int hifn_crypto(struct hifn_softc *, struct hifn_command *, struct cryptop *, int);
152 static int hifn_readramaddr(struct hifn_softc *, int, u_int8_t *);
153 static int hifn_writeramaddr(struct hifn_softc *, int, u_int8_t *);
154 static int hifn_dmamap_load_src(struct hifn_softc *, struct hifn_command *);
155 static int hifn_dmamap_load_dst(struct hifn_softc *, struct hifn_command *);
156 static int hifn_init_pubrng(struct hifn_softc *);
157 static void hifn_rng(void *);
158 static void hifn_tick(void *);
159 static void hifn_abort(struct hifn_softc *);
160 static void hifn_alloc_slot(struct hifn_softc *, int *, int *, int *, int *);
162 static void hifn_write_reg_0(struct hifn_softc *, bus_size_t, u_int32_t);
163 static void hifn_write_reg_1(struct hifn_softc *, bus_size_t, u_int32_t);
165 static __inline u_int32_t
166 READ_REG_0(struct hifn_softc *sc, bus_size_t reg)
168 u_int32_t v = bus_space_read_4(sc->sc_st0, sc->sc_sh0, reg);
169 sc->sc_bar0_lastreg = (bus_size_t) -1;
172 #define WRITE_REG_0(sc, reg, val) hifn_write_reg_0(sc, reg, val)
174 static __inline u_int32_t
175 READ_REG_1(struct hifn_softc *sc, bus_size_t reg)
177 u_int32_t v = bus_space_read_4(sc->sc_st1, sc->sc_sh1, reg);
178 sc->sc_bar1_lastreg = (bus_size_t) -1;
181 #define WRITE_REG_1(sc, reg, val) hifn_write_reg_1(sc, reg, val)
183 static SYSCTL_NODE(_hw, OID_AUTO, hifn, CTLFLAG_RD, 0,
184 "Hifn driver parameters");
187 static int hifn_debug = 0;
188 SYSCTL_INT(_hw_hifn, OID_AUTO, debug, CTLFLAG_RW, &hifn_debug,
189 0, "control debugging msgs");
192 static struct hifn_stats hifnstats;
193 SYSCTL_STRUCT(_hw_hifn, OID_AUTO, stats, CTLFLAG_RD, &hifnstats,
194 hifn_stats, "driver statistics");
195 static int hifn_maxbatch = 1;
196 SYSCTL_INT(_hw_hifn, OID_AUTO, maxbatch, CTLFLAG_RW, &hifn_maxbatch,
197 0, "max ops to batch w/o interrupt");
200 * Probe for a supported device. The PCI vendor and device
201 * IDs are used to detect devices we know how to handle.
204 hifn_probe(device_t dev)
206 if (pci_get_vendor(dev) == PCI_VENDOR_INVERTEX &&
207 pci_get_device(dev) == PCI_PRODUCT_INVERTEX_AEON)
208 return (BUS_PROBE_DEFAULT);
209 if (pci_get_vendor(dev) == PCI_VENDOR_HIFN &&
210 (pci_get_device(dev) == PCI_PRODUCT_HIFN_7751 ||
211 pci_get_device(dev) == PCI_PRODUCT_HIFN_7951 ||
212 pci_get_device(dev) == PCI_PRODUCT_HIFN_7955 ||
213 pci_get_device(dev) == PCI_PRODUCT_HIFN_7956 ||
214 pci_get_device(dev) == PCI_PRODUCT_HIFN_7811))
215 return (BUS_PROBE_DEFAULT);
216 if (pci_get_vendor(dev) == PCI_VENDOR_NETSEC &&
217 pci_get_device(dev) == PCI_PRODUCT_NETSEC_7751)
218 return (BUS_PROBE_DEFAULT);
223 hifn_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
225 bus_addr_t *paddr = (bus_addr_t*) arg;
226 *paddr = segs->ds_addr;
230 hifn_partname(struct hifn_softc *sc)
232 /* XXX sprintf numbers when not decoded */
233 switch (pci_get_vendor(sc->sc_dev)) {
234 case PCI_VENDOR_HIFN:
235 switch (pci_get_device(sc->sc_dev)) {
236 case PCI_PRODUCT_HIFN_6500: return "Hifn 6500";
237 case PCI_PRODUCT_HIFN_7751: return "Hifn 7751";
238 case PCI_PRODUCT_HIFN_7811: return "Hifn 7811";
239 case PCI_PRODUCT_HIFN_7951: return "Hifn 7951";
240 case PCI_PRODUCT_HIFN_7955: return "Hifn 7955";
241 case PCI_PRODUCT_HIFN_7956: return "Hifn 7956";
243 return "Hifn unknown-part";
244 case PCI_VENDOR_INVERTEX:
245 switch (pci_get_device(sc->sc_dev)) {
246 case PCI_PRODUCT_INVERTEX_AEON: return "Invertex AEON";
248 return "Invertex unknown-part";
249 case PCI_VENDOR_NETSEC:
250 switch (pci_get_device(sc->sc_dev)) {
251 case PCI_PRODUCT_NETSEC_7751: return "NetSec 7751";
253 return "NetSec unknown-part";
255 return "Unknown-vendor unknown-part";
259 default_harvest(struct rndtest_state *rsp, void *buf, u_int count)
261 random_harvest(buf, count, count*NBBY/2, RANDOM_PURE_HIFN);
265 checkmaxmin(device_t dev, const char *what, u_int v, u_int min, u_int max)
268 device_printf(dev, "Warning, %s %u out of range, "
269 "using max %u\n", what, v, max);
271 } else if (v < min) {
272 device_printf(dev, "Warning, %s %u out of range, "
273 "using min %u\n", what, v, min);
280 * Select PLL configuration for 795x parts. This is complicated in
281 * that we cannot determine the optimal parameters without user input.
282 * The reference clock is derived from an external clock through a
283 * multiplier. The external clock is either the host bus (i.e. PCI)
284 * or an external clock generator. When using the PCI bus we assume
285 * the clock is either 33 or 66 MHz; for an external source we cannot
288 * PLL configuration is done with a string: "pci" for PCI bus, or "ext"
289 * for an external source, followed by the frequency. We calculate
290 * the appropriate multiplier and PLL register contents accordingly.
291 * When no configuration is given we default to "pci66" since that
292 * always will allow the card to work. If a card is using the PCI
293 * bus clock and in a 33MHz slot then it will be operating at half
294 * speed until the correct information is provided.
296 * We use a default setting of "ext66" because according to Mike Ham
297 * of HiFn, almost every board in existence has an external crystal
298 * populated at 66Mhz. Using PCI can be a problem on modern motherboards,
299 * because PCI33 can have clocks from 0 to 33Mhz, and some have
300 * non-PCI-compliant spread-spectrum clocks, which can confuse the pll.
303 hifn_getpllconfig(device_t dev, u_int *pll)
306 u_int freq, mul, fl, fh;
310 if (resource_string_value("hifn", device_get_unit(dev),
311 "pllconfig", &pllspec))
315 if (strncmp(pllspec, "ext", 3) == 0) {
317 pllconfig |= HIFN_PLL_REF_SEL;
318 switch (pci_get_device(dev)) {
319 case PCI_PRODUCT_HIFN_7955:
320 case PCI_PRODUCT_HIFN_7956:
324 case PCI_PRODUCT_HIFN_7954:
329 } else if (strncmp(pllspec, "pci", 3) == 0)
331 freq = strtoul(pllspec, &nxt, 10);
335 freq = checkmaxmin(dev, "frequency", freq, fl, fh);
337 * Calculate multiplier. We target a Fck of 266 MHz,
338 * allowing only even values, possibly rounded down.
339 * Multipliers > 8 must set the charge pump current.
341 mul = checkmaxmin(dev, "PLL divisor", (266 / freq) &~ 1, 2, 12);
342 pllconfig |= (mul / 2 - 1) << HIFN_PLL_ND_SHIFT;
344 pllconfig |= HIFN_PLL_IS;
349 * Attach an interface that successfully probed.
352 hifn_attach(device_t dev)
354 struct hifn_softc *sc = device_get_softc(dev);
362 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), "hifn driver", MTX_DEF);
364 /* XXX handle power management */
367 * The 7951 and 795x have a random number generator and
368 * public key support; note this.
370 if (pci_get_vendor(dev) == PCI_VENDOR_HIFN &&
371 (pci_get_device(dev) == PCI_PRODUCT_HIFN_7951 ||
372 pci_get_device(dev) == PCI_PRODUCT_HIFN_7955 ||
373 pci_get_device(dev) == PCI_PRODUCT_HIFN_7956))
374 sc->sc_flags = HIFN_HAS_RNG | HIFN_HAS_PUBLIC;
376 * The 7811 has a random number generator and
377 * we also note it's identity 'cuz of some quirks.
379 if (pci_get_vendor(dev) == PCI_VENDOR_HIFN &&
380 pci_get_device(dev) == PCI_PRODUCT_HIFN_7811)
381 sc->sc_flags |= HIFN_IS_7811 | HIFN_HAS_RNG;
384 * The 795x parts support AES.
386 if (pci_get_vendor(dev) == PCI_VENDOR_HIFN &&
387 (pci_get_device(dev) == PCI_PRODUCT_HIFN_7955 ||
388 pci_get_device(dev) == PCI_PRODUCT_HIFN_7956)) {
389 sc->sc_flags |= HIFN_IS_7956 | HIFN_HAS_AES;
391 * Select PLL configuration. This depends on the
392 * bus and board design and must be manually configured
393 * if the default setting is unacceptable.
395 hifn_getpllconfig(dev, &sc->sc_pllconfig);
399 * Setup PCI resources. Note that we record the bus
400 * tag and handle for each register mapping, this is
401 * used by the READ_REG_0, WRITE_REG_0, READ_REG_1,
402 * and WRITE_REG_1 macros throughout the driver.
404 pci_enable_busmaster(dev);
407 sc->sc_bar0res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
409 if (sc->sc_bar0res == NULL) {
410 device_printf(dev, "cannot map bar%d register space\n", 0);
413 sc->sc_st0 = rman_get_bustag(sc->sc_bar0res);
414 sc->sc_sh0 = rman_get_bushandle(sc->sc_bar0res);
415 sc->sc_bar0_lastreg = (bus_size_t) -1;
418 sc->sc_bar1res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
420 if (sc->sc_bar1res == NULL) {
421 device_printf(dev, "cannot map bar%d register space\n", 1);
424 sc->sc_st1 = rman_get_bustag(sc->sc_bar1res);
425 sc->sc_sh1 = rman_get_bushandle(sc->sc_bar1res);
426 sc->sc_bar1_lastreg = (bus_size_t) -1;
431 * Setup the area where the Hifn DMA's descriptors
432 * and associated data structures.
434 if (bus_dma_tag_create(bus_get_dma_tag(dev), /* PCI parent */
435 1, 0, /* alignment,boundary */
436 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
437 BUS_SPACE_MAXADDR, /* highaddr */
438 NULL, NULL, /* filter, filterarg */
439 HIFN_MAX_DMALEN, /* maxsize */
440 MAX_SCATTER, /* nsegments */
441 HIFN_MAX_SEGLEN, /* maxsegsize */
442 BUS_DMA_ALLOCNOW, /* flags */
446 device_printf(dev, "cannot allocate DMA tag\n");
449 if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, &sc->sc_dmamap)) {
450 device_printf(dev, "cannot create dma map\n");
451 bus_dma_tag_destroy(sc->sc_dmat);
454 if (bus_dmamem_alloc(sc->sc_dmat, (void**) &kva, BUS_DMA_NOWAIT, &sc->sc_dmamap)) {
455 device_printf(dev, "cannot alloc dma buffer\n");
456 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap);
457 bus_dma_tag_destroy(sc->sc_dmat);
460 if (bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, kva,
461 sizeof (*sc->sc_dma),
462 hifn_dmamap_cb, &sc->sc_dma_physaddr,
464 device_printf(dev, "cannot load dma map\n");
465 bus_dmamem_free(sc->sc_dmat, kva, sc->sc_dmamap);
466 bus_dma_tag_destroy(sc->sc_dmat);
469 sc->sc_dma = (struct hifn_dma *)kva;
470 bzero(sc->sc_dma, sizeof(*sc->sc_dma));
472 KASSERT(sc->sc_st0 != 0, ("hifn_attach: null bar0 tag!"));
473 KASSERT(sc->sc_sh0 != 0, ("hifn_attach: null bar0 handle!"));
474 KASSERT(sc->sc_st1 != 0, ("hifn_attach: null bar1 tag!"));
475 KASSERT(sc->sc_sh1 != 0, ("hifn_attach: null bar1 handle!"));
478 * Reset the board and do the ``secret handshake''
479 * to enable the crypto support. Then complete the
480 * initialization procedure by setting up the interrupt
481 * and hooking in to the system crypto support so we'll
482 * get used for system services like the crypto device,
483 * IPsec, RNG device, etc.
485 hifn_reset_board(sc, 0);
487 if (hifn_enable_crypto(sc) != 0) {
488 device_printf(dev, "crypto enabling failed\n");
494 hifn_init_pci_registers(sc);
496 /* XXX can't dynamically determine ram type for 795x; force dram */
497 if (sc->sc_flags & HIFN_IS_7956)
498 sc->sc_drammodel = 1;
499 else if (hifn_ramtype(sc))
502 if (sc->sc_drammodel == 0)
508 * Workaround for NetSec 7751 rev A: half ram size because two
509 * of the address lines were left floating
511 if (pci_get_vendor(dev) == PCI_VENDOR_NETSEC &&
512 pci_get_device(dev) == PCI_PRODUCT_NETSEC_7751 &&
513 pci_get_revid(dev) == 0x61) /*XXX???*/
514 sc->sc_ramsize >>= 1;
517 * Arrange the interrupt line.
520 sc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
521 RF_SHAREABLE|RF_ACTIVE);
522 if (sc->sc_irq == NULL) {
523 device_printf(dev, "could not map interrupt\n");
527 * NB: Network code assumes we are blocked with splimp()
528 * so make sure the IRQ is marked appropriately.
530 if (bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_NET | INTR_MPSAFE,
531 NULL, hifn_intr, sc, &sc->sc_intrhand)) {
532 device_printf(dev, "could not setup interrupt\n");
539 * NB: Keep only the low 16 bits; this masks the chip id
542 rev = READ_REG_1(sc, HIFN_1_REVID) & 0xffff;
544 rseg = sc->sc_ramsize / 1024;
546 if (sc->sc_ramsize >= (1024 * 1024)) {
550 device_printf(sc->sc_dev, "%s, rev %u, %d%cB %cram",
551 hifn_partname(sc), rev,
552 rseg, rbase, sc->sc_drammodel ? 'd' : 's');
553 if (sc->sc_flags & HIFN_IS_7956)
554 printf(", pll=0x%x<%s clk, %ux mult>",
556 sc->sc_pllconfig & HIFN_PLL_REF_SEL ? "ext" : "pci",
557 2 + 2*((sc->sc_pllconfig & HIFN_PLL_ND) >> 11));
560 sc->sc_cid = crypto_get_driverid(dev, CRYPTOCAP_F_HARDWARE);
561 if (sc->sc_cid < 0) {
562 device_printf(dev, "could not get crypto driver id\n");
566 WRITE_REG_0(sc, HIFN_0_PUCNFG,
567 READ_REG_0(sc, HIFN_0_PUCNFG) | HIFN_PUCNFG_CHIPID);
568 ena = READ_REG_0(sc, HIFN_0_PUSTAT) & HIFN_PUSTAT_CHIPENA;
571 case HIFN_PUSTAT_ENA_2:
572 crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0);
573 crypto_register(sc->sc_cid, CRYPTO_ARC4, 0, 0);
574 if (sc->sc_flags & HIFN_HAS_AES)
575 crypto_register(sc->sc_cid, CRYPTO_AES_CBC, 0, 0);
577 case HIFN_PUSTAT_ENA_1:
578 crypto_register(sc->sc_cid, CRYPTO_MD5, 0, 0);
579 crypto_register(sc->sc_cid, CRYPTO_SHA1, 0, 0);
580 crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0);
581 crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0);
582 crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0);
586 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap,
587 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
589 if (sc->sc_flags & (HIFN_HAS_PUBLIC | HIFN_HAS_RNG))
590 hifn_init_pubrng(sc);
592 callout_init(&sc->sc_tickto, CALLOUT_MPSAFE);
593 callout_reset(&sc->sc_tickto, hz, hifn_tick, sc);
598 bus_teardown_intr(dev, sc->sc_irq, sc->sc_intrhand);
600 /* XXX don't store rid */
601 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq);
603 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap);
604 bus_dmamem_free(sc->sc_dmat, sc->sc_dma, sc->sc_dmamap);
605 bus_dma_tag_destroy(sc->sc_dmat);
607 /* Turn off DMA polling */
608 WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET |
609 HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE);
611 bus_release_resource(dev, SYS_RES_MEMORY, HIFN_BAR1, sc->sc_bar1res);
613 bus_release_resource(dev, SYS_RES_MEMORY, HIFN_BAR0, sc->sc_bar0res);
615 mtx_destroy(&sc->sc_mtx);
620 * Detach an interface that successfully probed.
623 hifn_detach(device_t dev)
625 struct hifn_softc *sc = device_get_softc(dev);
627 KASSERT(sc != NULL, ("hifn_detach: null software carrier!"));
629 /* disable interrupts */
630 WRITE_REG_1(sc, HIFN_1_DMA_IER, 0);
632 /*XXX other resources */
633 callout_stop(&sc->sc_tickto);
634 callout_stop(&sc->sc_rngto);
637 rndtest_detach(sc->sc_rndtest);
640 /* Turn off DMA polling */
641 WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET |
642 HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE);
644 crypto_unregister_all(sc->sc_cid);
646 bus_generic_detach(dev); /*XXX should be no children, right? */
648 bus_teardown_intr(dev, sc->sc_irq, sc->sc_intrhand);
649 /* XXX don't store rid */
650 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq);
652 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap);
653 bus_dmamem_free(sc->sc_dmat, sc->sc_dma, sc->sc_dmamap);
654 bus_dma_tag_destroy(sc->sc_dmat);
656 bus_release_resource(dev, SYS_RES_MEMORY, HIFN_BAR1, sc->sc_bar1res);
657 bus_release_resource(dev, SYS_RES_MEMORY, HIFN_BAR0, sc->sc_bar0res);
659 mtx_destroy(&sc->sc_mtx);
665 * Stop all chip I/O so that the kernel's probe routines don't
666 * get confused by errant DMAs when rebooting.
669 hifn_shutdown(device_t dev)
672 hifn_stop(device_get_softc(dev));
678 * Device suspend routine. Stop the interface and save some PCI
679 * settings in case the BIOS doesn't restore them properly on
683 hifn_suspend(device_t dev)
685 struct hifn_softc *sc = device_get_softc(dev);
689 sc->sc_suspended = 1;
695 * Device resume routine. Restore some PCI settings in case the BIOS
696 * doesn't, re-enable busmastering, and restart the interface if
700 hifn_resume(device_t dev)
702 struct hifn_softc *sc = device_get_softc(dev);
704 /* reinitialize interface if necessary */
705 if (ifp->if_flags & IFF_UP)
708 sc->sc_suspended = 0;
714 hifn_init_pubrng(struct hifn_softc *sc)
720 sc->sc_rndtest = rndtest_attach(sc->sc_dev);
722 sc->sc_harvest = rndtest_harvest;
724 sc->sc_harvest = default_harvest;
726 sc->sc_harvest = default_harvest;
728 if ((sc->sc_flags & HIFN_IS_7811) == 0) {
729 /* Reset 7951 public key/rng engine */
730 WRITE_REG_1(sc, HIFN_1_PUB_RESET,
731 READ_REG_1(sc, HIFN_1_PUB_RESET) | HIFN_PUBRST_RESET);
733 for (i = 0; i < 100; i++) {
735 if ((READ_REG_1(sc, HIFN_1_PUB_RESET) &
736 HIFN_PUBRST_RESET) == 0)
741 device_printf(sc->sc_dev, "public key init failed\n");
746 /* Enable the rng, if available */
747 if (sc->sc_flags & HIFN_HAS_RNG) {
748 if (sc->sc_flags & HIFN_IS_7811) {
749 r = READ_REG_1(sc, HIFN_1_7811_RNGENA);
750 if (r & HIFN_7811_RNGENA_ENA) {
751 r &= ~HIFN_7811_RNGENA_ENA;
752 WRITE_REG_1(sc, HIFN_1_7811_RNGENA, r);
754 WRITE_REG_1(sc, HIFN_1_7811_RNGCFG,
755 HIFN_7811_RNGCFG_DEFL);
756 r |= HIFN_7811_RNGENA_ENA;
757 WRITE_REG_1(sc, HIFN_1_7811_RNGENA, r);
759 WRITE_REG_1(sc, HIFN_1_RNG_CONFIG,
760 READ_REG_1(sc, HIFN_1_RNG_CONFIG) |
765 sc->sc_rnghz = hz / 100;
768 callout_init(&sc->sc_rngto, CALLOUT_MPSAFE);
769 callout_reset(&sc->sc_rngto, sc->sc_rnghz, hifn_rng, sc);
772 /* Enable public key engine, if available */
773 if (sc->sc_flags & HIFN_HAS_PUBLIC) {
774 WRITE_REG_1(sc, HIFN_1_PUB_IEN, HIFN_PUBIEN_DONE);
775 sc->sc_dmaier |= HIFN_DMAIER_PUBDONE;
776 WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier);
777 #ifdef HIFN_VULCANDEV
778 sc->sc_pkdev = make_dev(&vulcanpk_cdevsw, 0,
779 UID_ROOT, GID_WHEEL, 0666,
781 sc->sc_pkdev->si_drv1 = sc;
791 #define RANDOM_BITS(n) (n)*sizeof (u_int32_t), (n)*sizeof (u_int32_t)*NBBY, 0
792 struct hifn_softc *sc = vsc;
793 u_int32_t sts, num[2];
796 if (sc->sc_flags & HIFN_IS_7811) {
797 /* ONLY VALID ON 7811!!!! */
798 for (i = 0; i < 5; i++) {
799 sts = READ_REG_1(sc, HIFN_1_7811_RNGSTS);
800 if (sts & HIFN_7811_RNGSTS_UFL) {
801 device_printf(sc->sc_dev,
802 "RNG underflow: disabling\n");
805 if ((sts & HIFN_7811_RNGSTS_RDY) == 0)
809 * There are at least two words in the RNG FIFO
812 num[0] = READ_REG_1(sc, HIFN_1_7811_RNGDAT);
813 num[1] = READ_REG_1(sc, HIFN_1_7811_RNGDAT);
814 /* NB: discard first data read */
818 (*sc->sc_harvest)(sc->sc_rndtest,
822 num[0] = READ_REG_1(sc, HIFN_1_RNG_DATA);
824 /* NB: discard first data read */
828 (*sc->sc_harvest)(sc->sc_rndtest,
829 num, sizeof (num[0]));
832 callout_reset(&sc->sc_rngto, sc->sc_rnghz, hifn_rng, sc);
837 hifn_puc_wait(struct hifn_softc *sc)
840 int reg = HIFN_0_PUCTRL;
842 if (sc->sc_flags & HIFN_IS_7956) {
843 reg = HIFN_0_PUCTRL2;
846 for (i = 5000; i > 0; i--) {
848 if (!(READ_REG_0(sc, reg) & HIFN_PUCTRL_RESET))
852 device_printf(sc->sc_dev, "proc unit did not reset\n");
856 * Reset the processing unit.
859 hifn_reset_puc(struct hifn_softc *sc)
861 /* Reset processing unit */
862 int reg = HIFN_0_PUCTRL;
864 if (sc->sc_flags & HIFN_IS_7956) {
865 reg = HIFN_0_PUCTRL2;
867 WRITE_REG_0(sc, reg, HIFN_PUCTRL_DMAENA);
873 * Set the Retry and TRDY registers; note that we set them to
874 * zero because the 7811 locks up when forced to retry (section
875 * 3.6 of "Specification Update SU-0014-04". Not clear if we
876 * should do this for all Hifn parts, but it doesn't seem to hurt.
879 hifn_set_retry(struct hifn_softc *sc)
881 /* NB: RETRY only responds to 8-bit reads/writes */
882 pci_write_config(sc->sc_dev, HIFN_RETRY_TIMEOUT, 0, 1);
883 pci_write_config(sc->sc_dev, HIFN_TRDY_TIMEOUT, 0, 1);
887 * Resets the board. Values in the regesters are left as is
888 * from the reset (i.e. initial values are assigned elsewhere).
891 hifn_reset_board(struct hifn_softc *sc, int full)
896 * Set polling in the DMA configuration register to zero. 0x7 avoids
897 * resetting the board and zeros out the other fields.
899 WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET |
900 HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE);
903 * Now that polling has been disabled, we have to wait 1 ms
904 * before resetting the board.
908 /* Reset the DMA unit */
910 WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MODE);
913 WRITE_REG_1(sc, HIFN_1_DMA_CNFG,
914 HIFN_DMACNFG_MODE | HIFN_DMACNFG_MSTRESET);
918 KASSERT(sc->sc_dma != NULL, ("hifn_reset_board: null DMA tag!"));
919 bzero(sc->sc_dma, sizeof(*sc->sc_dma));
921 /* Bring dma unit out of reset */
922 WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET |
923 HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE);
928 if (sc->sc_flags & HIFN_IS_7811) {
929 for (reg = 0; reg < 1000; reg++) {
930 if (READ_REG_1(sc, HIFN_1_7811_MIPSRST) &
931 HIFN_MIPSRST_CRAMINIT)
936 printf(": cram init timeout\n");
938 /* set up DMA configuration register #2 */
939 /* turn off all PK and BAR0 swaps */
940 WRITE_REG_1(sc, HIFN_1_DMA_CNFG2,
941 (3 << HIFN_DMACNFG2_INIT_WRITE_BURST_SHIFT)|
942 (3 << HIFN_DMACNFG2_INIT_READ_BURST_SHIFT)|
943 (2 << HIFN_DMACNFG2_TGT_WRITE_BURST_SHIFT)|
944 (2 << HIFN_DMACNFG2_TGT_READ_BURST_SHIFT));
950 hifn_next_signature(u_int32_t a, u_int cnt)
955 for (i = 0; i < cnt; i++) {
965 a = (v & 1) ^ (a << 1);
976 static struct pci2id pci2id[] = {
979 PCI_PRODUCT_HIFN_7951,
980 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
981 0x00, 0x00, 0x00, 0x00, 0x00 }
984 PCI_PRODUCT_HIFN_7955,
985 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
986 0x00, 0x00, 0x00, 0x00, 0x00 }
989 PCI_PRODUCT_HIFN_7956,
990 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
991 0x00, 0x00, 0x00, 0x00, 0x00 }
994 PCI_PRODUCT_NETSEC_7751,
995 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
996 0x00, 0x00, 0x00, 0x00, 0x00 }
999 PCI_PRODUCT_INVERTEX_AEON,
1000 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1001 0x00, 0x00, 0x00, 0x00, 0x00 }
1004 PCI_PRODUCT_HIFN_7811,
1005 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1006 0x00, 0x00, 0x00, 0x00, 0x00 }
1009 * Other vendors share this PCI ID as well, such as
1010 * http://www.powercrypt.com, and obviously they also
1014 PCI_PRODUCT_HIFN_7751,
1015 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1016 0x00, 0x00, 0x00, 0x00, 0x00 }
1021 * Checks to see if crypto is already enabled. If crypto isn't enable,
1022 * "hifn_enable_crypto" is called to enable it. The check is important,
1023 * as enabling crypto twice will lock the board.
1026 hifn_enable_crypto(struct hifn_softc *sc)
1028 u_int32_t dmacfg, ramcfg, encl, addr, i;
1029 char *offtbl = NULL;
1031 for (i = 0; i < sizeof(pci2id)/sizeof(pci2id[0]); i++) {
1032 if (pci2id[i].pci_vendor == pci_get_vendor(sc->sc_dev) &&
1033 pci2id[i].pci_prod == pci_get_device(sc->sc_dev)) {
1034 offtbl = pci2id[i].card_id;
1038 if (offtbl == NULL) {
1039 device_printf(sc->sc_dev, "Unknown card!\n");
1043 ramcfg = READ_REG_0(sc, HIFN_0_PUCNFG);
1044 dmacfg = READ_REG_1(sc, HIFN_1_DMA_CNFG);
1047 * The RAM config register's encrypt level bit needs to be set before
1048 * every read performed on the encryption level register.
1050 WRITE_REG_0(sc, HIFN_0_PUCNFG, ramcfg | HIFN_PUCNFG_CHIPID);
1052 encl = READ_REG_0(sc, HIFN_0_PUSTAT) & HIFN_PUSTAT_CHIPENA;
1055 * Make sure we don't re-unlock. Two unlocks kills chip until the
1058 if (encl == HIFN_PUSTAT_ENA_1 || encl == HIFN_PUSTAT_ENA_2) {
1061 device_printf(sc->sc_dev,
1062 "Strong crypto already enabled!\n");
1067 if (encl != 0 && encl != HIFN_PUSTAT_ENA_0) {
1070 device_printf(sc->sc_dev,
1071 "Unknown encryption level 0x%x\n", encl);
1076 WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_UNLOCK |
1077 HIFN_DMACNFG_MSTRESET | HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE);
1079 addr = READ_REG_1(sc, HIFN_UNLOCK_SECRET1);
1081 WRITE_REG_1(sc, HIFN_UNLOCK_SECRET2, 0);
1084 for (i = 0; i <= 12; i++) {
1085 addr = hifn_next_signature(addr, offtbl[i] + 0x101);
1086 WRITE_REG_1(sc, HIFN_UNLOCK_SECRET2, addr);
1091 WRITE_REG_0(sc, HIFN_0_PUCNFG, ramcfg | HIFN_PUCNFG_CHIPID);
1092 encl = READ_REG_0(sc, HIFN_0_PUSTAT) & HIFN_PUSTAT_CHIPENA;
1096 if (encl != HIFN_PUSTAT_ENA_1 && encl != HIFN_PUSTAT_ENA_2)
1097 device_printf(sc->sc_dev, "Engine is permanently "
1098 "locked until next system reset!\n");
1100 device_printf(sc->sc_dev, "Engine enabled "
1106 WRITE_REG_0(sc, HIFN_0_PUCNFG, ramcfg);
1107 WRITE_REG_1(sc, HIFN_1_DMA_CNFG, dmacfg);
1110 case HIFN_PUSTAT_ENA_1:
1111 case HIFN_PUSTAT_ENA_2:
1113 case HIFN_PUSTAT_ENA_0:
1115 device_printf(sc->sc_dev, "disabled");
1123 * Give initial values to the registers listed in the "Register Space"
1124 * section of the HIFN Software Development reference manual.
1127 hifn_init_pci_registers(struct hifn_softc *sc)
1129 /* write fixed values needed by the Initialization registers */
1130 WRITE_REG_0(sc, HIFN_0_PUCTRL, HIFN_PUCTRL_DMAENA);
1131 WRITE_REG_0(sc, HIFN_0_FIFOCNFG, HIFN_FIFOCNFG_THRESHOLD);
1132 WRITE_REG_0(sc, HIFN_0_PUIER, HIFN_PUIER_DSTOVER);
1134 /* write all 4 ring address registers */
1135 WRITE_REG_1(sc, HIFN_1_DMA_CRAR, sc->sc_dma_physaddr +
1136 offsetof(struct hifn_dma, cmdr[0]));
1137 WRITE_REG_1(sc, HIFN_1_DMA_SRAR, sc->sc_dma_physaddr +
1138 offsetof(struct hifn_dma, srcr[0]));
1139 WRITE_REG_1(sc, HIFN_1_DMA_DRAR, sc->sc_dma_physaddr +
1140 offsetof(struct hifn_dma, dstr[0]));
1141 WRITE_REG_1(sc, HIFN_1_DMA_RRAR, sc->sc_dma_physaddr +
1142 offsetof(struct hifn_dma, resr[0]));
1146 /* write status register */
1147 WRITE_REG_1(sc, HIFN_1_DMA_CSR,
1148 HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS |
1149 HIFN_DMACSR_S_CTRL_DIS | HIFN_DMACSR_C_CTRL_DIS |
1150 HIFN_DMACSR_D_ABORT | HIFN_DMACSR_D_DONE | HIFN_DMACSR_D_LAST |
1151 HIFN_DMACSR_D_WAIT | HIFN_DMACSR_D_OVER |
1152 HIFN_DMACSR_R_ABORT | HIFN_DMACSR_R_DONE | HIFN_DMACSR_R_LAST |
1153 HIFN_DMACSR_R_WAIT | HIFN_DMACSR_R_OVER |
1154 HIFN_DMACSR_S_ABORT | HIFN_DMACSR_S_DONE | HIFN_DMACSR_S_LAST |
1155 HIFN_DMACSR_S_WAIT |
1156 HIFN_DMACSR_C_ABORT | HIFN_DMACSR_C_DONE | HIFN_DMACSR_C_LAST |
1157 HIFN_DMACSR_C_WAIT |
1158 HIFN_DMACSR_ENGINE |
1159 ((sc->sc_flags & HIFN_HAS_PUBLIC) ?
1160 HIFN_DMACSR_PUBDONE : 0) |
1161 ((sc->sc_flags & HIFN_IS_7811) ?
1162 HIFN_DMACSR_ILLW | HIFN_DMACSR_ILLR : 0));
1164 sc->sc_d_busy = sc->sc_r_busy = sc->sc_s_busy = sc->sc_c_busy = 0;
1165 sc->sc_dmaier |= HIFN_DMAIER_R_DONE | HIFN_DMAIER_C_ABORT |
1166 HIFN_DMAIER_D_OVER | HIFN_DMAIER_R_OVER |
1167 HIFN_DMAIER_S_ABORT | HIFN_DMAIER_D_ABORT | HIFN_DMAIER_R_ABORT |
1168 ((sc->sc_flags & HIFN_IS_7811) ?
1169 HIFN_DMAIER_ILLW | HIFN_DMAIER_ILLR : 0);
1170 sc->sc_dmaier &= ~HIFN_DMAIER_C_WAIT;
1171 WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier);
1174 if (sc->sc_flags & HIFN_IS_7956) {
1177 WRITE_REG_0(sc, HIFN_0_PUCNFG, HIFN_PUCNFG_COMPSING |
1178 HIFN_PUCNFG_TCALLPHASES |
1179 HIFN_PUCNFG_TCDRVTOTEM | HIFN_PUCNFG_BUS32);
1181 /* turn off the clocks and insure bypass is set */
1182 pll = READ_REG_1(sc, HIFN_1_PLL);
1183 pll = (pll &~ (HIFN_PLL_PK_CLK_SEL | HIFN_PLL_PE_CLK_SEL))
1184 | HIFN_PLL_BP | HIFN_PLL_MBSET;
1185 WRITE_REG_1(sc, HIFN_1_PLL, pll);
1186 DELAY(10*1000); /* 10ms */
1188 /* change configuration */
1189 pll = (pll &~ HIFN_PLL_CONFIG) | sc->sc_pllconfig;
1190 WRITE_REG_1(sc, HIFN_1_PLL, pll);
1191 DELAY(10*1000); /* 10ms */
1193 /* disable bypass */
1194 pll &= ~HIFN_PLL_BP;
1195 WRITE_REG_1(sc, HIFN_1_PLL, pll);
1196 /* enable clocks with new configuration */
1197 pll |= HIFN_PLL_PK_CLK_SEL | HIFN_PLL_PE_CLK_SEL;
1198 WRITE_REG_1(sc, HIFN_1_PLL, pll);
1200 WRITE_REG_0(sc, HIFN_0_PUCNFG, HIFN_PUCNFG_COMPSING |
1201 HIFN_PUCNFG_DRFR_128 | HIFN_PUCNFG_TCALLPHASES |
1202 HIFN_PUCNFG_TCDRVTOTEM | HIFN_PUCNFG_BUS32 |
1203 (sc->sc_drammodel ? HIFN_PUCNFG_DRAM : HIFN_PUCNFG_SRAM));
1206 WRITE_REG_0(sc, HIFN_0_PUISR, HIFN_PUISR_DSTOVER);
1207 WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET |
1208 HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE | HIFN_DMACNFG_LAST |
1209 ((HIFN_POLL_FREQUENCY << 16 ) & HIFN_DMACNFG_POLLFREQ) |
1210 ((HIFN_POLL_SCALAR << 8) & HIFN_DMACNFG_POLLINVAL));
1214 * The maximum number of sessions supported by the card
1215 * is dependent on the amount of context ram, which
1216 * encryption algorithms are enabled, and how compression
1217 * is configured. This should be configured before this
1218 * routine is called.
1221 hifn_sessions(struct hifn_softc *sc)
1226 pucnfg = READ_REG_0(sc, HIFN_0_PUCNFG);
1228 if (pucnfg & HIFN_PUCNFG_COMPSING) {
1229 if (pucnfg & HIFN_PUCNFG_ENCCNFG)
1234 * 7955/7956 has internal context memory of 32K
1236 if (sc->sc_flags & HIFN_IS_7956)
1237 sc->sc_maxses = 32768 / ctxsize;
1240 ((sc->sc_ramsize - 32768) / ctxsize);
1242 sc->sc_maxses = sc->sc_ramsize / 16384;
1244 if (sc->sc_maxses > 2048)
1245 sc->sc_maxses = 2048;
1249 * Determine ram type (sram or dram). Board should be just out of a reset
1250 * state when this is called.
1253 hifn_ramtype(struct hifn_softc *sc)
1255 u_int8_t data[8], dataexpect[8];
1258 for (i = 0; i < sizeof(data); i++)
1259 data[i] = dataexpect[i] = 0x55;
1260 if (hifn_writeramaddr(sc, 0, data))
1262 if (hifn_readramaddr(sc, 0, data))
1264 if (bcmp(data, dataexpect, sizeof(data)) != 0) {
1265 sc->sc_drammodel = 1;
1269 for (i = 0; i < sizeof(data); i++)
1270 data[i] = dataexpect[i] = 0xaa;
1271 if (hifn_writeramaddr(sc, 0, data))
1273 if (hifn_readramaddr(sc, 0, data))
1275 if (bcmp(data, dataexpect, sizeof(data)) != 0) {
1276 sc->sc_drammodel = 1;
1283 #define HIFN_SRAM_MAX (32 << 20)
1284 #define HIFN_SRAM_STEP_SIZE 16384
1285 #define HIFN_SRAM_GRANULARITY (HIFN_SRAM_MAX / HIFN_SRAM_STEP_SIZE)
1288 hifn_sramsize(struct hifn_softc *sc)
1292 u_int8_t dataexpect[sizeof(data)];
1295 for (i = 0; i < sizeof(data); i++)
1296 data[i] = dataexpect[i] = i ^ 0x5a;
1298 for (i = HIFN_SRAM_GRANULARITY - 1; i >= 0; i--) {
1299 a = i * HIFN_SRAM_STEP_SIZE;
1300 bcopy(&i, data, sizeof(i));
1301 hifn_writeramaddr(sc, a, data);
1304 for (i = 0; i < HIFN_SRAM_GRANULARITY; i++) {
1305 a = i * HIFN_SRAM_STEP_SIZE;
1306 bcopy(&i, dataexpect, sizeof(i));
1307 if (hifn_readramaddr(sc, a, data) < 0)
1309 if (bcmp(data, dataexpect, sizeof(data)) != 0)
1311 sc->sc_ramsize = a + HIFN_SRAM_STEP_SIZE;
1318 * XXX For dram boards, one should really try all of the
1319 * HIFN_PUCNFG_DSZ_*'s. This just assumes that PUCNFG
1320 * is already set up correctly.
1323 hifn_dramsize(struct hifn_softc *sc)
1327 if (sc->sc_flags & HIFN_IS_7956) {
1329 * 7955/7956 have a fixed internal ram of only 32K.
1331 sc->sc_ramsize = 32768;
1333 cnfg = READ_REG_0(sc, HIFN_0_PUCNFG) &
1334 HIFN_PUCNFG_DRAMMASK;
1335 sc->sc_ramsize = 1 << ((cnfg >> 13) + 18);
1341 hifn_alloc_slot(struct hifn_softc *sc, int *cmdp, int *srcp, int *dstp, int *resp)
1343 struct hifn_dma *dma = sc->sc_dma;
1345 if (sc->sc_cmdi == HIFN_D_CMD_RSIZE) {
1347 dma->cmdr[HIFN_D_CMD_RSIZE].l = htole32(HIFN_D_VALID |
1348 HIFN_D_JUMP | HIFN_D_MASKDONEIRQ);
1349 HIFN_CMDR_SYNC(sc, HIFN_D_CMD_RSIZE,
1350 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1352 *cmdp = sc->sc_cmdi++;
1353 sc->sc_cmdk = sc->sc_cmdi;
1355 if (sc->sc_srci == HIFN_D_SRC_RSIZE) {
1357 dma->srcr[HIFN_D_SRC_RSIZE].l = htole32(HIFN_D_VALID |
1358 HIFN_D_JUMP | HIFN_D_MASKDONEIRQ);
1359 HIFN_SRCR_SYNC(sc, HIFN_D_SRC_RSIZE,
1360 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1362 *srcp = sc->sc_srci++;
1363 sc->sc_srck = sc->sc_srci;
1365 if (sc->sc_dsti == HIFN_D_DST_RSIZE) {
1367 dma->dstr[HIFN_D_DST_RSIZE].l = htole32(HIFN_D_VALID |
1368 HIFN_D_JUMP | HIFN_D_MASKDONEIRQ);
1369 HIFN_DSTR_SYNC(sc, HIFN_D_DST_RSIZE,
1370 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1372 *dstp = sc->sc_dsti++;
1373 sc->sc_dstk = sc->sc_dsti;
1375 if (sc->sc_resi == HIFN_D_RES_RSIZE) {
1377 dma->resr[HIFN_D_RES_RSIZE].l = htole32(HIFN_D_VALID |
1378 HIFN_D_JUMP | HIFN_D_MASKDONEIRQ);
1379 HIFN_RESR_SYNC(sc, HIFN_D_RES_RSIZE,
1380 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1382 *resp = sc->sc_resi++;
1383 sc->sc_resk = sc->sc_resi;
1387 hifn_writeramaddr(struct hifn_softc *sc, int addr, u_int8_t *data)
1389 struct hifn_dma *dma = sc->sc_dma;
1390 hifn_base_command_t wc;
1391 const u_int32_t masks = HIFN_D_VALID | HIFN_D_LAST | HIFN_D_MASKDONEIRQ;
1392 int r, cmdi, resi, srci, dsti;
1394 wc.masks = htole16(3 << 13);
1395 wc.session_num = htole16(addr >> 14);
1396 wc.total_source_count = htole16(8);
1397 wc.total_dest_count = htole16(addr & 0x3fff);
1399 hifn_alloc_slot(sc, &cmdi, &srci, &dsti, &resi);
1401 WRITE_REG_1(sc, HIFN_1_DMA_CSR,
1402 HIFN_DMACSR_C_CTRL_ENA | HIFN_DMACSR_S_CTRL_ENA |
1403 HIFN_DMACSR_D_CTRL_ENA | HIFN_DMACSR_R_CTRL_ENA);
1405 /* build write command */
1406 bzero(dma->command_bufs[cmdi], HIFN_MAX_COMMAND);
1407 *(hifn_base_command_t *)dma->command_bufs[cmdi] = wc;
1408 bcopy(data, &dma->test_src, sizeof(dma->test_src));
1410 dma->srcr[srci].p = htole32(sc->sc_dma_physaddr
1411 + offsetof(struct hifn_dma, test_src));
1412 dma->dstr[dsti].p = htole32(sc->sc_dma_physaddr
1413 + offsetof(struct hifn_dma, test_dst));
1415 dma->cmdr[cmdi].l = htole32(16 | masks);
1416 dma->srcr[srci].l = htole32(8 | masks);
1417 dma->dstr[dsti].l = htole32(4 | masks);
1418 dma->resr[resi].l = htole32(4 | masks);
1420 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap,
1421 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1423 for (r = 10000; r >= 0; r--) {
1425 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap,
1426 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1427 if ((dma->resr[resi].l & htole32(HIFN_D_VALID)) == 0)
1429 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap,
1430 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1433 device_printf(sc->sc_dev, "writeramaddr -- "
1434 "result[%d](addr %d) still valid\n", resi, addr);
1440 WRITE_REG_1(sc, HIFN_1_DMA_CSR,
1441 HIFN_DMACSR_C_CTRL_DIS | HIFN_DMACSR_S_CTRL_DIS |
1442 HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS);
1448 hifn_readramaddr(struct hifn_softc *sc, int addr, u_int8_t *data)
1450 struct hifn_dma *dma = sc->sc_dma;
1451 hifn_base_command_t rc;
1452 const u_int32_t masks = HIFN_D_VALID | HIFN_D_LAST | HIFN_D_MASKDONEIRQ;
1453 int r, cmdi, srci, dsti, resi;
1455 rc.masks = htole16(2 << 13);
1456 rc.session_num = htole16(addr >> 14);
1457 rc.total_source_count = htole16(addr & 0x3fff);
1458 rc.total_dest_count = htole16(8);
1460 hifn_alloc_slot(sc, &cmdi, &srci, &dsti, &resi);
1462 WRITE_REG_1(sc, HIFN_1_DMA_CSR,
1463 HIFN_DMACSR_C_CTRL_ENA | HIFN_DMACSR_S_CTRL_ENA |
1464 HIFN_DMACSR_D_CTRL_ENA | HIFN_DMACSR_R_CTRL_ENA);
1466 bzero(dma->command_bufs[cmdi], HIFN_MAX_COMMAND);
1467 *(hifn_base_command_t *)dma->command_bufs[cmdi] = rc;
1469 dma->srcr[srci].p = htole32(sc->sc_dma_physaddr +
1470 offsetof(struct hifn_dma, test_src));
1472 dma->dstr[dsti].p = htole32(sc->sc_dma_physaddr +
1473 offsetof(struct hifn_dma, test_dst));
1475 dma->cmdr[cmdi].l = htole32(8 | masks);
1476 dma->srcr[srci].l = htole32(8 | masks);
1477 dma->dstr[dsti].l = htole32(8 | masks);
1478 dma->resr[resi].l = htole32(HIFN_MAX_RESULT | masks);
1480 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap,
1481 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1483 for (r = 10000; r >= 0; r--) {
1485 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap,
1486 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1487 if ((dma->resr[resi].l & htole32(HIFN_D_VALID)) == 0)
1489 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap,
1490 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1493 device_printf(sc->sc_dev, "readramaddr -- "
1494 "result[%d](addr %d) still valid\n", resi, addr);
1498 bcopy(&dma->test_dst, data, sizeof(dma->test_dst));
1501 WRITE_REG_1(sc, HIFN_1_DMA_CSR,
1502 HIFN_DMACSR_C_CTRL_DIS | HIFN_DMACSR_S_CTRL_DIS |
1503 HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS);
1509 * Initialize the descriptor rings.
1512 hifn_init_dma(struct hifn_softc *sc)
1514 struct hifn_dma *dma = sc->sc_dma;
1519 /* initialize static pointer values */
1520 for (i = 0; i < HIFN_D_CMD_RSIZE; i++)
1521 dma->cmdr[i].p = htole32(sc->sc_dma_physaddr +
1522 offsetof(struct hifn_dma, command_bufs[i][0]));
1523 for (i = 0; i < HIFN_D_RES_RSIZE; i++)
1524 dma->resr[i].p = htole32(sc->sc_dma_physaddr +
1525 offsetof(struct hifn_dma, result_bufs[i][0]));
1527 dma->cmdr[HIFN_D_CMD_RSIZE].p =
1528 htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, cmdr[0]));
1529 dma->srcr[HIFN_D_SRC_RSIZE].p =
1530 htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, srcr[0]));
1531 dma->dstr[HIFN_D_DST_RSIZE].p =
1532 htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, dstr[0]));
1533 dma->resr[HIFN_D_RES_RSIZE].p =
1534 htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, resr[0]));
1536 sc->sc_cmdu = sc->sc_srcu = sc->sc_dstu = sc->sc_resu = 0;
1537 sc->sc_cmdi = sc->sc_srci = sc->sc_dsti = sc->sc_resi = 0;
1538 sc->sc_cmdk = sc->sc_srck = sc->sc_dstk = sc->sc_resk = 0;
1542 * Writes out the raw command buffer space. Returns the
1543 * command buffer size.
1546 hifn_write_command(struct hifn_command *cmd, u_int8_t *buf)
1549 hifn_base_command_t *base_cmd;
1550 hifn_mac_command_t *mac_cmd;
1551 hifn_crypt_command_t *cry_cmd;
1552 int using_mac, using_crypt, len, ivlen;
1553 u_int32_t dlen, slen;
1556 using_mac = cmd->base_masks & HIFN_BASE_CMD_MAC;
1557 using_crypt = cmd->base_masks & HIFN_BASE_CMD_CRYPT;
1559 base_cmd = (hifn_base_command_t *)buf_pos;
1560 base_cmd->masks = htole16(cmd->base_masks);
1561 slen = cmd->src_mapsize;
1563 dlen = cmd->dst_mapsize - cmd->sloplen + sizeof(u_int32_t);
1565 dlen = cmd->dst_mapsize;
1566 base_cmd->total_source_count = htole16(slen & HIFN_BASE_CMD_LENMASK_LO);
1567 base_cmd->total_dest_count = htole16(dlen & HIFN_BASE_CMD_LENMASK_LO);
1570 base_cmd->session_num = htole16(
1571 ((slen << HIFN_BASE_CMD_SRCLEN_S) & HIFN_BASE_CMD_SRCLEN_M) |
1572 ((dlen << HIFN_BASE_CMD_DSTLEN_S) & HIFN_BASE_CMD_DSTLEN_M));
1573 buf_pos += sizeof(hifn_base_command_t);
1576 mac_cmd = (hifn_mac_command_t *)buf_pos;
1577 dlen = cmd->maccrd->crd_len;
1578 mac_cmd->source_count = htole16(dlen & 0xffff);
1580 mac_cmd->masks = htole16(cmd->mac_masks |
1581 ((dlen << HIFN_MAC_CMD_SRCLEN_S) & HIFN_MAC_CMD_SRCLEN_M));
1582 mac_cmd->header_skip = htole16(cmd->maccrd->crd_skip);
1583 mac_cmd->reserved = 0;
1584 buf_pos += sizeof(hifn_mac_command_t);
1588 cry_cmd = (hifn_crypt_command_t *)buf_pos;
1589 dlen = cmd->enccrd->crd_len;
1590 cry_cmd->source_count = htole16(dlen & 0xffff);
1592 cry_cmd->masks = htole16(cmd->cry_masks |
1593 ((dlen << HIFN_CRYPT_CMD_SRCLEN_S) & HIFN_CRYPT_CMD_SRCLEN_M));
1594 cry_cmd->header_skip = htole16(cmd->enccrd->crd_skip);
1595 cry_cmd->reserved = 0;
1596 buf_pos += sizeof(hifn_crypt_command_t);
1599 if (using_mac && cmd->mac_masks & HIFN_MAC_CMD_NEW_KEY) {
1600 bcopy(cmd->mac, buf_pos, HIFN_MAC_KEY_LENGTH);
1601 buf_pos += HIFN_MAC_KEY_LENGTH;
1604 if (using_crypt && cmd->cry_masks & HIFN_CRYPT_CMD_NEW_KEY) {
1605 switch (cmd->cry_masks & HIFN_CRYPT_CMD_ALG_MASK) {
1606 case HIFN_CRYPT_CMD_ALG_3DES:
1607 bcopy(cmd->ck, buf_pos, HIFN_3DES_KEY_LENGTH);
1608 buf_pos += HIFN_3DES_KEY_LENGTH;
1610 case HIFN_CRYPT_CMD_ALG_DES:
1611 bcopy(cmd->ck, buf_pos, HIFN_DES_KEY_LENGTH);
1612 buf_pos += HIFN_DES_KEY_LENGTH;
1614 case HIFN_CRYPT_CMD_ALG_RC4:
1619 clen = MIN(cmd->cklen, len);
1620 bcopy(cmd->ck, buf_pos, clen);
1627 case HIFN_CRYPT_CMD_ALG_AES:
1629 * AES keys are variable 128, 192 and
1630 * 256 bits (16, 24 and 32 bytes).
1632 bcopy(cmd->ck, buf_pos, cmd->cklen);
1633 buf_pos += cmd->cklen;
1638 if (using_crypt && cmd->cry_masks & HIFN_CRYPT_CMD_NEW_IV) {
1639 switch (cmd->cry_masks & HIFN_CRYPT_CMD_ALG_MASK) {
1640 case HIFN_CRYPT_CMD_ALG_AES:
1641 ivlen = HIFN_AES_IV_LENGTH;
1644 ivlen = HIFN_IV_LENGTH;
1647 bcopy(cmd->iv, buf_pos, ivlen);
1651 if ((cmd->base_masks & (HIFN_BASE_CMD_MAC|HIFN_BASE_CMD_CRYPT)) == 0) {
1656 return (buf_pos - buf);
1660 hifn_dmamap_aligned(struct hifn_operand *op)
1664 for (i = 0; i < op->nsegs; i++) {
1665 if (op->segs[i].ds_addr & 3)
1667 if ((i != (op->nsegs - 1)) && (op->segs[i].ds_len & 3))
1674 hifn_dmamap_dstwrap(struct hifn_softc *sc, int idx)
1676 struct hifn_dma *dma = sc->sc_dma;
1678 if (++idx == HIFN_D_DST_RSIZE) {
1679 dma->dstr[idx].l = htole32(HIFN_D_VALID | HIFN_D_JUMP |
1680 HIFN_D_MASKDONEIRQ);
1681 HIFN_DSTR_SYNC(sc, idx,
1682 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1689 hifn_dmamap_load_dst(struct hifn_softc *sc, struct hifn_command *cmd)
1691 struct hifn_dma *dma = sc->sc_dma;
1692 struct hifn_operand *dst = &cmd->dst;
1694 int idx, used = 0, i;
1697 for (i = 0; i < dst->nsegs - 1; i++) {
1698 dma->dstr[idx].p = htole32(dst->segs[i].ds_addr);
1699 dma->dstr[idx].l = htole32(HIFN_D_VALID |
1700 HIFN_D_MASKDONEIRQ | dst->segs[i].ds_len);
1701 HIFN_DSTR_SYNC(sc, idx,
1702 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1705 idx = hifn_dmamap_dstwrap(sc, idx);
1708 if (cmd->sloplen == 0) {
1709 p = dst->segs[i].ds_addr;
1710 l = HIFN_D_VALID | HIFN_D_MASKDONEIRQ | HIFN_D_LAST |
1711 dst->segs[i].ds_len;
1713 p = sc->sc_dma_physaddr +
1714 offsetof(struct hifn_dma, slop[cmd->slopidx]);
1715 l = HIFN_D_VALID | HIFN_D_MASKDONEIRQ | HIFN_D_LAST |
1718 if ((dst->segs[i].ds_len - cmd->sloplen) != 0) {
1719 dma->dstr[idx].p = htole32(dst->segs[i].ds_addr);
1720 dma->dstr[idx].l = htole32(HIFN_D_VALID |
1721 HIFN_D_MASKDONEIRQ |
1722 (dst->segs[i].ds_len - cmd->sloplen));
1723 HIFN_DSTR_SYNC(sc, idx,
1724 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1727 idx = hifn_dmamap_dstwrap(sc, idx);
1730 dma->dstr[idx].p = htole32(p);
1731 dma->dstr[idx].l = htole32(l);
1732 HIFN_DSTR_SYNC(sc, idx, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1735 idx = hifn_dmamap_dstwrap(sc, idx);
1738 sc->sc_dstu += used;
1743 hifn_dmamap_srcwrap(struct hifn_softc *sc, int idx)
1745 struct hifn_dma *dma = sc->sc_dma;
1747 if (++idx == HIFN_D_SRC_RSIZE) {
1748 dma->srcr[idx].l = htole32(HIFN_D_VALID |
1749 HIFN_D_JUMP | HIFN_D_MASKDONEIRQ);
1750 HIFN_SRCR_SYNC(sc, HIFN_D_SRC_RSIZE,
1751 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1758 hifn_dmamap_load_src(struct hifn_softc *sc, struct hifn_command *cmd)
1760 struct hifn_dma *dma = sc->sc_dma;
1761 struct hifn_operand *src = &cmd->src;
1766 for (i = 0; i < src->nsegs; i++) {
1767 if (i == src->nsegs - 1)
1770 dma->srcr[idx].p = htole32(src->segs[i].ds_addr);
1771 dma->srcr[idx].l = htole32(src->segs[i].ds_len |
1772 HIFN_D_VALID | HIFN_D_MASKDONEIRQ | last);
1773 HIFN_SRCR_SYNC(sc, idx,
1774 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1776 idx = hifn_dmamap_srcwrap(sc, idx);
1779 sc->sc_srcu += src->nsegs;
1784 hifn_op_cb(void* arg, bus_dma_segment_t *seg, int nsegs, bus_size_t mapsize, int error)
1786 struct hifn_operand *op = arg;
1788 KASSERT(nsegs <= MAX_SCATTER,
1789 ("hifn_op_cb: too many DMA segments (%u > %u) "
1790 "returned when mapping operand", nsegs, MAX_SCATTER));
1791 op->mapsize = mapsize;
1793 bcopy(seg, op->segs, nsegs * sizeof (seg[0]));
1798 struct hifn_softc *sc,
1799 struct hifn_command *cmd,
1800 struct cryptop *crp,
1803 struct hifn_dma *dma = sc->sc_dma;
1804 u_int32_t cmdlen, csr;
1805 int cmdi, resi, err = 0;
1808 * need 1 cmd, and 1 res
1810 * NB: check this first since it's easy.
1813 if ((sc->sc_cmdu + 1) > HIFN_D_CMD_RSIZE ||
1814 (sc->sc_resu + 1) > HIFN_D_RES_RSIZE) {
1817 device_printf(sc->sc_dev,
1818 "cmd/result exhaustion, cmdu %u resu %u\n",
1819 sc->sc_cmdu, sc->sc_resu);
1822 hifnstats.hst_nomem_cr++;
1827 if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, &cmd->src_map)) {
1828 hifnstats.hst_nomem_map++;
1833 if (crp->crp_flags & CRYPTO_F_IMBUF) {
1834 if (bus_dmamap_load_mbuf(sc->sc_dmat, cmd->src_map,
1835 cmd->src_m, hifn_op_cb, &cmd->src, BUS_DMA_NOWAIT)) {
1836 hifnstats.hst_nomem_load++;
1840 } else if (crp->crp_flags & CRYPTO_F_IOV) {
1841 if (bus_dmamap_load_uio(sc->sc_dmat, cmd->src_map,
1842 cmd->src_io, hifn_op_cb, &cmd->src, BUS_DMA_NOWAIT)) {
1843 hifnstats.hst_nomem_load++;
1852 if (hifn_dmamap_aligned(&cmd->src)) {
1853 cmd->sloplen = cmd->src_mapsize & 3;
1854 cmd->dst = cmd->src;
1856 if (crp->crp_flags & CRYPTO_F_IOV) {
1859 } else if (crp->crp_flags & CRYPTO_F_IMBUF) {
1861 struct mbuf *m, *m0, *mlast;
1863 KASSERT(cmd->dst_m == cmd->src_m,
1864 ("hifn_crypto: dst_m initialized improperly"));
1865 hifnstats.hst_unaligned++;
1867 * Source is not aligned on a longword boundary.
1868 * Copy the data to insure alignment. If we fail
1869 * to allocate mbufs or clusters while doing this
1870 * we return ERESTART so the operation is requeued
1871 * at the crypto later, but only if there are
1872 * ops already posted to the hardware; otherwise we
1873 * have no guarantee that we'll be re-entered.
1875 totlen = cmd->src_mapsize;
1876 if (cmd->src_m->m_flags & M_PKTHDR) {
1878 MGETHDR(m0, M_NOWAIT, MT_DATA);
1879 if (m0 && !m_dup_pkthdr(m0, cmd->src_m, M_NOWAIT)) {
1885 MGET(m0, M_NOWAIT, MT_DATA);
1888 hifnstats.hst_nomem_mbuf++;
1889 err = sc->sc_cmdu ? ERESTART : ENOMEM;
1892 if (totlen >= MINCLSIZE) {
1893 if (!(MCLGET(m0, M_NOWAIT))) {
1894 hifnstats.hst_nomem_mcl++;
1895 err = sc->sc_cmdu ? ERESTART : ENOMEM;
1902 m0->m_pkthdr.len = m0->m_len = len;
1905 while (totlen > 0) {
1906 MGET(m, M_NOWAIT, MT_DATA);
1908 hifnstats.hst_nomem_mbuf++;
1909 err = sc->sc_cmdu ? ERESTART : ENOMEM;
1914 if (totlen >= MINCLSIZE) {
1915 if (!(MCLGET(m, M_NOWAIT))) {
1916 hifnstats.hst_nomem_mcl++;
1917 err = sc->sc_cmdu ? ERESTART : ENOMEM;
1926 m0->m_pkthdr.len += len;
1936 if (cmd->dst_map == NULL) {
1937 if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, &cmd->dst_map)) {
1938 hifnstats.hst_nomem_map++;
1942 if (crp->crp_flags & CRYPTO_F_IMBUF) {
1943 if (bus_dmamap_load_mbuf(sc->sc_dmat, cmd->dst_map,
1944 cmd->dst_m, hifn_op_cb, &cmd->dst, BUS_DMA_NOWAIT)) {
1945 hifnstats.hst_nomem_map++;
1949 } else if (crp->crp_flags & CRYPTO_F_IOV) {
1950 if (bus_dmamap_load_uio(sc->sc_dmat, cmd->dst_map,
1951 cmd->dst_io, hifn_op_cb, &cmd->dst, BUS_DMA_NOWAIT)) {
1952 hifnstats.hst_nomem_load++;
1961 device_printf(sc->sc_dev,
1962 "Entering cmd: stat %8x ien %8x u %d/%d/%d/%d n %d/%d\n",
1963 READ_REG_1(sc, HIFN_1_DMA_CSR),
1964 READ_REG_1(sc, HIFN_1_DMA_IER),
1965 sc->sc_cmdu, sc->sc_srcu, sc->sc_dstu, sc->sc_resu,
1966 cmd->src_nsegs, cmd->dst_nsegs);
1970 if (cmd->src_map == cmd->dst_map) {
1971 bus_dmamap_sync(sc->sc_dmat, cmd->src_map,
1972 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
1974 bus_dmamap_sync(sc->sc_dmat, cmd->src_map,
1975 BUS_DMASYNC_PREWRITE);
1976 bus_dmamap_sync(sc->sc_dmat, cmd->dst_map,
1977 BUS_DMASYNC_PREREAD);
1981 * need N src, and N dst
1983 if ((sc->sc_srcu + cmd->src_nsegs) > HIFN_D_SRC_RSIZE ||
1984 (sc->sc_dstu + cmd->dst_nsegs + 1) > HIFN_D_DST_RSIZE) {
1987 device_printf(sc->sc_dev,
1988 "src/dst exhaustion, srcu %u+%u dstu %u+%u\n",
1989 sc->sc_srcu, cmd->src_nsegs,
1990 sc->sc_dstu, cmd->dst_nsegs);
1993 hifnstats.hst_nomem_sd++;
1998 if (sc->sc_cmdi == HIFN_D_CMD_RSIZE) {
2000 dma->cmdr[HIFN_D_CMD_RSIZE].l = htole32(HIFN_D_VALID |
2001 HIFN_D_JUMP | HIFN_D_MASKDONEIRQ);
2002 HIFN_CMDR_SYNC(sc, HIFN_D_CMD_RSIZE,
2003 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2005 cmdi = sc->sc_cmdi++;
2006 cmdlen = hifn_write_command(cmd, dma->command_bufs[cmdi]);
2007 HIFN_CMD_SYNC(sc, cmdi, BUS_DMASYNC_PREWRITE);
2009 /* .p for command/result already set */
2010 dma->cmdr[cmdi].l = htole32(cmdlen | HIFN_D_VALID | HIFN_D_LAST |
2011 HIFN_D_MASKDONEIRQ);
2012 HIFN_CMDR_SYNC(sc, cmdi,
2013 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2017 * We don't worry about missing an interrupt (which a "command wait"
2018 * interrupt salvages us from), unless there is more than one command
2021 if (sc->sc_cmdu > 1) {
2022 sc->sc_dmaier |= HIFN_DMAIER_C_WAIT;
2023 WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier);
2026 hifnstats.hst_ipackets++;
2027 hifnstats.hst_ibytes += cmd->src_mapsize;
2029 hifn_dmamap_load_src(sc, cmd);
2032 * Unlike other descriptors, we don't mask done interrupt from
2033 * result descriptor.
2037 printf("load res\n");
2039 if (sc->sc_resi == HIFN_D_RES_RSIZE) {
2041 dma->resr[HIFN_D_RES_RSIZE].l = htole32(HIFN_D_VALID |
2042 HIFN_D_JUMP | HIFN_D_MASKDONEIRQ);
2043 HIFN_RESR_SYNC(sc, HIFN_D_RES_RSIZE,
2044 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2046 resi = sc->sc_resi++;
2047 KASSERT(sc->sc_hifn_commands[resi] == NULL,
2048 ("hifn_crypto: command slot %u busy", resi));
2049 sc->sc_hifn_commands[resi] = cmd;
2050 HIFN_RES_SYNC(sc, resi, BUS_DMASYNC_PREREAD);
2051 if ((hint & CRYPTO_HINT_MORE) && sc->sc_curbatch < hifn_maxbatch) {
2052 dma->resr[resi].l = htole32(HIFN_MAX_RESULT |
2053 HIFN_D_VALID | HIFN_D_LAST | HIFN_D_MASKDONEIRQ);
2055 if (sc->sc_curbatch > hifnstats.hst_maxbatch)
2056 hifnstats.hst_maxbatch = sc->sc_curbatch;
2057 hifnstats.hst_totbatch++;
2059 dma->resr[resi].l = htole32(HIFN_MAX_RESULT |
2060 HIFN_D_VALID | HIFN_D_LAST);
2061 sc->sc_curbatch = 0;
2063 HIFN_RESR_SYNC(sc, resi,
2064 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2068 cmd->slopidx = resi;
2070 hifn_dmamap_load_dst(sc, cmd);
2073 if (sc->sc_c_busy == 0) {
2074 csr |= HIFN_DMACSR_C_CTRL_ENA;
2077 if (sc->sc_s_busy == 0) {
2078 csr |= HIFN_DMACSR_S_CTRL_ENA;
2081 if (sc->sc_r_busy == 0) {
2082 csr |= HIFN_DMACSR_R_CTRL_ENA;
2085 if (sc->sc_d_busy == 0) {
2086 csr |= HIFN_DMACSR_D_CTRL_ENA;
2090 WRITE_REG_1(sc, HIFN_1_DMA_CSR, csr);
2094 device_printf(sc->sc_dev, "command: stat %8x ier %8x\n",
2095 READ_REG_1(sc, HIFN_1_DMA_CSR),
2096 READ_REG_1(sc, HIFN_1_DMA_IER));
2102 KASSERT(err == 0, ("hifn_crypto: success with error %u", err));
2103 return (err); /* success */
2106 if (cmd->src_map != cmd->dst_map)
2107 bus_dmamap_unload(sc->sc_dmat, cmd->dst_map);
2109 if (cmd->src_map != cmd->dst_map)
2110 bus_dmamap_destroy(sc->sc_dmat, cmd->dst_map);
2112 if (crp->crp_flags & CRYPTO_F_IMBUF) {
2113 if (cmd->src_m != cmd->dst_m)
2114 m_freem(cmd->dst_m);
2116 bus_dmamap_unload(sc->sc_dmat, cmd->src_map);
2118 bus_dmamap_destroy(sc->sc_dmat, cmd->src_map);
2124 hifn_tick(void* vsc)
2126 struct hifn_softc *sc = vsc;
2129 if (sc->sc_active == 0) {
2132 if (sc->sc_cmdu == 0 && sc->sc_c_busy) {
2134 r |= HIFN_DMACSR_C_CTRL_DIS;
2136 if (sc->sc_srcu == 0 && sc->sc_s_busy) {
2138 r |= HIFN_DMACSR_S_CTRL_DIS;
2140 if (sc->sc_dstu == 0 && sc->sc_d_busy) {
2142 r |= HIFN_DMACSR_D_CTRL_DIS;
2144 if (sc->sc_resu == 0 && sc->sc_r_busy) {
2146 r |= HIFN_DMACSR_R_CTRL_DIS;
2149 WRITE_REG_1(sc, HIFN_1_DMA_CSR, r);
2153 callout_reset(&sc->sc_tickto, hz, hifn_tick, sc);
2157 hifn_intr(void *arg)
2159 struct hifn_softc *sc = arg;
2160 struct hifn_dma *dma;
2161 u_int32_t dmacsr, restart;
2164 dmacsr = READ_REG_1(sc, HIFN_1_DMA_CSR);
2166 /* Nothing in the DMA unit interrupted */
2167 if ((dmacsr & sc->sc_dmaier) == 0)
2176 device_printf(sc->sc_dev,
2177 "irq: stat %08x ien %08x damier %08x i %d/%d/%d/%d k %d/%d/%d/%d u %d/%d/%d/%d\n",
2178 dmacsr, READ_REG_1(sc, HIFN_1_DMA_IER), sc->sc_dmaier,
2179 sc->sc_cmdi, sc->sc_srci, sc->sc_dsti, sc->sc_resi,
2180 sc->sc_cmdk, sc->sc_srck, sc->sc_dstk, sc->sc_resk,
2181 sc->sc_cmdu, sc->sc_srcu, sc->sc_dstu, sc->sc_resu);
2185 WRITE_REG_1(sc, HIFN_1_DMA_CSR, dmacsr & sc->sc_dmaier);
2187 if ((sc->sc_flags & HIFN_HAS_PUBLIC) &&
2188 (dmacsr & HIFN_DMACSR_PUBDONE))
2189 WRITE_REG_1(sc, HIFN_1_PUB_STATUS,
2190 READ_REG_1(sc, HIFN_1_PUB_STATUS) | HIFN_PUBSTS_DONE);
2192 restart = dmacsr & (HIFN_DMACSR_D_OVER | HIFN_DMACSR_R_OVER);
2194 device_printf(sc->sc_dev, "overrun %x\n", dmacsr);
2196 if (sc->sc_flags & HIFN_IS_7811) {
2197 if (dmacsr & HIFN_DMACSR_ILLR)
2198 device_printf(sc->sc_dev, "illegal read\n");
2199 if (dmacsr & HIFN_DMACSR_ILLW)
2200 device_printf(sc->sc_dev, "illegal write\n");
2203 restart = dmacsr & (HIFN_DMACSR_C_ABORT | HIFN_DMACSR_S_ABORT |
2204 HIFN_DMACSR_D_ABORT | HIFN_DMACSR_R_ABORT);
2206 device_printf(sc->sc_dev, "abort, resetting.\n");
2207 hifnstats.hst_abort++;
2213 if ((dmacsr & HIFN_DMACSR_C_WAIT) && (sc->sc_cmdu == 0)) {
2215 * If no slots to process and we receive a "waiting on
2216 * command" interrupt, we disable the "waiting on command"
2219 sc->sc_dmaier &= ~HIFN_DMAIER_C_WAIT;
2220 WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier);
2223 /* clear the rings */
2224 i = sc->sc_resk; u = sc->sc_resu;
2226 HIFN_RESR_SYNC(sc, i,
2227 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2228 if (dma->resr[i].l & htole32(HIFN_D_VALID)) {
2229 HIFN_RESR_SYNC(sc, i,
2230 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2234 if (i != HIFN_D_RES_RSIZE) {
2235 struct hifn_command *cmd;
2236 u_int8_t *macbuf = NULL;
2238 HIFN_RES_SYNC(sc, i, BUS_DMASYNC_POSTREAD);
2239 cmd = sc->sc_hifn_commands[i];
2240 KASSERT(cmd != NULL,
2241 ("hifn_intr: null command slot %u", i));
2242 sc->sc_hifn_commands[i] = NULL;
2244 if (cmd->base_masks & HIFN_BASE_CMD_MAC) {
2245 macbuf = dma->result_bufs[i];
2249 hifn_callback(sc, cmd, macbuf);
2250 hifnstats.hst_opackets++;
2254 if (++i == (HIFN_D_RES_RSIZE + 1))
2257 sc->sc_resk = i; sc->sc_resu = u;
2259 i = sc->sc_srck; u = sc->sc_srcu;
2261 if (i == HIFN_D_SRC_RSIZE)
2263 HIFN_SRCR_SYNC(sc, i,
2264 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2265 if (dma->srcr[i].l & htole32(HIFN_D_VALID)) {
2266 HIFN_SRCR_SYNC(sc, i,
2267 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2272 sc->sc_srck = i; sc->sc_srcu = u;
2274 i = sc->sc_cmdk; u = sc->sc_cmdu;
2276 HIFN_CMDR_SYNC(sc, i,
2277 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2278 if (dma->cmdr[i].l & htole32(HIFN_D_VALID)) {
2279 HIFN_CMDR_SYNC(sc, i,
2280 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2283 if (i != HIFN_D_CMD_RSIZE) {
2285 HIFN_CMD_SYNC(sc, i, BUS_DMASYNC_POSTWRITE);
2287 if (++i == (HIFN_D_CMD_RSIZE + 1))
2290 sc->sc_cmdk = i; sc->sc_cmdu = u;
2294 if (sc->sc_needwakeup) { /* XXX check high watermark */
2295 int wakeup = sc->sc_needwakeup & (CRYPTO_SYMQ|CRYPTO_ASYMQ);
2298 device_printf(sc->sc_dev,
2299 "wakeup crypto (%x) u %d/%d/%d/%d\n",
2301 sc->sc_cmdu, sc->sc_srcu, sc->sc_dstu, sc->sc_resu);
2303 sc->sc_needwakeup &= ~wakeup;
2304 crypto_unblock(sc->sc_cid, wakeup);
2309 * Allocate a new 'session' and return an encoded session id. 'sidp'
2310 * contains our registration id, and should contain an encoded session
2311 * id on successful allocation.
2314 hifn_newsession(device_t dev, u_int32_t *sidp, struct cryptoini *cri)
2316 struct hifn_softc *sc = device_get_softc(dev);
2317 struct cryptoini *c;
2318 int mac = 0, cry = 0, sesn;
2319 struct hifn_session *ses = NULL;
2321 KASSERT(sc != NULL, ("hifn_newsession: null softc"));
2322 if (sidp == NULL || cri == NULL || sc == NULL)
2326 if (sc->sc_sessions == NULL) {
2327 ses = sc->sc_sessions = (struct hifn_session *)malloc(
2328 sizeof(*ses), M_DEVBUF, M_NOWAIT);
2334 sc->sc_nsessions = 1;
2336 for (sesn = 0; sesn < sc->sc_nsessions; sesn++) {
2337 if (!sc->sc_sessions[sesn].hs_used) {
2338 ses = &sc->sc_sessions[sesn];
2344 sesn = sc->sc_nsessions;
2345 ses = (struct hifn_session *)malloc((sesn + 1) *
2346 sizeof(*ses), M_DEVBUF, M_NOWAIT);
2351 bcopy(sc->sc_sessions, ses, sesn * sizeof(*ses));
2352 bzero(sc->sc_sessions, sesn * sizeof(*ses));
2353 free(sc->sc_sessions, M_DEVBUF);
2354 sc->sc_sessions = ses;
2355 ses = &sc->sc_sessions[sesn];
2361 bzero(ses, sizeof(*ses));
2364 for (c = cri; c != NULL; c = c->cri_next) {
2365 switch (c->cri_alg) {
2368 case CRYPTO_MD5_HMAC:
2369 case CRYPTO_SHA1_HMAC:
2373 ses->hs_mlen = c->cri_mlen;
2374 if (ses->hs_mlen == 0) {
2375 switch (c->cri_alg) {
2377 case CRYPTO_MD5_HMAC:
2381 case CRYPTO_SHA1_HMAC:
2387 case CRYPTO_DES_CBC:
2388 case CRYPTO_3DES_CBC:
2389 case CRYPTO_AES_CBC:
2390 /* XXX this may read fewer, does it matter? */
2391 read_random(ses->hs_iv,
2392 c->cri_alg == CRYPTO_AES_CBC ?
2393 HIFN_AES_IV_LENGTH : HIFN_IV_LENGTH);
2404 if (mac == 0 && cry == 0)
2407 *sidp = HIFN_SID(device_get_unit(sc->sc_dev), sesn);
2413 * Deallocate a session.
2414 * XXX this routine should run a zero'd mac/encrypt key into context ram.
2415 * XXX to blow away any keys already stored there.
2418 hifn_freesession(device_t dev, u_int64_t tid)
2420 struct hifn_softc *sc = device_get_softc(dev);
2422 u_int32_t sid = CRYPTO_SESID2LID(tid);
2424 KASSERT(sc != NULL, ("hifn_freesession: null softc"));
2429 session = HIFN_SESSION(sid);
2430 if (session < sc->sc_nsessions) {
2431 bzero(&sc->sc_sessions[session], sizeof(struct hifn_session));
2441 hifn_process(device_t dev, struct cryptop *crp, int hint)
2443 struct hifn_softc *sc = device_get_softc(dev);
2444 struct hifn_command *cmd = NULL;
2445 int session, err, ivlen;
2446 struct cryptodesc *crd1, *crd2, *maccrd, *enccrd;
2448 if (crp == NULL || crp->crp_callback == NULL) {
2449 hifnstats.hst_invalid++;
2452 session = HIFN_SESSION(crp->crp_sid);
2454 if (sc == NULL || session >= sc->sc_nsessions) {
2459 cmd = malloc(sizeof(struct hifn_command), M_DEVBUF, M_NOWAIT | M_ZERO);
2461 hifnstats.hst_nomem++;
2466 if (crp->crp_flags & CRYPTO_F_IMBUF) {
2467 cmd->src_m = (struct mbuf *)crp->crp_buf;
2468 cmd->dst_m = (struct mbuf *)crp->crp_buf;
2469 } else if (crp->crp_flags & CRYPTO_F_IOV) {
2470 cmd->src_io = (struct uio *)crp->crp_buf;
2471 cmd->dst_io = (struct uio *)crp->crp_buf;
2474 goto errout; /* XXX we don't handle contiguous buffers! */
2477 crd1 = crp->crp_desc;
2482 crd2 = crd1->crd_next;
2485 if (crd1->crd_alg == CRYPTO_MD5_HMAC ||
2486 crd1->crd_alg == CRYPTO_SHA1_HMAC ||
2487 crd1->crd_alg == CRYPTO_SHA1 ||
2488 crd1->crd_alg == CRYPTO_MD5) {
2491 } else if (crd1->crd_alg == CRYPTO_DES_CBC ||
2492 crd1->crd_alg == CRYPTO_3DES_CBC ||
2493 crd1->crd_alg == CRYPTO_AES_CBC ||
2494 crd1->crd_alg == CRYPTO_ARC4) {
2495 if ((crd1->crd_flags & CRD_F_ENCRYPT) == 0)
2496 cmd->base_masks |= HIFN_BASE_CMD_DECODE;
2504 if ((crd1->crd_alg == CRYPTO_MD5_HMAC ||
2505 crd1->crd_alg == CRYPTO_SHA1_HMAC ||
2506 crd1->crd_alg == CRYPTO_MD5 ||
2507 crd1->crd_alg == CRYPTO_SHA1) &&
2508 (crd2->crd_alg == CRYPTO_DES_CBC ||
2509 crd2->crd_alg == CRYPTO_3DES_CBC ||
2510 crd2->crd_alg == CRYPTO_AES_CBC ||
2511 crd2->crd_alg == CRYPTO_ARC4) &&
2512 ((crd2->crd_flags & CRD_F_ENCRYPT) == 0)) {
2513 cmd->base_masks = HIFN_BASE_CMD_DECODE;
2516 } else if ((crd1->crd_alg == CRYPTO_DES_CBC ||
2517 crd1->crd_alg == CRYPTO_ARC4 ||
2518 crd1->crd_alg == CRYPTO_3DES_CBC ||
2519 crd1->crd_alg == CRYPTO_AES_CBC) &&
2520 (crd2->crd_alg == CRYPTO_MD5_HMAC ||
2521 crd2->crd_alg == CRYPTO_SHA1_HMAC ||
2522 crd2->crd_alg == CRYPTO_MD5 ||
2523 crd2->crd_alg == CRYPTO_SHA1) &&
2524 (crd1->crd_flags & CRD_F_ENCRYPT)) {
2529 * We cannot order the 7751 as requested
2537 cmd->enccrd = enccrd;
2538 cmd->base_masks |= HIFN_BASE_CMD_CRYPT;
2539 switch (enccrd->crd_alg) {
2541 cmd->cry_masks |= HIFN_CRYPT_CMD_ALG_RC4;
2543 case CRYPTO_DES_CBC:
2544 cmd->cry_masks |= HIFN_CRYPT_CMD_ALG_DES |
2545 HIFN_CRYPT_CMD_MODE_CBC |
2546 HIFN_CRYPT_CMD_NEW_IV;
2548 case CRYPTO_3DES_CBC:
2549 cmd->cry_masks |= HIFN_CRYPT_CMD_ALG_3DES |
2550 HIFN_CRYPT_CMD_MODE_CBC |
2551 HIFN_CRYPT_CMD_NEW_IV;
2553 case CRYPTO_AES_CBC:
2554 cmd->cry_masks |= HIFN_CRYPT_CMD_ALG_AES |
2555 HIFN_CRYPT_CMD_MODE_CBC |
2556 HIFN_CRYPT_CMD_NEW_IV;
2562 if (enccrd->crd_alg != CRYPTO_ARC4) {
2563 ivlen = ((enccrd->crd_alg == CRYPTO_AES_CBC) ?
2564 HIFN_AES_IV_LENGTH : HIFN_IV_LENGTH);
2565 if (enccrd->crd_flags & CRD_F_ENCRYPT) {
2566 if (enccrd->crd_flags & CRD_F_IV_EXPLICIT)
2567 bcopy(enccrd->crd_iv, cmd->iv, ivlen);
2569 bcopy(sc->sc_sessions[session].hs_iv,
2572 if ((enccrd->crd_flags & CRD_F_IV_PRESENT)
2574 crypto_copyback(crp->crp_flags,
2575 crp->crp_buf, enccrd->crd_inject,
2579 if (enccrd->crd_flags & CRD_F_IV_EXPLICIT)
2580 bcopy(enccrd->crd_iv, cmd->iv, ivlen);
2582 crypto_copydata(crp->crp_flags,
2583 crp->crp_buf, enccrd->crd_inject,
2589 if (enccrd->crd_flags & CRD_F_KEY_EXPLICIT)
2590 cmd->cry_masks |= HIFN_CRYPT_CMD_NEW_KEY;
2591 cmd->ck = enccrd->crd_key;
2592 cmd->cklen = enccrd->crd_klen >> 3;
2593 cmd->cry_masks |= HIFN_CRYPT_CMD_NEW_KEY;
2596 * Need to specify the size for the AES key in the masks.
2598 if ((cmd->cry_masks & HIFN_CRYPT_CMD_ALG_MASK) ==
2599 HIFN_CRYPT_CMD_ALG_AES) {
2600 switch (cmd->cklen) {
2602 cmd->cry_masks |= HIFN_CRYPT_CMD_KSZ_128;
2605 cmd->cry_masks |= HIFN_CRYPT_CMD_KSZ_192;
2608 cmd->cry_masks |= HIFN_CRYPT_CMD_KSZ_256;
2618 cmd->maccrd = maccrd;
2619 cmd->base_masks |= HIFN_BASE_CMD_MAC;
2621 switch (maccrd->crd_alg) {
2623 cmd->mac_masks |= HIFN_MAC_CMD_ALG_MD5 |
2624 HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HASH |
2625 HIFN_MAC_CMD_POS_IPSEC;
2627 case CRYPTO_MD5_HMAC:
2628 cmd->mac_masks |= HIFN_MAC_CMD_ALG_MD5 |
2629 HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HMAC |
2630 HIFN_MAC_CMD_POS_IPSEC | HIFN_MAC_CMD_TRUNC;
2633 cmd->mac_masks |= HIFN_MAC_CMD_ALG_SHA1 |
2634 HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HASH |
2635 HIFN_MAC_CMD_POS_IPSEC;
2637 case CRYPTO_SHA1_HMAC:
2638 cmd->mac_masks |= HIFN_MAC_CMD_ALG_SHA1 |
2639 HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HMAC |
2640 HIFN_MAC_CMD_POS_IPSEC | HIFN_MAC_CMD_TRUNC;
2644 if (maccrd->crd_alg == CRYPTO_SHA1_HMAC ||
2645 maccrd->crd_alg == CRYPTO_MD5_HMAC) {
2646 cmd->mac_masks |= HIFN_MAC_CMD_NEW_KEY;
2647 bcopy(maccrd->crd_key, cmd->mac, maccrd->crd_klen >> 3);
2648 bzero(cmd->mac + (maccrd->crd_klen >> 3),
2649 HIFN_MAC_KEY_LENGTH - (maccrd->crd_klen >> 3));
2654 cmd->session_num = session;
2657 err = hifn_crypto(sc, cmd, crp, hint);
2660 } else if (err == ERESTART) {
2662 * There weren't enough resources to dispatch the request
2663 * to the part. Notify the caller so they'll requeue this
2664 * request and resubmit it again soon.
2668 device_printf(sc->sc_dev, "requeue request\n");
2670 free(cmd, M_DEVBUF);
2671 sc->sc_needwakeup |= CRYPTO_SYMQ;
2677 free(cmd, M_DEVBUF);
2679 hifnstats.hst_invalid++;
2681 hifnstats.hst_nomem++;
2682 crp->crp_etype = err;
2688 hifn_abort(struct hifn_softc *sc)
2690 struct hifn_dma *dma = sc->sc_dma;
2691 struct hifn_command *cmd;
2692 struct cryptop *crp;
2695 i = sc->sc_resk; u = sc->sc_resu;
2697 cmd = sc->sc_hifn_commands[i];
2698 KASSERT(cmd != NULL, ("hifn_abort: null command slot %u", i));
2699 sc->sc_hifn_commands[i] = NULL;
2702 if ((dma->resr[i].l & htole32(HIFN_D_VALID)) == 0) {
2703 /* Salvage what we can. */
2706 if (cmd->base_masks & HIFN_BASE_CMD_MAC) {
2707 macbuf = dma->result_bufs[i];
2711 hifnstats.hst_opackets++;
2712 hifn_callback(sc, cmd, macbuf);
2714 if (cmd->src_map == cmd->dst_map) {
2715 bus_dmamap_sync(sc->sc_dmat, cmd->src_map,
2716 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
2718 bus_dmamap_sync(sc->sc_dmat, cmd->src_map,
2719 BUS_DMASYNC_POSTWRITE);
2720 bus_dmamap_sync(sc->sc_dmat, cmd->dst_map,
2721 BUS_DMASYNC_POSTREAD);
2724 if (cmd->src_m != cmd->dst_m) {
2725 m_freem(cmd->src_m);
2726 crp->crp_buf = (caddr_t)cmd->dst_m;
2729 /* non-shared buffers cannot be restarted */
2730 if (cmd->src_map != cmd->dst_map) {
2732 * XXX should be EAGAIN, delayed until
2735 crp->crp_etype = ENOMEM;
2736 bus_dmamap_unload(sc->sc_dmat, cmd->dst_map);
2737 bus_dmamap_destroy(sc->sc_dmat, cmd->dst_map);
2739 crp->crp_etype = ENOMEM;
2741 bus_dmamap_unload(sc->sc_dmat, cmd->src_map);
2742 bus_dmamap_destroy(sc->sc_dmat, cmd->src_map);
2744 free(cmd, M_DEVBUF);
2745 if (crp->crp_etype != EAGAIN)
2749 if (++i == HIFN_D_RES_RSIZE)
2753 sc->sc_resk = i; sc->sc_resu = u;
2755 hifn_reset_board(sc, 1);
2757 hifn_init_pci_registers(sc);
2761 hifn_callback(struct hifn_softc *sc, struct hifn_command *cmd, u_int8_t *macbuf)
2763 struct hifn_dma *dma = sc->sc_dma;
2764 struct cryptop *crp = cmd->crp;
2765 struct cryptodesc *crd;
2767 int totlen, i, u, ivlen;
2769 if (cmd->src_map == cmd->dst_map) {
2770 bus_dmamap_sync(sc->sc_dmat, cmd->src_map,
2771 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
2773 bus_dmamap_sync(sc->sc_dmat, cmd->src_map,
2774 BUS_DMASYNC_POSTWRITE);
2775 bus_dmamap_sync(sc->sc_dmat, cmd->dst_map,
2776 BUS_DMASYNC_POSTREAD);
2779 if (crp->crp_flags & CRYPTO_F_IMBUF) {
2780 if (cmd->src_m != cmd->dst_m) {
2781 crp->crp_buf = (caddr_t)cmd->dst_m;
2782 totlen = cmd->src_mapsize;
2783 for (m = cmd->dst_m; m != NULL; m = m->m_next) {
2784 if (totlen < m->m_len) {
2790 cmd->dst_m->m_pkthdr.len = cmd->src_m->m_pkthdr.len;
2791 m_freem(cmd->src_m);
2795 if (cmd->sloplen != 0) {
2796 crypto_copyback(crp->crp_flags, crp->crp_buf,
2797 cmd->src_mapsize - cmd->sloplen, cmd->sloplen,
2798 (caddr_t)&dma->slop[cmd->slopidx]);
2801 i = sc->sc_dstk; u = sc->sc_dstu;
2803 if (i == HIFN_D_DST_RSIZE)
2805 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap,
2806 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2807 if (dma->dstr[i].l & htole32(HIFN_D_VALID)) {
2808 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap,
2809 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2814 sc->sc_dstk = i; sc->sc_dstu = u;
2816 hifnstats.hst_obytes += cmd->dst_mapsize;
2818 if ((cmd->base_masks & (HIFN_BASE_CMD_CRYPT | HIFN_BASE_CMD_DECODE)) ==
2819 HIFN_BASE_CMD_CRYPT) {
2820 for (crd = crp->crp_desc; crd; crd = crd->crd_next) {
2821 if (crd->crd_alg != CRYPTO_DES_CBC &&
2822 crd->crd_alg != CRYPTO_3DES_CBC &&
2823 crd->crd_alg != CRYPTO_AES_CBC)
2825 ivlen = ((crd->crd_alg == CRYPTO_AES_CBC) ?
2826 HIFN_AES_IV_LENGTH : HIFN_IV_LENGTH);
2827 crypto_copydata(crp->crp_flags, crp->crp_buf,
2828 crd->crd_skip + crd->crd_len - ivlen, ivlen,
2829 cmd->softc->sc_sessions[cmd->session_num].hs_iv);
2834 if (macbuf != NULL) {
2835 for (crd = crp->crp_desc; crd; crd = crd->crd_next) {
2838 if (crd->crd_alg != CRYPTO_MD5 &&
2839 crd->crd_alg != CRYPTO_SHA1 &&
2840 crd->crd_alg != CRYPTO_MD5_HMAC &&
2841 crd->crd_alg != CRYPTO_SHA1_HMAC) {
2844 len = cmd->softc->sc_sessions[cmd->session_num].hs_mlen;
2845 crypto_copyback(crp->crp_flags, crp->crp_buf,
2846 crd->crd_inject, len, macbuf);
2851 if (cmd->src_map != cmd->dst_map) {
2852 bus_dmamap_unload(sc->sc_dmat, cmd->dst_map);
2853 bus_dmamap_destroy(sc->sc_dmat, cmd->dst_map);
2855 bus_dmamap_unload(sc->sc_dmat, cmd->src_map);
2856 bus_dmamap_destroy(sc->sc_dmat, cmd->src_map);
2857 free(cmd, M_DEVBUF);
2862 * 7811 PB3 rev/2 parts lock-up on burst writes to Group 0
2863 * and Group 1 registers; avoid conditions that could create
2864 * burst writes by doing a read in between the writes.
2866 * NB: The read we interpose is always to the same register;
2867 * we do this because reading from an arbitrary (e.g. last)
2868 * register may not always work.
2871 hifn_write_reg_0(struct hifn_softc *sc, bus_size_t reg, u_int32_t val)
2873 if (sc->sc_flags & HIFN_IS_7811) {
2874 if (sc->sc_bar0_lastreg == reg - 4)
2875 bus_space_read_4(sc->sc_st0, sc->sc_sh0, HIFN_0_PUCNFG);
2876 sc->sc_bar0_lastreg = reg;
2878 bus_space_write_4(sc->sc_st0, sc->sc_sh0, reg, val);
2882 hifn_write_reg_1(struct hifn_softc *sc, bus_size_t reg, u_int32_t val)
2884 if (sc->sc_flags & HIFN_IS_7811) {
2885 if (sc->sc_bar1_lastreg == reg - 4)
2886 bus_space_read_4(sc->sc_st1, sc->sc_sh1, HIFN_1_REVID);
2887 sc->sc_bar1_lastreg = reg;
2889 bus_space_write_4(sc->sc_st1, sc->sc_sh1, reg, val);
2892 #ifdef HIFN_VULCANDEV
2894 * this code provides support for mapping the PK engine's register
2895 * into a userspace program.
2899 vulcanpk_mmap(struct cdev *dev, vm_ooffset_t offset,
2900 vm_paddr_t *paddr, int nprot, vm_memattr_t *memattr)
2902 struct hifn_softc *sc;
2908 pd = rman_get_start(sc->sc_bar1res);
2909 b = rman_get_virtual(sc->sc_bar1res);
2912 printf("vpk mmap: %p(%016llx) offset=%lld\n", b,
2913 (unsigned long long)pd, offset);
2914 hexdump(b, HIFN_1_PUB_MEMEND, "vpk", 0);
2924 static struct cdevsw vulcanpk_cdevsw = {
2925 .d_version = D_VERSION,
2926 .d_mmap = vulcanpk_mmap,
2927 .d_name = "vulcanpk",
2929 #endif /* HIFN_VULCANDEV */