2 * Copyright (c) 2004-2005 MARVELL SEMICONDUCTOR ISRAEL, LTD.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
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31 #ifndef SUPPORT_MV_SATA_GEN_1
32 #define SUPPORT_MV_SATA_GEN_1 1
35 #ifndef SUPPORT_MV_SATA_GEN_2
36 #define SUPPORT_MV_SATA_GEN_2 0
39 #if SUPPORT_MV_SATA_GEN_1==1 && SUPPORT_MV_SATA_GEN_2==1
40 #define MV_SATA_GEN_1(x) ((x)->sataAdapterGeneration==1)
41 #define MV_SATA_GEN_2(x) ((x)->sataAdapterGeneration==2)
42 #elif SUPPORT_MV_SATA_GEN_1==1
43 #define MV_SATA_GEN_1(x) 1
44 #define MV_SATA_GEN_2(x) 0
45 #elif SUPPORT_MV_SATA_GEN_2==1
46 #define MV_SATA_GEN_1(x) 0
47 #define MV_SATA_GEN_2(x) 1
49 #error "Which IC do you support?"
53 /* MV88SX50XX specific defines */
54 #define MV_SATA_VENDOR_ID 0x11AB
55 #define MV_SATA_DEVICE_ID_5080 0x5080
56 #define MV_SATA_DEVICE_ID_5081 0x5081
57 #define MV_SATA_DEVICE_ID_6080 0x6080
58 #define MV_SATA_DEVICE_ID_6081 0x6081
59 #define MV_SATA_CHANNELS_NUM 8
60 #define MV_SATA_UNITS_NUM 2
61 #define MV_SATA_PCI_BAR0_SPACE_SIZE (1<<18) /* 256 Kb*/
63 #define CHANNEL_QUEUE_LENGTH 32
64 #define CHANNEL_QUEUE_MASK 0x1F
66 #define MV_EDMA_QUEUE_LENGTH 32 /* Up to 32 outstanding */
67 /* commands per SATA channel*/
68 #define MV_EDMA_QUEUE_MASK 0x1F
69 #define MV_EDMA_REQUEST_QUEUE_SIZE 1024 /* 32*32 = 1KBytes */
70 #define MV_EDMA_RESPONSE_QUEUE_SIZE 256 /* 32*8 = 256 Bytes */
72 #define MV_EDMA_REQUEST_ENTRY_SIZE 32
73 #define MV_EDMA_RESPONSE_ENTRY_SIZE 8
75 #define MV_EDMA_PRD_ENTRY_SIZE 16 /* 16Bytes*/
76 #define MV_EDMA_PRD_NO_SNOOP_FLAG 0x00000001 /* MV_BIT0 */
77 #define MV_EDMA_PRD_EOT_FLAG 0x00008000 /* MV_BIT15 */
79 #define MV_ATA_IDENTIFY_DEV_DATA_LENGTH 256 /* number of words(2 byte)*/
80 #define MV_ATA_MODEL_NUMBER_LEN 40
81 #define ATA_SECTOR_SIZE 512
82 /* Log messages level defines */
84 #define MV_DEBUG_INIT 0x2
85 #define MV_DEBUG_INTERRUPTS 0x4
86 #define MV_DEBUG_SATA_LINK 0x8
87 #define MV_DEBUG_UDMA_COMMAND 0x10
88 #define MV_DEBUG_NON_UDMA_COMMAND 0x20
89 #define MV_DEBUG_ERROR 0x40
93 typedef enum mvUdmaType
95 MV_UDMA_TYPE_READ, MV_UDMA_TYPE_WRITE
98 typedef enum mvFlushType
100 MV_FLUSH_TYPE_CALLBACK, MV_FLUSH_TYPE_NONE
103 typedef enum mvCompletionType
105 MV_COMPLETION_TYPE_NORMAL, MV_COMPLETION_TYPE_ERROR,
106 MV_COMPLETION_TYPE_ABORT
107 } MV_COMPLETION_TYPE;
109 typedef enum mvEventType
111 MV_EVENT_TYPE_ADAPTER_ERROR, MV_EVENT_TYPE_SATA_CABLE
114 typedef enum mvEdmaMode
117 MV_EDMA_MODE_NOT_QUEUED,
118 MV_EDMA_MODE_NATIVE_QUEUING
121 typedef enum mvEdmaQueueResult
123 MV_EDMA_QUEUE_RESULT_OK = 0,
124 MV_EDMA_QUEUE_RESULT_EDMA_DISABLED,
125 MV_EDMA_QUEUE_RESULT_FULL,
126 MV_EDMA_QUEUE_RESULT_BAD_LBA_ADDRESS,
127 MV_EDMA_QUEUE_RESULT_BAD_PARAMS
128 } MV_EDMA_QUEUE_RESULT;
130 typedef enum mvQueueCommandResult
132 MV_QUEUE_COMMAND_RESULT_OK = 0,
133 MV_QUEUE_COMMAND_RESULT_QUEUED_MODE_DISABLED,
134 MV_QUEUE_COMMAND_RESULT_FULL,
135 MV_QUEUE_COMMAND_RESULT_BAD_LBA_ADDRESS,
136 MV_QUEUE_COMMAND_RESULT_BAD_PARAMS
137 } MV_QUEUE_COMMAND_RESULT;
139 typedef enum mvNonUdmaProtocol
141 MV_NON_UDMA_PROTOCOL_NON_DATA,
142 MV_NON_UDMA_PROTOCOL_PIO_DATA_IN,
143 MV_NON_UDMA_PROTOCOL_PIO_DATA_OUT
144 } MV_NON_UDMA_PROTOCOL;
147 struct mvDmaRequestQueueEntry;
148 struct mvDmaResponseQueueEntry;
149 struct mvDmaCommandEntry;
151 struct mvSataAdapter;
152 struct mvStorageDevRegisters;
154 typedef MV_BOOLEAN (* HPTLIBAPI mvSataCommandCompletionCallBack_t)(struct mvSataAdapter *,
159 struct mvStorageDevRegisters FAR*);
161 typedef enum mvQueuedCommandType
163 MV_QUEUED_COMMAND_TYPE_UDMA,
164 MV_QUEUED_COMMAND_TYPE_NONE_UDMA
165 } MV_QUEUED_COMMAND_TYPE;
167 typedef struct mvUdmaCommandParams
169 MV_UDMA_TYPE readWrite;
171 MV_U32 lowLBAAddress;
172 MV_U16 highLBAAddress;
176 mvSataCommandCompletionCallBack_t callBack;
177 MV_VOID_PTR commandId;
178 } MV_UDMA_COMMAND_PARAMS;
180 typedef struct mvNoneUdmaCommandParams
182 MV_NON_UDMA_PROTOCOL protocolType;
193 mvSataCommandCompletionCallBack_t callBack;
194 MV_VOID_PTR commandId;
195 } MV_NONE_UDMA_COMMAND_PARAMS;
197 typedef struct mvQueueCommandInfo
199 MV_QUEUED_COMMAND_TYPE type;
202 MV_UDMA_COMMAND_PARAMS udmaCommand;
203 MV_NONE_UDMA_COMMAND_PARAMS NoneUdmaCommand;
205 } MV_QUEUE_COMMAND_INFO;
207 /* The following structure is for the Core Driver internal usage */
208 typedef struct mvQueuedCommandEntry
210 MV_BOOLEAN isFreeEntry;
212 struct mvQueuedCommandEntry *next;
213 struct mvQueuedCommandEntry *prev;
214 MV_QUEUE_COMMAND_INFO commandInfo;
215 } MV_QUEUED_COMMAND_ENTRY;
217 /* The following structures are part of the Core Driver API */
218 typedef struct mvSataChannel
220 /* Fields set by Intermediate Application Layer */
222 MV_BOOLEAN waitingForInterrupt;
223 MV_BOOLEAN lba48Address;
224 MV_BOOLEAN maxReadTransfer;
225 struct mvDmaRequestQueueEntry FAR *requestQueue;
226 struct mvDmaResponseQueueEntry FAR *responseQueue;
227 MV_U32 requestQueuePciHiAddress;
228 MV_U32 requestQueuePciLowAddress;
229 MV_U32 responseQueuePciHiAddress;
230 MV_U32 responseQueuePciLowAddress;
231 /* Fields set by CORE driver */
232 struct mvSataAdapter *mvSataAdapter;
233 MV_OS_SEMAPHORE semaphore;
234 MV_U32 eDmaRegsOffset;
235 MV_U16 identifyDevice[MV_ATA_IDENTIFY_DEV_DATA_LENGTH];
236 MV_BOOLEAN EdmaActive;
237 MV_EDMA_MODE queuedDMA;
238 MV_U8 outstandingCommands;
239 MV_BOOLEAN workAroundDone;
240 struct mvQueuedCommandEntry commandsQueue[CHANNEL_QUEUE_LENGTH];
241 struct mvQueuedCommandEntry *commandsQueueHead;
242 struct mvQueuedCommandEntry *commandsQueueTail;
243 MV_BOOLEAN queueCommandsEnabled;
244 MV_U8 noneUdmaOutstandingCommands;
245 MV_U8 EdmaQueuedCommands;
246 MV_U32 freeIDsStack[MV_EDMA_QUEUE_LENGTH];
252 typedef struct mvSataAdapter
254 /* Fields set by Intermediate Application Layer */
257 MV_U8 pciConfigRevisionId;
258 MV_U16 pciConfigDeviceId;
260 MV_BUS_ADDR_T adapterIoBaseAddress;
261 MV_U32 intCoalThre[MV_SATA_UNITS_NUM];
262 MV_U32 intTimeThre[MV_SATA_UNITS_NUM];
263 MV_BOOLEAN (* HPTLIBAPI mvSataEventNotify)(struct mvSataAdapter *,
266 MV_SATA_CHANNEL *sataChannel[MV_SATA_CHANNELS_NUM];
269 MV_U32 pciInterruptMask;
271 /* Fields set by CORE driver */
272 MV_OS_SEMAPHORE semaphore;
274 MV_OS_SEMAPHORE interruptsMaskSem;
275 MV_BOOLEAN implementA0Workarounds;
276 MV_BOOLEAN implement50XXB0Workarounds;
277 MV_BOOLEAN implement50XXB1Workarounds;
278 MV_BOOLEAN implement50XXB2Workarounds;
279 MV_BOOLEAN implement60X1A0Workarounds;
280 MV_BOOLEAN implement60X1A1Workarounds;
281 MV_BOOLEAN implement60X1B0Workarounds;
282 MV_U8 sataAdapterGeneration;
284 MV_U8 signalAmps[MV_SATA_CHANNELS_NUM];
285 MV_U8 pre[MV_SATA_CHANNELS_NUM];
286 MV_BOOLEAN staggaredSpinup[MV_SATA_CHANNELS_NUM]; /* For 60x1 only */
289 typedef struct mvSataAdapterStatus
291 /* Fields set by CORE driver */
292 MV_BOOLEAN channelConnected[MV_SATA_CHANNELS_NUM];
293 MV_U32 pciDLLStatusAndControlRegister;
294 MV_U32 pciCommandRegister;
295 MV_U32 pciModeRegister;
296 MV_U32 pciSERRMaskRegister;
297 MV_U32 intCoalThre[MV_SATA_UNITS_NUM];
298 MV_U32 intTimeThre[MV_SATA_UNITS_NUM];
299 MV_U32 R00StatusBridgePortRegister[MV_SATA_CHANNELS_NUM];
300 }MV_SATA_ADAPTER_STATUS;
303 typedef struct mvSataChannelStatus
305 /* Fields set by CORE driver */
306 MV_BOOLEAN isConnected;
307 MV_U8 modelNumber[MV_ATA_MODEL_NUMBER_LEN];
308 MV_BOOLEAN DMAEnabled;
309 MV_EDMA_MODE queuedDMA;
310 MV_U8 outstandingCommands;
311 MV_U32 EdmaConfigurationRegister;
312 MV_U32 EdmaRequestQueueBaseAddressHighRegister;
313 MV_U32 EdmaRequestQueueInPointerRegister;
314 MV_U32 EdmaRequestQueueOutPointerRegister;
315 MV_U32 EdmaResponseQueueBaseAddressHighRegister;
316 MV_U32 EdmaResponseQueueInPointerRegister;
317 MV_U32 EdmaResponseQueueOutPointerRegister;
318 MV_U32 EdmaCommandRegister;
319 MV_U32 PHYModeRegister;
320 }MV_SATA_CHANNEL_STATUS;
322 /* this structure used by the IAL defines the PRD entries used by the EDMA HW */
323 typedef struct mvSataEdmaPRDEntry
325 volatile MV_U32 lowBaseAddr;
326 volatile MV_U16 byteCount;
327 volatile MV_U16 flags;
328 volatile MV_U32 highBaseAddr;
329 volatile MV_U32 reserved;
330 }MV_SATA_EDMA_PRD_ENTRY;
334 /* CORE driver Adapter Management */
335 MV_BOOLEAN HPTLIBAPI mvSataInitAdapter(MV_SATA_ADAPTER *pAdapter);
337 MV_BOOLEAN HPTLIBAPI mvSataShutdownAdapter(MV_SATA_ADAPTER *pAdapter);
339 MV_BOOLEAN HPTLIBAPI mvSataGetAdapterStatus(MV_SATA_ADAPTER *pAdapter,
340 MV_SATA_ADAPTER_STATUS *pAdapterStatus);
342 MV_U32 HPTLIBAPI mvSataReadReg(MV_SATA_ADAPTER *pAdapter, MV_U32 regOffset);
344 MV_VOID HPTLIBAPI mvSataWriteReg(MV_SATA_ADAPTER *pAdapter, MV_U32 regOffset,
347 MV_VOID HPTLIBAPI mvEnableAutoFlush(MV_VOID);
348 MV_VOID HPTLIBAPI mvDisableAutoFlush(MV_VOID);
351 /* CORE driver SATA Channel Management */
352 MV_BOOLEAN HPTLIBAPI mvSataConfigureChannel(MV_SATA_ADAPTER *pAdapter,
355 MV_BOOLEAN HPTLIBAPI mvSataRemoveChannel(MV_SATA_ADAPTER *pAdapter, MV_U8 channelIndex);
357 MV_BOOLEAN HPTLIBAPI mvSataIsStorageDeviceConnected(MV_SATA_ADAPTER *pAdapter,
360 MV_BOOLEAN HPTLIBAPI mvSataChannelHardReset(MV_SATA_ADAPTER *pAdapter,
363 MV_BOOLEAN HPTLIBAPI mvSataConfigEdmaMode(MV_SATA_ADAPTER *pAdapter, MV_U8 channelIndex,
364 MV_EDMA_MODE eDmaMode, MV_U8 maxQueueDepth);
366 MV_BOOLEAN HPTLIBAPI mvSataEnableChannelDma(MV_SATA_ADAPTER *pAdapter,
369 MV_BOOLEAN HPTLIBAPI mvSataDisableChannelDma(MV_SATA_ADAPTER *pAdapter,
372 MV_BOOLEAN HPTLIBAPI mvSataFlushDmaQueue(MV_SATA_ADAPTER *pAdapter, MV_U8 channelIndex,
373 MV_FLUSH_TYPE flushType);
375 MV_U8 HPTLIBAPI mvSataNumOfDmaCommands(MV_SATA_ADAPTER *pAdapter, MV_U8 channelIndex);
377 MV_BOOLEAN HPTLIBAPI mvSataSetIntCoalParams (MV_SATA_ADAPTER *pAdapter, MV_U8 sataUnit,
378 MV_U32 intCoalThre, MV_U32 intTimeThre);
380 MV_BOOLEAN HPTLIBAPI mvSataSetChannelPhyParams(MV_SATA_ADAPTER *pAdapter,
382 MV_U8 signalAmps, MV_U8 pre);
384 MV_BOOLEAN HPTLIBAPI mvSataChannelPhyShutdown(MV_SATA_ADAPTER *pAdapter,
387 MV_BOOLEAN HPTLIBAPI mvSataChannelPhyPowerOn(MV_SATA_ADAPTER *pAdapter,
390 MV_BOOLEAN HPTLIBAPI mvSataChannelSetEdmaLoopBackMode(MV_SATA_ADAPTER *pAdapter,
392 MV_BOOLEAN loopBackOn);
394 MV_BOOLEAN HPTLIBAPI mvSataGetChannelStatus(MV_SATA_ADAPTER *pAdapter, MV_U8 channelIndex,
395 MV_SATA_CHANNEL_STATUS *pChannelStatus);
397 /* Execute UDMA ATA commands */
398 MV_EDMA_QUEUE_RESULT HPTLIBAPI mvSataQueueUDmaCommand(MV_SATA_ADAPTER *pAdapter,
400 MV_UDMA_TYPE readWrite,
406 mvSataCommandCompletionCallBack_t callBack,
407 MV_VOID_PTR commandId);
409 MV_QUEUE_COMMAND_RESULT HPTLIBAPI mvSataQueueCommand(MV_SATA_ADAPTER *pAdapter,
411 MV_QUEUE_COMMAND_INFO FAR *pCommandParams);
413 /* Interrupt Service Routine */
414 MV_BOOLEAN HPTLIBAPI mvSataInterruptServiceRoutine(MV_SATA_ADAPTER *pAdapter);
416 MV_BOOLEAN HPTLIBAPI mvSataMaskAdapterInterrupt(MV_SATA_ADAPTER *pAdapter);
418 MV_BOOLEAN HPTLIBAPI mvSataUnmaskAdapterInterrupt(MV_SATA_ADAPTER *pAdapter);
420 /* Command Completion and Event Notification (user implemented) */
421 MV_BOOLEAN HPTLIBAPI mvSataEventNotify(MV_SATA_ADAPTER *, MV_EVENT_TYPE ,
425 * Staggered spin-ip support and SATA interface speed control
426 * (relevant for 60x1 adapters)
428 MV_BOOLEAN HPTLIBAPI mvSataEnableStaggeredSpinUpAll (MV_SATA_ADAPTER *pAdapter);
429 MV_BOOLEAN HPTLIBAPI mvSataDisableStaggeredSpinUpAll (MV_SATA_ADAPTER *pAdapter);