sys/dev/hwpmc/hwpmc_amd.c

   1 /*-
   2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
   3  *
   4  * Copyright (c) 2003-2008 Joseph Koshy
   5  * Copyright (c) 2007 The FreeBSD Foundation
   6  * All rights reserved.
   7  *
   8  * Portions of this software were developed by A. Joseph Koshy under
   9  * sponsorship from the FreeBSD Foundation and Google, Inc.
  10  *
  11  * Redistribution and use in source and binary forms, with or without
  12  * modification, are permitted provided that the following conditions
  13  * are met:
  14  * 1. Redistributions of source code must retain the above copyright
  15  *    notice, this list of conditions and the following disclaimer.
  16  * 2. Redistributions in binary form must reproduce the above copyright
  17  *    notice, this list of conditions and the following disclaimer in the
  18  *    documentation and/or other materials provided with the distribution.
  19  *
  20  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  21  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  24  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  25  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  26  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  27  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  28  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  29  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  30  * SUCH DAMAGE.
  31  */
  32
  33 #include <sys/cdefs.h>
  34 __FBSDID("$FreeBSD$");
  35
  36 /* Support for the AMD K7 and later processors */
  37
  38 #include <sys/param.h>
  39 #include <sys/lock.h>
  40 #include <sys/malloc.h>
  41 #include <sys/mutex.h>
  42 #include <sys/pcpu.h>
  43 #include <sys/pmc.h>
  44 #include <sys/pmckern.h>
  45 #include <sys/smp.h>
  46 #include <sys/systm.h>
  47
  48 #include <machine/cpu.h>
  49 #include <machine/cpufunc.h>
  50 #include <machine/md_var.h>
  51 #include <machine/specialreg.h>
  52
  53 #ifdef  HWPMC_DEBUG
  54 enum pmc_class  amd_pmc_class;
  55 #endif
  56
  57 #define OVERFLOW_WAIT_COUNT     50
  58
  59 DPCPU_DEFINE_STATIC(uint32_t, nmi_counter);
  60
  61 /* AMD K7 & K8 PMCs */
  62 struct amd_descr {
  63         struct pmc_descr pm_descr;  /* "base class" */
  64         uint32_t        pm_evsel;   /* address of EVSEL register */
  65         uint32_t        pm_perfctr; /* address of PERFCTR register */
  66 };
  67
  68 static  struct amd_descr amd_pmcdesc[AMD_NPMCS] =
  69 {
  70     {
  71         .pm_descr =
  72         {
  73                 .pd_name  = "",
  74                 .pd_class = -1,
  75                 .pd_caps  = AMD_PMC_CAPS,
  76                 .pd_width = 48
  77         },
  78         .pm_evsel   = AMD_PMC_EVSEL_0,
  79         .pm_perfctr = AMD_PMC_PERFCTR_0
  80     },
  81     {
  82         .pm_descr =
  83         {
  84                 .pd_name  = "",
  85                 .pd_class = -1,
  86                 .pd_caps  = AMD_PMC_CAPS,
  87                 .pd_width = 48
  88         },
  89         .pm_evsel   = AMD_PMC_EVSEL_1,
  90         .pm_perfctr = AMD_PMC_PERFCTR_1
  91     },
  92     {
  93         .pm_descr =
  94         {
  95                 .pd_name  = "",
  96                 .pd_class = -1,
  97                 .pd_caps  = AMD_PMC_CAPS,
  98                 .pd_width = 48
  99         },
 100         .pm_evsel   = AMD_PMC_EVSEL_2,
 101         .pm_perfctr = AMD_PMC_PERFCTR_2
 102     },
 103     {
 104         .pm_descr =
 105         {
 106                 .pd_name  = "",
 107                 .pd_class = -1,
 108                 .pd_caps  = AMD_PMC_CAPS,
 109                 .pd_width = 48
 110         },
 111         .pm_evsel   = AMD_PMC_EVSEL_3,
 112         .pm_perfctr = AMD_PMC_PERFCTR_3
 113      },
 114     {
 115         .pm_descr =
 116         {
 117                 .pd_name  = "",
 118                 .pd_class = -1,
 119                 .pd_caps  = AMD_PMC_CAPS,
 120                 .pd_width = 48
 121         },
 122         .pm_evsel   = AMD_PMC_EVSEL_4,
 123         .pm_perfctr = AMD_PMC_PERFCTR_4
 124     },
 125     {
 126         .pm_descr =
 127         {
 128                 .pd_name  = "",
 129                 .pd_class = -1,
 130                 .pd_caps  = AMD_PMC_CAPS,
 131                 .pd_width = 48
 132         },
 133         .pm_evsel   = AMD_PMC_EVSEL_5,
 134         .pm_perfctr = AMD_PMC_PERFCTR_5
 135     },
 136     {
 137         .pm_descr =
 138         {
 139                 .pd_name  = "",
 140                 .pd_class = -1,
 141                 .pd_caps  = AMD_PMC_CAPS,
 142                 .pd_width = 48
 143         },
 144         .pm_evsel   = AMD_PMC_EVSEL_EP_L3_0,
 145         .pm_perfctr = AMD_PMC_PERFCTR_EP_L3_0
 146     },
 147     {
 148         .pm_descr =
 149         {
 150                 .pd_name  = "",
 151                 .pd_class = -1,
 152                 .pd_caps  = AMD_PMC_CAPS,
 153                 .pd_width = 48
 154         },
 155         .pm_evsel   = AMD_PMC_EVSEL_EP_L3_1,
 156         .pm_perfctr = AMD_PMC_PERFCTR_EP_L3_1
 157     },
 158     {
 159         .pm_descr =
 160         {
 161                 .pd_name  = "",
 162                 .pd_class = -1,
 163                 .pd_caps  = AMD_PMC_CAPS,
 164                 .pd_width = 48
 165         },
 166         .pm_evsel   = AMD_PMC_EVSEL_EP_L3_2,
 167         .pm_perfctr = AMD_PMC_PERFCTR_EP_L3_2
 168     },
 169     {
 170         .pm_descr =
 171         {
 172                 .pd_name  = "",
 173                 .pd_class = -1,
 174                 .pd_caps  = AMD_PMC_CAPS,
 175                 .pd_width = 48
 176         },
 177         .pm_evsel   = AMD_PMC_EVSEL_EP_L3_3,
 178         .pm_perfctr = AMD_PMC_PERFCTR_EP_L3_3
 179     },
 180     {
 181         .pm_descr =
 182         {
 183                 .pd_name  = "",
 184                 .pd_class = -1,
 185                 .pd_caps  = AMD_PMC_CAPS,
 186                 .pd_width = 48
 187         },
 188         .pm_evsel   = AMD_PMC_EVSEL_EP_L3_4,
 189         .pm_perfctr = AMD_PMC_PERFCTR_EP_L3_4
 190     },
 191     {
 192         .pm_descr =
 193         {
 194                 .pd_name  = "",
 195                 .pd_class = -1,
 196                 .pd_caps  = AMD_PMC_CAPS,
 197                 .pd_width = 48
 198         },
 199         .pm_evsel   = AMD_PMC_EVSEL_EP_L3_5,
 200         .pm_perfctr = AMD_PMC_PERFCTR_EP_L3_5
 201     },
 202     {
 203         .pm_descr =
 204         {
 205                 .pd_name  = "",
 206                 .pd_class = -1,
 207                 .pd_caps  = AMD_PMC_CAPS,
 208                 .pd_width = 48
 209         },
 210         .pm_evsel   = AMD_PMC_EVSEL_EP_DF_0,
 211         .pm_perfctr = AMD_PMC_PERFCTR_EP_DF_0
 212     },
 213     {
 214         .pm_descr =
 215         {
 216                 .pd_name  = "",
 217                 .pd_class = -1,
 218                 .pd_caps  = AMD_PMC_CAPS,
 219                 .pd_width = 48
 220         },
 221         .pm_evsel   = AMD_PMC_EVSEL_EP_DF_1,
 222         .pm_perfctr = AMD_PMC_PERFCTR_EP_DF_1
 223     },
 224     {
 225         .pm_descr =
 226         {
 227                 .pd_name  = "",
 228                 .pd_class = -1,
 229                 .pd_caps  = AMD_PMC_CAPS,
 230                 .pd_width = 48
 231         },
 232         .pm_evsel   = AMD_PMC_EVSEL_EP_DF_2,
 233         .pm_perfctr = AMD_PMC_PERFCTR_EP_DF_2
 234     },
 235     {
 236         .pm_descr =
 237         {
 238                 .pd_name  = "",
 239                 .pd_class = -1,
 240                 .pd_caps  = AMD_PMC_CAPS,
 241                 .pd_width = 48
 242         },
 243         .pm_evsel   = AMD_PMC_EVSEL_EP_DF_3,
 244         .pm_perfctr = AMD_PMC_PERFCTR_EP_DF_3
 245      }
 246 };
 247
 248 struct amd_event_code_map {
 249         enum pmc_event  pe_ev;   /* enum value */
 250         uint16_t        pe_code; /* encoded event mask */
 251         uint8_t         pe_mask; /* bits allowed in unit mask */
 252 };
 253
 254 const struct amd_event_code_map amd_event_codes[] = {
 255 #if     defined(__i386__)       /* 32 bit Athlon (K7) only */
 256         { PMC_EV_K7_DC_ACCESSES,                0x40, 0 },
 257         { PMC_EV_K7_DC_MISSES,                  0x41, 0 },
 258         { PMC_EV_K7_DC_REFILLS_FROM_L2,         0x42, AMD_PMC_UNITMASK_MOESI },
 259         { PMC_EV_K7_DC_REFILLS_FROM_SYSTEM,     0x43, AMD_PMC_UNITMASK_MOESI },
 260         { PMC_EV_K7_DC_WRITEBACKS,              0x44, AMD_PMC_UNITMASK_MOESI },
 261         { PMC_EV_K7_L1_DTLB_MISS_AND_L2_DTLB_HITS, 0x45, 0 },
 262         { PMC_EV_K7_L1_AND_L2_DTLB_MISSES,      0x46, 0 },
 263         { PMC_EV_K7_MISALIGNED_REFERENCES,      0x47, 0 },
 264
 265         { PMC_EV_K7_IC_FETCHES,                 0x80, 0 },
 266         { PMC_EV_K7_IC_MISSES,                  0x81, 0 },
 267
 268         { PMC_EV_K7_L1_ITLB_MISSES,             0x84, 0 },
 269         { PMC_EV_K7_L1_L2_ITLB_MISSES,          0x85, 0 },
 270
 271         { PMC_EV_K7_RETIRED_INSTRUCTIONS,       0xC0, 0 },
 272         { PMC_EV_K7_RETIRED_OPS,                0xC1, 0 },
 273         { PMC_EV_K7_RETIRED_BRANCHES,           0xC2, 0 },
 274         { PMC_EV_K7_RETIRED_BRANCHES_MISPREDICTED, 0xC3, 0 },
 275         { PMC_EV_K7_RETIRED_TAKEN_BRANCHES,     0xC4, 0 },
 276         { PMC_EV_K7_RETIRED_TAKEN_BRANCHES_MISPREDICTED, 0xC5, 0 },
 277         { PMC_EV_K7_RETIRED_FAR_CONTROL_TRANSFERS, 0xC6, 0 },
 278         { PMC_EV_K7_RETIRED_RESYNC_BRANCHES,    0xC7, 0 },
 279         { PMC_EV_K7_INTERRUPTS_MASKED_CYCLES,   0xCD, 0 },
 280         { PMC_EV_K7_INTERRUPTS_MASKED_WHILE_PENDING_CYCLES, 0xCE, 0 },
 281         { PMC_EV_K7_HARDWARE_INTERRUPTS,        0xCF, 0 },
 282 #endif
 283
 284         { PMC_EV_K8_FP_DISPATCHED_FPU_OPS,              0x00, 0x3F },
 285         { PMC_EV_K8_FP_CYCLES_WITH_NO_FPU_OPS_RETIRED,  0x01, 0x00 },
 286         { PMC_EV_K8_FP_DISPATCHED_FPU_FAST_FLAG_OPS,    0x02, 0x00 },
 287
 288         { PMC_EV_K8_LS_SEGMENT_REGISTER_LOAD,           0x20, 0x7F },
 289         { PMC_EV_K8_LS_MICROARCHITECTURAL_RESYNC_BY_SELF_MODIFYING_CODE,
 290                                                         0x21, 0x00 },
 291         { PMC_EV_K8_LS_MICROARCHITECTURAL_RESYNC_BY_SNOOP, 0x22, 0x00 },
 292         { PMC_EV_K8_LS_BUFFER2_FULL,                    0x23, 0x00 },
 293         { PMC_EV_K8_LS_LOCKED_OPERATION,                0x24, 0x07 },
 294         { PMC_EV_K8_LS_MICROARCHITECTURAL_LATE_CANCEL,  0x25, 0x00 },
 295         { PMC_EV_K8_LS_RETIRED_CFLUSH_INSTRUCTIONS,     0x26, 0x00 },
 296         { PMC_EV_K8_LS_RETIRED_CPUID_INSTRUCTIONS,      0x27, 0x00 },
 297
 298         { PMC_EV_K8_DC_ACCESS,                          0x40, 0x00 },
 299         { PMC_EV_K8_DC_MISS,                            0x41, 0x00 },
 300         { PMC_EV_K8_DC_REFILL_FROM_L2,                  0x42, 0x1F },
 301         { PMC_EV_K8_DC_REFILL_FROM_SYSTEM,              0x43, 0x1F },
 302         { PMC_EV_K8_DC_COPYBACK,                        0x44, 0x1F },
 303         { PMC_EV_K8_DC_L1_DTLB_MISS_AND_L2_DTLB_HIT,    0x45, 0x00 },
 304         { PMC_EV_K8_DC_L1_DTLB_MISS_AND_L2_DTLB_MISS,   0x46, 0x00 },
 305         { PMC_EV_K8_DC_MISALIGNED_DATA_REFERENCE,       0x47, 0x00 },
 306         { PMC_EV_K8_DC_MICROARCHITECTURAL_LATE_CANCEL,  0x48, 0x00 },
 307         { PMC_EV_K8_DC_MICROARCHITECTURAL_EARLY_CANCEL, 0x49, 0x00 },
 308         { PMC_EV_K8_DC_ONE_BIT_ECC_ERROR,               0x4A, 0x03 },
 309         { PMC_EV_K8_DC_DISPATCHED_PREFETCH_INSTRUCTIONS, 0x4B, 0x07 },
 310         { PMC_EV_K8_DC_DCACHE_ACCESSES_BY_LOCKS,        0x4C, 0x03 },
 311
 312         { PMC_EV_K8_BU_CPU_CLK_UNHALTED,                0x76, 0x00 },
 313         { PMC_EV_K8_BU_INTERNAL_L2_REQUEST,             0x7D, 0x1F },
 314         { PMC_EV_K8_BU_FILL_REQUEST_L2_MISS,            0x7E, 0x07 },
 315         { PMC_EV_K8_BU_FILL_INTO_L2,                    0x7F, 0x03 },
 316
 317         { PMC_EV_K8_IC_FETCH,                           0x80, 0x00 },
 318         { PMC_EV_K8_IC_MISS,                            0x81, 0x00 },
 319         { PMC_EV_K8_IC_REFILL_FROM_L2,                  0x82, 0x00 },
 320         { PMC_EV_K8_IC_REFILL_FROM_SYSTEM,              0x83, 0x00 },
 321         { PMC_EV_K8_IC_L1_ITLB_MISS_AND_L2_ITLB_HIT,    0x84, 0x00 },
 322         { PMC_EV_K8_IC_L1_ITLB_MISS_AND_L2_ITLB_MISS,   0x85, 0x00 },
 323         { PMC_EV_K8_IC_MICROARCHITECTURAL_RESYNC_BY_SNOOP, 0x86, 0x00 },
 324         { PMC_EV_K8_IC_INSTRUCTION_FETCH_STALL,         0x87, 0x00 },
 325         { PMC_EV_K8_IC_RETURN_STACK_HIT,                0x88, 0x00 },
 326         { PMC_EV_K8_IC_RETURN_STACK_OVERFLOW,           0x89, 0x00 },
 327
 328         { PMC_EV_K8_FR_RETIRED_X86_INSTRUCTIONS,        0xC0, 0x00 },
 329         { PMC_EV_K8_FR_RETIRED_UOPS,                    0xC1, 0x00 },
 330         { PMC_EV_K8_FR_RETIRED_BRANCHES,                0xC2, 0x00 },
 331         { PMC_EV_K8_FR_RETIRED_BRANCHES_MISPREDICTED,   0xC3, 0x00 },
 332         { PMC_EV_K8_FR_RETIRED_TAKEN_BRANCHES,          0xC4, 0x00 },
 333         { PMC_EV_K8_FR_RETIRED_TAKEN_BRANCHES_MISPREDICTED, 0xC5, 0x00 },
 334         { PMC_EV_K8_FR_RETIRED_FAR_CONTROL_TRANSFERS,   0xC6, 0x00 },
 335         { PMC_EV_K8_FR_RETIRED_RESYNCS,                 0xC7, 0x00 },
 336         { PMC_EV_K8_FR_RETIRED_NEAR_RETURNS,            0xC8, 0x00 },
 337         { PMC_EV_K8_FR_RETIRED_NEAR_RETURNS_MISPREDICTED, 0xC9, 0x00 },
 338         { PMC_EV_K8_FR_RETIRED_TAKEN_BRANCHES_MISPREDICTED_BY_ADDR_MISCOMPARE,
 339                                                         0xCA, 0x00 },
 340         { PMC_EV_K8_FR_RETIRED_FPU_INSTRUCTIONS,        0xCB, 0x0F },
 341         { PMC_EV_K8_FR_RETIRED_FASTPATH_DOUBLE_OP_INSTRUCTIONS,
 342                                                         0xCC, 0x07 },
 343         { PMC_EV_K8_FR_INTERRUPTS_MASKED_CYCLES,        0xCD, 0x00 },
 344         { PMC_EV_K8_FR_INTERRUPTS_MASKED_WHILE_PENDING_CYCLES, 0xCE, 0x00 },
 345         { PMC_EV_K8_FR_TAKEN_HARDWARE_INTERRUPTS,       0xCF, 0x00 },
 346
 347         { PMC_EV_K8_FR_DECODER_EMPTY,                   0xD0, 0x00 },
 348         { PMC_EV_K8_FR_DISPATCH_STALLS,                 0xD1, 0x00 },
 349         { PMC_EV_K8_FR_DISPATCH_STALL_FROM_BRANCH_ABORT_TO_RETIRE,
 350                                                         0xD2, 0x00 },
 351         { PMC_EV_K8_FR_DISPATCH_STALL_FOR_SERIALIZATION, 0xD3, 0x00 },
 352         { PMC_EV_K8_FR_DISPATCH_STALL_FOR_SEGMENT_LOAD, 0xD4, 0x00 },
 353         { PMC_EV_K8_FR_DISPATCH_STALL_WHEN_REORDER_BUFFER_IS_FULL,
 354                                                         0xD5, 0x00 },
 355         { PMC_EV_K8_FR_DISPATCH_STALL_WHEN_RESERVATION_STATIONS_ARE_FULL,
 356                                                         0xD6, 0x00 },
 357         { PMC_EV_K8_FR_DISPATCH_STALL_WHEN_FPU_IS_FULL, 0xD7, 0x00 },
 358         { PMC_EV_K8_FR_DISPATCH_STALL_WHEN_LS_IS_FULL,  0xD8, 0x00 },
 359         { PMC_EV_K8_FR_DISPATCH_STALL_WHEN_WAITING_FOR_ALL_TO_BE_QUIET,
 360                                                         0xD9, 0x00 },
 361         { PMC_EV_K8_FR_DISPATCH_STALL_WHEN_FAR_XFER_OR_RESYNC_BRANCH_PENDING,
 362                                                         0xDA, 0x00 },
 363         { PMC_EV_K8_FR_FPU_EXCEPTIONS,                  0xDB, 0x0F },
 364         { PMC_EV_K8_FR_NUMBER_OF_BREAKPOINTS_FOR_DR0,   0xDC, 0x00 },
 365         { PMC_EV_K8_FR_NUMBER_OF_BREAKPOINTS_FOR_DR1,   0xDD, 0x00 },
 366         { PMC_EV_K8_FR_NUMBER_OF_BREAKPOINTS_FOR_DR2,   0xDE, 0x00 },
 367         { PMC_EV_K8_FR_NUMBER_OF_BREAKPOINTS_FOR_DR3,   0xDF, 0x00 },
 368
 369         { PMC_EV_K8_NB_MEMORY_CONTROLLER_PAGE_ACCESS_EVENT, 0xE0, 0x7 },
 370         { PMC_EV_K8_NB_MEMORY_CONTROLLER_PAGE_TABLE_OVERFLOW, 0xE1, 0x00 },
 371         { PMC_EV_K8_NB_MEMORY_CONTROLLER_DRAM_COMMAND_SLOTS_MISSED,
 372                                                         0xE2, 0x00 },
 373         { PMC_EV_K8_NB_MEMORY_CONTROLLER_TURNAROUND,    0xE3, 0x07 },
 374         { PMC_EV_K8_NB_MEMORY_CONTROLLER_BYPASS_SATURATION, 0xE4, 0x0F },
 375         { PMC_EV_K8_NB_SIZED_COMMANDS,                  0xEB, 0x7F },
 376         { PMC_EV_K8_NB_PROBE_RESULT,                    0xEC, 0x0F },
 377         { PMC_EV_K8_NB_HT_BUS0_BANDWIDTH,               0xF6, 0x0F },
 378         { PMC_EV_K8_NB_HT_BUS1_BANDWIDTH,               0xF7, 0x0F },
 379         { PMC_EV_K8_NB_HT_BUS2_BANDWIDTH,               0xF8, 0x0F }
 380
 381 };
 382
 383 const int amd_event_codes_size = nitems(amd_event_codes);
 384
 385 /*
 386  * Per-processor information
 387  */
 388
 389 struct amd_cpu {
 390         struct pmc_hw   pc_amdpmcs[AMD_NPMCS];
 391 };
 392
 393 static struct amd_cpu **amd_pcpu;
 394
 395 /*
 396  * read a pmc register
 397  */
 398
 399 static int
 400 amd_read_pmc(int cpu, int ri, pmc_value_t *v)
 401 {
 402         enum pmc_mode mode;
 403         const struct amd_descr *pd;
 404         struct pmc *pm;
 405         pmc_value_t tmp;
 406
 407         KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
 408             ("[amd,%d] illegal CPU value %d", __LINE__, cpu));
 409         KASSERT(ri >= 0 && ri < AMD_NPMCS,
 410             ("[amd,%d] illegal row-index %d", __LINE__, ri));
 411         KASSERT(amd_pcpu[cpu],
 412             ("[amd,%d] null per-cpu, cpu %d", __LINE__, cpu));
 413
 414         pm = amd_pcpu[cpu]->pc_amdpmcs[ri].phw_pmc;
 415         pd = &amd_pmcdesc[ri];
 416
 417         KASSERT(pm != NULL,
 418             ("[amd,%d] No owner for HWPMC [cpu%d,pmc%d]", __LINE__,
 419                 cpu, ri));
 420
 421         mode = PMC_TO_MODE(pm);
 422
 423         PMCDBG2(MDP,REA,1,"amd-read id=%d class=%d", ri, pd->pm_descr.pd_class);
 424
 425 #ifdef  HWPMC_DEBUG
 426         KASSERT(pd->pm_descr.pd_class == amd_pmc_class,
 427             ("[amd,%d] unknown PMC class (%d)", __LINE__,
 428                 pd->pm_descr.pd_class));
 429 #endif
 430
 431         tmp = rdmsr(pd->pm_perfctr); /* RDMSR serializes */
 432         PMCDBG2(MDP,REA,2,"amd-read (pre-munge) id=%d -> %jd", ri, tmp);
 433         if (PMC_IS_SAMPLING_MODE(mode)) {
 434                 /* Sign extend 48 bit value to 64 bits. */
 435                 tmp = (pmc_value_t) (((int64_t) tmp << 16) >> 16);
 436                 tmp = AMD_PERFCTR_VALUE_TO_RELOAD_COUNT(tmp);
 437         }
 438         *v = tmp;
 439
 440         PMCDBG2(MDP,REA,2,"amd-read (post-munge) id=%d -> %jd", ri, *v);
 441
 442         return 0;
 443 }
 444
 445 /*
 446  * Write a PMC MSR.
 447  */
 448
 449 static int
 450 amd_write_pmc(int cpu, int ri, pmc_value_t v)
 451 {
 452         const struct amd_descr *pd;
 453         enum pmc_mode mode;
 454         struct pmc *pm;
 455
 456         KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
 457             ("[amd,%d] illegal CPU value %d", __LINE__, cpu));
 458         KASSERT(ri >= 0 && ri < AMD_NPMCS,
 459             ("[amd,%d] illegal row-index %d", __LINE__, ri));
 460
 461         pm = amd_pcpu[cpu]->pc_amdpmcs[ri].phw_pmc;
 462         pd = &amd_pmcdesc[ri];
 463
 464         KASSERT(pm != NULL,
 465             ("[amd,%d] PMC not owned (cpu%d,pmc%d)", __LINE__,
 466                 cpu, ri));
 467
 468         mode = PMC_TO_MODE(pm);
 469
 470 #ifdef  HWPMC_DEBUG
 471         KASSERT(pd->pm_descr.pd_class == amd_pmc_class,
 472             ("[amd,%d] unknown PMC class (%d)", __LINE__,
 473                 pd->pm_descr.pd_class));
 474 #endif
 475
 476         /* use 2's complement of the count for sampling mode PMCs */
 477         if (PMC_IS_SAMPLING_MODE(mode))
 478                 v = AMD_RELOAD_COUNT_TO_PERFCTR_VALUE(v);
 479
 480         PMCDBG3(MDP,WRI,1,"amd-write cpu=%d ri=%d v=%jx", cpu, ri, v);
 481
 482         /* write the PMC value */
 483         wrmsr(pd->pm_perfctr, v);
 484         return 0;
 485 }
 486
 487 /*
 488  * configure hardware pmc according to the configuration recorded in
 489  * pmc 'pm'.
 490  */
 491
 492 static int
 493 amd_config_pmc(int cpu, int ri, struct pmc *pm)
 494 {
 495         struct pmc_hw *phw;
 496
 497         PMCDBG3(MDP,CFG,1, "cpu=%d ri=%d pm=%p", cpu, ri, pm);
 498
 499         KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
 500             ("[amd,%d] illegal CPU value %d", __LINE__, cpu));
 501         KASSERT(ri >= 0 && ri < AMD_NPMCS,
 502             ("[amd,%d] illegal row-index %d", __LINE__, ri));
 503
 504         phw = &amd_pcpu[cpu]->pc_amdpmcs[ri];
 505
 506         KASSERT(pm == NULL || phw->phw_pmc == NULL,
 507             ("[amd,%d] pm=%p phw->pm=%p hwpmc not unconfigured",
 508                 __LINE__, pm, phw->phw_pmc));
 509
 510         phw->phw_pmc = pm;
 511         return 0;
 512 }
 513
 514 /*
 515  * Retrieve a configured PMC pointer from hardware state.
 516  */
 517
 518 static int
 519 amd_get_config(int cpu, int ri, struct pmc **ppm)
 520 {
 521         *ppm = amd_pcpu[cpu]->pc_amdpmcs[ri].phw_pmc;
 522
 523         return 0;
 524 }
 525
 526 /*
 527  * Machine dependent actions taken during the context switch in of a
 528  * thread.
 529  */
 530
 531 static int
 532 amd_switch_in(struct pmc_cpu *pc, struct pmc_process *pp)
 533 {
 534         (void) pc;
 535
 536         PMCDBG3(MDP,SWI,1, "pc=%p pp=%p enable-msr=%d", pc, pp,
 537             (pp->pp_flags & PMC_PP_ENABLE_MSR_ACCESS) != 0);
 538
 539         /* enable the RDPMC instruction if needed */
 540         if (pp->pp_flags & PMC_PP_ENABLE_MSR_ACCESS)
 541                 load_cr4(rcr4() | CR4_PCE);
 542
 543         return 0;
 544 }
 545
 546 /*
 547  * Machine dependent actions taken during the context switch out of a
 548  * thread.
 549  */
 550
 551 static int
 552 amd_switch_out(struct pmc_cpu *pc, struct pmc_process *pp)
 553 {
 554         (void) pc;
 555         (void) pp;              /* can be NULL */
 556
 557         PMCDBG3(MDP,SWO,1, "pc=%p pp=%p enable-msr=%d", pc, pp, pp ?
 558             (pp->pp_flags & PMC_PP_ENABLE_MSR_ACCESS) == 1 : 0);
 559
 560         /* always turn off the RDPMC instruction */
 561         load_cr4(rcr4() & ~CR4_PCE);
 562
 563         return 0;
 564 }
 565
 566 /*
 567  * Check if a given allocation is feasible.
 568  */
 569
 570 static int
 571 amd_allocate_pmc(int cpu, int ri, struct pmc *pm,
 572     const struct pmc_op_pmcallocate *a)
 573 {
 574         int i;
 575         uint64_t allowed_unitmask, caps, config, unitmask;
 576         enum pmc_event pe;
 577         const struct pmc_descr *pd;
 578
 579         (void) cpu;
 580
 581         KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
 582             ("[amd,%d] illegal CPU value %d", __LINE__, cpu));
 583         KASSERT(ri >= 0 && ri < AMD_NPMCS,
 584             ("[amd,%d] illegal row index %d", __LINE__, ri));
 585
 586         pd = &amd_pmcdesc[ri].pm_descr;
 587
 588         /* check class match */
 589         if (pd->pd_class != a->pm_class)
 590                 return EINVAL;
 591
 592         caps = pm->pm_caps;
 593
 594         PMCDBG2(MDP,ALL,1,"amd-allocate ri=%d caps=0x%x", ri, caps);
 595
 596         if((ri >= 0 && ri < 6) && !(a->pm_md.pm_amd.pm_amd_sub_class == PMC_AMD_SUB_CLASS_CORE))
 597                 return EINVAL;
 598         if((ri >= 6 && ri < 12) && !(a->pm_md.pm_amd.pm_amd_sub_class == PMC_AMD_SUB_CLASS_L3_CACHE))
 599                 return EINVAL;
 600         if((ri >= 12 && ri < 16) && !(a->pm_md.pm_amd.pm_amd_sub_class == PMC_AMD_SUB_CLASS_DATA_FABRIC))
 601                 return EINVAL;
 602
 603         if ((pd->pd_caps & caps) != caps)
 604                 return EPERM;
 605         if (strlen(pmc_cpuid) != 0) {
 606                 pm->pm_md.pm_amd.pm_amd_evsel =
 607                         a->pm_md.pm_amd.pm_amd_config;
 608                 PMCDBG2(MDP,ALL,2,"amd-allocate ri=%d -> config=0x%x", ri, a->pm_md.pm_amd.pm_amd_config);
 609                 return (0);
 610         }
 611
 612         pe = a->pm_ev;
 613
 614         /* map ev to the correct event mask code */
 615         config = allowed_unitmask = 0;
 616         for (i = 0; i < amd_event_codes_size; i++)
 617                 if (amd_event_codes[i].pe_ev == pe) {
 618                         config =
 619                             AMD_PMC_TO_EVENTMASK(amd_event_codes[i].pe_code);
 620                         allowed_unitmask =
 621                             AMD_PMC_TO_UNITMASK(amd_event_codes[i].pe_mask);
 622                         break;
 623                 }
 624         if (i == amd_event_codes_size)
 625                 return EINVAL;
 626
 627         unitmask = a->pm_md.pm_amd.pm_amd_config & AMD_PMC_UNITMASK;
 628         if (unitmask & ~allowed_unitmask) /* disallow reserved bits */
 629                 return EINVAL;
 630
 631         if (unitmask && (caps & PMC_CAP_QUALIFIER))
 632                 config |= unitmask;
 633
 634         if (caps & PMC_CAP_THRESHOLD)
 635                 config |= a->pm_md.pm_amd.pm_amd_config & AMD_PMC_COUNTERMASK;
 636
 637         /* set at least one of the 'usr' or 'os' caps */
 638         if (caps & PMC_CAP_USER)
 639                 config |= AMD_PMC_USR;
 640         if (caps & PMC_CAP_SYSTEM)
 641                 config |= AMD_PMC_OS;
 642         if ((caps & (PMC_CAP_USER|PMC_CAP_SYSTEM)) == 0)
 643                 config |= (AMD_PMC_USR|AMD_PMC_OS);
 644
 645         if (caps & PMC_CAP_EDGE)
 646                 config |= AMD_PMC_EDGE;
 647         if (caps & PMC_CAP_INVERT)
 648                 config |= AMD_PMC_INVERT;
 649         if (caps & PMC_CAP_INTERRUPT)
 650                 config |= AMD_PMC_INT;
 651
 652         pm->pm_md.pm_amd.pm_amd_evsel = config; /* save config value */
 653
 654         PMCDBG2(MDP,ALL,2,"amd-allocate ri=%d -> config=0x%x", ri, config);
 655
 656         return 0;
 657 }
 658
 659 /*
 660  * Release machine dependent state associated with a PMC.  This is a
 661  * no-op on this architecture.
 662  *
 663  */
 664
 665 /* ARGSUSED0 */
 666 static int
 667 amd_release_pmc(int cpu, int ri, struct pmc *pmc)
 668 {
 669 #ifdef  HWPMC_DEBUG
 670         const struct amd_descr *pd;
 671 #endif
 672         struct pmc_hw *phw;
 673
 674         (void) pmc;
 675
 676         KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
 677             ("[amd,%d] illegal CPU value %d", __LINE__, cpu));
 678         KASSERT(ri >= 0 && ri < AMD_NPMCS,
 679             ("[amd,%d] illegal row-index %d", __LINE__, ri));
 680
 681         phw = &amd_pcpu[cpu]->pc_amdpmcs[ri];
 682
 683         KASSERT(phw->phw_pmc == NULL,
 684             ("[amd,%d] PHW pmc %p non-NULL", __LINE__, phw->phw_pmc));
 685
 686 #ifdef  HWPMC_DEBUG
 687         pd = &amd_pmcdesc[ri];
 688         if (pd->pm_descr.pd_class == amd_pmc_class)
 689                 KASSERT(AMD_PMC_IS_STOPPED(pd->pm_evsel),
 690                     ("[amd,%d] PMC %d released while active", __LINE__, ri));
 691 #endif
 692
 693         return 0;
 694 }
 695
 696 /*
 697  * start a PMC.
 698  */
 699
 700 static int
 701 amd_start_pmc(int cpu, int ri)
 702 {
 703         uint64_t config;
 704         struct pmc *pm;
 705         struct pmc_hw *phw;
 706         const struct amd_descr *pd;
 707
 708         KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
 709             ("[amd,%d] illegal CPU value %d", __LINE__, cpu));
 710         KASSERT(ri >= 0 && ri < AMD_NPMCS,
 711             ("[amd,%d] illegal row-index %d", __LINE__, ri));
 712
 713         phw = &amd_pcpu[cpu]->pc_amdpmcs[ri];
 714         pm  = phw->phw_pmc;
 715         pd = &amd_pmcdesc[ri];
 716
 717         KASSERT(pm != NULL,
 718             ("[amd,%d] starting cpu%d,pmc%d with null pmc record", __LINE__,
 719                 cpu, ri));
 720
 721         PMCDBG2(MDP,STA,1,"amd-start cpu=%d ri=%d", cpu, ri);
 722
 723         KASSERT(AMD_PMC_IS_STOPPED(pd->pm_evsel),
 724             ("[amd,%d] pmc%d,cpu%d: Starting active PMC \"%s\"", __LINE__,
 725             ri, cpu, pd->pm_descr.pd_name));
 726
 727         /* turn on the PMC ENABLE bit */
 728         config = pm->pm_md.pm_amd.pm_amd_evsel | AMD_PMC_ENABLE;
 729
 730         PMCDBG1(MDP,STA,2,"amd-start config=0x%x", config);
 731
 732         wrmsr(pd->pm_evsel, config);
 733         return 0;
 734 }
 735
 736 /*
 737  * Stop a PMC.
 738  */
 739
 740 static int
 741 amd_stop_pmc(int cpu, int ri)
 742 {
 743         struct pmc *pm;
 744         struct pmc_hw *phw;
 745         const struct amd_descr *pd;
 746         uint64_t config;
 747         int i;
 748
 749         KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
 750             ("[amd,%d] illegal CPU value %d", __LINE__, cpu));
 751         KASSERT(ri >= 0 && ri < AMD_NPMCS,
 752             ("[amd,%d] illegal row-index %d", __LINE__, ri));
 753
 754         phw = &amd_pcpu[cpu]->pc_amdpmcs[ri];
 755         pm  = phw->phw_pmc;
 756         pd  = &amd_pmcdesc[ri];
 757
 758         KASSERT(pm != NULL,
 759             ("[amd,%d] cpu%d,pmc%d no PMC to stop", __LINE__,
 760                 cpu, ri));
 761         KASSERT(!AMD_PMC_IS_STOPPED(pd->pm_evsel),
 762             ("[amd,%d] PMC%d, CPU%d \"%s\" already stopped",
 763                 __LINE__, ri, cpu, pd->pm_descr.pd_name));
 764
 765         PMCDBG1(MDP,STO,1,"amd-stop ri=%d", ri);
 766
 767         /* turn off the PMC ENABLE bit */
 768         config = pm->pm_md.pm_amd.pm_amd_evsel & ~AMD_PMC_ENABLE;
 769         wrmsr(pd->pm_evsel, config);
 770
 771         /*
 772          * Due to NMI latency on newer AMD processors
 773          * NMI interrupts are ignored, which leads to
 774          * panic or messages based on kernel configuraiton
 775          */
 776
 777         /* Wait for the count to be reset */
 778         for (i = 0; i < OVERFLOW_WAIT_COUNT; i++) {
 779                 if (rdmsr(pd->pm_perfctr) & (1 << (pd->pm_descr.pd_width - 1)))
 780                         break;
 781
 782                 DELAY(1);
 783         }
 784
 785         return 0;
 786 }
 787
 788 /*
 789  * Interrupt handler.  This function needs to return '1' if the
 790  * interrupt was this CPU's PMCs or '0' otherwise.  It is not allowed
 791  * to sleep or do anything a 'fast' interrupt handler is not allowed
 792  * to do.
 793  */
 794
 795 static int
 796 amd_intr(struct trapframe *tf)
 797 {
 798         int i, error, retval, cpu;
 799         uint64_t config, evsel, perfctr;
 800         struct pmc *pm;
 801         struct amd_cpu *pac;
 802         pmc_value_t v;
 803         uint32_t active = 0, count = 0;
 804
 805         cpu = curcpu;
 806         KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
 807             ("[amd,%d] out of range CPU %d", __LINE__, cpu));
 808
 809         PMCDBG3(MDP,INT,1, "cpu=%d tf=%p um=%d", cpu, (void *) tf,
 810             TRAPF_USERMODE(tf));
 811
 812         retval = 0;
 813
 814         pac = amd_pcpu[cpu];
 815
 816         /*
 817          * look for all PMCs that have interrupted:
 818          * - look for a running, sampling PMC which has overflowed
 819          *   and which has a valid 'struct pmc' association
 820          *
 821          * If found, we call a helper to process the interrupt.
 822          *
 823          * PMCs interrupting at the same time are collapsed into
 824          * a single interrupt. Check all the valid pmcs for
 825          * overflow.
 826          */
 827
 828         for (i = 0; i < AMD_CORE_NPMCS; i++) {
 829
 830                 if ((pm = pac->pc_amdpmcs[i].phw_pmc) == NULL ||
 831                     !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) {
 832                         continue;
 833                 }
 834
 835                 /* Consider pmc with valid handle as active */
 836                 active++;
 837
 838                 if (!AMD_PMC_HAS_OVERFLOWED(i))
 839                         continue;
 840
 841                 retval = 1;     /* Found an interrupting PMC. */
 842
 843                 if (pm->pm_state != PMC_STATE_RUNNING)
 844                         continue;
 845
 846                 /* Stop the PMC, reload count. */
 847                 evsel   = amd_pmcdesc[i].pm_evsel;
 848                 perfctr = amd_pmcdesc[i].pm_perfctr;
 849                 v       = pm->pm_sc.pm_reloadcount;
 850                 config  = rdmsr(evsel);
 851
 852                 KASSERT((config & ~AMD_PMC_ENABLE) ==
 853                     (pm->pm_md.pm_amd.pm_amd_evsel & ~AMD_PMC_ENABLE),
 854                     ("[amd,%d] config mismatch reg=0x%jx pm=0x%jx", __LINE__,
 855                          (uintmax_t)config, (uintmax_t)pm->pm_md.pm_amd.pm_amd_evsel));
 856
 857                 wrmsr(evsel, config & ~AMD_PMC_ENABLE);
 858                 wrmsr(perfctr, AMD_RELOAD_COUNT_TO_PERFCTR_VALUE(v));
 859
 860                 /* Restart the counter if logging succeeded. */
 861                 error = pmc_process_interrupt(PMC_HR, pm, tf);
 862                 if (error == 0)
 863                         wrmsr(evsel, config);
 864         }
 865
 866         /*
 867          * Due to NMI latency, there can be a scenario in which
 868          * multiple pmcs gets serviced in an earlier NMI and we
 869          * do not find an overflow in the subsequent NMI.
 870          *
 871          * For such cases we keep a per-cpu count of active NMIs
 872          * and compare it with min(active pmcs, 2) to determine
 873          * if this NMI was for a pmc overflow which was serviced
 874          * in an earlier request or should be ignored.
 875          */
 876
 877         if (retval) {
 878                 DPCPU_SET(nmi_counter, min(2, active));
 879         } else {
 880                 if ((count = DPCPU_GET(nmi_counter))) {
 881                         retval = 1;
 882                         DPCPU_SET(nmi_counter, --count);
 883                 }
 884         }
 885
 886         if (retval)
 887                 counter_u64_add(pmc_stats.pm_intr_processed, 1);
 888         else
 889                 counter_u64_add(pmc_stats.pm_intr_ignored, 1);
 890
 891         PMCDBG1(MDP,INT,2, "retval=%d", retval);
 892         return (retval);
 893 }
 894
 895 /*
 896  * describe a PMC
 897  */
 898 static int
 899 amd_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc)
 900 {
 901         int error;
 902         size_t copied;
 903         const struct amd_descr *pd;
 904         struct pmc_hw *phw;
 905
 906         KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
 907             ("[amd,%d] illegal CPU %d", __LINE__, cpu));
 908         KASSERT(ri >= 0 && ri < AMD_NPMCS,
 909             ("[amd,%d] row-index %d out of range", __LINE__, ri));
 910
 911         phw = &amd_pcpu[cpu]->pc_amdpmcs[ri];
 912         pd  = &amd_pmcdesc[ri];
 913
 914         if ((error = copystr(pd->pm_descr.pd_name, pi->pm_name,
 915                  PMC_NAME_MAX, &copied)) != 0)
 916                 return error;
 917
 918         pi->pm_class = pd->pm_descr.pd_class;
 919
 920         if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) {
 921                 pi->pm_enabled = TRUE;
 922                 *ppmc          = phw->phw_pmc;
 923         } else {
 924                 pi->pm_enabled = FALSE;
 925                 *ppmc          = NULL;
 926         }
 927
 928         return 0;
 929 }
 930
 931 /*
 932  * i386 specific entry points
 933  */
 934
 935 /*
 936  * return the MSR address of the given PMC.
 937  */
 938
 939 static int
 940 amd_get_msr(int ri, uint32_t *msr)
 941 {
 942         KASSERT(ri >= 0 && ri < AMD_NPMCS,
 943             ("[amd,%d] ri %d out of range", __LINE__, ri));
 944
 945         *msr = amd_pmcdesc[ri].pm_perfctr - AMD_PMC_PERFCTR_0;
 946
 947         return (0);
 948 }
 949
 950 /*
 951  * processor dependent initialization.
 952  */
 953
 954 static int
 955 amd_pcpu_init(struct pmc_mdep *md, int cpu)
 956 {
 957         int classindex, first_ri, n;
 958         struct pmc_cpu *pc;
 959         struct amd_cpu *pac;
 960         struct pmc_hw  *phw;
 961
 962         KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
 963             ("[amd,%d] insane cpu number %d", __LINE__, cpu));
 964
 965         PMCDBG1(MDP,INI,1,"amd-init cpu=%d", cpu);
 966
 967         amd_pcpu[cpu] = pac = malloc(sizeof(struct amd_cpu), M_PMC,
 968             M_WAITOK|M_ZERO);
 969
 970         /*
 971          * Set the content of the hardware descriptors to a known
 972          * state and initialize pointers in the MI per-cpu descriptor.
 973          */
 974         pc = pmc_pcpu[cpu];
 975 #if     defined(__amd64__)
 976         classindex = PMC_MDEP_CLASS_INDEX_K8;
 977 #elif   defined(__i386__)
 978         classindex = md->pmd_cputype == PMC_CPU_AMD_K8 ?
 979             PMC_MDEP_CLASS_INDEX_K8 : PMC_MDEP_CLASS_INDEX_K7;
 980 #endif
 981         first_ri = md->pmd_classdep[classindex].pcd_ri;
 982
 983         KASSERT(pc != NULL, ("[amd,%d] NULL per-cpu pointer", __LINE__));
 984
 985         for (n = 0, phw = pac->pc_amdpmcs; n < AMD_NPMCS; n++, phw++) {
 986                 phw->phw_state    = PMC_PHW_FLAG_IS_ENABLED |
 987                     PMC_PHW_CPU_TO_STATE(cpu) | PMC_PHW_INDEX_TO_STATE(n);
 988                 phw->phw_pmc      = NULL;
 989                 pc->pc_hwpmcs[n + first_ri]  = phw;
 990         }
 991
 992         return (0);
 993 }
 994
 995
 996 /*
 997  * processor dependent cleanup prior to the KLD
 998  * being unloaded
 999  */
1000
1001 static int
1002 amd_pcpu_fini(struct pmc_mdep *md, int cpu)
1003 {
1004         int classindex, first_ri, i;
1005         uint32_t evsel;
1006         struct pmc_cpu *pc;
1007         struct amd_cpu *pac;
1008
1009         KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
1010             ("[amd,%d] insane cpu number (%d)", __LINE__, cpu));
1011
1012         PMCDBG1(MDP,INI,1,"amd-cleanup cpu=%d", cpu);
1013
1014         /*
1015          * First, turn off all PMCs on this CPU.
1016          */
1017         for (i = 0; i < 4; i++) { /* XXX this loop is now not needed */
1018                 evsel = rdmsr(AMD_PMC_EVSEL_0 + i);
1019                 evsel &= ~AMD_PMC_ENABLE;
1020                 wrmsr(AMD_PMC_EVSEL_0 + i, evsel);
1021         }
1022
1023         /*
1024          * Next, free up allocated space.
1025          */
1026         if ((pac = amd_pcpu[cpu]) == NULL)
1027                 return (0);
1028
1029         amd_pcpu[cpu] = NULL;
1030
1031 #ifdef  HWPMC_DEBUG
1032         for (i = 0; i < AMD_NPMCS; i++) {
1033                 KASSERT(pac->pc_amdpmcs[i].phw_pmc == NULL,
1034                     ("[amd,%d] CPU%d/PMC%d in use", __LINE__, cpu, i));
1035                 KASSERT(AMD_PMC_IS_STOPPED(AMD_PMC_EVSEL_0 + i),
1036                     ("[amd,%d] CPU%d/PMC%d not stopped", __LINE__, cpu, i));
1037         }
1038 #endif
1039
1040         pc = pmc_pcpu[cpu];
1041         KASSERT(pc != NULL, ("[amd,%d] NULL per-cpu state", __LINE__));
1042
1043 #if     defined(__amd64__)
1044         classindex = PMC_MDEP_CLASS_INDEX_K8;
1045 #elif   defined(__i386__)
1046         classindex = md->pmd_cputype == PMC_CPU_AMD_K8 ? PMC_MDEP_CLASS_INDEX_K8 :
1047             PMC_MDEP_CLASS_INDEX_K7;
1048 #endif
1049         first_ri = md->pmd_classdep[classindex].pcd_ri;
1050
1051         /*
1052          * Reset pointers in the MI 'per-cpu' state.
1053          */
1054         for (i = 0; i < AMD_NPMCS; i++) {
1055                 pc->pc_hwpmcs[i + first_ri] = NULL;
1056         }
1057
1058
1059         free(pac, M_PMC);
1060
1061         return (0);
1062 }
1063
1064 /*
1065  * Initialize ourselves.
1066  */
1067
1068 struct pmc_mdep *
1069 pmc_amd_initialize(void)
1070 {
1071         int classindex, error, i, ncpus;
1072         struct pmc_classdep *pcd;
1073         enum pmc_cputype cputype;
1074         struct pmc_mdep *pmc_mdep;
1075         enum pmc_class class;
1076         int family, model, stepping;
1077         char *name;
1078
1079         /*
1080          * The presence of hardware performance counters on the AMD
1081          * Athlon, Duron or later processors, is _not_ indicated by
1082          * any of the processor feature flags set by the 'CPUID'
1083          * instruction, so we only check the 'instruction family'
1084          * field returned by CPUID for instruction family >= 6.
1085          */
1086
1087         name = NULL;
1088         family = CPUID_TO_FAMILY(cpu_id);
1089         model = CPUID_TO_MODEL(cpu_id);
1090         stepping = CPUID_TO_STEPPING(cpu_id);
1091
1092         if (family == 0x18)
1093                 snprintf(pmc_cpuid, sizeof(pmc_cpuid), "HygonGenuine-%d-%02X-%X",
1094                     family, model, stepping);
1095         else
1096                 snprintf(pmc_cpuid, sizeof(pmc_cpuid), "AuthenticAMD-%d-%02X-%X",
1097                     family, model, stepping);
1098
1099         switch (cpu_id & 0xF00) {
1100 #if     defined(__i386__)
1101         case 0x600:             /* Athlon(tm) processor */
1102                 classindex = PMC_MDEP_CLASS_INDEX_K7;
1103                 cputype = PMC_CPU_AMD_K7;
1104                 class = PMC_CLASS_K7;
1105                 name = "K7";
1106                 break;
1107 #endif
1108         case 0xF00:             /* Athlon64/Opteron processor */
1109                 classindex = PMC_MDEP_CLASS_INDEX_K8;
1110                 cputype = PMC_CPU_AMD_K8;
1111                 class = PMC_CLASS_K8;
1112                 name = "K8";
1113                 break;
1114
1115         default:
1116                 (void) printf("pmc: Unknown AMD CPU %x %d-%d.\n", cpu_id, (cpu_id & 0xF00) >> 8, model);
1117                 return NULL;
1118         }
1119
1120 #ifdef  HWPMC_DEBUG
1121         amd_pmc_class = class;
1122 #endif
1123
1124         /*
1125          * Allocate space for pointers to PMC HW descriptors and for
1126          * the MDEP structure used by MI code.
1127          */
1128         amd_pcpu = malloc(sizeof(struct amd_cpu *) * pmc_cpu_max(), M_PMC,
1129             M_WAITOK|M_ZERO);
1130
1131         /*
1132          * These processors have two classes of PMCs: the TSC and
1133          * programmable PMCs.
1134          */
1135         pmc_mdep = pmc_mdep_alloc(2);
1136
1137         pmc_mdep->pmd_cputype = cputype;
1138
1139         ncpus = pmc_cpu_max();
1140
1141         /* Initialize the TSC. */
1142         error = pmc_tsc_initialize(pmc_mdep, ncpus);
1143         if (error)
1144                 goto error;
1145
1146         /* Initialize AMD K7 and K8 PMC handling. */
1147         pcd = &pmc_mdep->pmd_classdep[classindex];
1148
1149         pcd->pcd_caps           = AMD_PMC_CAPS;
1150         pcd->pcd_class          = class;
1151         pcd->pcd_num            = AMD_NPMCS;
1152         pcd->pcd_ri             = pmc_mdep->pmd_npmc;
1153         pcd->pcd_width          = 48;
1154
1155         /* fill in the correct pmc name and class */
1156         for (i = 0; i < AMD_NPMCS; i++) {
1157                 (void) snprintf(amd_pmcdesc[i].pm_descr.pd_name,
1158                     sizeof(amd_pmcdesc[i].pm_descr.pd_name), "%s-%d",
1159                     name, i);
1160                 amd_pmcdesc[i].pm_descr.pd_class = class;
1161         }
1162
1163         pcd->pcd_allocate_pmc   = amd_allocate_pmc;
1164         pcd->pcd_config_pmc     = amd_config_pmc;
1165         pcd->pcd_describe       = amd_describe;
1166         pcd->pcd_get_config     = amd_get_config;
1167         pcd->pcd_get_msr        = amd_get_msr;
1168         pcd->pcd_pcpu_fini      = amd_pcpu_fini;
1169         pcd->pcd_pcpu_init      = amd_pcpu_init;
1170         pcd->pcd_read_pmc       = amd_read_pmc;
1171         pcd->pcd_release_pmc    = amd_release_pmc;
1172         pcd->pcd_start_pmc      = amd_start_pmc;
1173         pcd->pcd_stop_pmc       = amd_stop_pmc;
1174         pcd->pcd_write_pmc      = amd_write_pmc;
1175
1176         pmc_mdep->pmd_pcpu_init = NULL;
1177         pmc_mdep->pmd_pcpu_fini = NULL;
1178         pmc_mdep->pmd_intr      = amd_intr;
1179         pmc_mdep->pmd_switch_in = amd_switch_in;
1180         pmc_mdep->pmd_switch_out = amd_switch_out;
1181
1182         pmc_mdep->pmd_npmc     += AMD_NPMCS;
1183
1184         PMCDBG0(MDP,INI,0,"amd-initialize");
1185
1186         return (pmc_mdep);
1187
1188   error:
1189         if (error) {
1190                 free(pmc_mdep, M_PMC);
1191                 pmc_mdep = NULL;
1192         }
1193
1194         return (NULL);
1195 }
1196
1197 /*
1198  * Finalization code for AMD CPUs.
1199  */
1200
1201 void
1202 pmc_amd_finalize(struct pmc_mdep *md)
1203 {
1204 #if     defined(INVARIANTS)
1205         int classindex, i, ncpus, pmcclass;
1206 #endif
1207
1208         pmc_tsc_finalize(md);
1209
1210         KASSERT(amd_pcpu != NULL, ("[amd,%d] NULL per-cpu array pointer",
1211             __LINE__));
1212
1213 #if     defined(INVARIANTS)
1214         switch (md->pmd_cputype) {
1215 #if     defined(__i386__)
1216         case PMC_CPU_AMD_K7:
1217                 classindex = PMC_MDEP_CLASS_INDEX_K7;
1218                 pmcclass = PMC_CLASS_K7;
1219                 break;
1220 #endif
1221         default:
1222                 classindex = PMC_MDEP_CLASS_INDEX_K8;
1223                 pmcclass = PMC_CLASS_K8;
1224         }
1225
1226         KASSERT(md->pmd_classdep[classindex].pcd_class == pmcclass,
1227             ("[amd,%d] pmc class mismatch", __LINE__));
1228
1229         ncpus = pmc_cpu_max();
1230
1231         for (i = 0; i < ncpus; i++)
1232                 KASSERT(amd_pcpu[i] == NULL, ("[amd,%d] non-null pcpu",
1233                     __LINE__));
1234 #endif
1235
1236         free(amd_pcpu, M_PMC);
1237         amd_pcpu = NULL;
1238 }