2 * Copyright (c) 2003-2008 Joseph Koshy
3 * Copyright (c) 2007 The FreeBSD Foundation
6 * Portions of this software were developed by A. Joseph Koshy under
7 * sponsorship from the FreeBSD Foundation and Google, Inc.
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 #include <sys/cdefs.h>
33 __FBSDID("$FreeBSD$");
35 /* Support for the AMD K7 and later processors */
37 #include <sys/param.h>
39 #include <sys/malloc.h>
40 #include <sys/mutex.h>
42 #include <sys/pmckern.h>
44 #include <sys/systm.h>
46 #include <machine/cpu.h>
47 #include <machine/cpufunc.h>
48 #include <machine/md_var.h>
49 #include <machine/specialreg.h>
52 enum pmc_class amd_pmc_class;
55 /* AMD K7 & K8 PMCs */
57 struct pmc_descr pm_descr; /* "base class" */
58 uint32_t pm_evsel; /* address of EVSEL register */
59 uint32_t pm_perfctr; /* address of PERFCTR register */
62 static struct amd_descr amd_pmcdesc[AMD_NPMCS] =
68 .pd_class = PMC_CLASS_TSC,
69 .pd_caps = PMC_CAP_READ,
73 .pm_perfctr = 0 /* unused */
81 .pd_caps = AMD_PMC_CAPS,
84 .pm_evsel = AMD_PMC_EVSEL_0,
85 .pm_perfctr = AMD_PMC_PERFCTR_0
92 .pd_caps = AMD_PMC_CAPS,
95 .pm_evsel = AMD_PMC_EVSEL_1,
96 .pm_perfctr = AMD_PMC_PERFCTR_1
103 .pd_caps = AMD_PMC_CAPS,
106 .pm_evsel = AMD_PMC_EVSEL_2,
107 .pm_perfctr = AMD_PMC_PERFCTR_2
114 .pd_caps = AMD_PMC_CAPS,
117 .pm_evsel = AMD_PMC_EVSEL_3,
118 .pm_perfctr = AMD_PMC_PERFCTR_3
122 struct amd_event_code_map {
123 enum pmc_event pe_ev; /* enum value */
124 uint8_t pe_code; /* encoded event mask */
125 uint8_t pe_mask; /* bits allowed in unit mask */
128 const struct amd_event_code_map amd_event_codes[] = {
129 #if defined(__i386__) /* 32 bit Athlon (K7) only */
130 { PMC_EV_K7_DC_ACCESSES, 0x40, 0 },
131 { PMC_EV_K7_DC_MISSES, 0x41, 0 },
132 { PMC_EV_K7_DC_REFILLS_FROM_L2, 0x42, AMD_PMC_UNITMASK_MOESI },
133 { PMC_EV_K7_DC_REFILLS_FROM_SYSTEM, 0x43, AMD_PMC_UNITMASK_MOESI },
134 { PMC_EV_K7_DC_WRITEBACKS, 0x44, AMD_PMC_UNITMASK_MOESI },
135 { PMC_EV_K7_L1_DTLB_MISS_AND_L2_DTLB_HITS, 0x45, 0 },
136 { PMC_EV_K7_L1_AND_L2_DTLB_MISSES, 0x46, 0 },
137 { PMC_EV_K7_MISALIGNED_REFERENCES, 0x47, 0 },
139 { PMC_EV_K7_IC_FETCHES, 0x80, 0 },
140 { PMC_EV_K7_IC_MISSES, 0x81, 0 },
142 { PMC_EV_K7_L1_ITLB_MISSES, 0x84, 0 },
143 { PMC_EV_K7_L1_L2_ITLB_MISSES, 0x85, 0 },
145 { PMC_EV_K7_RETIRED_INSTRUCTIONS, 0xC0, 0 },
146 { PMC_EV_K7_RETIRED_OPS, 0xC1, 0 },
147 { PMC_EV_K7_RETIRED_BRANCHES, 0xC2, 0 },
148 { PMC_EV_K7_RETIRED_BRANCHES_MISPREDICTED, 0xC3, 0 },
149 { PMC_EV_K7_RETIRED_TAKEN_BRANCHES, 0xC4, 0 },
150 { PMC_EV_K7_RETIRED_TAKEN_BRANCHES_MISPREDICTED, 0xC5, 0 },
151 { PMC_EV_K7_RETIRED_FAR_CONTROL_TRANSFERS, 0xC6, 0 },
152 { PMC_EV_K7_RETIRED_RESYNC_BRANCHES, 0xC7, 0 },
153 { PMC_EV_K7_INTERRUPTS_MASKED_CYCLES, 0xCD, 0 },
154 { PMC_EV_K7_INTERRUPTS_MASKED_WHILE_PENDING_CYCLES, 0xCE, 0 },
155 { PMC_EV_K7_HARDWARE_INTERRUPTS, 0xCF, 0 },
158 { PMC_EV_K8_FP_DISPATCHED_FPU_OPS, 0x00, 0x3F },
159 { PMC_EV_K8_FP_CYCLES_WITH_NO_FPU_OPS_RETIRED, 0x01, 0x00 },
160 { PMC_EV_K8_FP_DISPATCHED_FPU_FAST_FLAG_OPS, 0x02, 0x00 },
162 { PMC_EV_K8_LS_SEGMENT_REGISTER_LOAD, 0x20, 0x7F },
163 { PMC_EV_K8_LS_MICROARCHITECTURAL_RESYNC_BY_SELF_MODIFYING_CODE,
165 { PMC_EV_K8_LS_MICROARCHITECTURAL_RESYNC_BY_SNOOP, 0x22, 0x00 },
166 { PMC_EV_K8_LS_BUFFER2_FULL, 0x23, 0x00 },
167 { PMC_EV_K8_LS_LOCKED_OPERATION, 0x24, 0x07 },
168 { PMC_EV_K8_LS_MICROARCHITECTURAL_LATE_CANCEL, 0x25, 0x00 },
169 { PMC_EV_K8_LS_RETIRED_CFLUSH_INSTRUCTIONS, 0x26, 0x00 },
170 { PMC_EV_K8_LS_RETIRED_CPUID_INSTRUCTIONS, 0x27, 0x00 },
172 { PMC_EV_K8_DC_ACCESS, 0x40, 0x00 },
173 { PMC_EV_K8_DC_MISS, 0x41, 0x00 },
174 { PMC_EV_K8_DC_REFILL_FROM_L2, 0x42, 0x1F },
175 { PMC_EV_K8_DC_REFILL_FROM_SYSTEM, 0x43, 0x1F },
176 { PMC_EV_K8_DC_COPYBACK, 0x44, 0x1F },
177 { PMC_EV_K8_DC_L1_DTLB_MISS_AND_L2_DTLB_HIT, 0x45, 0x00 },
178 { PMC_EV_K8_DC_L1_DTLB_MISS_AND_L2_DTLB_MISS, 0x46, 0x00 },
179 { PMC_EV_K8_DC_MISALIGNED_DATA_REFERENCE, 0x47, 0x00 },
180 { PMC_EV_K8_DC_MICROARCHITECTURAL_LATE_CANCEL, 0x48, 0x00 },
181 { PMC_EV_K8_DC_MICROARCHITECTURAL_EARLY_CANCEL, 0x49, 0x00 },
182 { PMC_EV_K8_DC_ONE_BIT_ECC_ERROR, 0x4A, 0x03 },
183 { PMC_EV_K8_DC_DISPATCHED_PREFETCH_INSTRUCTIONS, 0x4B, 0x07 },
184 { PMC_EV_K8_DC_DCACHE_ACCESSES_BY_LOCKS, 0x4C, 0x03 },
186 { PMC_EV_K8_BU_CPU_CLK_UNHALTED, 0x76, 0x00 },
187 { PMC_EV_K8_BU_INTERNAL_L2_REQUEST, 0x7D, 0x1F },
188 { PMC_EV_K8_BU_FILL_REQUEST_L2_MISS, 0x7E, 0x07 },
189 { PMC_EV_K8_BU_FILL_INTO_L2, 0x7F, 0x03 },
191 { PMC_EV_K8_IC_FETCH, 0x80, 0x00 },
192 { PMC_EV_K8_IC_MISS, 0x81, 0x00 },
193 { PMC_EV_K8_IC_REFILL_FROM_L2, 0x82, 0x00 },
194 { PMC_EV_K8_IC_REFILL_FROM_SYSTEM, 0x83, 0x00 },
195 { PMC_EV_K8_IC_L1_ITLB_MISS_AND_L2_ITLB_HIT, 0x84, 0x00 },
196 { PMC_EV_K8_IC_L1_ITLB_MISS_AND_L2_ITLB_MISS, 0x85, 0x00 },
197 { PMC_EV_K8_IC_MICROARCHITECTURAL_RESYNC_BY_SNOOP, 0x86, 0x00 },
198 { PMC_EV_K8_IC_INSTRUCTION_FETCH_STALL, 0x87, 0x00 },
199 { PMC_EV_K8_IC_RETURN_STACK_HIT, 0x88, 0x00 },
200 { PMC_EV_K8_IC_RETURN_STACK_OVERFLOW, 0x89, 0x00 },
202 { PMC_EV_K8_FR_RETIRED_X86_INSTRUCTIONS, 0xC0, 0x00 },
203 { PMC_EV_K8_FR_RETIRED_UOPS, 0xC1, 0x00 },
204 { PMC_EV_K8_FR_RETIRED_BRANCHES, 0xC2, 0x00 },
205 { PMC_EV_K8_FR_RETIRED_BRANCHES_MISPREDICTED, 0xC3, 0x00 },
206 { PMC_EV_K8_FR_RETIRED_TAKEN_BRANCHES, 0xC4, 0x00 },
207 { PMC_EV_K8_FR_RETIRED_TAKEN_BRANCHES_MISPREDICTED, 0xC5, 0x00 },
208 { PMC_EV_K8_FR_RETIRED_FAR_CONTROL_TRANSFERS, 0xC6, 0x00 },
209 { PMC_EV_K8_FR_RETIRED_RESYNCS, 0xC7, 0x00 },
210 { PMC_EV_K8_FR_RETIRED_NEAR_RETURNS, 0xC8, 0x00 },
211 { PMC_EV_K8_FR_RETIRED_NEAR_RETURNS_MISPREDICTED, 0xC9, 0x00 },
212 { PMC_EV_K8_FR_RETIRED_TAKEN_BRANCHES_MISPREDICTED_BY_ADDR_MISCOMPARE,
214 { PMC_EV_K8_FR_RETIRED_FPU_INSTRUCTIONS, 0xCB, 0x0F },
215 { PMC_EV_K8_FR_RETIRED_FASTPATH_DOUBLE_OP_INSTRUCTIONS,
217 { PMC_EV_K8_FR_INTERRUPTS_MASKED_CYCLES, 0xCD, 0x00 },
218 { PMC_EV_K8_FR_INTERRUPTS_MASKED_WHILE_PENDING_CYCLES, 0xCE, 0x00 },
219 { PMC_EV_K8_FR_TAKEN_HARDWARE_INTERRUPTS, 0xCF, 0x00 },
221 { PMC_EV_K8_FR_DECODER_EMPTY, 0xD0, 0x00 },
222 { PMC_EV_K8_FR_DISPATCH_STALLS, 0xD1, 0x00 },
223 { PMC_EV_K8_FR_DISPATCH_STALL_FROM_BRANCH_ABORT_TO_RETIRE,
225 { PMC_EV_K8_FR_DISPATCH_STALL_FOR_SERIALIZATION, 0xD3, 0x00 },
226 { PMC_EV_K8_FR_DISPATCH_STALL_FOR_SEGMENT_LOAD, 0xD4, 0x00 },
227 { PMC_EV_K8_FR_DISPATCH_STALL_WHEN_REORDER_BUFFER_IS_FULL,
229 { PMC_EV_K8_FR_DISPATCH_STALL_WHEN_RESERVATION_STATIONS_ARE_FULL,
231 { PMC_EV_K8_FR_DISPATCH_STALL_WHEN_FPU_IS_FULL, 0xD7, 0x00 },
232 { PMC_EV_K8_FR_DISPATCH_STALL_WHEN_LS_IS_FULL, 0xD8, 0x00 },
233 { PMC_EV_K8_FR_DISPATCH_STALL_WHEN_WAITING_FOR_ALL_TO_BE_QUIET,
235 { PMC_EV_K8_FR_DISPATCH_STALL_WHEN_FAR_XFER_OR_RESYNC_BRANCH_PENDING,
237 { PMC_EV_K8_FR_FPU_EXCEPTIONS, 0xDB, 0x0F },
238 { PMC_EV_K8_FR_NUMBER_OF_BREAKPOINTS_FOR_DR0, 0xDC, 0x00 },
239 { PMC_EV_K8_FR_NUMBER_OF_BREAKPOINTS_FOR_DR1, 0xDD, 0x00 },
240 { PMC_EV_K8_FR_NUMBER_OF_BREAKPOINTS_FOR_DR2, 0xDE, 0x00 },
241 { PMC_EV_K8_FR_NUMBER_OF_BREAKPOINTS_FOR_DR3, 0xDF, 0x00 },
243 { PMC_EV_K8_NB_MEMORY_CONTROLLER_PAGE_ACCESS_EVENT, 0xE0, 0x7 },
244 { PMC_EV_K8_NB_MEMORY_CONTROLLER_PAGE_TABLE_OVERFLOW, 0xE1, 0x00 },
245 { PMC_EV_K8_NB_MEMORY_CONTROLLER_DRAM_COMMAND_SLOTS_MISSED,
247 { PMC_EV_K8_NB_MEMORY_CONTROLLER_TURNAROUND, 0xE3, 0x07 },
248 { PMC_EV_K8_NB_MEMORY_CONTROLLER_BYPASS_SATURATION, 0xE4, 0x0F },
249 { PMC_EV_K8_NB_SIZED_COMMANDS, 0xEB, 0x7F },
250 { PMC_EV_K8_NB_PROBE_RESULT, 0xEC, 0x0F },
251 { PMC_EV_K8_NB_HT_BUS0_BANDWIDTH, 0xF6, 0x0F },
252 { PMC_EV_K8_NB_HT_BUS1_BANDWIDTH, 0xF7, 0x0F },
253 { PMC_EV_K8_NB_HT_BUS2_BANDWIDTH, 0xF8, 0x0F }
257 const int amd_event_codes_size =
258 sizeof(amd_event_codes) / sizeof(amd_event_codes[0]);
261 * read a pmc register
265 amd_read_pmc(int cpu, int ri, pmc_value_t *v)
268 const struct amd_descr *pd;
270 const struct pmc_hw *phw;
273 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
274 ("[amd,%d] illegal CPU value %d", __LINE__, cpu));
275 KASSERT(ri >= 0 && ri < AMD_NPMCS,
276 ("[amd,%d] illegal row-index %d", __LINE__, ri));
278 phw = pmc_pcpu[cpu]->pc_hwpmcs[ri];
279 pd = &amd_pmcdesc[ri];
283 ("[amd,%d] No owner for HWPMC [cpu%d,pmc%d]", __LINE__,
286 mode = PMC_TO_MODE(pm);
288 PMCDBG(MDP,REA,1,"amd-read id=%d class=%d", ri, pd->pm_descr.pd_class);
290 /* Reading the TSC is a special case */
291 if (pd->pm_descr.pd_class == PMC_CLASS_TSC) {
292 KASSERT(PMC_IS_COUNTING_MODE(mode),
293 ("[amd,%d] TSC counter in non-counting mode", __LINE__));
295 PMCDBG(MDP,REA,2,"amd-read id=%d -> %jd", ri, *v);
300 KASSERT(pd->pm_descr.pd_class == amd_pmc_class,
301 ("[amd,%d] unknown PMC class (%d)", __LINE__,
302 pd->pm_descr.pd_class));
305 tmp = rdmsr(pd->pm_perfctr); /* RDMSR serializes */
306 PMCDBG(MDP,REA,2,"amd-read (pre-munge) id=%d -> %jd", ri, tmp);
307 if (PMC_IS_SAMPLING_MODE(mode)) {
308 /* Sign extend 48 bit value to 64 bits. */
309 tmp = (pmc_value_t) (((int64_t) tmp << 16) >> 16);
310 tmp = AMD_PERFCTR_VALUE_TO_RELOAD_COUNT(tmp);
314 PMCDBG(MDP,REA,2,"amd-read (post-munge) id=%d -> %jd", ri, *v);
324 amd_write_pmc(int cpu, int ri, pmc_value_t v)
326 const struct amd_descr *pd;
328 const struct pmc_hw *phw;
331 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
332 ("[amd,%d] illegal CPU value %d", __LINE__, cpu));
333 KASSERT(ri >= 0 && ri < AMD_NPMCS,
334 ("[amd,%d] illegal row-index %d", __LINE__, ri));
336 phw = pmc_pcpu[cpu]->pc_hwpmcs[ri];
337 pd = &amd_pmcdesc[ri];
341 ("[amd,%d] PMC not owned (cpu%d,pmc%d)", __LINE__,
344 mode = PMC_TO_MODE(pm);
346 if (pd->pm_descr.pd_class == PMC_CLASS_TSC)
350 KASSERT(pd->pm_descr.pd_class == amd_pmc_class,
351 ("[amd,%d] unknown PMC class (%d)", __LINE__,
352 pd->pm_descr.pd_class));
355 /* use 2's complement of the count for sampling mode PMCs */
356 if (PMC_IS_SAMPLING_MODE(mode))
357 v = AMD_RELOAD_COUNT_TO_PERFCTR_VALUE(v);
359 PMCDBG(MDP,WRI,1,"amd-write cpu=%d ri=%d v=%jx", cpu, ri, v);
361 /* write the PMC value */
362 wrmsr(pd->pm_perfctr, v);
367 * configure hardware pmc according to the configuration recorded in
372 amd_config_pmc(int cpu, int ri, struct pmc *pm)
376 PMCDBG(MDP,CFG,1, "cpu=%d ri=%d pm=%p", cpu, ri, pm);
378 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
379 ("[amd,%d] illegal CPU value %d", __LINE__, cpu));
380 KASSERT(ri >= 0 && ri < AMD_NPMCS,
381 ("[amd,%d] illegal row-index %d", __LINE__, ri));
383 phw = pmc_pcpu[cpu]->pc_hwpmcs[ri];
385 KASSERT(pm == NULL || phw->phw_pmc == NULL,
386 ("[amd,%d] pm=%p phw->pm=%p hwpmc not unconfigured",
387 __LINE__, pm, phw->phw_pmc));
394 * Retrieve a configured PMC pointer from hardware state.
398 amd_get_config(int cpu, int ri, struct pmc **ppm)
400 *ppm = pmc_pcpu[cpu]->pc_hwpmcs[ri]->phw_pmc;
406 * Machine dependent actions taken during the context switch in of a
411 amd_switch_in(struct pmc_cpu *pc, struct pmc_process *pp)
415 PMCDBG(MDP,SWI,1, "pc=%p pp=%p enable-msr=%d", pc, pp,
416 (pp->pp_flags & PMC_PP_ENABLE_MSR_ACCESS) != 0);
418 /* enable the RDPMC instruction if needed */
419 if (pp->pp_flags & PMC_PP_ENABLE_MSR_ACCESS)
420 load_cr4(rcr4() | CR4_PCE);
426 * Machine dependent actions taken during the context switch out of a
431 amd_switch_out(struct pmc_cpu *pc, struct pmc_process *pp)
434 (void) pp; /* can be NULL */
436 PMCDBG(MDP,SWO,1, "pc=%p pp=%p enable-msr=%d", pc, pp, pp ?
437 (pp->pp_flags & PMC_PP_ENABLE_MSR_ACCESS) == 1 : 0);
439 /* always turn off the RDPMC instruction */
440 load_cr4(rcr4() & ~CR4_PCE);
446 * Check if a given allocation is feasible.
450 amd_allocate_pmc(int cpu, int ri, struct pmc *pm,
451 const struct pmc_op_pmcallocate *a)
454 uint32_t allowed_unitmask, caps, config, unitmask;
456 const struct pmc_descr *pd;
460 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
461 ("[amd,%d] illegal CPU value %d", __LINE__, cpu));
462 KASSERT(ri >= 0 && ri < AMD_NPMCS,
463 ("[amd,%d] illegal row index %d", __LINE__, ri));
465 pd = &amd_pmcdesc[ri].pm_descr;
467 /* check class match */
468 if (pd->pd_class != a->pm_class)
473 PMCDBG(MDP,ALL,1,"amd-allocate ri=%d caps=0x%x", ri, caps);
475 if ((pd->pd_caps & caps) != caps)
477 if (pd->pd_class == PMC_CLASS_TSC) {
478 /* TSC's are always allocated in system-wide counting mode */
479 if (a->pm_ev != PMC_EV_TSC_TSC ||
480 a->pm_mode != PMC_MODE_SC)
486 KASSERT(pd->pd_class == amd_pmc_class,
487 ("[amd,%d] Unknown PMC class (%d)", __LINE__, pd->pd_class));
492 /* map ev to the correct event mask code */
493 config = allowed_unitmask = 0;
494 for (i = 0; i < amd_event_codes_size; i++)
495 if (amd_event_codes[i].pe_ev == pe) {
497 AMD_PMC_TO_EVENTMASK(amd_event_codes[i].pe_code);
499 AMD_PMC_TO_UNITMASK(amd_event_codes[i].pe_mask);
502 if (i == amd_event_codes_size)
505 unitmask = a->pm_md.pm_amd.pm_amd_config & AMD_PMC_UNITMASK;
506 if (unitmask & ~allowed_unitmask) /* disallow reserved bits */
509 if (unitmask && (caps & PMC_CAP_QUALIFIER))
512 if (caps & PMC_CAP_THRESHOLD)
513 config |= a->pm_md.pm_amd.pm_amd_config & AMD_PMC_COUNTERMASK;
515 /* set at least one of the 'usr' or 'os' caps */
516 if (caps & PMC_CAP_USER)
517 config |= AMD_PMC_USR;
518 if (caps & PMC_CAP_SYSTEM)
519 config |= AMD_PMC_OS;
520 if ((caps & (PMC_CAP_USER|PMC_CAP_SYSTEM)) == 0)
521 config |= (AMD_PMC_USR|AMD_PMC_OS);
523 if (caps & PMC_CAP_EDGE)
524 config |= AMD_PMC_EDGE;
525 if (caps & PMC_CAP_INVERT)
526 config |= AMD_PMC_INVERT;
527 if (caps & PMC_CAP_INTERRUPT)
528 config |= AMD_PMC_INT;
530 pm->pm_md.pm_amd.pm_amd_evsel = config; /* save config value */
532 PMCDBG(MDP,ALL,2,"amd-allocate ri=%d -> config=0x%x", ri, config);
538 * Release machine dependent state associated with a PMC. This is a
539 * no-op on this architecture.
545 amd_release_pmc(int cpu, int ri, struct pmc *pmc)
548 const struct amd_descr *pd;
554 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
555 ("[amd,%d] illegal CPU value %d", __LINE__, cpu));
556 KASSERT(ri >= 0 && ri < AMD_NPMCS,
557 ("[amd,%d] illegal row-index %d", __LINE__, ri));
559 phw = pmc_pcpu[cpu]->pc_hwpmcs[ri];
561 KASSERT(phw->phw_pmc == NULL,
562 ("[amd,%d] PHW pmc %p non-NULL", __LINE__, phw->phw_pmc));
565 pd = &amd_pmcdesc[ri];
566 if (pd->pm_descr.pd_class == amd_pmc_class)
567 KASSERT(AMD_PMC_IS_STOPPED(pd->pm_evsel),
568 ("[amd,%d] PMC %d released while active", __LINE__, ri));
579 amd_start_pmc(int cpu, int ri)
584 const struct amd_descr *pd;
586 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
587 ("[amd,%d] illegal CPU value %d", __LINE__, cpu));
588 KASSERT(ri >= 0 && ri < AMD_NPMCS,
589 ("[amd,%d] illegal row-index %d", __LINE__, ri));
591 phw = pmc_pcpu[cpu]->pc_hwpmcs[ri];
593 pd = &amd_pmcdesc[ri];
596 ("[amd,%d] starting cpu%d,pmc%d with null pmc record", __LINE__,
599 PMCDBG(MDP,STA,1,"amd-start cpu=%d ri=%d", cpu, ri);
601 if (pd->pm_descr.pd_class == PMC_CLASS_TSC)
602 return 0; /* TSCs are always running */
605 KASSERT(pd->pm_descr.pd_class == amd_pmc_class,
606 ("[amd,%d] unknown PMC class (%d)", __LINE__,
607 pd->pm_descr.pd_class));
610 KASSERT(AMD_PMC_IS_STOPPED(pd->pm_evsel),
611 ("[amd,%d] pmc%d,cpu%d: Starting active PMC \"%s\"", __LINE__,
612 ri, cpu, pd->pm_descr.pd_name));
614 /* turn on the PMC ENABLE bit */
615 config = pm->pm_md.pm_amd.pm_amd_evsel | AMD_PMC_ENABLE;
617 PMCDBG(MDP,STA,2,"amd-start config=0x%x", config);
619 wrmsr(pd->pm_evsel, config);
628 amd_stop_pmc(int cpu, int ri)
632 const struct amd_descr *pd;
635 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
636 ("[amd,%d] illegal CPU value %d", __LINE__, cpu));
637 KASSERT(ri >= 0 && ri < AMD_NPMCS,
638 ("[amd,%d] illegal row-index %d", __LINE__, ri));
640 phw = pmc_pcpu[cpu]->pc_hwpmcs[ri];
642 pd = &amd_pmcdesc[ri];
645 ("[amd,%d] cpu%d,pmc%d no PMC to stop", __LINE__,
648 /* can't stop a TSC */
649 if (pd->pm_descr.pd_class == PMC_CLASS_TSC)
653 KASSERT(pd->pm_descr.pd_class == amd_pmc_class,
654 ("[amd,%d] unknown PMC class (%d)", __LINE__,
655 pd->pm_descr.pd_class));
658 KASSERT(!AMD_PMC_IS_STOPPED(pd->pm_evsel),
659 ("[amd,%d] PMC%d, CPU%d \"%s\" already stopped",
660 __LINE__, ri, cpu, pd->pm_descr.pd_name));
662 PMCDBG(MDP,STO,1,"amd-stop ri=%d", ri);
664 /* turn off the PMC ENABLE bit */
665 config = pm->pm_md.pm_amd.pm_amd_evsel & ~AMD_PMC_ENABLE;
666 wrmsr(pd->pm_evsel, config);
671 * Interrupt handler. This function needs to return '1' if the
672 * interrupt was this CPU's PMCs or '0' otherwise. It is not allowed
673 * to sleep or do anything a 'fast' interrupt handler is not allowed
678 amd_intr(int cpu, struct trapframe *tf)
680 int i, error, retval, ri;
681 uint32_t config, evsel, perfctr;
687 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
688 ("[amd,%d] out of range CPU %d", __LINE__, cpu));
690 PMCDBG(MDP,INT,1, "cpu=%d tf=%p um=%d", cpu, (void *) tf,
698 * look for all PMCs that have interrupted:
699 * - skip over the TSC [PMC#0]
700 * - look for a running, sampling PMC which has overflowed
701 * and which has a valid 'struct pmc' association
703 * If found, we call a helper to process the interrupt.
705 * If multiple PMCs interrupt at the same time, the AMD64
706 * processor appears to deliver as many NMIs as there are
707 * outstanding PMC interrupts. So we process only one NMI
708 * interrupt at a time.
711 for (i = 0; retval == 0 && i < AMD_NPMCS-1; i++) {
713 ri = i + 1; /* row index; TSC is at ri == 0 */
715 if (!AMD_PMC_HAS_OVERFLOWED(i))
718 phw = pc->pc_hwpmcs[ri];
720 KASSERT(phw != NULL, ("[amd,%d] null PHW pointer", __LINE__));
722 if ((pm = phw->phw_pmc) == NULL ||
723 pm->pm_state != PMC_STATE_RUNNING ||
724 !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) {
728 retval = 1; /* Found an interrupting PMC. */
730 /* Stop the PMC, reload count. */
731 evsel = AMD_PMC_EVSEL_0 + i;
732 perfctr = AMD_PMC_PERFCTR_0 + i;
733 v = pm->pm_sc.pm_reloadcount;
734 config = rdmsr(evsel);
736 KASSERT((config & ~AMD_PMC_ENABLE) ==
737 (pm->pm_md.pm_amd.pm_amd_evsel & ~AMD_PMC_ENABLE),
738 ("[amd,%d] config mismatch reg=0x%x pm=0x%x", __LINE__,
739 config, pm->pm_md.pm_amd.pm_amd_evsel));
741 wrmsr(evsel, config & ~AMD_PMC_ENABLE);
742 wrmsr(perfctr, AMD_RELOAD_COUNT_TO_PERFCTR_VALUE(v));
744 /* Restart the counter if logging succeeded. */
745 error = pmc_process_interrupt(cpu, pm, tf, TRAPF_USERMODE(tf));
747 wrmsr(evsel, config | AMD_PMC_ENABLE);
750 atomic_add_int(retval ? &pmc_stats.pm_intr_processed :
751 &pmc_stats.pm_intr_ignored, 1);
760 amd_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc)
764 const struct amd_descr *pd;
767 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
768 ("[amd,%d] illegal CPU %d", __LINE__, cpu));
769 KASSERT(ri >= 0 && ri < AMD_NPMCS,
770 ("[amd,%d] row-index %d out of range", __LINE__, ri));
772 phw = pmc_pcpu[cpu]->pc_hwpmcs[ri];
773 pd = &amd_pmcdesc[ri];
775 if ((error = copystr(pd->pm_descr.pd_name, pi->pm_name,
776 PMC_NAME_MAX, &copied)) != 0)
779 pi->pm_class = pd->pm_descr.pd_class;
781 if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) {
782 pi->pm_enabled = TRUE;
783 *ppmc = phw->phw_pmc;
785 pi->pm_enabled = FALSE;
793 * i386 specific entry points
797 * return the MSR address of the given PMC.
801 amd_get_msr(int ri, uint32_t *msr)
803 KASSERT(ri >= 0 && ri < AMD_NPMCS,
804 ("[amd,%d] ri %d out of range", __LINE__, ri));
806 *msr = amd_pmcdesc[ri].pm_perfctr - AMD_PMC_PERFCTR_0;
811 * processor dependent initialization.
815 * Per-processor data structure
818 * [5 struct pmc_hw pointers]
819 * [5 struct pmc_hw structures]
823 struct pmc_cpu pc_common;
824 struct pmc_hw *pc_hwpmcs[AMD_NPMCS];
825 struct pmc_hw pc_amdpmcs[AMD_NPMCS];
836 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
837 ("[amd,%d] insane cpu number %d", __LINE__, cpu));
839 PMCDBG(MDP,INI,1,"amd-init cpu=%d", cpu);
841 MALLOC(pcs, struct amd_cpu *, sizeof(struct amd_cpu), M_PMC,
844 phw = &pcs->pc_amdpmcs[0];
847 * Initialize the per-cpu mutex and set the content of the
848 * hardware descriptors to a known state.
851 for (n = 0; n < AMD_NPMCS; n++, phw++) {
852 phw->phw_state = PMC_PHW_FLAG_IS_ENABLED |
853 PMC_PHW_CPU_TO_STATE(cpu) | PMC_PHW_INDEX_TO_STATE(n);
855 pcs->pc_hwpmcs[n] = phw;
858 /* Mark the TSC as shareable */
859 pcs->pc_hwpmcs[0]->phw_state |= PMC_PHW_FLAG_IS_SHAREABLE;
861 pmc_pcpu[cpu] = (struct pmc_cpu *) pcs;
868 * processor dependent cleanup prior to the KLD
879 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
880 ("[amd,%d] insane cpu number (%d)", __LINE__, cpu));
882 PMCDBG(MDP,INI,1,"amd-cleanup cpu=%d", cpu);
885 * First, turn off all PMCs on this CPU.
888 for (i = 0; i < 4; i++) { /* XXX this loop is now not needed */
889 evsel = rdmsr(AMD_PMC_EVSEL_0 + i);
890 evsel &= ~AMD_PMC_ENABLE;
891 wrmsr(AMD_PMC_EVSEL_0 + i, evsel);
895 * Next, free up allocated space.
898 if ((pcs = pmc_pcpu[cpu]) == NULL)
903 KASSERT(pcs->pc_hwpmcs[0]->phw_pmc == NULL,
904 ("[amd,%d] CPU%d,PMC0 still in use", __LINE__, cpu));
905 for (i = 1; i < AMD_NPMCS; i++) {
906 KASSERT(pcs->pc_hwpmcs[i]->phw_pmc == NULL,
907 ("[amd,%d] CPU%d/PMC%d in use", __LINE__, cpu, i));
908 KASSERT(AMD_PMC_IS_STOPPED(AMD_PMC_EVSEL_0 + (i-1)),
909 ("[amd,%d] CPU%d/PMC%d not stopped", __LINE__, cpu, i));
913 pmc_pcpu[cpu] = NULL;
919 * Initialize ourselves.
923 pmc_amd_initialize(void)
925 enum pmc_cputype cputype;
926 enum pmc_class class;
927 struct pmc_mdep *pmc_mdep;
932 * The presence of hardware performance counters on the AMD
933 * Athlon, Duron or later processors, is _not_ indicated by
934 * any of the processor feature flags set by the 'CPUID'
935 * instruction, so we only check the 'instruction family'
936 * field returned by CPUID for instruction family >= 6.
939 class = cputype = -1;
941 switch (cpu_id & 0xF00) {
942 case 0x600: /* Athlon(tm) processor */
943 cputype = PMC_CPU_AMD_K7;
944 class = PMC_CLASS_K7;
947 case 0xF00: /* Athlon64/Opteron processor */
948 cputype = PMC_CPU_AMD_K8;
949 class = PMC_CLASS_K8;
954 if ((int) cputype == -1) {
955 (void) printf("pmc: Unknown AMD CPU.\n");
960 amd_pmc_class = class;
963 MALLOC(pmc_mdep, struct pmc_mdep *, sizeof(struct pmc_mdep),
964 M_PMC, M_WAITOK|M_ZERO);
966 pmc_mdep->pmd_cputype = cputype;
967 pmc_mdep->pmd_npmc = AMD_NPMCS;
969 /* this processor has two classes of usable PMCs */
970 pmc_mdep->pmd_nclass = 2;
973 pmc_mdep->pmd_classes[0].pm_class = PMC_CLASS_TSC;
974 pmc_mdep->pmd_classes[0].pm_caps = PMC_CAP_READ;
975 pmc_mdep->pmd_classes[0].pm_width = 64;
978 pmc_mdep->pmd_classes[1].pm_class = class;
979 pmc_mdep->pmd_classes[1].pm_caps = AMD_PMC_CAPS;
980 pmc_mdep->pmd_classes[1].pm_width = 48;
982 pmc_mdep->pmd_nclasspmcs[0] = 1;
983 pmc_mdep->pmd_nclasspmcs[1] = (AMD_NPMCS-1);
985 /* fill in the correct pmc name and class */
986 for (i = 1; i < AMD_NPMCS; i++) {
987 (void) snprintf(amd_pmcdesc[i].pm_descr.pd_name,
988 sizeof(amd_pmcdesc[i].pm_descr.pd_name), "%s-%d",
990 amd_pmcdesc[i].pm_descr.pd_class = class;
993 pmc_mdep->pmd_init = amd_init;
994 pmc_mdep->pmd_cleanup = amd_cleanup;
995 pmc_mdep->pmd_switch_in = amd_switch_in;
996 pmc_mdep->pmd_switch_out = amd_switch_out;
997 pmc_mdep->pmd_read_pmc = amd_read_pmc;
998 pmc_mdep->pmd_write_pmc = amd_write_pmc;
999 pmc_mdep->pmd_config_pmc = amd_config_pmc;
1000 pmc_mdep->pmd_get_config = amd_get_config;
1001 pmc_mdep->pmd_allocate_pmc = amd_allocate_pmc;
1002 pmc_mdep->pmd_release_pmc = amd_release_pmc;
1003 pmc_mdep->pmd_start_pmc = amd_start_pmc;
1004 pmc_mdep->pmd_stop_pmc = amd_stop_pmc;
1005 pmc_mdep->pmd_intr = amd_intr;
1006 pmc_mdep->pmd_describe = amd_describe;
1007 pmc_mdep->pmd_get_msr = amd_get_msr; /* i386 */
1009 PMCDBG(MDP,INI,0,"%s","amd-initialize");