sys/dev/hwpmc/hwpmc_amd.c

   1 /*-
   2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
   3  *
   4  * Copyright (c) 2003-2008 Joseph Koshy
   5  * Copyright (c) 2007 The FreeBSD Foundation
   6  * All rights reserved.
   7  *
   8  * Portions of this software were developed by A. Joseph Koshy under
   9  * sponsorship from the FreeBSD Foundation and Google, Inc.
  10  *
  11  * Redistribution and use in source and binary forms, with or without
  12  * modification, are permitted provided that the following conditions
  13  * are met:
  14  * 1. Redistributions of source code must retain the above copyright
  15  *    notice, this list of conditions and the following disclaimer.
  16  * 2. Redistributions in binary form must reproduce the above copyright
  17  *    notice, this list of conditions and the following disclaimer in the
  18  *    documentation and/or other materials provided with the distribution.
  19  *
  20  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  21  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  24  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  25  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  26  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  27  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  28  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  29  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  30  * SUCH DAMAGE.
  31  */
  32
  33 #include <sys/cdefs.h>
  34 __FBSDID("$FreeBSD$");
  35
  36 /* Support for the AMD K7 and later processors */
  37
  38 #include <sys/param.h>
  39 #include <sys/lock.h>
  40 #include <sys/malloc.h>
  41 #include <sys/mutex.h>
  42 #include <sys/pmc.h>
  43 #include <sys/pmckern.h>
  44 #include <sys/smp.h>
  45 #include <sys/systm.h>
  46
  47 #include <machine/cpu.h>
  48 #include <machine/cpufunc.h>
  49 #include <machine/md_var.h>
  50 #include <machine/specialreg.h>
  51
  52 #ifdef  HWPMC_DEBUG
  53 enum pmc_class  amd_pmc_class;
  54 #endif
  55
  56 /* AMD K7 & K8 PMCs */
  57 struct amd_descr {
  58         struct pmc_descr pm_descr;  /* "base class" */
  59         uint32_t        pm_evsel;   /* address of EVSEL register */
  60         uint32_t        pm_perfctr; /* address of PERFCTR register */
  61 };
  62
  63 static  struct amd_descr amd_pmcdesc[AMD_NPMCS] =
  64 {
  65     {
  66         .pm_descr =
  67         {
  68                 .pd_name  = "",
  69                 .pd_class = -1,
  70                 .pd_caps  = AMD_PMC_CAPS,
  71                 .pd_width = 48
  72         },
  73         .pm_evsel   = AMD_PMC_EVSEL_0,
  74         .pm_perfctr = AMD_PMC_PERFCTR_0
  75     },
  76     {
  77         .pm_descr =
  78         {
  79                 .pd_name  = "",
  80                 .pd_class = -1,
  81                 .pd_caps  = AMD_PMC_CAPS,
  82                 .pd_width = 48
  83         },
  84         .pm_evsel   = AMD_PMC_EVSEL_1,
  85         .pm_perfctr = AMD_PMC_PERFCTR_1
  86     },
  87     {
  88         .pm_descr =
  89         {
  90                 .pd_name  = "",
  91                 .pd_class = -1,
  92                 .pd_caps  = AMD_PMC_CAPS,
  93                 .pd_width = 48
  94         },
  95         .pm_evsel   = AMD_PMC_EVSEL_2,
  96         .pm_perfctr = AMD_PMC_PERFCTR_2
  97     },
  98     {
  99         .pm_descr =
 100         {
 101                 .pd_name  = "",
 102                 .pd_class = -1,
 103                 .pd_caps  = AMD_PMC_CAPS,
 104                 .pd_width = 48
 105         },
 106         .pm_evsel   = AMD_PMC_EVSEL_3,
 107         .pm_perfctr = AMD_PMC_PERFCTR_3
 108     }
 109 };
 110
 111 struct amd_event_code_map {
 112         enum pmc_event  pe_ev;   /* enum value */
 113         uint16_t        pe_code; /* encoded event mask */
 114         uint8_t         pe_mask; /* bits allowed in unit mask */
 115 };
 116
 117 const struct amd_event_code_map amd_event_codes[] = {
 118 #if     defined(__i386__)       /* 32 bit Athlon (K7) only */
 119         { PMC_EV_K7_DC_ACCESSES,                0x40, 0 },
 120         { PMC_EV_K7_DC_MISSES,                  0x41, 0 },
 121         { PMC_EV_K7_DC_REFILLS_FROM_L2,         0x42, AMD_PMC_UNITMASK_MOESI },
 122         { PMC_EV_K7_DC_REFILLS_FROM_SYSTEM,     0x43, AMD_PMC_UNITMASK_MOESI },
 123         { PMC_EV_K7_DC_WRITEBACKS,              0x44, AMD_PMC_UNITMASK_MOESI },
 124         { PMC_EV_K7_L1_DTLB_MISS_AND_L2_DTLB_HITS, 0x45, 0 },
 125         { PMC_EV_K7_L1_AND_L2_DTLB_MISSES,      0x46, 0 },
 126         { PMC_EV_K7_MISALIGNED_REFERENCES,      0x47, 0 },
 127
 128         { PMC_EV_K7_IC_FETCHES,                 0x80, 0 },
 129         { PMC_EV_K7_IC_MISSES,                  0x81, 0 },
 130
 131         { PMC_EV_K7_L1_ITLB_MISSES,             0x84, 0 },
 132         { PMC_EV_K7_L1_L2_ITLB_MISSES,          0x85, 0 },
 133
 134         { PMC_EV_K7_RETIRED_INSTRUCTIONS,       0xC0, 0 },
 135         { PMC_EV_K7_RETIRED_OPS,                0xC1, 0 },
 136         { PMC_EV_K7_RETIRED_BRANCHES,           0xC2, 0 },
 137         { PMC_EV_K7_RETIRED_BRANCHES_MISPREDICTED, 0xC3, 0 },
 138         { PMC_EV_K7_RETIRED_TAKEN_BRANCHES,     0xC4, 0 },
 139         { PMC_EV_K7_RETIRED_TAKEN_BRANCHES_MISPREDICTED, 0xC5, 0 },
 140         { PMC_EV_K7_RETIRED_FAR_CONTROL_TRANSFERS, 0xC6, 0 },
 141         { PMC_EV_K7_RETIRED_RESYNC_BRANCHES,    0xC7, 0 },
 142         { PMC_EV_K7_INTERRUPTS_MASKED_CYCLES,   0xCD, 0 },
 143         { PMC_EV_K7_INTERRUPTS_MASKED_WHILE_PENDING_CYCLES, 0xCE, 0 },
 144         { PMC_EV_K7_HARDWARE_INTERRUPTS,        0xCF, 0 },
 145 #endif
 146
 147         { PMC_EV_K8_FP_DISPATCHED_FPU_OPS,              0x00, 0x3F },
 148         { PMC_EV_K8_FP_CYCLES_WITH_NO_FPU_OPS_RETIRED,  0x01, 0x00 },
 149         { PMC_EV_K8_FP_DISPATCHED_FPU_FAST_FLAG_OPS,    0x02, 0x00 },
 150
 151         { PMC_EV_K8_LS_SEGMENT_REGISTER_LOAD,           0x20, 0x7F },
 152         { PMC_EV_K8_LS_MICROARCHITECTURAL_RESYNC_BY_SELF_MODIFYING_CODE,
 153                                                         0x21, 0x00 },
 154         { PMC_EV_K8_LS_MICROARCHITECTURAL_RESYNC_BY_SNOOP, 0x22, 0x00 },
 155         { PMC_EV_K8_LS_BUFFER2_FULL,                    0x23, 0x00 },
 156         { PMC_EV_K8_LS_LOCKED_OPERATION,                0x24, 0x07 },
 157         { PMC_EV_K8_LS_MICROARCHITECTURAL_LATE_CANCEL,  0x25, 0x00 },
 158         { PMC_EV_K8_LS_RETIRED_CFLUSH_INSTRUCTIONS,     0x26, 0x00 },
 159         { PMC_EV_K8_LS_RETIRED_CPUID_INSTRUCTIONS,      0x27, 0x00 },
 160
 161         { PMC_EV_K8_DC_ACCESS,                          0x40, 0x00 },
 162         { PMC_EV_K8_DC_MISS,                            0x41, 0x00 },
 163         { PMC_EV_K8_DC_REFILL_FROM_L2,                  0x42, 0x1F },
 164         { PMC_EV_K8_DC_REFILL_FROM_SYSTEM,              0x43, 0x1F },
 165         { PMC_EV_K8_DC_COPYBACK,                        0x44, 0x1F },
 166         { PMC_EV_K8_DC_L1_DTLB_MISS_AND_L2_DTLB_HIT,    0x45, 0x00 },
 167         { PMC_EV_K8_DC_L1_DTLB_MISS_AND_L2_DTLB_MISS,   0x46, 0x00 },
 168         { PMC_EV_K8_DC_MISALIGNED_DATA_REFERENCE,       0x47, 0x00 },
 169         { PMC_EV_K8_DC_MICROARCHITECTURAL_LATE_CANCEL,  0x48, 0x00 },
 170         { PMC_EV_K8_DC_MICROARCHITECTURAL_EARLY_CANCEL, 0x49, 0x00 },
 171         { PMC_EV_K8_DC_ONE_BIT_ECC_ERROR,               0x4A, 0x03 },
 172         { PMC_EV_K8_DC_DISPATCHED_PREFETCH_INSTRUCTIONS, 0x4B, 0x07 },
 173         { PMC_EV_K8_DC_DCACHE_ACCESSES_BY_LOCKS,        0x4C, 0x03 },
 174
 175         { PMC_EV_K8_BU_CPU_CLK_UNHALTED,                0x76, 0x00 },
 176         { PMC_EV_K8_BU_INTERNAL_L2_REQUEST,             0x7D, 0x1F },
 177         { PMC_EV_K8_BU_FILL_REQUEST_L2_MISS,            0x7E, 0x07 },
 178         { PMC_EV_K8_BU_FILL_INTO_L2,                    0x7F, 0x03 },
 179
 180         { PMC_EV_K8_IC_FETCH,                           0x80, 0x00 },
 181         { PMC_EV_K8_IC_MISS,                            0x81, 0x00 },
 182         { PMC_EV_K8_IC_REFILL_FROM_L2,                  0x82, 0x00 },
 183         { PMC_EV_K8_IC_REFILL_FROM_SYSTEM,              0x83, 0x00 },
 184         { PMC_EV_K8_IC_L1_ITLB_MISS_AND_L2_ITLB_HIT,    0x84, 0x00 },
 185         { PMC_EV_K8_IC_L1_ITLB_MISS_AND_L2_ITLB_MISS,   0x85, 0x00 },
 186         { PMC_EV_K8_IC_MICROARCHITECTURAL_RESYNC_BY_SNOOP, 0x86, 0x00 },
 187         { PMC_EV_K8_IC_INSTRUCTION_FETCH_STALL,         0x87, 0x00 },
 188         { PMC_EV_K8_IC_RETURN_STACK_HIT,                0x88, 0x00 },
 189         { PMC_EV_K8_IC_RETURN_STACK_OVERFLOW,           0x89, 0x00 },
 190
 191         { PMC_EV_K8_FR_RETIRED_X86_INSTRUCTIONS,        0xC0, 0x00 },
 192         { PMC_EV_K8_FR_RETIRED_UOPS,                    0xC1, 0x00 },
 193         { PMC_EV_K8_FR_RETIRED_BRANCHES,                0xC2, 0x00 },
 194         { PMC_EV_K8_FR_RETIRED_BRANCHES_MISPREDICTED,   0xC3, 0x00 },
 195         { PMC_EV_K8_FR_RETIRED_TAKEN_BRANCHES,          0xC4, 0x00 },
 196         { PMC_EV_K8_FR_RETIRED_TAKEN_BRANCHES_MISPREDICTED, 0xC5, 0x00 },
 197         { PMC_EV_K8_FR_RETIRED_FAR_CONTROL_TRANSFERS,   0xC6, 0x00 },
 198         { PMC_EV_K8_FR_RETIRED_RESYNCS,                 0xC7, 0x00 },
 199         { PMC_EV_K8_FR_RETIRED_NEAR_RETURNS,            0xC8, 0x00 },
 200         { PMC_EV_K8_FR_RETIRED_NEAR_RETURNS_MISPREDICTED, 0xC9, 0x00 },
 201         { PMC_EV_K8_FR_RETIRED_TAKEN_BRANCHES_MISPREDICTED_BY_ADDR_MISCOMPARE,
 202                                                         0xCA, 0x00 },
 203         { PMC_EV_K8_FR_RETIRED_FPU_INSTRUCTIONS,        0xCB, 0x0F },
 204         { PMC_EV_K8_FR_RETIRED_FASTPATH_DOUBLE_OP_INSTRUCTIONS,
 205                                                         0xCC, 0x07 },
 206         { PMC_EV_K8_FR_INTERRUPTS_MASKED_CYCLES,        0xCD, 0x00 },
 207         { PMC_EV_K8_FR_INTERRUPTS_MASKED_WHILE_PENDING_CYCLES, 0xCE, 0x00 },
 208         { PMC_EV_K8_FR_TAKEN_HARDWARE_INTERRUPTS,       0xCF, 0x00 },
 209
 210         { PMC_EV_K8_FR_DECODER_EMPTY,                   0xD0, 0x00 },
 211         { PMC_EV_K8_FR_DISPATCH_STALLS,                 0xD1, 0x00 },
 212         { PMC_EV_K8_FR_DISPATCH_STALL_FROM_BRANCH_ABORT_TO_RETIRE,
 213                                                         0xD2, 0x00 },
 214         { PMC_EV_K8_FR_DISPATCH_STALL_FOR_SERIALIZATION, 0xD3, 0x00 },
 215         { PMC_EV_K8_FR_DISPATCH_STALL_FOR_SEGMENT_LOAD, 0xD4, 0x00 },
 216         { PMC_EV_K8_FR_DISPATCH_STALL_WHEN_REORDER_BUFFER_IS_FULL,
 217                                                         0xD5, 0x00 },
 218         { PMC_EV_K8_FR_DISPATCH_STALL_WHEN_RESERVATION_STATIONS_ARE_FULL,
 219                                                         0xD6, 0x00 },
 220         { PMC_EV_K8_FR_DISPATCH_STALL_WHEN_FPU_IS_FULL, 0xD7, 0x00 },
 221         { PMC_EV_K8_FR_DISPATCH_STALL_WHEN_LS_IS_FULL,  0xD8, 0x00 },
 222         { PMC_EV_K8_FR_DISPATCH_STALL_WHEN_WAITING_FOR_ALL_TO_BE_QUIET,
 223                                                         0xD9, 0x00 },
 224         { PMC_EV_K8_FR_DISPATCH_STALL_WHEN_FAR_XFER_OR_RESYNC_BRANCH_PENDING,
 225                                                         0xDA, 0x00 },
 226         { PMC_EV_K8_FR_FPU_EXCEPTIONS,                  0xDB, 0x0F },
 227         { PMC_EV_K8_FR_NUMBER_OF_BREAKPOINTS_FOR_DR0,   0xDC, 0x00 },
 228         { PMC_EV_K8_FR_NUMBER_OF_BREAKPOINTS_FOR_DR1,   0xDD, 0x00 },
 229         { PMC_EV_K8_FR_NUMBER_OF_BREAKPOINTS_FOR_DR2,   0xDE, 0x00 },
 230         { PMC_EV_K8_FR_NUMBER_OF_BREAKPOINTS_FOR_DR3,   0xDF, 0x00 },
 231
 232         { PMC_EV_K8_NB_MEMORY_CONTROLLER_PAGE_ACCESS_EVENT, 0xE0, 0x7 },
 233         { PMC_EV_K8_NB_MEMORY_CONTROLLER_PAGE_TABLE_OVERFLOW, 0xE1, 0x00 },
 234         { PMC_EV_K8_NB_MEMORY_CONTROLLER_DRAM_COMMAND_SLOTS_MISSED,
 235                                                         0xE2, 0x00 },
 236         { PMC_EV_K8_NB_MEMORY_CONTROLLER_TURNAROUND,    0xE3, 0x07 },
 237         { PMC_EV_K8_NB_MEMORY_CONTROLLER_BYPASS_SATURATION, 0xE4, 0x0F },
 238         { PMC_EV_K8_NB_SIZED_COMMANDS,                  0xEB, 0x7F },
 239         { PMC_EV_K8_NB_PROBE_RESULT,                    0xEC, 0x0F },
 240         { PMC_EV_K8_NB_HT_BUS0_BANDWIDTH,               0xF6, 0x0F },
 241         { PMC_EV_K8_NB_HT_BUS1_BANDWIDTH,               0xF7, 0x0F },
 242         { PMC_EV_K8_NB_HT_BUS2_BANDWIDTH,               0xF8, 0x0F }
 243
 244 };
 245
 246 const int amd_event_codes_size = nitems(amd_event_codes);
 247
 248 /*
 249  * Per-processor information
 250  */
 251
 252 struct amd_cpu {
 253         struct pmc_hw   pc_amdpmcs[AMD_NPMCS];
 254 };
 255
 256 static struct amd_cpu **amd_pcpu;
 257
 258 /*
 259  * read a pmc register
 260  */
 261
 262 static int
 263 amd_read_pmc(int cpu, int ri, pmc_value_t *v)
 264 {
 265         enum pmc_mode mode;
 266         const struct amd_descr *pd;
 267         struct pmc *pm;
 268         pmc_value_t tmp;
 269
 270         KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
 271             ("[amd,%d] illegal CPU value %d", __LINE__, cpu));
 272         KASSERT(ri >= 0 && ri < AMD_NPMCS,
 273             ("[amd,%d] illegal row-index %d", __LINE__, ri));
 274         KASSERT(amd_pcpu[cpu],
 275             ("[amd,%d] null per-cpu, cpu %d", __LINE__, cpu));
 276
 277         pm = amd_pcpu[cpu]->pc_amdpmcs[ri].phw_pmc;
 278         pd = &amd_pmcdesc[ri];
 279
 280         KASSERT(pm != NULL,
 281             ("[amd,%d] No owner for HWPMC [cpu%d,pmc%d]", __LINE__,
 282                 cpu, ri));
 283
 284         mode = PMC_TO_MODE(pm);
 285
 286         PMCDBG2(MDP,REA,1,"amd-read id=%d class=%d", ri, pd->pm_descr.pd_class);
 287
 288 #ifdef  HWPMC_DEBUG
 289         KASSERT(pd->pm_descr.pd_class == amd_pmc_class,
 290             ("[amd,%d] unknown PMC class (%d)", __LINE__,
 291                 pd->pm_descr.pd_class));
 292 #endif
 293
 294         tmp = rdmsr(pd->pm_perfctr); /* RDMSR serializes */
 295         PMCDBG2(MDP,REA,2,"amd-read (pre-munge) id=%d -> %jd", ri, tmp);
 296         if (PMC_IS_SAMPLING_MODE(mode)) {
 297                 /* Sign extend 48 bit value to 64 bits. */
 298                 tmp = (pmc_value_t) (((int64_t) tmp << 16) >> 16);
 299                 tmp = AMD_PERFCTR_VALUE_TO_RELOAD_COUNT(tmp);
 300         }
 301         *v = tmp;
 302
 303         PMCDBG2(MDP,REA,2,"amd-read (post-munge) id=%d -> %jd", ri, *v);
 304
 305         return 0;
 306 }
 307
 308 /*
 309  * Write a PMC MSR.
 310  */
 311
 312 static int
 313 amd_write_pmc(int cpu, int ri, pmc_value_t v)
 314 {
 315         const struct amd_descr *pd;
 316         enum pmc_mode mode;
 317         struct pmc *pm;
 318
 319         KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
 320             ("[amd,%d] illegal CPU value %d", __LINE__, cpu));
 321         KASSERT(ri >= 0 && ri < AMD_NPMCS,
 322             ("[amd,%d] illegal row-index %d", __LINE__, ri));
 323
 324         pm = amd_pcpu[cpu]->pc_amdpmcs[ri].phw_pmc;
 325         pd = &amd_pmcdesc[ri];
 326
 327         KASSERT(pm != NULL,
 328             ("[amd,%d] PMC not owned (cpu%d,pmc%d)", __LINE__,
 329                 cpu, ri));
 330
 331         mode = PMC_TO_MODE(pm);
 332
 333 #ifdef  HWPMC_DEBUG
 334         KASSERT(pd->pm_descr.pd_class == amd_pmc_class,
 335             ("[amd,%d] unknown PMC class (%d)", __LINE__,
 336                 pd->pm_descr.pd_class));
 337 #endif
 338
 339         /* use 2's complement of the count for sampling mode PMCs */
 340         if (PMC_IS_SAMPLING_MODE(mode))
 341                 v = AMD_RELOAD_COUNT_TO_PERFCTR_VALUE(v);
 342
 343         PMCDBG3(MDP,WRI,1,"amd-write cpu=%d ri=%d v=%jx", cpu, ri, v);
 344
 345         /* write the PMC value */
 346         wrmsr(pd->pm_perfctr, v);
 347         return 0;
 348 }
 349
 350 /*
 351  * configure hardware pmc according to the configuration recorded in
 352  * pmc 'pm'.
 353  */
 354
 355 static int
 356 amd_config_pmc(int cpu, int ri, struct pmc *pm)
 357 {
 358         struct pmc_hw *phw;
 359
 360         PMCDBG3(MDP,CFG,1, "cpu=%d ri=%d pm=%p", cpu, ri, pm);
 361
 362         KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
 363             ("[amd,%d] illegal CPU value %d", __LINE__, cpu));
 364         KASSERT(ri >= 0 && ri < AMD_NPMCS,
 365             ("[amd,%d] illegal row-index %d", __LINE__, ri));
 366
 367         phw = &amd_pcpu[cpu]->pc_amdpmcs[ri];
 368
 369         KASSERT(pm == NULL || phw->phw_pmc == NULL,
 370             ("[amd,%d] pm=%p phw->pm=%p hwpmc not unconfigured",
 371                 __LINE__, pm, phw->phw_pmc));
 372
 373         phw->phw_pmc = pm;
 374         return 0;
 375 }
 376
 377 /*
 378  * Retrieve a configured PMC pointer from hardware state.
 379  */
 380
 381 static int
 382 amd_get_config(int cpu, int ri, struct pmc **ppm)
 383 {
 384         *ppm = amd_pcpu[cpu]->pc_amdpmcs[ri].phw_pmc;
 385
 386         return 0;
 387 }
 388
 389 /*
 390  * Machine dependent actions taken during the context switch in of a
 391  * thread.
 392  */
 393
 394 static int
 395 amd_switch_in(struct pmc_cpu *pc, struct pmc_process *pp)
 396 {
 397         (void) pc;
 398
 399         PMCDBG3(MDP,SWI,1, "pc=%p pp=%p enable-msr=%d", pc, pp,
 400             (pp->pp_flags & PMC_PP_ENABLE_MSR_ACCESS) != 0);
 401
 402         /* enable the RDPMC instruction if needed */
 403         if (pp->pp_flags & PMC_PP_ENABLE_MSR_ACCESS)
 404                 load_cr4(rcr4() | CR4_PCE);
 405
 406         return 0;
 407 }
 408
 409 /*
 410  * Machine dependent actions taken during the context switch out of a
 411  * thread.
 412  */
 413
 414 static int
 415 amd_switch_out(struct pmc_cpu *pc, struct pmc_process *pp)
 416 {
 417         (void) pc;
 418         (void) pp;              /* can be NULL */
 419
 420         PMCDBG3(MDP,SWO,1, "pc=%p pp=%p enable-msr=%d", pc, pp, pp ?
 421             (pp->pp_flags & PMC_PP_ENABLE_MSR_ACCESS) == 1 : 0);
 422
 423         /* always turn off the RDPMC instruction */
 424         load_cr4(rcr4() & ~CR4_PCE);
 425
 426         return 0;
 427 }
 428
 429 /*
 430  * Check if a given allocation is feasible.
 431  */
 432
 433 static int
 434 amd_allocate_pmc(int cpu, int ri, struct pmc *pm,
 435     const struct pmc_op_pmcallocate *a)
 436 {
 437         int i;
 438         uint32_t allowed_unitmask, caps, config, unitmask;
 439         enum pmc_event pe;
 440         const struct pmc_descr *pd;
 441
 442         (void) cpu;
 443
 444         KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
 445             ("[amd,%d] illegal CPU value %d", __LINE__, cpu));
 446         KASSERT(ri >= 0 && ri < AMD_NPMCS,
 447             ("[amd,%d] illegal row index %d", __LINE__, ri));
 448
 449         pd = &amd_pmcdesc[ri].pm_descr;
 450
 451         /* check class match */
 452         if (pd->pd_class != a->pm_class)
 453                 return EINVAL;
 454
 455         caps = pm->pm_caps;
 456
 457         PMCDBG2(MDP,ALL,1,"amd-allocate ri=%d caps=0x%x", ri, caps);
 458
 459         if ((pd->pd_caps & caps) != caps)
 460                 return EPERM;
 461
 462         pe = a->pm_ev;
 463
 464         /* map ev to the correct event mask code */
 465         config = allowed_unitmask = 0;
 466         for (i = 0; i < amd_event_codes_size; i++)
 467                 if (amd_event_codes[i].pe_ev == pe) {
 468                         config =
 469                             AMD_PMC_TO_EVENTMASK(amd_event_codes[i].pe_code);
 470                         allowed_unitmask =
 471                             AMD_PMC_TO_UNITMASK(amd_event_codes[i].pe_mask);
 472                         break;
 473                 }
 474         if (i == amd_event_codes_size)
 475                 return EINVAL;
 476
 477         unitmask = a->pm_md.pm_amd.pm_amd_config & AMD_PMC_UNITMASK;
 478         if (unitmask & ~allowed_unitmask) /* disallow reserved bits */
 479                 return EINVAL;
 480
 481         if (unitmask && (caps & PMC_CAP_QUALIFIER))
 482                 config |= unitmask;
 483
 484         if (caps & PMC_CAP_THRESHOLD)
 485                 config |= a->pm_md.pm_amd.pm_amd_config & AMD_PMC_COUNTERMASK;
 486
 487         /* set at least one of the 'usr' or 'os' caps */
 488         if (caps & PMC_CAP_USER)
 489                 config |= AMD_PMC_USR;
 490         if (caps & PMC_CAP_SYSTEM)
 491                 config |= AMD_PMC_OS;
 492         if ((caps & (PMC_CAP_USER|PMC_CAP_SYSTEM)) == 0)
 493                 config |= (AMD_PMC_USR|AMD_PMC_OS);
 494
 495         if (caps & PMC_CAP_EDGE)
 496                 config |= AMD_PMC_EDGE;
 497         if (caps & PMC_CAP_INVERT)
 498                 config |= AMD_PMC_INVERT;
 499         if (caps & PMC_CAP_INTERRUPT)
 500                 config |= AMD_PMC_INT;
 501
 502         pm->pm_md.pm_amd.pm_amd_evsel = config; /* save config value */
 503
 504         PMCDBG2(MDP,ALL,2,"amd-allocate ri=%d -> config=0x%x", ri, config);
 505
 506         return 0;
 507 }
 508
 509 /*
 510  * Release machine dependent state associated with a PMC.  This is a
 511  * no-op on this architecture.
 512  *
 513  */
 514
 515 /* ARGSUSED0 */
 516 static int
 517 amd_release_pmc(int cpu, int ri, struct pmc *pmc)
 518 {
 519 #ifdef  HWPMC_DEBUG
 520         const struct amd_descr *pd;
 521 #endif
 522         struct pmc_hw *phw;
 523
 524         (void) pmc;
 525
 526         KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
 527             ("[amd,%d] illegal CPU value %d", __LINE__, cpu));
 528         KASSERT(ri >= 0 && ri < AMD_NPMCS,
 529             ("[amd,%d] illegal row-index %d", __LINE__, ri));
 530
 531         phw = &amd_pcpu[cpu]->pc_amdpmcs[ri];
 532
 533         KASSERT(phw->phw_pmc == NULL,
 534             ("[amd,%d] PHW pmc %p non-NULL", __LINE__, phw->phw_pmc));
 535
 536 #ifdef  HWPMC_DEBUG
 537         pd = &amd_pmcdesc[ri];
 538         if (pd->pm_descr.pd_class == amd_pmc_class)
 539                 KASSERT(AMD_PMC_IS_STOPPED(pd->pm_evsel),
 540                     ("[amd,%d] PMC %d released while active", __LINE__, ri));
 541 #endif
 542
 543         return 0;
 544 }
 545
 546 /*
 547  * start a PMC.
 548  */
 549
 550 static int
 551 amd_start_pmc(int cpu, int ri)
 552 {
 553         uint32_t config;
 554         struct pmc *pm;
 555         struct pmc_hw *phw;
 556         const struct amd_descr *pd;
 557
 558         KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
 559             ("[amd,%d] illegal CPU value %d", __LINE__, cpu));
 560         KASSERT(ri >= 0 && ri < AMD_NPMCS,
 561             ("[amd,%d] illegal row-index %d", __LINE__, ri));
 562
 563         phw = &amd_pcpu[cpu]->pc_amdpmcs[ri];
 564         pm  = phw->phw_pmc;
 565         pd = &amd_pmcdesc[ri];
 566
 567         KASSERT(pm != NULL,
 568             ("[amd,%d] starting cpu%d,pmc%d with null pmc record", __LINE__,
 569                 cpu, ri));
 570
 571         PMCDBG2(MDP,STA,1,"amd-start cpu=%d ri=%d", cpu, ri);
 572
 573         KASSERT(AMD_PMC_IS_STOPPED(pd->pm_evsel),
 574             ("[amd,%d] pmc%d,cpu%d: Starting active PMC \"%s\"", __LINE__,
 575             ri, cpu, pd->pm_descr.pd_name));
 576
 577         /* turn on the PMC ENABLE bit */
 578         config = pm->pm_md.pm_amd.pm_amd_evsel | AMD_PMC_ENABLE;
 579
 580         PMCDBG1(MDP,STA,2,"amd-start config=0x%x", config);
 581
 582         wrmsr(pd->pm_evsel, config);
 583         return 0;
 584 }
 585
 586 /*
 587  * Stop a PMC.
 588  */
 589
 590 static int
 591 amd_stop_pmc(int cpu, int ri)
 592 {
 593         struct pmc *pm;
 594         struct pmc_hw *phw;
 595         const struct amd_descr *pd;
 596         uint64_t config;
 597
 598         KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
 599             ("[amd,%d] illegal CPU value %d", __LINE__, cpu));
 600         KASSERT(ri >= 0 && ri < AMD_NPMCS,
 601             ("[amd,%d] illegal row-index %d", __LINE__, ri));
 602
 603         phw = &amd_pcpu[cpu]->pc_amdpmcs[ri];
 604         pm  = phw->phw_pmc;
 605         pd  = &amd_pmcdesc[ri];
 606
 607         KASSERT(pm != NULL,
 608             ("[amd,%d] cpu%d,pmc%d no PMC to stop", __LINE__,
 609                 cpu, ri));
 610         KASSERT(!AMD_PMC_IS_STOPPED(pd->pm_evsel),
 611             ("[amd,%d] PMC%d, CPU%d \"%s\" already stopped",
 612                 __LINE__, ri, cpu, pd->pm_descr.pd_name));
 613
 614         PMCDBG1(MDP,STO,1,"amd-stop ri=%d", ri);
 615
 616         /* turn off the PMC ENABLE bit */
 617         config = pm->pm_md.pm_amd.pm_amd_evsel & ~AMD_PMC_ENABLE;
 618         wrmsr(pd->pm_evsel, config);
 619         return 0;
 620 }
 621
 622 /*
 623  * Interrupt handler.  This function needs to return '1' if the
 624  * interrupt was this CPU's PMCs or '0' otherwise.  It is not allowed
 625  * to sleep or do anything a 'fast' interrupt handler is not allowed
 626  * to do.
 627  */
 628
 629 static int
 630 amd_intr(int cpu, struct trapframe *tf)
 631 {
 632         int i, error, retval;
 633         uint32_t config, evsel, perfctr;
 634         struct pmc *pm;
 635         struct amd_cpu *pac;
 636         pmc_value_t v;
 637
 638         KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
 639             ("[amd,%d] out of range CPU %d", __LINE__, cpu));
 640
 641         PMCDBG3(MDP,INT,1, "cpu=%d tf=%p um=%d", cpu, (void *) tf,
 642             TRAPF_USERMODE(tf));
 643
 644         retval = 0;
 645
 646         pac = amd_pcpu[cpu];
 647
 648         /*
 649          * look for all PMCs that have interrupted:
 650          * - look for a running, sampling PMC which has overflowed
 651          *   and which has a valid 'struct pmc' association
 652          *
 653          * If found, we call a helper to process the interrupt.
 654          *
 655          * If multiple PMCs interrupt at the same time, the AMD64
 656          * processor appears to deliver as many NMIs as there are
 657          * outstanding PMC interrupts.  So we process only one NMI
 658          * interrupt at a time.
 659          */
 660
 661         for (i = 0; retval == 0 && i < AMD_NPMCS; i++) {
 662
 663                 if ((pm = pac->pc_amdpmcs[i].phw_pmc) == NULL ||
 664                     !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) {
 665                         continue;
 666                 }
 667
 668                 if (!AMD_PMC_HAS_OVERFLOWED(i))
 669                         continue;
 670
 671                 retval = 1;     /* Found an interrupting PMC. */
 672
 673                 if (pm->pm_state != PMC_STATE_RUNNING)
 674                         continue;
 675
 676                 /* Stop the PMC, reload count. */
 677                 evsel   = AMD_PMC_EVSEL_0 + i;
 678                 perfctr = AMD_PMC_PERFCTR_0 + i;
 679                 v       = pm->pm_sc.pm_reloadcount;
 680                 config  = rdmsr(evsel);
 681
 682                 KASSERT((config & ~AMD_PMC_ENABLE) ==
 683                     (pm->pm_md.pm_amd.pm_amd_evsel & ~AMD_PMC_ENABLE),
 684                     ("[amd,%d] config mismatch reg=0x%x pm=0x%x", __LINE__,
 685                         config, pm->pm_md.pm_amd.pm_amd_evsel));
 686
 687                 wrmsr(evsel, config & ~AMD_PMC_ENABLE);
 688                 wrmsr(perfctr, AMD_RELOAD_COUNT_TO_PERFCTR_VALUE(v));
 689
 690                 /* Restart the counter if logging succeeded. */
 691                 error = pmc_process_interrupt(cpu, PMC_HR, pm, tf,
 692                     TRAPF_USERMODE(tf));
 693                 if (error == 0)
 694                         wrmsr(evsel, config);
 695         }
 696
 697         if (retval)
 698                 counter_u64_add(pmc_stats.pm_intr_processed, 1);
 699         else
 700                 counter_u64_add(pmc_stats.pm_intr_ignored, 1);
 701
 702         PMCDBG1(MDP,INT,2, "retval=%d", retval);
 703         return (retval);
 704 }
 705
 706 /*
 707  * describe a PMC
 708  */
 709 static int
 710 amd_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc)
 711 {
 712         int error;
 713         size_t copied;
 714         const struct amd_descr *pd;
 715         struct pmc_hw *phw;
 716
 717         KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
 718             ("[amd,%d] illegal CPU %d", __LINE__, cpu));
 719         KASSERT(ri >= 0 && ri < AMD_NPMCS,
 720             ("[amd,%d] row-index %d out of range", __LINE__, ri));
 721
 722         phw = &amd_pcpu[cpu]->pc_amdpmcs[ri];
 723         pd  = &amd_pmcdesc[ri];
 724
 725         if ((error = copystr(pd->pm_descr.pd_name, pi->pm_name,
 726                  PMC_NAME_MAX, &copied)) != 0)
 727                 return error;
 728
 729         pi->pm_class = pd->pm_descr.pd_class;
 730
 731         if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) {
 732                 pi->pm_enabled = TRUE;
 733                 *ppmc          = phw->phw_pmc;
 734         } else {
 735                 pi->pm_enabled = FALSE;
 736                 *ppmc          = NULL;
 737         }
 738
 739         return 0;
 740 }
 741
 742 /*
 743  * i386 specific entry points
 744  */
 745
 746 /*
 747  * return the MSR address of the given PMC.
 748  */
 749
 750 static int
 751 amd_get_msr(int ri, uint32_t *msr)
 752 {
 753         KASSERT(ri >= 0 && ri < AMD_NPMCS,
 754             ("[amd,%d] ri %d out of range", __LINE__, ri));
 755
 756         *msr = amd_pmcdesc[ri].pm_perfctr - AMD_PMC_PERFCTR_0;
 757
 758         return (0);
 759 }
 760
 761 /*
 762  * processor dependent initialization.
 763  */
 764
 765 static int
 766 amd_pcpu_init(struct pmc_mdep *md, int cpu)
 767 {
 768         int classindex, first_ri, n;
 769         struct pmc_cpu *pc;
 770         struct amd_cpu *pac;
 771         struct pmc_hw  *phw;
 772
 773         KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
 774             ("[amd,%d] insane cpu number %d", __LINE__, cpu));
 775
 776         PMCDBG1(MDP,INI,1,"amd-init cpu=%d", cpu);
 777
 778         amd_pcpu[cpu] = pac = malloc(sizeof(struct amd_cpu), M_PMC,
 779             M_WAITOK|M_ZERO);
 780
 781         /*
 782          * Set the content of the hardware descriptors to a known
 783          * state and initialize pointers in the MI per-cpu descriptor.
 784          */
 785         pc = pmc_pcpu[cpu];
 786 #if     defined(__amd64__)
 787         classindex = PMC_MDEP_CLASS_INDEX_K8;
 788 #elif   defined(__i386__)
 789         classindex = md->pmd_cputype == PMC_CPU_AMD_K8 ?
 790             PMC_MDEP_CLASS_INDEX_K8 : PMC_MDEP_CLASS_INDEX_K7;
 791 #endif
 792         first_ri = md->pmd_classdep[classindex].pcd_ri;
 793
 794         KASSERT(pc != NULL, ("[amd,%d] NULL per-cpu pointer", __LINE__));
 795
 796         for (n = 0, phw = pac->pc_amdpmcs; n < AMD_NPMCS; n++, phw++) {
 797                 phw->phw_state    = PMC_PHW_FLAG_IS_ENABLED |
 798                     PMC_PHW_CPU_TO_STATE(cpu) | PMC_PHW_INDEX_TO_STATE(n);
 799                 phw->phw_pmc      = NULL;
 800                 pc->pc_hwpmcs[n + first_ri]  = phw;
 801         }
 802
 803         return (0);
 804 }
 805
 806
 807 /*
 808  * processor dependent cleanup prior to the KLD
 809  * being unloaded
 810  */
 811
 812 static int
 813 amd_pcpu_fini(struct pmc_mdep *md, int cpu)
 814 {
 815         int classindex, first_ri, i;
 816         uint32_t evsel;
 817         struct pmc_cpu *pc;
 818         struct amd_cpu *pac;
 819
 820         KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
 821             ("[amd,%d] insane cpu number (%d)", __LINE__, cpu));
 822
 823         PMCDBG1(MDP,INI,1,"amd-cleanup cpu=%d", cpu);
 824
 825         /*
 826          * First, turn off all PMCs on this CPU.
 827          */
 828         for (i = 0; i < 4; i++) { /* XXX this loop is now not needed */
 829                 evsel = rdmsr(AMD_PMC_EVSEL_0 + i);
 830                 evsel &= ~AMD_PMC_ENABLE;
 831                 wrmsr(AMD_PMC_EVSEL_0 + i, evsel);
 832         }
 833
 834         /*
 835          * Next, free up allocated space.
 836          */
 837         if ((pac = amd_pcpu[cpu]) == NULL)
 838                 return (0);
 839
 840         amd_pcpu[cpu] = NULL;
 841
 842 #ifdef  HWPMC_DEBUG
 843         for (i = 0; i < AMD_NPMCS; i++) {
 844                 KASSERT(pac->pc_amdpmcs[i].phw_pmc == NULL,
 845                     ("[amd,%d] CPU%d/PMC%d in use", __LINE__, cpu, i));
 846                 KASSERT(AMD_PMC_IS_STOPPED(AMD_PMC_EVSEL_0 + i),
 847                     ("[amd,%d] CPU%d/PMC%d not stopped", __LINE__, cpu, i));
 848         }
 849 #endif
 850
 851         pc = pmc_pcpu[cpu];
 852         KASSERT(pc != NULL, ("[amd,%d] NULL per-cpu state", __LINE__));
 853
 854 #if     defined(__amd64__)
 855         classindex = PMC_MDEP_CLASS_INDEX_K8;
 856 #elif   defined(__i386__)
 857         classindex = md->pmd_cputype == PMC_CPU_AMD_K8 ? PMC_MDEP_CLASS_INDEX_K8 :
 858             PMC_MDEP_CLASS_INDEX_K7;
 859 #endif
 860         first_ri = md->pmd_classdep[classindex].pcd_ri;
 861
 862         /*
 863          * Reset pointers in the MI 'per-cpu' state.
 864          */
 865         for (i = 0; i < AMD_NPMCS; i++) {
 866                 pc->pc_hwpmcs[i + first_ri] = NULL;
 867         }
 868
 869
 870         free(pac, M_PMC);
 871
 872         return (0);
 873 }
 874
 875 /*
 876  * Initialize ourselves.
 877  */
 878
 879 struct pmc_mdep *
 880 pmc_amd_initialize(void)
 881 {
 882         int classindex, error, i, ncpus;
 883         struct pmc_classdep *pcd;
 884         enum pmc_cputype cputype;
 885         struct pmc_mdep *pmc_mdep;
 886         enum pmc_class class;
 887         char *name;
 888
 889         /*
 890          * The presence of hardware performance counters on the AMD
 891          * Athlon, Duron or later processors, is _not_ indicated by
 892          * any of the processor feature flags set by the 'CPUID'
 893          * instruction, so we only check the 'instruction family'
 894          * field returned by CPUID for instruction family >= 6.
 895          */
 896
 897         name = NULL;
 898         switch (cpu_id & 0xF00) {
 899 #if     defined(__i386__)
 900         case 0x600:             /* Athlon(tm) processor */
 901                 classindex = PMC_MDEP_CLASS_INDEX_K7;
 902                 cputype = PMC_CPU_AMD_K7;
 903                 class = PMC_CLASS_K7;
 904                 name = "K7";
 905                 break;
 906 #endif
 907         case 0xF00:             /* Athlon64/Opteron processor */
 908                 classindex = PMC_MDEP_CLASS_INDEX_K8;
 909                 cputype = PMC_CPU_AMD_K8;
 910                 class = PMC_CLASS_K8;
 911                 name = "K8";
 912                 break;
 913
 914         default:
 915                 (void) printf("pmc: Unknown AMD CPU.\n");
 916                 return NULL;
 917         }
 918
 919 #ifdef  HWPMC_DEBUG
 920         amd_pmc_class = class;
 921 #endif
 922
 923         /*
 924          * Allocate space for pointers to PMC HW descriptors and for
 925          * the MDEP structure used by MI code.
 926          */
 927         amd_pcpu = malloc(sizeof(struct amd_cpu *) * pmc_cpu_max(), M_PMC,
 928             M_WAITOK|M_ZERO);
 929
 930         /*
 931          * These processors have two classes of PMCs: the TSC and
 932          * programmable PMCs.
 933          */
 934         pmc_mdep = pmc_mdep_alloc(2);
 935
 936         pmc_mdep->pmd_cputype = cputype;
 937
 938         ncpus = pmc_cpu_max();
 939
 940         /* Initialize the TSC. */
 941         error = pmc_tsc_initialize(pmc_mdep, ncpus);
 942         if (error)
 943                 goto error;
 944
 945         /* Initialize AMD K7 and K8 PMC handling. */
 946         pcd = &pmc_mdep->pmd_classdep[classindex];
 947
 948         pcd->pcd_caps           = AMD_PMC_CAPS;
 949         pcd->pcd_class          = class;
 950         pcd->pcd_num            = AMD_NPMCS;
 951         pcd->pcd_ri             = pmc_mdep->pmd_npmc;
 952         pcd->pcd_width          = 48;
 953
 954         /* fill in the correct pmc name and class */
 955         for (i = 0; i < AMD_NPMCS; i++) {
 956                 (void) snprintf(amd_pmcdesc[i].pm_descr.pd_name,
 957                     sizeof(amd_pmcdesc[i].pm_descr.pd_name), "%s-%d",
 958                     name, i);
 959                 amd_pmcdesc[i].pm_descr.pd_class = class;
 960         }
 961
 962         pcd->pcd_allocate_pmc   = amd_allocate_pmc;
 963         pcd->pcd_config_pmc     = amd_config_pmc;
 964         pcd->pcd_describe       = amd_describe;
 965         pcd->pcd_get_config     = amd_get_config;
 966         pcd->pcd_get_msr        = amd_get_msr;
 967         pcd->pcd_pcpu_fini      = amd_pcpu_fini;
 968         pcd->pcd_pcpu_init      = amd_pcpu_init;
 969         pcd->pcd_read_pmc       = amd_read_pmc;
 970         pcd->pcd_release_pmc    = amd_release_pmc;
 971         pcd->pcd_start_pmc      = amd_start_pmc;
 972         pcd->pcd_stop_pmc       = amd_stop_pmc;
 973         pcd->pcd_write_pmc      = amd_write_pmc;
 974
 975         pmc_mdep->pmd_pcpu_init = NULL;
 976         pmc_mdep->pmd_pcpu_fini = NULL;
 977         pmc_mdep->pmd_intr      = amd_intr;
 978         pmc_mdep->pmd_switch_in = amd_switch_in;
 979         pmc_mdep->pmd_switch_out = amd_switch_out;
 980
 981         pmc_mdep->pmd_npmc     += AMD_NPMCS;
 982
 983         PMCDBG0(MDP,INI,0,"amd-initialize");
 984
 985         return (pmc_mdep);
 986
 987   error:
 988         if (error) {
 989                 free(pmc_mdep, M_PMC);
 990                 pmc_mdep = NULL;
 991         }
 992
 993         return (NULL);
 994 }
 995
 996 /*
 997  * Finalization code for AMD CPUs.
 998  */
 999
1000 void
1001 pmc_amd_finalize(struct pmc_mdep *md)
1002 {
1003 #if     defined(INVARIANTS)
1004         int classindex, i, ncpus, pmcclass;
1005 #endif
1006
1007         pmc_tsc_finalize(md);
1008
1009         KASSERT(amd_pcpu != NULL, ("[amd,%d] NULL per-cpu array pointer",
1010             __LINE__));
1011
1012 #if     defined(INVARIANTS)
1013         switch (md->pmd_cputype) {
1014 #if     defined(__i386__)
1015         case PMC_CPU_AMD_K7:
1016                 classindex = PMC_MDEP_CLASS_INDEX_K7;
1017                 pmcclass = PMC_CLASS_K7;
1018                 break;
1019 #endif
1020         default:
1021                 classindex = PMC_MDEP_CLASS_INDEX_K8;
1022                 pmcclass = PMC_CLASS_K8;
1023         }
1024
1025         KASSERT(md->pmd_classdep[classindex].pcd_class == pmcclass,
1026             ("[amd,%d] pmc class mismatch", __LINE__));
1027
1028         ncpus = pmc_cpu_max();
1029
1030         for (i = 0; i < ncpus; i++)
1031                 KASSERT(amd_pcpu[i] == NULL, ("[amd,%d] non-null pcpu",
1032                     __LINE__));
1033 #endif
1034
1035         free(amd_pcpu, M_PMC);
1036         amd_pcpu = NULL;
1037 }